Index: lib/Target/PowerPC/PPCInstrInfo.td =================================================================== --- lib/Target/PowerPC/PPCInstrInfo.td +++ lib/Target/PowerPC/PPCInstrInfo.td @@ -3933,6 +3933,63 @@ def STDCIX : XForm_base_r3xo<31, 1013, (outs), (ins gprc:$RST, gprc:$A, gprc:$B), "stdcix $RST, $A, $B", IIC_LdStLoad, []>; +// External PID Load Store Instructions + +def LBEPX : XForm_1<31, 95, (outs gprc:$rD), (ins memrr:$src), + "lbepx $rD, $src", IIC_LdStLoad, []>, + Requires<[IsE500]>; + +def LFDEPX : XForm_25<31, 607, (outs f8rc:$frD), (ins memrr:$src), + "lfdepx $frD, $src", IIC_LdStLFD, []>, + Requires<[IsE500]>; + +def LHEPX : XForm_1<31, 287, (outs gprc:$rD), (ins memrr:$src), + "lhepx $rD, $src", IIC_LdStLoad, []>, + Requires<[IsE500]>; + +def LWEPX : XForm_1<31, 31, (outs gprc:$rD), (ins memrr:$src), + "lwepx $rD, $src", IIC_LdStLoad, []>, + Requires<[IsE500]>; + +def STBEPX : XForm_8<31, 223, (outs), (ins gprc:$rS, memrr:$dst), + "stbepx $rS, $dst", IIC_LdStStore, []>, + Requires<[IsE500]>; + +def STFDEPX : XForm_28<31, 735, (outs), (ins f8rc:$frS, memrr:$dst), + "stfdepx $frS, $dst", IIC_LdStSTFD, []>, + Requires<[IsE500]>; + +def STHEPX : XForm_8<31, 415, (outs), (ins gprc:$rS, memrr:$dst), + "sthepx $rS, $dst", IIC_LdStStore, []>, + Requires<[IsE500]>; + +def STWEPX : XForm_8<31, 159, (outs), (ins gprc:$rS, memrr:$dst), + "stwepx $rS, $dst", IIC_LdStStore, []>, + Requires<[IsE500]>; + +def DCBFEP : DCB_Form<127, 0, (outs), (ins memrr:$dst), "dcbfep $dst", + IIC_LdStDCBF, []>, Requires<[IsE500]>; + +def DCBSTEP : DCB_Form<63, 0, (outs), (ins memrr:$dst), "dcbstep $dst", + IIC_LdStDCBF, []>, Requires<[IsE500]>; + +def DCBTEP : DCB_Form_hint<319, (outs), (ins memrr:$dst, u5imm:$TH), + "dcbtep $TH, $dst", IIC_LdStDCBF, []>, + Requires<[IsE500]>; + +def DCBTSTEP : DCB_Form_hint<255, (outs), (ins memrr:$dst, u5imm:$TH), + "dcbtstep $TH, $dst", IIC_LdStDCBF, []>, + Requires<[IsE500]>; + +def DCBZEP : DCB_Form<1023, 0, (outs), (ins memrr:$dst), "dcbzep $dst", + IIC_LdStDCBF, []>, Requires<[IsE500]>; + +def DCBZLEP : DCB_Form<1023, 1, (outs), (ins memrr:$dst), "dcbzlep $dst", + IIC_LdStDCBF, []>, Requires<[IsE500]>; + +def ICBIEP : XForm_1a<31, 991, (outs), (ins memrr:$src), "icbiep $src", + IIC_LdStICBI, []>, Requires<[IsE500]>; + //===----------------------------------------------------------------------===// // PowerPC Assembler Instruction Aliases // Index: test/MC/Disassembler/PowerPC/ppc32-extpid-e500.txt =================================================================== --- test/MC/Disassembler/PowerPC/ppc32-extpid-e500.txt +++ test/MC/Disassembler/PowerPC/ppc32-extpid-e500.txt @@ -0,0 +1,34 @@ +# RUN: llvm-mc --disassemble %s -triple powerpc-unknown-unknown | FileCheck %s + +# Extended PID instructions specific to the e500 / e500mc cores: + +# CHECK: lbepx 1, 2, 3 +0x7c 0x22 0x18 0xbe +# CHECK: lfdepx 4, 5, 6 +0x7c 0x85 0x34 0xbe +# CHECK: lhepx 7, 8, 9 +0x7c 0xe8 0x4a 0x3e +# CHECK: lwepx 10, 11, 12 +0x7d 0x4b 0x60 0x3e +# CHECK: stbepx 13, 14, 15 +0x7d 0xae 0x79 0xbe +# CHECK: stfdepx 16, 17, 18 +0x7e 0x11 0x95 0xbe +# CHECK: sthepx 19, 20, 21 +0x7e 0x74 0xab 0x3e +# CHECK: stwepx 22, 23, 24 +0x7e 0xd7 0xc1 0x3e +# CHECK: dcbfep 25, 26 +0x7c 0x19 0xd0 0xfe +# CHECK: dcbstep 27, 28 +0x7c 0x1b 0xe0 0x7e +# CHECK: dcbtep 29, 30, 31 +0x7f 0xbe 0xfa 0x7e +# CHECK: dcbtstep 0, 1, 2 +0x7c 0x01 0x11 0xfe +# CHECK: dcbzep 3, 4 +0x7c 0x03 0x27 0xfe +# CHECK: dcbzlep 5, 6 +0x7c 0x25 0x37 0xfe +# CHECK: icbiep 7, 8 +0x7c 0x07 0x47 0xbe Index: test/MC/PowerPC/ppc32-extpid-e500.s =================================================================== --- test/MC/PowerPC/ppc32-extpid-e500.s +++ test/MC/PowerPC/ppc32-extpid-e500.s @@ -0,0 +1,34 @@ +# RUN: llvm-mc -triple powerpc-unknown-unknown --show-encoding %s | FileCheck %s + +# Extended PID instructions specific to the e500 / e500mc cores: + +# CHECK: lbepx 1, 2, 3 # encoding: [0x7c,0x22,0x18,0xbe] + lbepx 1, 2, 3 +# CHECK: lfdepx 4, 5, 6 # encoding: [0x7c,0x85,0x34,0xbe] + lfdepx 4, 5, 6 +# CHECK: lhepx 7, 8, 9 # encoding: [0x7c,0xe8,0x4a,0x3e] + lhepx 7, 8, 9 +# CHECK: lwepx 10, 11, 12 # encoding: [0x7d,0x4b,0x60,0x3e] + lwepx 10, 11, 12 +# CHECK: stbepx 13, 14, 15 # encoding: [0x7d,0xae,0x79,0xbe] + stbepx 13, 14, 15 +# CHECK: stfdepx 16, 17, 18 # encoding: [0x7e,0x11,0x95,0xbe] + stfdepx 16, 17, 18 +# CHECK: sthepx 19, 20, 21 # encoding: [0x7e,0x74,0xab,0x3e] + sthepx 19, 20, 21 +# CHECK: stwepx 22, 23, 24 # encoding: [0x7e,0xd7,0xc1,0x3e] + stwepx 22, 23, 24 +# CHECK: dcbfep 25, 26 # encoding: [0x7c,0x19,0xd0,0xfe] + dcbfep 25, 26 +# CHECK: dcbstep 27, 28 # encoding: [0x7c,0x1b,0xe0,0x7e] + dcbstep 27, 28 +# CHECK: dcbtep 29, 30, 31 # encoding: [0x7f,0xbe,0xfa,0x7e] + dcbtep 29, 30, 31 +# CHECK: dcbtstep 0, 1, 2 # encoding: [0x7c,0x01,0x11,0xfe] + dcbtstep 0, 1, 2 +# CHECK: dcbzep 3, 4 # encoding: [0x7c,0x03,0x27,0xfe] + dcbzep 3, 4 +# CHECK: dcbzlep 5, 6 # encoding: [0x7c,0x25,0x37,0xfe] + dcbzlep 5, 6 +# CHECK: icbiep 7, 8 # encoding: [0x7c,0x07,0x47,0xbe] + icbiep 7, 8