Index: include/llvm/CodeGen/GlobalISel/InstructionSelector.h =================================================================== --- include/llvm/CodeGen/GlobalISel/InstructionSelector.h +++ include/llvm/CodeGen/GlobalISel/InstructionSelector.h @@ -187,6 +187,13 @@ /// - OldInsnID - Instruction ID to copy from /// - OpIdx - The operand to copy GIR_Copy, + /// Copy an operand to the specified instruction or add a zero register if the + /// operand is a zero immediate. + /// - NewInsnID - Instruction ID to modify + /// - OldInsnID - Instruction ID to copy from + /// - OpIdx - The operand to copy + /// - ZeroReg - The zero register to use + GIR_CopyOrAddZeroReg, /// Copy an operand to the specified instruction /// - NewInsnID - Instruction ID to modify /// - OldInsnID - Instruction ID to copy from Index: include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h =================================================================== --- include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h +++ include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h @@ -440,6 +440,23 @@ break; } + case GIR_CopyOrAddZeroReg: { + int64_t NewInsnID = MatchTable[CurrentIdx++]; + int64_t OldInsnID = MatchTable[CurrentIdx++]; + int64_t OpIdx = MatchTable[CurrentIdx++]; + int64_t ZeroReg = MatchTable[CurrentIdx++]; + assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction"); + MachineOperand &MO = State.MIs[OldInsnID]->getOperand(OpIdx); + if (isOperandImmEqual(MO, 0, MRI)) + OutMIs[NewInsnID].addReg(ZeroReg); + else + OutMIs[NewInsnID].add(MO); + DEBUG(dbgs() << CurrentIdx << ": GIR_CopyOrAddZeroReg(OutMIs[" + << NewInsnID << "], MIs[" << OldInsnID << "], " << OpIdx + << ", " << ZeroReg << ")\n"); + break; + } + case GIR_CopySubReg: { int64_t NewInsnID = MatchTable[CurrentIdx++]; int64_t OldInsnID = MatchTable[CurrentIdx++]; Index: include/llvm/Target/Target.td =================================================================== --- include/llvm/Target/Target.td +++ include/llvm/Target/Target.td @@ -284,6 +284,12 @@ // the assembly matcher will provide a function to map from diagnostic types // to message strings. string DiagnosticString = ""; + + // When referenced in the result of a CodeGen pattern, GlobalISel will + // normally copy the matched operand to the result. When this is set, it will + // emit a special copy that will replace zero-immediates with the specified + // zero-register. + Register GIZeroRegister = ?; } // The memberList in a RegisterClass is a dag of set operations. TableGen Index: lib/Target/AArch64/AArch64RegisterInfo.td =================================================================== --- lib/Target/AArch64/AArch64RegisterInfo.td +++ lib/Target/AArch64/AArch64RegisterInfo.td @@ -140,10 +140,12 @@ def GPR32 : RegisterClass<"AArch64", [i32], 32, (add GPR32common, WZR)> { let AltOrders = [(rotl GPR32, 8)]; let AltOrderSelect = [{ return 1; }]; + let GIZeroRegister = WZR; } def GPR64 : RegisterClass<"AArch64", [i64], 64, (add GPR64common, XZR)> { let AltOrders = [(rotl GPR64, 8)]; let AltOrderSelect = [{ return 1; }]; + let GIZeroRegister = XZR; } // GPR register classes which include SP/WSP. @@ -171,8 +173,12 @@ // GPR register classes which include WZR/XZR AND SP/WSP. This is not a // constraint used by any instructions, it is used as a common super-class. -def GPR32all : RegisterClass<"AArch64", [i32], 32, (add GPR32common, WZR, WSP)>; -def GPR64all : RegisterClass<"AArch64", [i64], 64, (add GPR64common, XZR, SP)>; +def GPR32all : RegisterClass<"AArch64", [i32], 32, (add GPR32common, WZR, WSP)> { + let GIZeroRegister = WZR; +} +def GPR64all : RegisterClass<"AArch64", [i64], 64, (add GPR64common, XZR, SP)> { + let GIZeroRegister = XZR; +} // For tail calls, we can't use callee-saved registers, as they are restored // to the saved value before the tail call, which would clobber a call address. Index: test/CodeGen/AArch64/GlobalISel/select-store.mir =================================================================== --- test/CodeGen/AArch64/GlobalISel/select-store.mir +++ test/CodeGen/AArch64/GlobalISel/select-store.mir @@ -27,6 +27,8 @@ define void @store_gep_8_s64_fpr(i64* %addr) { ret void } define void @store_gep_8_s32_fpr(i32* %addr) { ret void } + + define void @store_v2s32(i64 *%addr) { ret void } ... --- @@ -447,3 +449,29 @@ %3(p0) = G_GEP %0, %2 G_STORE %1, %3 :: (store 4 into %ir.addr) ... +--- +# CHECK-LABEL: name: store_v2s32 +name: store_v2s32 +legalized: true +regBankSelected: true + +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' } +# CHECK-NEXT: - { id: 1, class: fpr64, preferred-register: '' } +registers: + - { id: 0, class: gpr } + - { id: 1, class: fpr } + +# CHECK: body: +# CHECK: %0 = COPY %x0 +# CHECK: %1 = COPY %d1 +# CHECK: STRDui %1, %0, 0 :: (store 8 into %ir.addr) +body: | + bb.0: + liveins: %x0, %d1 + + %0(p0) = COPY %x0 + %1(<2 x s32>) = COPY %d1 + G_STORE %1, %0 :: (store 8 into %ir.addr) + +... Index: utils/TableGen/GlobalISelEmitter.cpp =================================================================== --- utils/TableGen/GlobalISelEmitter.cpp +++ utils/TableGen/GlobalISelEmitter.cpp @@ -246,6 +246,13 @@ if (Predicate.isNonExtLoad()) continue; + + if (Predicate.isStore() && Predicate.isUnindexed()) + continue; + + if (Predicate.isNonTruncStore()) + continue; + HasUnsupportedPredicate = true; Explanation = Separator + "Has a predicate (" + explainPredicates(N) + ")"; Separator = ", "; @@ -1419,6 +1426,7 @@ public: enum RendererKind { OR_Copy, + OR_CopyOrAddZeroReg, OR_CopySubReg, OR_CopyConstantAsImm, OR_CopyFConstantAsFPImm, @@ -1477,6 +1485,48 @@ } }; +/// A CopyOrAddZeroRegRenderer emits code to copy a single operand from an +/// existing instruction to the one being built. If the operand turns out to be +/// a 'G_CONSTANT 0' then it replaces the operand with a zero register. +class CopyOrAddZeroRegRenderer : public OperandRenderer { +protected: + unsigned NewInsnID; + /// The name of the operand. + const StringRef SymbolicName; + const Record *ZeroRegisterDef; + +public: + CopyOrAddZeroRegRenderer(unsigned NewInsnID, + const InstructionMatcher &Matched, + StringRef SymbolicName, Record *ZeroRegisterDef) + : OperandRenderer(OR_CopyOrAddZeroReg), NewInsnID(NewInsnID), + SymbolicName(SymbolicName), ZeroRegisterDef(ZeroRegisterDef) { + assert(!SymbolicName.empty() && "Cannot copy from an unspecified source"); + } + + static bool classof(const OperandRenderer *R) { + return R->getKind() == OR_CopyOrAddZeroReg; + } + + const StringRef getSymbolicName() const { return SymbolicName; } + + void emitRenderOpcodes(MatchTable &Table, RuleMatcher &Rule) const override { + const OperandMatcher &Operand = Rule.getOperandMatcher(SymbolicName); + unsigned OldInsnVarID = Rule.getInsnVarID(Operand.getInstructionMatcher()); + Table << MatchTable::Opcode("GIR_CopyOrAddZeroReg") + << MatchTable::Comment("NewInsnID") << MatchTable::IntValue(NewInsnID) + << MatchTable::Comment("OldInsnID") + << MatchTable::IntValue(OldInsnVarID) << MatchTable::Comment("OpIdx") + << MatchTable::IntValue(Operand.getOperandIndex()) + << MatchTable::NamedValue( + (ZeroRegisterDef->getValue("Namespace") + ? ZeroRegisterDef->getValueAsString("Namespace") + : ""), + ZeroRegisterDef->getName()) + << MatchTable::Comment(SymbolicName) << MatchTable::LineBreak; + } +}; + /// A CopyConstantAsImmRenderer emits code to render a G_CONSTANT instruction to /// an extended immediate operand. class CopyConstantAsImmRenderer : public OperandRenderer { @@ -2275,6 +2325,25 @@ continue; } + // No check required. A G_STORE is an unindexed store. + if (Predicate.isStore() && Predicate.isUnindexed()) + continue; + + // No check required. G_STORE by itself is a non-extending store. + if (Predicate.isNonTruncStore()) + continue; + + if (Predicate.isStore() && Predicate.getMemoryVT() != nullptr) { + Optional MemTyOrNone = + MVTToLLT(getValueType(Predicate.getMemoryVT())); + + if (!MemTyOrNone) + return failedImport("MemVT could not be converted to LLT"); + + InsnMatcher.getOperand(0).addPredicate(MemTyOrNone.getValue()); + continue; + } + return failedImport("Src pattern child has predicate (" + explainPredicates(Src) + ")"); } @@ -2311,7 +2380,8 @@ // Coerce integers to pointers to address space 0 if the context indicates a pointer. // TODO: Find a better way to do this, SDTCisPtrTy? bool OperandIsAPointer = - SrcGIOrNull->TheDef->getName() == "G_LOAD" && i == 0; + (SrcGIOrNull->TheDef->getName() == "G_LOAD" && i == 0) || + (SrcGIOrNull->TheDef->getName() == "G_STORE" && i == 1); // For G_INTRINSIC/G_INTRINSIC_W_SIDE_EFFECTS, the operand immediately // following the defs is an intrinsic ID. @@ -2530,6 +2600,14 @@ if (ChildRec->isSubClassOf("RegisterClass") || ChildRec->isSubClassOf("RegisterOperand") || ChildRec->isSubClassOf("ValueType")) { + if (ChildRec->isSubClassOf("RegisterClass") && + !ChildRec->isValueUnset("GIZeroRegister")) { + DstMIBuilder.addRenderer( + 0, InsnMatcher, DstChild->getName(), + ChildRec->getValueAsDef("GIZeroRegister")); + return Error::success(); + } + DstMIBuilder.addRenderer(0, InsnMatcher, DstChild->getName()); return Error::success();