Index: lib/Target/Hexagon/Hexagon.td =================================================================== --- lib/Target/Hexagon/Hexagon.td +++ lib/Target/Hexagon/Hexagon.td @@ -25,10 +25,31 @@ include "HexagonDepArch.td" // Hexagon ISA Extensions -def ExtensionHVX: SubtargetFeature<"hvx", "UseHVXOps", "true", - "Hexagon HVX instructions">; -def ExtensionHVXDbl: SubtargetFeature<"hvx-double", "UseHVXDblOps", "true", - "Hexagon HVX Double instructions">; +def ExtensionHVXV60: SubtargetFeature<"hvxv60", "HexagonHVXVersion", + "Hexagon::ArchEnum::V60", "Hexagon HVX instructions">; +def ExtensionHVXV62: SubtargetFeature<"hvxv62", "HexagonHVXVersion", + "Hexagon::ArchEnum::V62", "Hexagon HVX instructions", + [ExtensionHVXV60]>; +def ExtensionHVX: SubtargetFeature<"hvx", "HexagonHVXVersion", + "Hexagon::ArchEnum::V62", "Hexagon HVX instructions", + [ExtensionHVXV60, + ExtensionHVXV62]>; +def ExtensionHVX64B + : SubtargetFeature<"hvx-length64b", "UseHVX64BOps", "true", + "Hexagon HVX 64B instructions", + [ExtensionHVXV60, ExtensionHVXV62]>; +def ExtensionHVX128B + : SubtargetFeature<"hvx-length128b", "UseHVX128BOps", "true", + "Hexagon HVX 128B instructions", + [ExtensionHVXV60, ExtensionHVXV62]>; + +// This is an alias to ExtensionHVX128B to accept the hvx-double as +// an acceptable subtarget feature. +def ExtensionHVXDbl + : SubtargetFeature<"hvx-double", "UseHVX128BOps", "true", + "Hexagon HVX 128B instructions", + [ExtensionHVXV60, ExtensionHVXV62]>; + def FeatureLongCalls: SubtargetFeature<"long-calls", "UseLongCalls", "true", "Use constant-extended calls">; @@ -38,14 +59,21 @@ def UseMEMOP : Predicate<"HST->useMemOps()">; def IEEERndNearV5T : Predicate<"HST->modeIEEERndNear()">; -def UseHVXDbl : Predicate<"HST->useHVXDblOps()">, - AssemblerPredicate<"ExtensionHVXDbl">; -def UseHVXSgl : Predicate<"HST->useHVXSglOps()">; -def UseHVX : Predicate<"HST->useHVXSglOps() ||HST->useHVXDblOps()">, - AssemblerPredicate<"ExtensionHVX">; - -def Hvx64 : HwMode<"+hvx,-hvx-double">; -def Hvx128 : HwMode<"+hvx,+hvx-double">; +def UseHVX64B : Predicate<"HST->useHVX64BOps()">, + AssemblerPredicate<"ExtensionHVX64B">; +def UseHVX128B : Predicate<"HST->useHVX128BOps()">, + AssemblerPredicate<"ExtensionHVX128B">; +def UseHVX : Predicate<"HST->useHVXOps()">, + AssemblerPredicate<"ExtensionHVXV60">; +def UseHVXV60 : Predicate<"HST->useHVXOps()">, + AssemblerPredicate<"ExtensionHVXV60">; +def UseHVXV62 : Predicate<"HST->useHVXOps()">, + AssemblerPredicate<"ExtensionHVXV62">; + +def Hvx64 : HwMode<"+hvx-length64b">; +def Hvx64old : HwMode<"-hvx-double">; +def Hvx128 : HwMode<"+hvx-length128b">; +def Hvx128old : HwMode<"+hvx-double">; //===----------------------------------------------------------------------===// // Classes used for relation maps. @@ -274,9 +302,9 @@ def : Proc<"hexagonv55", HexagonModelV55, [ArchV4, ArchV5, ArchV55]>; def : Proc<"hexagonv60", HexagonModelV60, - [ArchV4, ArchV5, ArchV55, ArchV60, ExtensionHVX]>; + [ArchV4, ArchV5, ArchV55, ArchV60]>; def : Proc<"hexagonv62", HexagonModelV62, - [ArchV4, ArchV5, ArchV55, ArchV60, ArchV62, ExtensionHVX]>; + [ArchV4, ArchV5, ArchV55, ArchV60, ArchV62]>; //===----------------------------------------------------------------------===// // Declare the target which we are implementing Index: lib/Target/Hexagon/HexagonISelLowering.cpp =================================================================== --- lib/Target/Hexagon/HexagonISelLowering.cpp +++ lib/Target/Hexagon/HexagonISelLowering.cpp @@ -357,7 +357,7 @@ auto &MF = State.getMachineFunction(); auto &HST = MF.getSubtarget(); - if (HST.useHVXSglOps() && + if (HST.useHVX64BOps() && (LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v32i16 || LocVT == MVT::v64i8 || LocVT == MVT::v512i1)) { if (unsigned Reg = State.AllocateReg(VecLstS)) { @@ -368,7 +368,7 @@ State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); return false; } - if (HST.useHVXSglOps() && (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || + if (HST.useHVX64BOps() && (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 || LocVT == MVT::v128i8)) { if (unsigned Reg = State.AllocateReg(VecLstD)) { State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); @@ -379,8 +379,8 @@ return false; } // 128B Mode - if (HST.useHVXDblOps() && (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 || - LocVT == MVT::v128i16 || LocVT == MVT::v256i8)) { + if (HST.useHVX128BOps() && (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 || + LocVT == MVT::v128i16 || LocVT == MVT::v256i8)) { if (unsigned Reg = State.AllocateReg(VecLstD)) { State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); return false; @@ -389,7 +389,7 @@ State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); return false; } - if (HST.useHVXDblOps() && + if (HST.useHVX128BOps() && (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 || LocVT == MVT::v128i8 || LocVT == MVT::v1024i1)) { if (unsigned Reg = State.AllocateReg(VecLstS)) { @@ -437,7 +437,7 @@ LocInfo = CCValAssign::Full; } else if (LocVT == MVT::v128i8 || LocVT == MVT::v64i16 || LocVT == MVT::v32i32 || LocVT == MVT::v16i64 || - (LocVT == MVT::v1024i1 && HST.useHVXDblOps())) { + (LocVT == MVT::v1024i1 && HST.useHVX128BOps())) { LocVT = MVT::v32i32; ValVT = MVT::v32i32; LocInfo = CCValAssign::Full; @@ -507,7 +507,7 @@ return false; } } else if (LocVT == MVT::v32i32) { - unsigned Req = HST.useHVXDblOps() ? Hexagon::V0 : Hexagon::W0; + unsigned Req = HST.useHVX128BOps() ? Hexagon::V0 : Hexagon::W0; if (unsigned Reg = State.AllocateReg(Req)) { State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); return false; @@ -827,9 +827,9 @@ DEBUG(dbgs() << "Function needs byte stack align due to call args\n"); // V6 vectors passed by value have 64 or 128 byte alignment depending // on whether we are 64 byte vector mode or 128 byte. - bool UseHVXDbl = Subtarget.useHVXDblOps(); + bool UseHVX128B = Subtarget.useHVX128BOps(); assert(Subtarget.useHVXOps()); - const unsigned ObjAlign = UseHVXDbl ? 128 : 64; + const unsigned ObjAlign = UseHVX128B ? 128 : 64; LargestAlignSeen = std::max(LargestAlignSeen, ObjAlign); MFI.ensureMaxAlignment(LargestAlignSeen); } @@ -940,15 +940,15 @@ auto &HST = static_cast(DAG.getSubtarget()); - bool ValidHVXDblType = - HST.useHVXDblOps() && (VT == MVT::v32i32 || VT == MVT::v16i64 || - VT == MVT::v64i16 || VT == MVT::v128i8); + bool ValidHVX128BType = + HST.useHVX128BOps() && (VT == MVT::v32i32 || VT == MVT::v16i64 || + VT == MVT::v64i16 || VT == MVT::v128i8); bool ValidHVXType = - HST.useHVXSglOps() && (VT == MVT::v16i32 || VT == MVT::v8i64 || + HST.useHVX64BOps() && (VT == MVT::v16i32 || VT == MVT::v8i64 || VT == MVT::v32i16 || VT == MVT::v64i8); - if (ValidHVXDblType || ValidHVXType || - VT == MVT::i64 || VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { + if (ValidHVX128BType || ValidHVXType || VT == MVT::i64 || VT == MVT::i32 || + VT == MVT::i16 || VT == MVT::i8) { IsInc = (Ptr->getOpcode() == ISD::ADD); Base = Ptr->getOperand(0); Offset = Ptr->getOperand(1); @@ -1182,7 +1182,7 @@ RegInfo.createVirtualRegister(&Hexagon::HvxVRRegClass); RegInfo.addLiveIn(VA.getLocReg(), VReg); InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); - } else if (Subtarget.useHVXDblOps() && + } else if (Subtarget.useHVX128BOps() && ((RegVT == MVT::v16i64 || RegVT == MVT::v32i32 || RegVT == MVT::v64i16 || RegVT == MVT::v128i8))) { unsigned VReg = @@ -1197,7 +1197,7 @@ RegInfo.createVirtualRegister(&Hexagon::HvxWRRegClass); RegInfo.addLiveIn(VA.getLocReg(), VReg); InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); - } else if (Subtarget.useHVXDblOps() && + } else if (Subtarget.useHVX128BOps() && ((RegVT == MVT::v32i64 || RegVT == MVT::v64i32 || RegVT == MVT::v128i16 || RegVT == MVT::v256i8))) { unsigned VReg = @@ -1743,7 +1743,7 @@ } if (Subtarget.hasV60TOps()) { - if (Subtarget.useHVXSglOps()) { + if (Subtarget.useHVX64BOps()) { addRegisterClass(MVT::v64i8, &Hexagon::HvxVRRegClass); addRegisterClass(MVT::v32i16, &Hexagon::HvxVRRegClass); addRegisterClass(MVT::v16i32, &Hexagon::HvxVRRegClass); @@ -1753,7 +1753,7 @@ addRegisterClass(MVT::v32i32, &Hexagon::HvxWRRegClass); addRegisterClass(MVT::v16i64, &Hexagon::HvxWRRegClass); addRegisterClass(MVT::v512i1, &Hexagon::HvxQRRegClass); - } else if (Subtarget.useHVXDblOps()) { + } else if (Subtarget.useHVX128BOps()) { addRegisterClass(MVT::v128i8, &Hexagon::HvxVRRegClass); addRegisterClass(MVT::v64i16, &Hexagon::HvxVRRegClass); addRegisterClass(MVT::v32i32, &Hexagon::HvxVRRegClass); @@ -1992,7 +1992,7 @@ setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom); if (Subtarget.useHVXOps()) { - if (Subtarget.useHVXSglOps()) { + if (Subtarget.useHVX64BOps()) { setOperationAction(ISD::CONCAT_VECTORS, MVT::v128i8, Custom); setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i16, Custom); setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i32, Custom); @@ -2004,7 +2004,7 @@ setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v64i8, Custom); setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v32i16, Custom); setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v16i32, Custom); - } else if (Subtarget.useHVXDblOps()) { + } else if (Subtarget.useHVX128BOps()) { setOperationAction(ISD::CONCAT_VECTORS, MVT::v256i8, Custom); setOperationAction(ISD::CONCAT_VECTORS, MVT::v128i16, Custom); setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i32, Custom); @@ -2082,13 +2082,13 @@ setIndexedStoreAction(ISD::POST_INC, VT, Legal); } - if (Subtarget.useHVXSglOps()) { + if (Subtarget.useHVX64BOps()) { for (MVT VT : {MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64, MVT::v128i8, MVT::v64i16, MVT::v32i32, MVT::v16i64}) { setIndexedLoadAction(ISD::POST_INC, VT, Legal); setIndexedStoreAction(ISD::POST_INC, VT, Legal); } - } else if (Subtarget.useHVXDblOps()) { + } else if (Subtarget.useHVX128BOps()) { for (MVT VT : {MVT::v128i8, MVT::v64i16, MVT::v32i32, MVT::v16i64, MVT::v256i8, MVT::v128i16, MVT::v64i32, MVT::v32i64}) { setIndexedLoadAction(ISD::POST_INC, VT, Legal); @@ -2353,8 +2353,8 @@ size_t MaskLen = Mask.size(); unsigned SizeInBits = VT.getScalarSizeInBits() * MaskLen; - if ((Subtarget.useHVXSglOps() && SizeInBits == 64 * 8) || - (Subtarget.useHVXDblOps() && SizeInBits == 128 * 8)) { + if ((Subtarget.useHVX64BOps() && SizeInBits == 64 * 8) || + (Subtarget.useHVX128BOps() && SizeInBits == 128 * 8)) { StridedLoadKind Pattern = isStridedLoad(Mask); if (Pattern == StridedLoadKind::NoPattern) return SDValue(); @@ -2617,11 +2617,11 @@ return DAG.getNode(HexagonISD::COMBINE, dl, VT, Op.getOperand(1), Vec0); if (UseHVX) { - assert((Width == 64*8 && Subtarget.useHVXSglOps()) || - (Width == 128*8 && Subtarget.useHVXDblOps())); + assert((Width == 64 * 8 && Subtarget.useHVX64BOps()) || + (Width == 128 * 8 && Subtarget.useHVX128BOps())); SDValue Vec1 = Op.getOperand(1); - MVT OpTy = Subtarget.useHVXSglOps() ? MVT::v16i32 : MVT::v32i32; - MVT ReTy = Subtarget.useHVXSglOps() ? MVT::v32i32 : MVT::v64i32; + MVT OpTy = Subtarget.useHVX64BOps() ? MVT::v16i32 : MVT::v32i32; + MVT ReTy = Subtarget.useHVX64BOps() ? MVT::v32i32 : MVT::v64i32; SDValue B0 = DAG.getNode(ISD::BITCAST, dl, OpTy, Vec0); SDValue B1 = DAG.getNode(ISD::BITCAST, dl, OpTy, Vec1); SDValue VC = DAG.getNode(HexagonISD::VCOMBINE, dl, ReTy, B1, B0); @@ -2667,7 +2667,7 @@ EVT VT = Op.getOperand(0).getValueType(); SDLoc dl(Op); bool UseHVX = Subtarget.useHVXOps(); - bool UseHVXSgl = Subtarget.useHVXSglOps(); + bool UseHVX64B = Subtarget.useHVX64BOps(); // Just in case... if (!VT.isVector() || !UseHVX) @@ -2675,7 +2675,7 @@ EVT ResVT = Op.getValueType(); unsigned ResSize = ResVT.getSizeInBits(); - unsigned VectorSizeInBits = UseHVXSgl ? (64 * 8) : (128 * 8); + unsigned VectorSizeInBits = UseHVX64B ? (64 * 8) : (128 * 8); unsigned OpSize = VT.getSizeInBits(); // We deal only with cases where the result is the vector size @@ -3001,7 +3001,7 @@ case 512: return std::make_pair(0U, &Hexagon::HvxVRRegClass); case 1024: - if (Subtarget.hasV60TOps() && Subtarget.useHVXDblOps()) + if (Subtarget.hasV60TOps() && Subtarget.useHVX128BOps()) return std::make_pair(0U, &Hexagon::HvxVRRegClass); return std::make_pair(0U, &Hexagon::HvxWRRegClass); case 2048: @@ -3204,7 +3204,7 @@ case MVT::v32i32: case MVT::v16i64: if (Subtarget.hasV60TOps() && Subtarget.useHVXOps() && - Subtarget.useHVXDblOps()) + Subtarget.useHVX128BOps()) RRC = &Hexagon::HvxVRRegClass; else RRC = &Hexagon::HvxWRRegClass; Index: lib/Target/Hexagon/HexagonPseudo.td =================================================================== --- lib/Target/Hexagon/HexagonPseudo.td +++ lib/Target/Hexagon/HexagonPseudo.td @@ -427,7 +427,7 @@ def PS_vloadrw_ai: LDrivv_template, Requires<[HasV60T,UseHVX]>; def PS_vloadrw_nt_ai: LDrivv_template, - Requires<[HasV60T,UseHVXSgl]>; + Requires<[HasV60T,UseHVX]>; def PS_vloadrwu_ai: LDrivv_template, Requires<[HasV60T,UseHVX]>; Index: lib/Target/Hexagon/HexagonRegisterInfo.td =================================================================== --- lib/Target/Hexagon/HexagonRegisterInfo.td +++ lib/Target/Hexagon/HexagonRegisterInfo.td @@ -216,25 +216,33 @@ // HVX types -def VecI1 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], - [v512i1, v1024i1, v512i1]>; -def VecI8 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], - [v64i8, v128i8, v64i8]>; -def VecI16 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], - [v32i16, v64i16, v32i16]>; -def VecI32 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], - [v16i32, v32i32, v16i32]>; -def VecI64 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], - [v8i64, v16i64, v8i64]>; -def VecPI8 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], - [v128i8, v256i8, v128i8]>; -def VecPI16 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], - [v64i16, v128i16, v64i16]>; -def VecPI32 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], - [v32i32, v64i32, v32i32]>; -def VecPI64 : ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], - [v16i64, v32i64, v16i64]>; - +def VecI1 + : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode], + [v512i1, v512i1, v1024i1, v1024i1, v512i1]>; +def VecI8 + : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode], + [v64i8, v64i8, v128i8, v128i8, v64i8]>; +def VecI16 + : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode], + [v32i16, v32i16, v64i16, v64i16, v32i16]>; +def VecI32 + : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode], + [v16i32, v16i32, v32i32, v32i32, v16i32]>; +def VecI64 + : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode], + [v8i64, v8i64, v16i64, v16i64, v8i64]>; +def VecPI8 + : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode], + [v128i8, v128i8, v256i8, v256i8, v128i8]>; +def VecPI16 + : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode], + [v64i16, v64i16, v128i16, v128i16, v64i16]>; +def VecPI32 + : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode], + [v32i32, v32i32, v64i32, v64i32, v32i32]>; +def VecPI64 + : ValueTypeByHwMode<[Hvx64, Hvx64old, Hvx128, Hvx128old, DefaultMode], + [v16i64, v16i64, v32i64, v32i64, v16i64]>; // Register classes. // Index: lib/Target/Hexagon/HexagonSubtarget.h =================================================================== --- lib/Target/Hexagon/HexagonSubtarget.h +++ lib/Target/Hexagon/HexagonSubtarget.h @@ -46,12 +46,13 @@ class HexagonSubtarget : public HexagonGenSubtargetInfo { virtual void anchor(); - bool UseMemOps, UseHVXOps, UseHVXDblOps; + bool UseMemOps, UseHVX64BOps, UseHVX128BOps; bool UseLongCalls; bool ModeIEEERndNear; public: Hexagon::ArchEnum HexagonArchVersion; + Hexagon::ArchEnum HexagonHVXVersion = Hexagon::ArchEnum::V4; /// True if the target should use Back-Skip-Back scheduling. This is the /// default for V60. bool UseBSBScheduling; @@ -138,9 +139,9 @@ } bool modeIEEERndNear() const { return ModeIEEERndNear; } - bool useHVXOps() const { return UseHVXOps; } - bool useHVXDblOps() const { return UseHVXOps && UseHVXDblOps; } - bool useHVXSglOps() const { return UseHVXOps && !UseHVXDblOps; } + bool useHVXOps() const { return HexagonHVXVersion > Hexagon::ArchEnum::V4; } + bool useHVX128BOps() const { return useHVXOps() && UseHVX128BOps; } + bool useHVX64BOps() const { return useHVXOps() && UseHVX64BOps; } bool useLongCalls() const { return UseLongCalls; } bool usePredicatedCalls() const; Index: lib/Target/Hexagon/HexagonSubtarget.cpp =================================================================== --- lib/Target/Hexagon/HexagonSubtarget.cpp +++ lib/Target/Hexagon/HexagonSubtarget.cpp @@ -53,14 +53,6 @@ static cl::opt EnableBSBSched("enable-bsb-sched", cl::Hidden, cl::ZeroOrMore, cl::init(true)); -static cl::opt EnableHexagonHVXDouble("enable-hexagon-hvx-double", - cl::Hidden, cl::ZeroOrMore, cl::init(false), - cl::desc("Enable Hexagon Double Vector eXtensions")); - -static cl::opt EnableHexagonHVX("enable-hexagon-hvx", - cl::Hidden, cl::ZeroOrMore, cl::init(false), - cl::desc("Enable Hexagon Vector eXtensions")); - static cl::opt EnableTCLatencySched("enable-tc-latency-sched", cl::Hidden, cl::ZeroOrMore, cl::init(false)); @@ -126,8 +118,8 @@ else llvm_unreachable("Unrecognized Hexagon processor version"); - UseHVXOps = false; - UseHVXDblOps = false; + UseHVX128BOps = false; + UseHVX64BOps = false; UseLongCalls = false; UseMemOps = DisableMemOps ? false : EnableMemOps; @@ -136,10 +128,6 @@ ParseSubtargetFeatures(CPUString, FS); - if (EnableHexagonHVX.getPosition()) - UseHVXOps = EnableHexagonHVX; - if (EnableHexagonHVXDouble.getPosition()) - UseHVXDblOps = EnableHexagonHVXDouble; if (OverrideLongCalls.getPosition()) UseLongCalls = OverrideLongCalls; Index: lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp =================================================================== --- lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp +++ lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp @@ -288,7 +288,7 @@ } MCSubtargetInfo *X = createHexagonMCSubtargetInfoImpl(TT, CPUName, ArchFS); - if (X->getFeatureBits()[Hexagon::ExtensionHVXDbl]) { + if (X->getFeatureBits()[Hexagon::ExtensionHVX128B]) { llvm::FeatureBitset Features = X->getFeatureBits(); X->setFeatureBits(Features.set(Hexagon::ExtensionHVX)); } Index: test/CodeGen/Hexagon/SUnit-boundary-prob.ll =================================================================== --- test/CodeGen/Hexagon/SUnit-boundary-prob.ll +++ test/CodeGen/Hexagon/SUnit-boundary-prob.ll @@ -187,7 +187,7 @@ } attributes #0 = { nounwind readnone } -attributes #1 = { "target-cpu"="hexagonv60" "target-features"="+hvx" } +attributes #1 = { "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } attributes #2 = { nounwind } !llvm.module.flags = !{!0} Index: test/CodeGen/Hexagon/bit-bitsplit-at.ll =================================================================== --- test/CodeGen/Hexagon/bit-bitsplit-at.ll +++ test/CodeGen/Hexagon/bit-bitsplit-at.ll @@ -30,4 +30,4 @@ ret i32 %v10 } -attributes #0 = { nounwind optsize "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" } +attributes #0 = { nounwind optsize "target-cpu"="hexagonv60" "target-features"="-hvxv60,-hvx-length128b,-long-calls" } Index: test/CodeGen/Hexagon/bit-bitsplit-src.ll =================================================================== --- test/CodeGen/Hexagon/bit-bitsplit-src.ll +++ test/CodeGen/Hexagon/bit-bitsplit-src.ll @@ -32,4 +32,4 @@ ; Function Attrs: nounwind declare void @printf(i8* nocapture readonly, ...) local_unnamed_addr #0 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-length128b,-long-calls" } Index: test/CodeGen/Hexagon/bit-bitsplit.ll =================================================================== --- test/CodeGen/Hexagon/bit-bitsplit.ll +++ test/CodeGen/Hexagon/bit-bitsplit.ll @@ -14,4 +14,4 @@ ret i32 %and2 } -attributes #0 = { norecurse nounwind readonly "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double" } +attributes #0 = { norecurse nounwind readonly "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-length128b" } Index: test/CodeGen/Hexagon/bit-ext-sat.ll =================================================================== --- test/CodeGen/Hexagon/bit-ext-sat.ll +++ test/CodeGen/Hexagon/bit-ext-sat.ll @@ -53,5 +53,5 @@ declare i32 @llvm.hexagon.A2.satub(i32) #1 declare i32 @llvm.hexagon.A2.satuh(i32) #1 -attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-length128b,-long-calls" } attributes #1 = { nounwind readnone } Index: test/CodeGen/Hexagon/bit-extract-off.ll =================================================================== --- test/CodeGen/Hexagon/bit-extract-off.ll +++ test/CodeGen/Hexagon/bit-extract-off.ll @@ -19,5 +19,5 @@ declare double @fabs(double) #1 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" } -attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-length128b,-long-calls" } +attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-length128b,-long-calls" } Index: test/CodeGen/Hexagon/bit-extract.ll =================================================================== --- test/CodeGen/Hexagon/bit-extract.ll +++ test/CodeGen/Hexagon/bit-extract.ll @@ -72,4 +72,4 @@ ret i32 %bf.ashr } -attributes #0 = { noinline norecurse nounwind readnone "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #0 = { noinline norecurse nounwind readnone "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-length128b,-long-calls" } Index: test/CodeGen/Hexagon/bit-has.ll =================================================================== --- test/CodeGen/Hexagon/bit-has.ll +++ test/CodeGen/Hexagon/bit-has.ll @@ -60,5 +60,5 @@ declare i32 @llvm.hexagon.A2.sath(i32) #1 -attributes #0 = { nounwind "target-cpu"="hexagonv5" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #0 = { nounwind "target-cpu"="hexagonv5" "target-features"="-hvx,-hvx-length128b,-long-calls" } attributes #1 = { nounwind readnone } Index: test/CodeGen/Hexagon/bit-loop-rc-mismatch.ll =================================================================== --- test/CodeGen/Hexagon/bit-loop-rc-mismatch.ll +++ test/CodeGen/Hexagon/bit-loop-rc-mismatch.ll @@ -24,7 +24,7 @@ declare hidden i64 @danny(i32*, i32* nocapture readonly dereferenceable(4)) #1 align 2 declare hidden i32 @sammy(i32* nocapture, i32) #0 align 2 -attributes #0 = { nounwind optsize "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { nounwind optsize readonly "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind optsize "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind optsize readonly "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #2 = { optsize } Index: test/CodeGen/Hexagon/bit-rie.ll =================================================================== --- test/CodeGen/Hexagon/bit-rie.ll +++ test/CodeGen/Hexagon/bit-rie.ll @@ -190,7 +190,7 @@ declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1 declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1 -attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { argmemonly nounwind } attributes #2 = { nounwind readnone } Index: test/CodeGen/Hexagon/bitconvert-vector.ll =================================================================== --- test/CodeGen/Hexagon/bitconvert-vector.ll +++ test/CodeGen/Hexagon/bitconvert-vector.ll @@ -24,4 +24,4 @@ attributes #0 = { nounwind readnone } -attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } +attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" } Index: test/CodeGen/Hexagon/build-vector-shuffle.ll =================================================================== --- test/CodeGen/Hexagon/build-vector-shuffle.ll +++ test/CodeGen/Hexagon/build-vector-shuffle.ll @@ -17,5 +17,5 @@ ; Function Attrs: nounwind readnone declare <16 x i32> @llvm.hexagon.V6.vshuffh(<16 x i32>) #1 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } attributes #1 = { nounwind readnone } Index: test/CodeGen/Hexagon/builtin-expect.ll =================================================================== --- test/CodeGen/Hexagon/builtin-expect.ll +++ test/CodeGen/Hexagon/builtin-expect.ll @@ -39,6 +39,6 @@ declare i32 @bar(i32) local_unnamed_addr #0 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double,-long-calls" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b,-long-calls" } !0 = !{!"branch_weights", i32 1, i32 2000} Index: test/CodeGen/Hexagon/cfgopt-fall-through.ll =================================================================== --- test/CodeGen/Hexagon/cfgopt-fall-through.ll +++ test/CodeGen/Hexagon/cfgopt-fall-through.ll @@ -68,4 +68,4 @@ unreachable } -attributes #0 = { nounwind "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #0 = { nounwind "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-length128b,-long-calls" } Index: test/CodeGen/Hexagon/cfi-offset.ll =================================================================== --- test/CodeGen/Hexagon/cfi-offset.ll +++ test/CodeGen/Hexagon/cfi-offset.ll @@ -39,5 +39,5 @@ declare void @__cxa_end_catch() -attributes #0 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-length128b" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind } Index: test/CodeGen/Hexagon/common-gep-inbounds.ll =================================================================== --- test/CodeGen/Hexagon/common-gep-inbounds.ll +++ test/CodeGen/Hexagon/common-gep-inbounds.ll @@ -17,4 +17,4 @@ ret i16 %a } -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-length128b,-long-calls" } Index: test/CodeGen/Hexagon/const-pool-tf.ll =================================================================== --- test/CodeGen/Hexagon/const-pool-tf.ll +++ test/CodeGen/Hexagon/const-pool-tf.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv60 -relocation-model pic < %s | FileCheck %s +; RUN: opt -relocation-model pic -march=hexagon -mcpu=hexagonv60 -O2 -S < %s | llc -march=hexagon -mcpu=hexagonv60 -relocation-model pic -; CHECK: @PCREL +; CHECK: jumpr target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" target triple = "hexagon-unknown--elf" Index: test/CodeGen/Hexagon/convert-to-dot-old.ll =================================================================== --- test/CodeGen/Hexagon/convert-to-dot-old.ll +++ test/CodeGen/Hexagon/convert-to-dot-old.ll @@ -103,8 +103,8 @@ declare i32 @llvm.hexagon.A2.aslh(i32) #2 declare void @foo(i16*, i32*, i16*, i16 signext, i16 signext, i16 signext) local_unnamed_addr #3 -attributes #0 = { nounwind optsize "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #0 = { nounwind optsize "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-length128b,-long-calls" } attributes #1 = { argmemonly nounwind } attributes #2 = { nounwind readnone } -attributes #3 = { optsize "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #3 = { optsize "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-length128b,-long-calls" } attributes #4 = { nounwind optsize } Index: test/CodeGen/Hexagon/convert_const_i1_to_i8.ll =================================================================== --- test/CodeGen/Hexagon/convert_const_i1_to_i8.ll +++ test/CodeGen/Hexagon/convert_const_i1_to_i8.ll @@ -14,4 +14,4 @@ declare <32 x i32> @llvm.hexagon.V6.vrdelta.128B(<32 x i32>, <32 x i32>) declare <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1>, <32 x i32>, <32 x i32>) -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" } Index: test/CodeGen/Hexagon/dead-store-stack.ll =================================================================== --- test/CodeGen/Hexagon/dead-store-stack.ll +++ test/CodeGen/Hexagon/dead-store-stack.ll @@ -1,4 +1,4 @@ -; RUN: llc -O2 -march=hexagon < %s | FileCheck %s +; RUN: llc -O2 -march=hexagon -mcpu=hexagonv62< %s | FileCheck %s ; CHECK: ParseFunc: ; CHECK: r[[ARG0:[0-9]+]] = memuh(r[[ARG1:[0-9]+]]+#[[OFFSET:[0-9]+]]) ; CHECK: memw(r[[ARG1]]+#[[OFFSET]]) = r[[ARG0]] @@ -126,6 +126,7 @@ ; Function Attrs: nounwind declare void @snprintf(i8* nocapture, i32, i8* nocapture readonly, ...) local_unnamed_addr #1 -attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "stack-protector-buffer-size"="8" "target-features"="+hvx" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "stack-protector-buffer-size"="8" "target-features"="+hvx" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv62" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv62" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #2 = { nounwind } + Index: test/CodeGen/Hexagon/early-if-merge-loop.ll =================================================================== --- test/CodeGen/Hexagon/early-if-merge-loop.ll +++ test/CodeGen/Hexagon/early-if-merge-loop.ll @@ -82,7 +82,7 @@ declare i64 @llvm.hexagon.A2.subp(i64, i64) #1 declare i64 @llvm.hexagon.A2.combinew(i32, i32) #1 -attributes #0 = { nounwind readonly "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #0 = { nounwind readonly "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-length128b,-long-calls" } attributes #1 = { nounwind readnone } !0 = !{!1, !1, i64 0} Index: test/CodeGen/Hexagon/early-if-vecpi.ll =================================================================== --- test/CodeGen/Hexagon/early-if-vecpi.ll +++ test/CodeGen/Hexagon/early-if-vecpi.ll @@ -66,4 +66,4 @@ ret void } -attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } +attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } Index: test/CodeGen/Hexagon/early-if-vecpred.ll =================================================================== --- test/CodeGen/Hexagon/early-if-vecpred.ll +++ test/CodeGen/Hexagon/early-if-vecpred.ll @@ -31,7 +31,7 @@ declare <1024 x i1> @llvm.hexagon.V6.pred.scalar2.128B(i32) #1 declare <1024 x i1> @llvm.hexagon.V6.pred.not.128B(<1024 x i1>) #1 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" } attributes #1 = { nounwind readnone } attributes #2 = { nounwind } Index: test/CodeGen/Hexagon/eliminate-pred-spill.ll =================================================================== --- test/CodeGen/Hexagon/eliminate-pred-spill.ll +++ test/CodeGen/Hexagon/eliminate-pred-spill.ll @@ -139,5 +139,5 @@ declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #1 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" } attributes #1 = { nounwind readnone } Index: test/CodeGen/Hexagon/expand-condsets-dead-bad.ll =================================================================== --- test/CodeGen/Hexagon/expand-condsets-dead-bad.ll +++ test/CodeGen/Hexagon/expand-condsets-dead-bad.ll @@ -51,4 +51,4 @@ ret void } -attributes #0 = { nounwind "target-cpu"="hexagonv5" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #0 = { nounwind "target-cpu"="hexagonv5" "target-features"="-hvx,-hvx-length128b,-long-calls" } Index: test/CodeGen/Hexagon/expand-condsets-dead-pred.ll =================================================================== --- test/CodeGen/Hexagon/expand-condsets-dead-pred.ll +++ test/CodeGen/Hexagon/expand-condsets-dead-pred.ll @@ -42,4 +42,4 @@ br label %b1 } -attributes #0 = { nounwind "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #0 = { nounwind "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-length128b,-long-calls" } Index: test/CodeGen/Hexagon/expand-vselect-kill.ll =================================================================== --- test/CodeGen/Hexagon/expand-vselect-kill.ll +++ test/CodeGen/Hexagon/expand-vselect-kill.ll @@ -48,6 +48,6 @@ declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #2 declare <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32>, <32 x i32>, i32) #2 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" } -attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } +attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" } attributes #2 = { nounwind readnone } Index: test/CodeGen/Hexagon/expand-vstorerw-undef.ll =================================================================== --- test/CodeGen/Hexagon/expand-vstorerw-undef.ll +++ test/CodeGen/Hexagon/expand-vstorerw-undef.ll @@ -91,5 +91,5 @@ attributes #0 = { nounwind } attributes #1 = { nounwind readnone } -attributes #2 = { nounwind "reciprocal-estimates"="none" "target-cpu"="hexagonv60" "target-features"="+hvx-double" } +attributes #2 = { nounwind "reciprocal-estimates"="none" "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" } attributes #3 = { nobuiltin nounwind } Index: test/CodeGen/Hexagon/expand-vstorerw-undef2.ll =================================================================== --- test/CodeGen/Hexagon/expand-vstorerw-undef2.ll +++ test/CodeGen/Hexagon/expand-vstorerw-undef2.ll @@ -210,7 +210,7 @@ br i1 %v146, label %b33, label %b34 } -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" } attributes #1 = { nounwind readnone } attributes #2 = { nounwind } attributes #3 = { nobuiltin nounwind } Index: test/CodeGen/Hexagon/find-loop-instr.ll =================================================================== --- test/CodeGen/Hexagon/find-loop-instr.ll +++ test/CodeGen/Hexagon/find-loop-instr.ll @@ -76,4 +76,4 @@ br i1 %v23, label %b13, label %b10 } -attributes #0 = { norecurse "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #0 = { norecurse "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-length128b,-long-calls" } Index: test/CodeGen/Hexagon/fminmax.ll =================================================================== --- test/CodeGen/Hexagon/fminmax.ll +++ test/CodeGen/Hexagon/fminmax.ll @@ -22,6 +22,6 @@ declare float @fminf(float, float) #0 declare float @fmaxf(float, float) #0 -attributes #0 = { nounwind readnone "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind readnone "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind readnone } Index: test/CodeGen/Hexagon/frame-offset-overflow.ll =================================================================== --- test/CodeGen/Hexagon/frame-offset-overflow.ll +++ test/CodeGen/Hexagon/frame-offset-overflow.ll @@ -156,7 +156,7 @@ declare <32 x i32> @llvm.hexagon.V6.vmpyhsat.acc(<32 x i32>, <16 x i32>, i32) #0 attributes #0 = { nounwind readnone } -attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } +attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } !1 = !{!2, !2, i64 0} !2 = !{!"omnipotent char", !3, i64 0} Index: test/CodeGen/Hexagon/hasfp-crash1.ll =================================================================== --- test/CodeGen/Hexagon/hasfp-crash1.ll +++ test/CodeGen/Hexagon/hasfp-crash1.ll @@ -18,7 +18,7 @@ ; Function Attrs: nounwind readnone speculatable declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1 -attributes #0 = { nounwind "disable-tail-calls"="true" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv5" "target-features"="-hvx-double,-long-calls" } +attributes #0 = { nounwind "disable-tail-calls"="true" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv5" "target-features"="-hvx,-hvx-length128b,-long-calls" } attributes #1 = { nounwind readnone speculatable } !llvm.dbg.cu = !{!0} Index: test/CodeGen/Hexagon/hasfp-crash2.ll =================================================================== --- test/CodeGen/Hexagon/hasfp-crash2.ll +++ test/CodeGen/Hexagon/hasfp-crash2.ll @@ -19,7 +19,7 @@ ; Function Attrs: nounwind readnone speculatable declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1 -attributes #0 = { nounwind "disable-tail-calls"="true" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv5" "target-features"="-hvx-double,-long-calls" } +attributes #0 = { nounwind "disable-tail-calls"="true" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv5" "target-features"=",-hvx,-hvx-length128b,-long-calls" } attributes #1 = { nounwind readnone speculatable } !llvm.dbg.cu = !{!0} Index: test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse.ll =================================================================== --- test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse.ll +++ test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse.ll @@ -73,7 +73,7 @@ ; Function Attrs: nounwind readnone declare <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32>, <32 x i32>, i32) #1 -attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind readnone } !llvm.ident = !{!0} Index: test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse_constant.ll =================================================================== --- test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse_constant.ll +++ test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse_constant.ll @@ -73,7 +73,7 @@ ; Function Attrs: nounwind readnone declare <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32>, <32 x i32>, i32) #1 -attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind readnone } !llvm.ident = !{!0} Index: test/CodeGen/Hexagon/hvx-nontemporal.ll =================================================================== --- test/CodeGen/Hexagon/hvx-nontemporal.ll +++ test/CodeGen/Hexagon/hvx-nontemporal.ll @@ -20,7 +20,7 @@ ret void } -attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } +attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" } !1 = !{!2, !2, i64 0} !2 = !{!"omnipotent char", !3, i64 0} Index: test/CodeGen/Hexagon/hwloop-noreturn-call.ll =================================================================== --- test/CodeGen/Hexagon/hwloop-noreturn-call.ll +++ test/CodeGen/Hexagon/hwloop-noreturn-call.ll @@ -58,6 +58,6 @@ declare void @trap() #1 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" } attributes #1 = { nounwind noreturn } Index: test/CodeGen/Hexagon/hwloop-preh.ll =================================================================== --- test/CodeGen/Hexagon/hwloop-preh.ll +++ test/CodeGen/Hexagon/hwloop-preh.ll @@ -41,4 +41,4 @@ !1 = !{!"omnipotent char", !2} !2 = !{!"Simple C/C++ TBAA"} -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-length128b" } Index: test/CodeGen/Hexagon/inline-asm-qv.ll =================================================================== --- test/CodeGen/Hexagon/inline-asm-qv.ll +++ test/CodeGen/Hexagon/inline-asm-qv.ll @@ -15,5 +15,5 @@ ret void } -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } attributes #1 = { nounwind readnone } Index: test/CodeGen/Hexagon/inline-asm-vecpred128.ll =================================================================== --- test/CodeGen/Hexagon/inline-asm-vecpred128.ll +++ test/CodeGen/Hexagon/inline-asm-vecpred128.ll @@ -12,4 +12,4 @@ ret void } -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" } Index: test/CodeGen/Hexagon/intrinsics/byte-store-double.ll =================================================================== --- test/CodeGen/Hexagon/intrinsics/byte-store-double.ll +++ test/CodeGen/Hexagon/intrinsics/byte-store-double.ll @@ -1,4 +1,4 @@ -; RUN: llc -mattr=+hvx-double -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mattr=+hvxv60,hvx-length128b -march=hexagon -O2 < %s | FileCheck %s ; CHECK-LABEL: V6_vmaskedstoreq_128B ; CHECK: if (q{{[0-3]+}}) vmem(r{{[0-9]+}}+#0) = v{{[0-9]+}} Index: test/CodeGen/Hexagon/intrinsics/byte-store.ll =================================================================== --- test/CodeGen/Hexagon/intrinsics/byte-store.ll +++ test/CodeGen/Hexagon/intrinsics/byte-store.ll @@ -1,4 +1,4 @@ -; RUN: llc -mattr=+hvx -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mattr=+hvxv60,hvx-length64b -march=hexagon -O2 < %s | FileCheck %s ; CHECK-LABEL: V6_vmaskedstoreq ; CHECK: if (q{{[0-3]+}}) vmem(r{{[0-9]+}}+#0) = v{{[0-9]+}} Index: test/CodeGen/Hexagon/intrinsics/system_user.ll =================================================================== --- test/CodeGen/Hexagon/intrinsics/system_user.ll +++ test/CodeGen/Hexagon/intrinsics/system_user.ll @@ -65,7 +65,7 @@ declare void @llvm.hexagon.Y4.l2fetch(i8* nocapture readonly, i32) #2 declare void @llvm.hexagon.Y5.l2fetch(i8* nocapture readonly, i64) #2 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-length128b,-long-calls" } attributes #1 = { inaccessiblemem_or_argmemonly nounwind } attributes #2 = { nounwind } attributes #3 = { argmemonly nounwind writeonly } Index: test/CodeGen/Hexagon/jt-in-text.ll =================================================================== --- test/CodeGen/Hexagon/jt-in-text.ll +++ test/CodeGen/Hexagon/jt-in-text.ll @@ -54,4 +54,4 @@ ret void } -attributes #0 = { noinline nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { noinline nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-length128b,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } Index: test/CodeGen/Hexagon/loop-idiom/pmpy-infinite-loop.ll =================================================================== --- test/CodeGen/Hexagon/loop-idiom/pmpy-infinite-loop.ll +++ test/CodeGen/Hexagon/loop-idiom/pmpy-infinite-loop.ll @@ -80,4 +80,4 @@ br label %for.body405 } -attributes #0 = { noinline nounwind "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" } +attributes #0 = { noinline nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-length128b,-long-calls" } Index: test/CodeGen/Hexagon/loop-idiom/pmpy-mod.ll =================================================================== --- test/CodeGen/Hexagon/loop-idiom/pmpy-mod.ll +++ test/CodeGen/Hexagon/loop-idiom/pmpy-mod.ll @@ -81,4 +81,4 @@ ret i16 %v5 } -attributes #0 = { noinline nounwind "target-cpu"="hexagonv5" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #0 = { noinline nounwind "target-cpu"="hexagonv5" "target-features"="-hvx,-hvx-length128b,-long-calls" } Index: test/CodeGen/Hexagon/loop-prefetch.ll =================================================================== --- test/CodeGen/Hexagon/loop-prefetch.ll +++ test/CodeGen/Hexagon/loop-prefetch.ll @@ -24,4 +24,4 @@ ret void } -attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double" } +attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-length128b" } Index: test/CodeGen/Hexagon/lower-extract-subvector.ll =================================================================== --- test/CodeGen/Hexagon/lower-extract-subvector.ll +++ test/CodeGen/Hexagon/lower-extract-subvector.ll @@ -43,5 +43,5 @@ ; Function Attrs: nounwind readnone declare <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32>, <32 x i32>, i32) #1 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } -attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" } +attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" } Index: test/CodeGen/Hexagon/memops-stack.ll =================================================================== --- test/CodeGen/Hexagon/memops-stack.ll +++ test/CodeGen/Hexagon/memops-stack.ll @@ -136,9 +136,9 @@ declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1 declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1 -attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { argmemonly nounwind } -attributes #2 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #2 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #3 = { nounwind } !1 = !{!2, !2, i64 0} Index: test/CodeGen/Hexagon/misaligned_double_vector_store_not_fast.ll =================================================================== --- test/CodeGen/Hexagon/misaligned_double_vector_store_not_fast.ll +++ test/CodeGen/Hexagon/misaligned_double_vector_store_not_fast.ll @@ -42,6 +42,6 @@ declare <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32>, <32 x i32>, i32) #1 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } -attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" } +attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" } Index: test/CodeGen/Hexagon/multi-cycle.ll =================================================================== --- test/CodeGen/Hexagon/multi-cycle.ll +++ test/CodeGen/Hexagon/multi-cycle.ll @@ -95,7 +95,7 @@ declare <16 x i32> @llvm.hexagon.V6.vabsdiffh(<16 x i32>, <16 x i32>) #1 declare <16 x i32> @llvm.hexagon.V6.vabsh(<16 x i32>) #1 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } attributes #1 = { nounwind readnone } !1 = !{!2, !2, i64 0} Index: test/CodeGen/Hexagon/newify-crash.ll =================================================================== --- test/CodeGen/Hexagon/newify-crash.ll +++ test/CodeGen/Hexagon/newify-crash.ll @@ -40,5 +40,5 @@ declare <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32>, <32 x i32>) #1 declare void @f0() #0 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" } attributes #1 = { nounwind readnone } Index: test/CodeGen/Hexagon/newvaluejump3.ll =================================================================== --- test/CodeGen/Hexagon/newvaluejump3.ll +++ test/CodeGen/Hexagon/newvaluejump3.ll @@ -74,6 +74,6 @@ } attributes #0 = { argmemonly nounwind } -attributes #1 = { nounwind readonly "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double,-long-calls" } -attributes #2 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double,-long-calls" } +attributes #1 = { nounwind readonly "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b,-long-calls" } +attributes #2 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b,-long-calls" } Index: test/CodeGen/Hexagon/peephole-kill-flags.ll =================================================================== --- test/CodeGen/Hexagon/peephole-kill-flags.ll +++ test/CodeGen/Hexagon/peephole-kill-flags.ll @@ -23,5 +23,5 @@ ret void } -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" } Index: test/CodeGen/Hexagon/plt-rel.ll =================================================================== --- test/CodeGen/Hexagon/plt-rel.ll +++ test/CodeGen/Hexagon/plt-rel.ll @@ -34,4 +34,4 @@ ret i1 %.sink } -attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" } +attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } Index: test/CodeGen/Hexagon/post-inc-aa-metadata.ll =================================================================== --- test/CodeGen/Hexagon/post-inc-aa-metadata.ll +++ test/CodeGen/Hexagon/post-inc-aa-metadata.ll @@ -29,7 +29,7 @@ ret void } -attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } +attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" } !1 = !{!2, !2, i64 0} Index: test/CodeGen/Hexagon/propagate-vcombine.ll =================================================================== --- test/CodeGen/Hexagon/propagate-vcombine.ll +++ test/CodeGen/Hexagon/propagate-vcombine.ll @@ -42,7 +42,7 @@ declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #3 declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #3 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" } -attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } -attributes #2 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx" } -attributes #3 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } +attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" } +attributes #2 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } +attributes #3 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" } Index: test/CodeGen/Hexagon/rdf-def-mask.ll =================================================================== --- test/CodeGen/Hexagon/rdf-def-mask.ll +++ test/CodeGen/Hexagon/rdf-def-mask.ll @@ -48,5 +48,5 @@ declare i32 @llvm.hexagon.S2.asl.r.r(i32, i32) #1 declare i32 @llvm.hexagon.M2.mpyu.nac.ll.s0(i32, i32, i32) #1 -attributes #0 = { nounwind readnone "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #0 = { nounwind readnone "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-length128b,-long-calls" } attributes #1 = { nounwind readnone } Index: test/CodeGen/Hexagon/rdf-inline-asm-fixed.ll =================================================================== --- test/CodeGen/Hexagon/rdf-inline-asm-fixed.ll +++ test/CodeGen/Hexagon/rdf-inline-asm-fixed.ll @@ -26,7 +26,7 @@ ; Function Attrs: argmemonly nounwind declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1 -attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv5" "target-features"="-hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv5" "target-features"="-hvx,-hvx-length128b" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { argmemonly nounwind } attributes #2 = { nounwind } Index: test/CodeGen/Hexagon/rdf-inline-asm.ll =================================================================== --- test/CodeGen/Hexagon/rdf-inline-asm.ll +++ test/CodeGen/Hexagon/rdf-inline-asm.ll @@ -24,7 +24,7 @@ ret i32 %retval1.0 } -attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind } !1 = !{i32 155} Index: test/CodeGen/Hexagon/reg-scavengebug-3.ll =================================================================== --- test/CodeGen/Hexagon/reg-scavengebug-3.ll +++ test/CodeGen/Hexagon/reg-scavengebug-3.ll @@ -1,4 +1,4 @@ -; RUN: llc -O0 -march=hexagon -mcpu=hexagonv60 < %s | FileCheck %s +; RUN: llc -O0 -march=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b < %s | FileCheck %s ; CHECK: vmem Index: test/CodeGen/Hexagon/reg-scavenger-valid-slot.ll =================================================================== --- test/CodeGen/Hexagon/reg-scavenger-valid-slot.ll +++ test/CodeGen/Hexagon/reg-scavenger-valid-slot.ll @@ -95,6 +95,6 @@ ret void } -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } attributes #1 = { nounwind readnone } attributes #2 = { nounwind } Index: test/CodeGen/Hexagon/regalloc-bad-undef.mir =================================================================== --- test/CodeGen/Hexagon/regalloc-bad-undef.mir +++ test/CodeGen/Hexagon/regalloc-bad-undef.mir @@ -58,7 +58,7 @@ declare i32 @lrand48() #0 declare i64 @llvm.hexagon.S2.extractup(i64, i32, i32) #1 - attributes #0 = { nounwind optsize "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-double" } + attributes #0 = { nounwind optsize "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-length128b" } attributes #1 = { nounwind readnone } ... Index: test/CodeGen/Hexagon/regalloc-block-overlap.ll =================================================================== --- test/CodeGen/Hexagon/regalloc-block-overlap.ll +++ test/CodeGen/Hexagon/regalloc-block-overlap.ll @@ -138,6 +138,6 @@ br label %b39 } -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" } attributes #1 = { nounwind readnone } attributes #2 = { nounwind } Index: test/CodeGen/Hexagon/select-instr-align.ll =================================================================== --- test/CodeGen/Hexagon/select-instr-align.ll +++ test/CodeGen/Hexagon/select-instr-align.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-hexagon-hvx < %s | FileCheck %s +; RUN: llc -march=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b < %s | FileCheck %s ; CHECK-LABEL: aligned_load: ; CHECK: = vmem({{.*}}) ; CHECK-LABEL: aligned_store: Index: test/CodeGen/Hexagon/stack-align-reset.ll =================================================================== --- test/CodeGen/Hexagon/stack-align-reset.ll +++ test/CodeGen/Hexagon/stack-align-reset.ll @@ -47,5 +47,5 @@ declare i32 @llvm.hexagon.V6.extractw(<16 x i32>, i32) #1 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } attributes #1 = { nounwind readnone } Index: test/CodeGen/Hexagon/store-shift.ll =================================================================== --- test/CodeGen/Hexagon/store-shift.ll +++ test/CodeGen/Hexagon/store-shift.ll @@ -42,7 +42,7 @@ ret void } -attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } +attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" } !1 = !{!2, !2, i64 0} !2 = !{!"int", !3, i64 0} Index: test/CodeGen/Hexagon/switch-lut-explicit-section.ll =================================================================== --- test/CodeGen/Hexagon/switch-lut-explicit-section.ll +++ test/CodeGen/Hexagon/switch-lut-explicit-section.ll @@ -29,4 +29,4 @@ ret i32 19 } -attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-length128b,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } Index: test/CodeGen/Hexagon/switch-lut-function-section.ll =================================================================== --- test/CodeGen/Hexagon/switch-lut-function-section.ll +++ test/CodeGen/Hexagon/switch-lut-function-section.ll @@ -27,4 +27,4 @@ ret i32 19 } -attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-length128b,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } Index: test/CodeGen/Hexagon/switch-lut-multiple-functions.ll =================================================================== --- test/CodeGen/Hexagon/switch-lut-multiple-functions.ll +++ test/CodeGen/Hexagon/switch-lut-multiple-functions.ll @@ -39,4 +39,4 @@ ret i32 19 } -attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-length128b,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } Index: test/CodeGen/Hexagon/switch-lut-text-section.ll =================================================================== --- test/CodeGen/Hexagon/switch-lut-text-section.ll +++ test/CodeGen/Hexagon/switch-lut-text-section.ll @@ -24,4 +24,4 @@ ret i32 19 } -attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-length128b,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } Index: test/CodeGen/Hexagon/undo-dag-shift.ll =================================================================== --- test/CodeGen/Hexagon/undo-dag-shift.ll +++ test/CodeGen/Hexagon/undo-dag-shift.ll @@ -54,6 +54,6 @@ ret void } -attributes #0 = { norecurse nounwind readonly "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" } -attributes #1 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #0 = { norecurse nounwind readonly "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-length128b,-long-calls" } +attributes #1 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-length128b,-long-calls" } Index: test/CodeGen/Hexagon/v60-cur.ll =================================================================== --- test/CodeGen/Hexagon/v60-cur.ll +++ test/CodeGen/Hexagon/v60-cur.ll @@ -54,7 +54,7 @@ declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1 declare <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32>, <16 x i32>) #1 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } attributes #1 = { nounwind readnone } !1 = !{!2, !2, i64 0} Index: test/CodeGen/Hexagon/v60-vsel1.ll =================================================================== --- test/CodeGen/Hexagon/v60-vsel1.ll +++ test/CodeGen/Hexagon/v60-vsel1.ll @@ -65,5 +65,5 @@ declare <16 x i32> @llvm.hexagon.V6.vnot(<16 x i32>) #1 declare <16 x i32> @llvm.hexagon.V6.vand(<16 x i32>, <16 x i32>) #1 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } attributes #1 = { nounwind readnone } Index: test/CodeGen/Hexagon/v60Intrins.ll =================================================================== --- test/CodeGen/Hexagon/v60Intrins.ll +++ test/CodeGen/Hexagon/v60Intrins.ll @@ -2555,5 +2555,5 @@ ; Function Attrs: nounwind readnone declare <32 x i32> @llvm.hexagon.V6.vunpackoh(<32 x i32>, <16 x i32>) #1 -attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind readnone } Index: test/CodeGen/Hexagon/v60Vasr.ll =================================================================== --- test/CodeGen/Hexagon/v60Vasr.ll +++ test/CodeGen/Hexagon/v60Vasr.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 -mcpu=hexagonv60 < %s | FileCheck %s +; RUN: llc -march=hexagon -O2 -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b < %s | FileCheck %s ; CHECK: vasr(v{{[0-9]+}}.h,v{{[0-9]+}}.h,r{{[0-7]+}}):sat Index: test/CodeGen/Hexagon/v60small.ll =================================================================== --- test/CodeGen/Hexagon/v60small.ll +++ test/CodeGen/Hexagon/v60small.ll @@ -47,5 +47,5 @@ ; Function Attrs: nounwind readnone declare <512 x i1> @llvm.hexagon.V6.pred.and.n(<512 x i1>, <512 x i1>) #1 -attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind readnone } Index: test/CodeGen/Hexagon/v6vec-vprint.ll =================================================================== --- test/CodeGen/Hexagon/v6vec-vprint.ll +++ test/CodeGen/Hexagon/v6vec-vprint.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv60 -enable-hexagon-hvx -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print < %s | FileCheck %s -; RUN: llc -march=hexagon -mcpu=hexagonv60 -enable-hexagon-hvx -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print -trace-hex-vector-stores-only < %s | FileCheck --check-prefix=VSTPRINT %s +; RUN: llc -march=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print < %s | FileCheck --check-prefix=CHECK %s +; RUN: llc -march=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print -trace-hex-vector-stores-only < %s | FileCheck --check-prefix=VSTPRINT %s ; generate .long XXXX which is a vector debug print instruction. ; CHECK: .long 0x1dffe0 ; CHECK: .long 0x1dffe0 Index: test/CodeGen/Hexagon/vassign-to-combine.ll =================================================================== --- test/CodeGen/Hexagon/vassign-to-combine.ll +++ test/CodeGen/Hexagon/vassign-to-combine.ll @@ -52,5 +52,5 @@ } attributes #0 = { nounwind readnone } -attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } +attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" } Index: test/CodeGen/Hexagon/vdmpy-halide-test.ll =================================================================== --- test/CodeGen/Hexagon/vdmpy-halide-test.ll +++ test/CodeGen/Hexagon/vdmpy-halide-test.ll @@ -155,8 +155,8 @@ ; Function Attrs: nounwind readnone declare <16 x i32> @llvm.hexagon.V6.vdmpyhvsat(<16 x i32>, <16 x i32>) #1 -attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } -attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } +attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } +attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } !5 = !{!6, !6, i64 0} !6 = !{!"inputOne", !7} Index: test/CodeGen/Hexagon/vec-pred-spill1.ll =================================================================== --- test/CodeGen/Hexagon/vec-pred-spill1.ll +++ test/CodeGen/Hexagon/vec-pred-spill1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv60 -O2 -enable-hexagon-hvx < %s | FileCheck %s +; RUN: llc -march=hexagon -mcpu=hexagonv60 -O2 -mattr=+hvxv60,hvx-length64b < %s | FileCheck %s ; CHECK: vmem(r{{[0-9]+}}+#3) = v{{[0-9]+}} ; CHECK: call puts Index: test/CodeGen/Hexagon/vec-vararg-align.ll =================================================================== --- test/CodeGen/Hexagon/vec-vararg-align.ll +++ test/CodeGen/Hexagon/vec-vararg-align.ll @@ -27,4 +27,4 @@ declare i32 @printf(i8*, ...) #0 declare void @VarVec1(i8*, i32, ...) #0 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } Index: test/CodeGen/Hexagon/vector-align.ll =================================================================== --- test/CodeGen/Hexagon/vector-align.ll +++ test/CodeGen/Hexagon/vector-align.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv60 -enable-hexagon-hvx < %s \ +; RUN: llc -march=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b < %s \ ; RUN: | FileCheck %s ; Check that the store to Q6VecPredResult does not get expanded into multiple Index: test/CodeGen/Hexagon/vload-postinc-sel.ll =================================================================== --- test/CodeGen/Hexagon/vload-postinc-sel.ll +++ test/CodeGen/Hexagon/vload-postinc-sel.ll @@ -49,4 +49,4 @@ declare <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32>, <32 x i32>, i32) #0 attributes #0 = { nounwind readnone } -attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } +attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" } Index: test/CodeGen/Hexagon/vmpa-halide-test.ll =================================================================== --- test/CodeGen/Hexagon/vmpa-halide-test.ll +++ test/CodeGen/Hexagon/vmpa-halide-test.ll @@ -133,8 +133,8 @@ ; Function Attrs: nounwind readnone declare <32 x i32> @llvm.hexagon.V6.vmpabuuv(<32 x i32>, <32 x i32>) #1 -attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } -attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } +attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } +attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } !5 = !{!6, !6, i64 0} !6 = !{!"inputOne", !7} Index: test/CodeGen/Hexagon/vpack_eo.ll =================================================================== --- test/CodeGen/Hexagon/vpack_eo.ll +++ test/CodeGen/Hexagon/vpack_eo.ll @@ -61,8 +61,8 @@ ; Function Attrs: nounwind readnone declare <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32>, <16 x i32>) #1 -attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } -attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } +attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } +attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } !4 = !{!5, !5, i64 0} !5 = !{!"InputOne", !6} Index: test/CodeGen/Hexagon/vselect-pseudo.ll =================================================================== --- test/CodeGen/Hexagon/vselect-pseudo.ll +++ test/CodeGen/Hexagon/vselect-pseudo.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -march=hexagon -mattr="+hvxv60,+hvx-length64b" < %s ; REQUIRES: asserts target triple = "hexagon" Index: test/MC/Hexagon/align.s =================================================================== --- test/MC/Hexagon/align.s +++ test/MC/Hexagon/align.s @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple=hexagon -filetype=obj %s | llvm-objdump -d - | FileCheck %s +# RUN: llvm-mc -triple=hexagon -filetype=obj -mhvx %s | llvm-objdump -mhvx -d - | FileCheck %s # Verify that the .align directive emits the proper insn packets. Index: test/MC/Hexagon/double-vector-producer.s =================================================================== --- test/MC/Hexagon/double-vector-producer.s +++ test/MC/Hexagon/double-vector-producer.s @@ -1,4 +1,4 @@ -# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv60 -filetype=obj %s | llvm-objdump -d - | FileCheck %s +# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv60 -mhvx -filetype=obj %s | llvm-objdump -d - | FileCheck %s { v1:0 = vshuff(v1,v0,r7) v2.w = vadd(v13.w,v15.w) Index: test/MC/Hexagon/test.s =================================================================== --- test/MC/Hexagon/test.s +++ test/MC/Hexagon/test.s @@ -1,4 +1,4 @@ -#RUN: llvm-mc -filetype=obj -triple=hexagon -mcpu=hexagonv60 %s +#RUN: llvm-mc -filetype=obj -triple=hexagon -mcpu=hexagonv60 -mhvx %s { vmem (r0 + #0) = v0 - r0 = memw(r0) } \ No newline at end of file + r0 = memw(r0) } Index: test/MC/Hexagon/v60-alu.s =================================================================== --- test/MC/Hexagon/v60-alu.s +++ test/MC/Hexagon/v60-alu.s @@ -1,5 +1,5 @@ -#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj %s | \ -#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -d - | \ +#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \ +#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -mhvx -d - | \ #RUN: FileCheck %s #CHECK: 1ce2cbd7 { v23.w = vavg(v11.w,{{ *}}v2.w):rnd } Index: test/MC/Hexagon/v60-misc.s =================================================================== --- test/MC/Hexagon/v60-misc.s +++ test/MC/Hexagon/v60-misc.s @@ -1,4 +1,4 @@ -# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv60 -mattr=+hvx -filetype=obj %s | llvm-objdump -arch=hexagon -mcpu=hexagonv60 -d - | FileCheck %s +# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv60 -mattr=+hvx -filetype=obj %s | llvm-objdump -arch=hexagon -mcpu=hexagonv60 -mhvx -d - | FileCheck %s .L0: Index: test/MC/Hexagon/v60-permute.s =================================================================== --- test/MC/Hexagon/v60-permute.s +++ test/MC/Hexagon/v60-permute.s @@ -1,5 +1,5 @@ -#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj %s | \ -#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -d - | \ +#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \ +#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -mhvx -d - | \ #RUN: FileCheck %s #CHECK: 1fd2d5cf { v15.b = vpack(v21.h{{ *}},{{ *}}v18.h):sat } Index: test/MC/Hexagon/v60-shift.s =================================================================== --- test/MC/Hexagon/v60-shift.s +++ test/MC/Hexagon/v60-shift.s @@ -1,5 +1,5 @@ -#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj %s | \ -#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -d - | \ +#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \ +#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -mhvx -d - | \ #RUN: FileCheck %s #CHECK: 198fd829 { v9.uw = vlsr(v24.uw,{{ *}}r15) } Index: test/MC/Hexagon/v60-vcmp.s =================================================================== --- test/MC/Hexagon/v60-vcmp.s +++ test/MC/Hexagon/v60-vcmp.s @@ -1,5 +1,5 @@ -#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj %s | \ -#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -d - | \ +#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \ +#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -mhvx -d - | \ #RUN: FileCheck %s #CHECK: 1c81f142 { q2 |= vcmp.eq(v17.b{{ *}},{{ *}}v1.b) } Index: test/MC/Hexagon/v60-vmem.s =================================================================== --- test/MC/Hexagon/v60-vmem.s +++ test/MC/Hexagon/v60-vmem.s @@ -1,5 +1,5 @@ -#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj %s | \ -#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -d - | \ +#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \ +#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -mhvx -d - | \ #RUN: FileCheck %s #CHECK: 292cc11b { vmem(r12++#1) = v27 } Index: test/MC/Hexagon/v60-vmpy-acc.s =================================================================== --- test/MC/Hexagon/v60-vmpy-acc.s +++ test/MC/Hexagon/v60-vmpy-acc.s @@ -1,5 +1,5 @@ -#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj %s | \ -#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -d - | \ +#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \ +#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -mhvx -d - | \ #RUN: FileCheck %s #CHECK: 1936ee37 { v23.w += vdmpy(v15:14.h,r22.uh,#1):sat } Index: test/MC/Hexagon/v60-vmpy1.s =================================================================== --- test/MC/Hexagon/v60-vmpy1.s +++ test/MC/Hexagon/v60-vmpy1.s @@ -1,5 +1,5 @@ -#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj %s | \ -#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -d - | \ +#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \ +#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -mhvx -d - | \ #RUN: FileCheck %s #CHECK: 1939c223 { v3.w = vdmpy(v3:2.h,{{ *}}r25.uh,{{ *}}#1):sat } Index: test/MC/Hexagon/v60lookup.s =================================================================== --- test/MC/Hexagon/v60lookup.s +++ test/MC/Hexagon/v60lookup.s @@ -1,5 +1,5 @@ -#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj %s | \ -#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -d - | \ +#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \ +#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -mhvx -d - | \ #RUN: FileCheck %s V31.b = vlut32(V29.b, V15.b, R1) Index: test/MC/Hexagon/v62_all.s =================================================================== --- test/MC/Hexagon/v62_all.s +++ test/MC/Hexagon/v62_all.s @@ -1,4 +1,4 @@ -# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv62 -filetype=obj %s | llvm-objdump -arch=hexagon -mcpu=hexagonv62 -d - | FileCheck %s +# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv62 -filetype=obj -mhvx %s | llvm-objdump -arch=hexagon -mcpu=hexagonv62 -mhvx -d - | FileCheck %s // V6_lvsplatb // Vd32.b=vsplat(Rt32) Index: test/Transforms/SimplifyCFG/Hexagon/switch-to-lookup-table.ll =================================================================== --- test/Transforms/SimplifyCFG/Hexagon/switch-to-lookup-table.ll +++ test/Transforms/SimplifyCFG/Hexagon/switch-to-lookup-table.ll @@ -59,4 +59,4 @@ ret i32 %1 } -attributes #0 = { noinline nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { noinline nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-length128b,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } Index: test/tools/llvm-objdump/Hexagon/source-interleave-hexagon.ll =================================================================== --- test/tools/llvm-objdump/Hexagon/source-interleave-hexagon.ll +++ test/tools/llvm-objdump/Hexagon/source-interleave-hexagon.ll @@ -34,7 +34,7 @@ ; Function Attrs: nounwind readnone declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 -attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-length128b" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind readnone } !llvm.dbg.cu = !{!0}