Index: lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
===================================================================
--- lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -1639,16 +1639,13 @@
     return;
   }
 
-  if (isCBranchSCC(N)) {
-    // This brcond will use S_CBRANCH_SCC*, so let tablegen handle it.
-    SelectCode(N);
-    return;
-  }
-
+  bool UseSCCBr = isCBranchSCC(N) && isUniformBr(N);
+  unsigned BrOp = UseSCCBr ? AMDGPU::S_CBRANCH_SCC1 : AMDGPU::S_CBRANCH_VCCNZ;
+  unsigned CondReg = UseSCCBr ? AMDGPU::SCC : AMDGPU::VCC;
   SDLoc SL(N);
 
-  SDValue VCC = CurDAG->getCopyToReg(N->getOperand(0), SL, AMDGPU::VCC, Cond);
-  CurDAG->SelectNodeTo(N, AMDGPU::S_CBRANCH_VCCNZ, MVT::Other,
+  SDValue VCC = CurDAG->getCopyToReg(N->getOperand(0), SL, CondReg, Cond);
+  CurDAG->SelectNodeTo(N, BrOp, MVT::Other,
                        N->getOperand(2), // Basic Block
                        VCC.getValue(0));
 }
Index: lib/Target/AMDGPU/SIInstrInfo.td
===================================================================
--- lib/Target/AMDGPU/SIInstrInfo.td
+++ lib/Target/AMDGPU/SIInstrInfo.td
@@ -232,16 +232,6 @@
   return true;
 }]>;
 
-def si_uniform_br : PatFrag <
-  (ops node:$cond, node:$bb), (brcond node:$cond, node:$bb), [{
-  return isUniformBr(N);
-}]>;
-
-def si_uniform_br_scc : PatFrag <
-  (ops node:$cond, node:$bb), (si_uniform_br node:$cond, node:$bb), [{
-  return isCBranchSCC(N);
-}]>;
-
 def lshr_rev : PatFrag <
   (ops node:$src1, node:$src0),
   (srl $src0, $src1)
Index: lib/Target/AMDGPU/SOPInstructions.td
===================================================================
--- lib/Target/AMDGPU/SOPInstructions.td
+++ lib/Target/AMDGPU/SOPInstructions.td
@@ -817,8 +817,7 @@
 >;
 def S_CBRANCH_SCC1 : SOPP <
   0x00000005, (ins sopp_brtarget:$simm16),
-  "s_cbranch_scc1 $simm16",
-  [(si_uniform_br_scc SCC, bb:$simm16)]
+  "s_cbranch_scc1 $simm16"
 >;
 } // End Uses = [SCC]
 
Index: test/CodeGen/AMDGPU/control-flow-optnone.ll
===================================================================
--- /dev/null
+++ test/CodeGen/AMDGPU/control-flow-optnone.ll
@@ -0,0 +1,54 @@
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+
+; optnone disables AMDGPUAnnotateUniformValues, so no branch is known
+; to be uniform during instruction selection. The custom selection for
+; brcond was not checking if the branch was uniform, relying on the
+; selection pattern to check that. That would fail, so then the branch
+; would fail to select.
+
+; GCN-LABEL: {{^}}copytoreg_divergent_brcond:
+; GCN: s_branch
+
+; GCN-DAG: v_cmp_lt_i32
+; GCN-DAG: v_cmp_gt_i32
+; GCN: s_and_b64
+; GCN: s_and_saveexec_b64
+
+; GCN: s_or_b64 exec, exec
+; GCN: v_cmp_eq_u32
+; GCN: s_cbranch_vccnz
+; GCN-NEXT: s_branch
+define amdgpu_kernel void @copytoreg_divergent_brcond(i32 %arg, i32 %arg1, i32 %arg2) #0 {
+bb:
+  %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
+  %tmp3 = zext i32 %tmp to i64
+  %tmp5 = add i64 %tmp3, undef
+  %tmp6 = trunc i64 %tmp5 to i32
+  %tmp7 = mul nsw i32 %tmp6, %arg2
+  br label %bb8
+
+bb8.loopexit:                                     ; preds = %bb14
+  br label %bb8
+
+bb8:                                              ; preds = %bb8.loopexit, %bb
+  br label %bb9
+
+bb9:                                              ; preds = %bb14, %bb8
+  %tmp10 = icmp slt i32 %tmp7, %arg1
+  %tmp11 = icmp sgt i32 %arg, 0
+  %tmp12 = and i1 %tmp10, %tmp11
+  br i1 %tmp12, label %bb13, label %bb14
+
+bb13:                                             ; preds = %bb9
+  store volatile i32 0, i32 addrspace(1)* undef, align 4
+  br label %bb14
+
+bb14:                                             ; preds = %bb13, %bb9
+  %tmp15 = icmp eq i32 %arg2, 1
+  br i1 %tmp15, label %bb8.loopexit, label %bb9
+}
+
+declare i32 @llvm.amdgcn.workitem.id.x() #1
+
+attributes #0 = { nounwind optnone noinline }
+attributes #1 = { nounwind readnone speculatable }