Index: include/llvm/IR/IntrinsicsAMDGPU.td
===================================================================
--- include/llvm/IR/IntrinsicsAMDGPU.td
+++ include/llvm/IR/IntrinsicsAMDGPU.td
@@ -747,6 +747,12 @@
   [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable]
 >;
 
+// Return true if at least one thread within the pixel quad passes true into
+// the function.
+def int_amdgcn_wqm_vote : Intrinsic<[llvm_i1_ty],
+  [llvm_i1_ty], [IntrNoMem, IntrSpeculatable, IntrConvergent]
+>;
+
 // Copies the active channels of the source value to the destination value,
 // with the guarantee that the source value is computed as if the entire
 // program were executed in Whole Wavefront Mode, i.e. with all channels
Index: lib/Target/AMDGPU/SOPInstructions.td
===================================================================
--- lib/Target/AMDGPU/SOPInstructions.td
+++ lib/Target/AMDGPU/SOPInstructions.td
@@ -139,7 +139,9 @@
     [(set i64:$sdst, (not i64:$src0))]
   >;
   def S_WQM_B32 : SOP1_32 <"s_wqm_b32">;
-  def S_WQM_B64 : SOP1_64 <"s_wqm_b64">;
+  def S_WQM_B64 : SOP1_64 <"s_wqm_b64",
+    [(set i1:$sdst, (int_amdgcn_wqm_vote i1:$src0))]
+  >;
 } // End Defs = [SCC]
 
 
Index: lib/Transforms/InstCombine/InstCombineCalls.cpp
===================================================================
--- lib/Transforms/InstCombine/InstCombineCalls.cpp
+++ lib/Transforms/InstCombine/InstCombineCalls.cpp
@@ -3532,6 +3532,13 @@
 
     break;
   }
+  case Intrinsic::amdgcn_wqm_vote: {
+    // wqm_vote is identity when the argument is constant.
+    if (!isa<Constant>(II->getArgOperand(0)))
+      break;
+
+    return replaceInstUsesWith(*II, II->getArgOperand(0));
+  }
   case Intrinsic::stackrestore: {
     // If the save is right next to the restore, remove the restore.  This can
     // happen when variable allocas are DCE'd.
Index: test/CodeGen/AMDGPU/llvm.amdgcn.wqm.vote.ll
===================================================================
--- /dev/null
+++ test/CodeGen/AMDGPU/llvm.amdgcn.wqm.vote.ll
@@ -0,0 +1,53 @@
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=CHECK %s
+
+;CHECK-LABEL: {{^}}ret:
+;CHECK: v_cmp_eq_u32_e32 [[CMP:[^,]+]], v0, v1
+;CHECK: s_wqm_b64 [[WQM:[^,]+]], [[CMP]]
+;CHECK: v_cndmask_b32_e64 v0, 0, 1.0, [[WQM]]
+define amdgpu_ps float @ret(i32 %v0, i32 %v1) #1 {
+main_body:
+  %c = icmp eq i32 %v0, %v1
+  %w = call i1 @llvm.amdgcn.wqm.vote(i1 %c)
+  %r = select i1 %w, float 1.0, float 0.0
+  ret float %r
+}
+
+;CHECK-LABEL: {{^}}true:
+;CHECK: s_wqm_b64
+define amdgpu_ps float @true() #1 {
+main_body:
+  %w = call i1 @llvm.amdgcn.wqm.vote(i1 true)
+  %r = select i1 %w, float 1.0, float 0.0
+  ret float %r
+}
+
+;CHECK-LABEL: {{^}}false:
+;CHECK: s_wqm_b64
+define amdgpu_ps float @false() #1 {
+main_body:
+  %w = call i1 @llvm.amdgcn.wqm.vote(i1 false)
+  %r = select i1 %w, float 1.0, float 0.0
+  ret float %r
+}
+
+;CHECK-LABEL: {{^}}kill:
+;CHECK: v_cmp_eq_u32_e32 [[CMP:[^,]+]], v0, v1
+;CHECK: s_wqm_b64 [[WQM:[^,]+]], [[CMP]]
+;FIXME: This could just be: s_and_b64 exec, exec, [[WQM]]
+;CHECK: v_cndmask_b32_e64 [[KILL:[^,]+]], -1.0, 1.0, [[WQM]]
+;CHECK: v_cmpx_le_f32_e32 {{[^,]+}}, 0, [[KILL]]
+;CHECK: s_endpgm
+define amdgpu_ps void @kill(i32 %v0, i32 %v1) #1 {
+main_body:
+  %c = icmp eq i32 %v0, %v1
+  %w = call i1 @llvm.amdgcn.wqm.vote(i1 %c)
+  %r = select i1 %w, float 1.0, float -1.0
+  call void @llvm.AMDGPU.kill(float %r)
+  ret void
+}
+
+declare void @llvm.AMDGPU.kill(float) #1
+declare i1 @llvm.amdgcn.wqm.vote(i1) #0
+
+attributes #0 = { nounwind readnone speculatable convergent }
+attributes #1 = { nounwind }
Index: test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
===================================================================
--- test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
+++ test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
@@ -1259,7 +1259,7 @@
 }
 
 ; CHECK-LABEL: @icmp_constant_inputs_true(
-; CHECK: %result = call i64 @llvm.read_register.i64(metadata !0) #5
+; CHECK: %result = call i64 @llvm.read_register.i64(metadata !0) #6
 define i64 @icmp_constant_inputs_true() {
   %result = call i64 @llvm.amdgcn.icmp.i32(i32 9, i32 8, i32 34)
   ret i64 %result
@@ -1524,7 +1524,7 @@
 }
 
 ; CHECK-LABEL: @fcmp_constant_inputs_true(
-; CHECK: %result = call i64 @llvm.read_register.i64(metadata !0) #5
+; CHECK: %result = call i64 @llvm.read_register.i64(metadata !0) #6
 define i64 @fcmp_constant_inputs_true() {
   %result = call i64 @llvm.amdgcn.fcmp.f32(float 2.0, float 4.0, i32 4)
   ret i64 %result
@@ -1537,4 +1537,37 @@
   ret i64 %result
 }
 
-; CHECK: attributes #5 = { convergent }
+; --------------------------------------------------------------------
+; llvm.amdgcn.wqm.vote
+; --------------------------------------------------------------------
+
+declare i1 @llvm.amdgcn.wqm.vote(i1)
+
+; CHECK-LABEL: @wqm_vote_true(
+; CHECK: ret float 1.000000e+00
+define float @wqm_vote_true() {
+main_body:
+  %w = call i1 @llvm.amdgcn.wqm.vote(i1 true)
+  %r = select i1 %w, float 1.0, float 0.0
+  ret float %r
+}
+
+; CHECK-LABEL: @wqm_vote_false(
+; CHECK: ret float 0.000000e+00
+define float @wqm_vote_false() {
+main_body:
+  %w = call i1 @llvm.amdgcn.wqm.vote(i1 false)
+  %r = select i1 %w, float 1.0, float 0.0
+  ret float %r
+}
+
+; CHECK-LABEL: @wqm_vote_undef(
+; CHECK: ret float undef
+define float @wqm_vote_undef() {
+main_body:
+  %w = call i1 @llvm.amdgcn.wqm.vote(i1 undef)
+  %r = select i1 %w, float 1.0, float 0.0
+  ret float %r
+}
+
+; CHECK: attributes #6 = { convergent }