Index: include/llvm/CodeGen/Analysis.h
===================================================================
--- include/llvm/CodeGen/Analysis.h
+++ include/llvm/CodeGen/Analysis.h
@@ -30,7 +30,7 @@
 class MachineFunction;
 class TargetLoweringBase;
 class TargetLowering;
-class TargetMachine;
+class LLVMTargetMachine;
 class SDNode;
 class SDValue;
 class SelectionDAG;
@@ -103,7 +103,7 @@
 /// between it and the return.
 ///
 /// This function only tests target-independent requirements.
-bool isInTailCallPosition(ImmutableCallSite CS, const TargetMachine &TM);
+bool isInTailCallPosition(ImmutableCallSite CS, const LLVMTargetMachine &TM);
 
 /// Test if given that the input instruction is in the tail call position, if
 /// there is an attribute mismatch between the caller and the callee that will
Index: include/llvm/CodeGen/AsmPrinter.h
===================================================================
--- include/llvm/CodeGen/AsmPrinter.h
+++ include/llvm/CodeGen/AsmPrinter.h
@@ -26,6 +26,8 @@
 #include "llvm/IR/LLVMContext.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/SourceMgr.h"
+#include "llvm/Support/TargetRegistry.h"
+#include "llvm/Target/TargetMachine.h"
 #include <cstdint>
 #include <memory>
 #include <utility>
@@ -45,9 +47,10 @@
 class GCMetadataPrinter;
 class GlobalIndirectSymbol;
 class GlobalObject;
+class GCStrategy;
 class GlobalValue;
 class GlobalVariable;
-class GCStrategy;
+class LLVMTargetMachine;
 class MachineBasicBlock;
 class MachineConstantPoolValue;
 class MachineFunction;
@@ -70,14 +73,13 @@
 class Module;
 class raw_ostream;
 class TargetLoweringObjectFile;
-class TargetMachine;
 
 /// This class is intended to be used as a driving class for all asm writers.
 class AsmPrinter : public MachineFunctionPass {
 public:
   /// Target machine description.
   ///
-  TargetMachine &TM;
+  LLVMTargetMachine &TM;
 
   /// Target Asm Printer information.
   ///
@@ -173,7 +175,8 @@
   bool isCFIMoveForDebugging = false;
 
 protected:
-  explicit AsmPrinter(TargetMachine &TM, std::unique_ptr<MCStreamer> Streamer);
+  explicit AsmPrinter(LLVMTargetMachine &TM,
+                      std::unique_ptr<MCStreamer> Streamer);
 
 public:
   ~AsmPrinter() override;
@@ -204,7 +207,7 @@
   /// Return information about data layout.
   const DataLayout &getDataLayout() const;
 
-  /// Return the pointer size from the TargetMachine
+  /// Return the pointer size from the LLVMTargetMachine
   unsigned getPointerSize() const;
 
   /// Return information about subtarget.
@@ -638,6 +641,26 @@
                                 const GlobalIndirectSymbol& GIS);
 };
 
+/// Helper template for registering a target specific assembly printer, for use
+/// in the target machine initialization function. Usage:
+///
+/// extern "C" void LLVMInitializeFooAsmPrinter() {
+///   extern Target TheFooTarget;
+///   RegisterAsmPrinter<FooAsmPrinter> X(TheFooTarget);
+/// }
+template <class AsmPrinterImpl> struct RegisterAsmPrinter {
+  RegisterAsmPrinter(Target &T) {
+    TargetRegistry::RegisterAsmPrinter(T, &Allocator);
+  }
+
+private:
+  static AsmPrinter *Allocator(TargetMachine &TM,
+                               std::unique_ptr<MCStreamer> &&Streamer) {
+    LLVMTargetMachine &LLVMTM = static_cast<LLVMTargetMachine&>(TM);
+    return new AsmPrinterImpl(LLVMTM, std::move(Streamer));
+  }
+};
+
 } // end namespace llvm
 
 #endif // LLVM_CODEGEN_ASMPRINTER_H
Index: include/llvm/CodeGen/BasicTTIImpl.h
===================================================================
--- include/llvm/CodeGen/BasicTTIImpl.h
+++ include/llvm/CodeGen/BasicTTIImpl.h
@@ -25,6 +25,8 @@
 
 namespace llvm {
 
+class LLVMTargetMachine;
+
 extern cl::opt<unsigned> PartialUnrollingThreshold;
 
 /// \brief Base class which can be used to help build a TTI implementation.
@@ -74,7 +76,7 @@
   }
 
 protected:
-  explicit BasicTTIImplBase(const TargetMachine *TM, const DataLayout &DL)
+  explicit BasicTTIImplBase(const LLVMTargetMachine *TM, const DataLayout &DL)
       : BaseT(DL) {}
 
   using TargetTransformInfoImplBase::DL;
@@ -1255,7 +1257,7 @@
   const TargetLoweringBase *getTLI() const { return TLI; }
 
 public:
-  explicit BasicTTIImpl(const TargetMachine *ST, const Function &F);
+  explicit BasicTTIImpl(const LLVMTargetMachine *ST, const Function &F);
 };
 
 }
Index: include/llvm/CodeGen/FastISel.h
===================================================================
--- include/llvm/CodeGen/FastISel.h
+++ include/llvm/CodeGen/FastISel.h
@@ -41,6 +41,7 @@
 class ConstantFP;
 class DataLayout;
 class FunctionLoweringInfo;
+class LLVMTargetMachine;
 class LoadInst;
 class MachineConstantPool;
 class MachineFrameInfo;
@@ -54,7 +55,6 @@
 class MCSymbol;
 class TargetInstrInfo;
 class TargetLibraryInfo;
-class TargetMachine;
 class TargetRegisterClass;
 class TargetRegisterInfo;
 class Type;
@@ -207,7 +207,7 @@
   MachineFrameInfo &MFI;
   MachineConstantPool &MCP;
   DebugLoc DbgLoc;
-  const TargetMachine &TM;
+  const LLVMTargetMachine &TM;
   const DataLayout &DL;
   const TargetInstrInfo &TII;
   const TargetLowering &TLI;
Index: include/llvm/CodeGen/MachineFunction.h
===================================================================
--- include/llvm/CodeGen/MachineFunction.h
+++ include/llvm/CodeGen/MachineFunction.h
@@ -58,6 +58,7 @@
 class DILocation;
 class Function;
 class GlobalValue;
+class LLVMTargetMachine;
 class MachineConstantPool;
 class MachineFrameInfo;
 class MachineFunction;
@@ -70,7 +71,6 @@
 class PseudoSourceValueManager;
 class raw_ostream;
 class SlotIndexes;
-class TargetMachine;
 class TargetRegisterClass;
 class TargetSubtargetInfo;
 struct WinEHFuncInfo;
@@ -224,7 +224,7 @@
 
 class MachineFunction {
   const Function *Fn;
-  const TargetMachine &Target;
+  const LLVMTargetMachine &Target;
   const TargetSubtargetInfo *STI;
   MCContext &Ctx;
   MachineModuleInfo &MMI;
@@ -359,7 +359,7 @@
   using VariableDbgInfoMapTy = SmallVector<VariableDbgInfo, 4>;
   VariableDbgInfoMapTy VariableDbgInfos;
 
-  MachineFunction(const Function *Fn, const TargetMachine &TM,
+  MachineFunction(const Function *Fn, const LLVMTargetMachine &TM,
                   unsigned FunctionNum, MachineModuleInfo &MMI);
   MachineFunction(const MachineFunction &) = delete;
   MachineFunction &operator=(const MachineFunction &) = delete;
@@ -389,7 +389,7 @@
   unsigned getFunctionNumber() const { return FunctionNumber; }
 
   /// getTarget - Return the target machine this machine code is compiled with
-  const TargetMachine &getTarget() const { return Target; }
+  const LLVMTargetMachine &getTarget() const { return Target; }
 
   /// getSubtarget - Return the subtarget for which this machine code is being
   /// compiled.
Index: include/llvm/CodeGen/MachineModuleInfo.h
===================================================================
--- include/llvm/CodeGen/MachineModuleInfo.h
+++ include/llvm/CodeGen/MachineModuleInfo.h
@@ -46,10 +46,10 @@
 class BasicBlock;
 class CallInst;
 class Function;
-class MachineFunction;
+class LLVMTargetMachine;
 class MMIAddrLabelMap;
+class MachineFunction;
 class Module;
-class TargetMachine;
 
 //===----------------------------------------------------------------------===//
 /// This class can be derived from and used by targets to hold private
@@ -76,7 +76,7 @@
 /// for specific use.
 ///
 class MachineModuleInfo : public ImmutablePass {
-  const TargetMachine &TM;
+  const LLVMTargetMachine &TM;
 
   /// This is the MCContext used for the entire code generator.
   MCContext Context;
@@ -145,7 +145,7 @@
 public:
   static char ID; // Pass identification, replacement for typeid
 
-  explicit MachineModuleInfo(const TargetMachine *TM = nullptr);
+  explicit MachineModuleInfo(const LLVMTargetMachine *TM = nullptr);
   ~MachineModuleInfo() override;
 
   // Initialization and Finalization
Index: include/llvm/CodeGen/RegisterUsageInfo.h
===================================================================
--- include/llvm/CodeGen/RegisterUsageInfo.h
+++ include/llvm/CodeGen/RegisterUsageInfo.h
@@ -27,7 +27,7 @@
 namespace llvm {
 
 class Function;
-class TargetMachine;
+class LLVMTargetMachine;
 
 class PhysicalRegisterUsageInfo : public ImmutablePass {
   virtual void anchor();
@@ -44,9 +44,9 @@
     AU.setPreservesAll();
   }
 
-  /// To set TargetMachine *, which is used to print
+  /// To set LLVMTargetMachine *, which is used to print
   /// analysis when command line option -print-regusage is used.
-  void setTargetMachine(const TargetMachine *TM_) { TM = TM_; }
+  void setTargetMachine(const LLVMTargetMachine *TM_) { TM = TM_; }
 
   bool doInitialization(Module &M) override;
 
@@ -68,7 +68,7 @@
   /// and 1 means content of register will be preserved around function call.
   DenseMap<const Function *, std::vector<uint32_t>> RegMasks;
 
-  const TargetMachine *TM;
+  const LLVMTargetMachine *TM;
 };
 
 } // end namespace llvm
Index: include/llvm/CodeGen/SelectionDAG.h
===================================================================
--- include/llvm/CodeGen/SelectionDAG.h
+++ include/llvm/CodeGen/SelectionDAG.h
@@ -66,6 +66,7 @@
 class GlobalValue;
 struct KnownBits;
 class LLVMContext;
+class LLVMTargetMachine;
 class MachineBasicBlock;
 class MachineConstantPoolValue;
 class MCSymbol;
@@ -74,7 +75,6 @@
 class SelectionDAG;
 class SelectionDAGTargetInfo;
 class TargetLowering;
-class TargetMachine;
 class TargetSubtargetInfo;
 class Value;
 
@@ -207,7 +207,7 @@
 /// linear form.
 ///
 class SelectionDAG {
-  const TargetMachine &TM;
+  const LLVMTargetMachine &TM;
   const SelectionDAGTargetInfo *TSI = nullptr;
   const TargetLowering *TLI = nullptr;
   MachineFunction *MF;
@@ -361,7 +361,7 @@
   }
 
 public:
-  explicit SelectionDAG(const TargetMachine &TM, CodeGenOpt::Level);
+  explicit SelectionDAG(const LLVMTargetMachine &TM, CodeGenOpt::Level);
   SelectionDAG(const SelectionDAG &) = delete;
   SelectionDAG &operator=(const SelectionDAG &) = delete;
   ~SelectionDAG();
@@ -378,7 +378,7 @@
   const Pass *getPass() const { return SDAGISelPass; }
 
   const DataLayout &getDataLayout() const { return MF->getDataLayout(); }
-  const TargetMachine &getTarget() const { return TM; }
+  const LLVMTargetMachine &getTarget() const { return TM; }
   const TargetSubtargetInfo &getSubtarget() const { return MF->getSubtarget(); }
   const TargetLowering &getTargetLoweringInfo() const { return *TLI; }
   const SelectionDAGTargetInfo &getSelectionDAGInfo() const { return *TSI; }
Index: include/llvm/CodeGen/SelectionDAGISel.h
===================================================================
--- include/llvm/CodeGen/SelectionDAGISel.h
+++ include/llvm/CodeGen/SelectionDAGISel.h
@@ -43,7 +43,7 @@
 /// pattern-matching instruction selectors.
 class SelectionDAGISel : public MachineFunctionPass {
 public:
-  TargetMachine &TM;
+  LLVMTargetMachine &TM;
   const TargetLibraryInfo *LibInfo;
   FunctionLoweringInfo *FuncInfo;
   MachineFunction *MF;
@@ -64,7 +64,7 @@
 
   static char ID;
 
-  explicit SelectionDAGISel(TargetMachine &tm,
+  explicit SelectionDAGISel(LLVMTargetMachine &tm,
                             CodeGenOpt::Level OL = CodeGenOpt::Default);
   ~SelectionDAGISel() override;
 
Index: include/llvm/CodeGen/StackProtector.h
===================================================================
--- include/llvm/CodeGen/StackProtector.h
+++ include/llvm/CodeGen/StackProtector.h
@@ -29,9 +29,9 @@
 class DominatorTree;
 class Function;
 class Instruction;
+class LLVMTargetMachine;
 class Module;
 class TargetLoweringBase;
-class TargetMachine;
 class Type;
 
 class StackProtector : public FunctionPass {
@@ -53,7 +53,7 @@
   using SSPLayoutMap = ValueMap<const AllocaInst *, SSPLayoutKind>;
 
 private:
-  const TargetMachine *TM = nullptr;
+  const LLVMTargetMachine *TM = nullptr;
 
   /// TLI - Keep a pointer of a TargetLowering to consult for determining
   /// target type sizes.
Index: include/llvm/Support/TargetRegistry.h
===================================================================
--- include/llvm/Support/TargetRegistry.h
+++ include/llvm/Support/TargetRegistry.h
@@ -37,6 +37,7 @@
 namespace llvm {
 
 class AsmPrinter;
+class LLVMTargetMachine;
 class MCAsmBackend;
 class MCAsmInfo;
 class MCAsmParser;
@@ -1109,26 +1110,6 @@
   }
 };
 
-/// RegisterAsmPrinter - Helper template for registering a target specific
-/// assembly printer, for use in the target machine initialization
-/// function. Usage:
-///
-/// extern "C" void LLVMInitializeFooAsmPrinter() {
-///   extern Target TheFooTarget;
-///   RegisterAsmPrinter<FooAsmPrinter> X(TheFooTarget);
-/// }
-template <class AsmPrinterImpl> struct RegisterAsmPrinter {
-  RegisterAsmPrinter(Target &T) {
-    TargetRegistry::RegisterAsmPrinter(T, &Allocator);
-  }
-
-private:
-  static AsmPrinter *Allocator(TargetMachine &TM,
-                               std::unique_ptr<MCStreamer> &&Streamer) {
-    return new AsmPrinterImpl(TM, std::move(Streamer));
-  }
-};
-
 /// RegisterMCCodeEmitter - Helper template for registering a target specific
 /// machine code emitter, for use in the target initialization
 /// function. Usage:
Index: include/llvm/Target/TargetLowering.h
===================================================================
--- include/llvm/Target/TargetLowering.h
+++ include/llvm/Target/TargetLowering.h
@@ -215,8 +215,8 @@
     llvm_unreachable("Invalid content kind");
   }
 
-  /// NOTE: The TargetMachine owns TLOF.
-  explicit TargetLoweringBase(const TargetMachine &TM);
+  /// NOTE: The LLVMTargetMachine owns TLOF.
+  explicit TargetLoweringBase(const LLVMTargetMachine &TM);
   TargetLoweringBase(const TargetLoweringBase &) = delete;
   TargetLoweringBase &operator=(const TargetLoweringBase &) = delete;
   virtual ~TargetLoweringBase() = default;
@@ -226,7 +226,7 @@
   void initActions();
 
 public:
-  const TargetMachine &getTargetMachine() const { return TM; }
+  const LLVMTargetMachine &getTargetMachine() const { return TM; }
 
   virtual bool useSoftFloat() const { return false; }
 
@@ -2230,7 +2230,7 @@
   virtual void finalizeLowering(MachineFunction &MF) const;
 
 private:
-  const TargetMachine &TM;
+  const LLVMTargetMachine &TM;
 
   /// Tells the code generator that the target has multiple (allocatable)
   /// condition registers that can be used to store the results of comparisons
@@ -2501,8 +2501,8 @@
   TargetLowering(const TargetLowering &) = delete;
   TargetLowering &operator=(const TargetLowering &) = delete;
 
-  /// NOTE: The TargetMachine owns TLOF.
-  explicit TargetLowering(const TargetMachine &TM);
+  /// NOTE: The LLVMTargetMachine owns TLOF.
+  explicit TargetLowering(const LLVMTargetMachine &TM);
 
   bool isPositionIndependent() const;
 
Index: include/llvm/Target/TargetMachine.h
===================================================================
--- include/llvm/Target/TargetMachine.h
+++ include/llvm/Target/TargetMachine.h
@@ -38,6 +38,7 @@
 class Target;
 class TargetIntrinsicInfo;
 class TargetIRAnalysis;
+class TargetLowering;
 class TargetLoweringObjectFile;
 class TargetPassConfig;
 class TargetSubtargetInfo;
@@ -105,22 +106,10 @@
   StringRef getTargetCPU() const { return TargetCPU; }
   StringRef getTargetFeatureString() const { return TargetFS; }
 
-  /// Virtual method implemented by subclasses that returns a reference to that
-  /// target's TargetSubtargetInfo-derived member variable.
-  virtual const TargetSubtargetInfo *getSubtargetImpl(const Function &) const {
-    return nullptr;
-  }
   virtual TargetLoweringObjectFile *getObjFileLowering() const {
     return nullptr;
   }
 
-  /// This method returns a pointer to the specified type of
-  /// TargetSubtargetInfo.  In debug builds, it verifies that the object being
-  /// returned is of the correct type.
-  template <typename STC> const STC &getSubtarget(const Function &F) const {
-    return *static_cast<const STC*>(getSubtargetImpl(F));
-  }
-
   /// Create a DataLayout.
   const DataLayout createDataLayout() const { return DL; }
 
@@ -243,27 +232,14 @@
     return true;
   }
 
-  /// True if subtarget inserts the final scheduling pass on its own.
-  ///
-  /// Branch relaxation, which must happen after block placement, can
-  /// on some targets (e.g. SystemZ) expose additional post-RA
-  /// scheduling opportunities.
-  virtual bool targetSchedulesPostRAScheduling() const { return false; };
-
   void getNameWithPrefix(SmallVectorImpl<char> &Name, const GlobalValue *GV,
                          Mangler &Mang, bool MayAlwaysUsePrivate = false) const;
   MCSymbol *getSymbol(const GlobalValue *GV) const;
 
-  /// True if the target uses physical regs at Prolog/Epilog insertion
-  /// time. If true (most machines), all vregs must be allocated before
-  /// PEI. If false (virtual-register machines), then callee-save register
-  /// spilling and scavenging are not needed or used.
-  virtual bool usesPhysRegsForPEI() const { return true; }
+  virtual bool useAA(const Function &F) const { return false; }
 
-  /// True if the target wants to use interprocedural register allocation by
-  /// default. The -enable-ipra flag can be used to override this.
-  virtual bool useIPRA() const {
-    return false;
+  virtual const TargetLowering *getTargetLowering(const Function &F) const {
+    return nullptr;
   }
 };
 
@@ -306,16 +282,51 @@
                          raw_pwrite_stream &OS,
                          bool DisableVerify = true) override;
 
+  /// \brief Adds an AsmPrinter pass to the pipeline that prints assembly or
+  /// machine code from the MI representation.
+  bool addAsmPrinter(PassManagerBase &PM, raw_pwrite_stream &Out,
+                     CodeGenFileType FileTYpe, MCContext &Context);
+
+  /// Virtual method implemented by subclasses that returns a reference to that
+  /// target's TargetSubtargetInfo-derived member variable.
+  virtual const TargetSubtargetInfo *getSubtargetImpl(const Function &) const
+    = 0;
+
+  /// This method returns a pointer to the specified type of
+  /// TargetSubtargetInfo.  In debug builds, it verifies that the object being
+  /// returned is of the correct type.
+  template <typename STC> const STC &getSubtarget(const Function &F) const {
+    return *static_cast<const STC*>(getSubtargetImpl(F));
+  }
+
+  /// True if subtarget inserts the final scheduling pass on its own.
+  ///
+  /// Branch relaxation, which must happen after block placement, can
+  /// on some targets (e.g. SystemZ) expose additional post-RA
+  /// scheduling opportunities.
+  virtual bool targetSchedulesPostRAScheduling() const { return false; };
+
+  /// True if the target uses physical regs at Prolog/Epilog insertion
+  /// time. If true (most machines), all vregs must be allocated before
+  /// PEI. If false (virtual-register machines), then callee-save register
+  /// spilling and scavenging are not needed or used.
+  virtual bool usesPhysRegsForPEI() const { return true; }
+
+  /// True if the target wants to use interprocedural register allocation by
+  /// default. The -enable-ipra flag can be used to override this.
+  virtual bool useIPRA() const {
+    return false;
+  }
+
   /// Returns true if the target is expected to pass all machine verifier
   /// checks. This is a stopgap measure to fix targets one by one. We will
   /// remove this at some point and always enable the verifier when
   /// EXPENSIVE_CHECKS is enabled.
   virtual bool isMachineVerifierClean() const { return true; }
 
-  /// \brief Adds an AsmPrinter pass to the pipeline that prints assembly or
-  /// machine code from the MI representation.
-  bool addAsmPrinter(PassManagerBase &PM, raw_pwrite_stream &Out,
-                     CodeGenFileType FileTYpe, MCContext &Context);
+  bool useAA(const Function &F) const override;
+
+  const TargetLowering *getTargetLowering(const Function &F) const override;
 };
 
 } // end namespace llvm
Index: lib/CodeGen/Analysis.cpp
===================================================================
--- lib/CodeGen/Analysis.cpp
+++ lib/CodeGen/Analysis.cpp
@@ -469,7 +469,8 @@
 /// between it and the return.
 ///
 /// This function only tests target-independent requirements.
-bool llvm::isInTailCallPosition(ImmutableCallSite CS, const TargetMachine &TM) {
+bool llvm::isInTailCallPosition(ImmutableCallSite CS,
+                                const LLVMTargetMachine &TM) {
   const Instruction *I = CS.getInstruction();
   const BasicBlock *ExitBB = I->getParent();
   const TerminatorInst *Term = ExitBB->getTerminator();
Index: lib/CodeGen/AsmPrinter/AsmPrinter.cpp
===================================================================
--- lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+++ lib/CodeGen/AsmPrinter/AsmPrinter.cpp
@@ -163,7 +163,8 @@
   return NumBits;
 }
 
-AsmPrinter::AsmPrinter(TargetMachine &tm, std::unique_ptr<MCStreamer> Streamer)
+AsmPrinter::AsmPrinter(LLVMTargetMachine &tm,
+                       std::unique_ptr<MCStreamer> Streamer)
     : MachineFunctionPass(ID), TM(tm), MAI(tm.getMCAsmInfo()),
       OutContext(Streamer->getContext()), OutStreamer(std::move(Streamer)) {
   VerboseAsm = OutStreamer->isVerboseAsm();
Index: lib/CodeGen/AtomicExpandPass.cpp
===================================================================
--- lib/CodeGen/AtomicExpandPass.cpp
+++ lib/CodeGen/AtomicExpandPass.cpp
@@ -196,7 +196,7 @@
   if (!TPC)
     return false;
 
-  auto &TM = TPC->getTM<TargetMachine>();
+  auto &TM = TPC->getTM<LLVMTargetMachine>();
   if (!TM.getSubtargetImpl(F)->enableAtomicExpand())
     return false;
   TLI = TM.getSubtargetImpl(F)->getTargetLowering();
Index: lib/CodeGen/BasicTargetTransformInfo.cpp
===================================================================
--- lib/CodeGen/BasicTargetTransformInfo.cpp
+++ lib/CodeGen/BasicTargetTransformInfo.cpp
@@ -31,6 +31,6 @@
                                     cl::desc("Threshold for partial unrolling"),
                                     cl::Hidden);
 
-BasicTTIImpl::BasicTTIImpl(const TargetMachine *TM, const Function &F)
+BasicTTIImpl::BasicTTIImpl(const LLVMTargetMachine *TM, const Function &F)
     : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
       TLI(ST->getTargetLowering()) {}
Index: lib/CodeGen/CodeGenPrepare.cpp
===================================================================
--- lib/CodeGen/CodeGenPrepare.cpp
+++ lib/CodeGen/CodeGenPrepare.cpp
@@ -205,7 +205,7 @@
 class TypePromotionTransaction;
 
   class CodeGenPrepare : public FunctionPass {
-    const TargetMachine *TM = nullptr;
+    const LLVMTargetMachine *TM = nullptr;
     const TargetSubtargetInfo *SubtargetInfo;
     const TargetLowering *TLI = nullptr;
     const TargetRegisterInfo *TRI;
@@ -335,7 +335,7 @@
 
   ModifiedDT = false;
   if (auto *TPC = getAnalysisIfAvailable<TargetPassConfig>()) {
-    TM = &TPC->getTM<TargetMachine>();
+    TM = &TPC->getTM<LLVMTargetMachine>();
     SubtargetInfo = TM->getSubtargetImpl(F);
     TLI = SubtargetInfo->getTargetLowering();
     TRI = SubtargetInfo->getRegisterInfo();
Index: lib/CodeGen/DwarfEHPrepare.cpp
===================================================================
--- lib/CodeGen/DwarfEHPrepare.cpp
+++ lib/CodeGen/DwarfEHPrepare.cpp
@@ -257,8 +257,8 @@
 }
 
 bool DwarfEHPrepare::runOnFunction(Function &Fn) {
-  const TargetMachine &TM =
-      getAnalysis<TargetPassConfig>().getTM<TargetMachine>();
+  const LLVMTargetMachine &TM =
+      getAnalysis<TargetPassConfig>().getTM<LLVMTargetMachine>();
   DT = &getAnalysis<DominatorTreeWrapperPass>().getDomTree();
   TLI = TM.getSubtargetImpl(Fn)->getTargetLowering();
   bool Changed = InsertUnwindResumeCalls(Fn);
Index: lib/CodeGen/InterleavedAccessPass.cpp
===================================================================
--- lib/CodeGen/InterleavedAccessPass.cpp
+++ lib/CodeGen/InterleavedAccessPass.cpp
@@ -444,7 +444,7 @@
   DEBUG(dbgs() << "*** " << getPassName() << ": " << F.getName() << "\n");
 
   DT = &getAnalysis<DominatorTreeWrapperPass>().getDomTree();
-  auto &TM = TPC->getTM<TargetMachine>();
+  auto &TM = TPC->getTM<LLVMTargetMachine>();
   TLI = TM.getSubtargetImpl(F)->getTargetLowering();
   MaxFactor = TLI->getMaxSupportedInterleaveFactor();
 
Index: lib/CodeGen/LLVMTargetMachine.cpp
===================================================================
--- lib/CodeGen/LLVMTargetMachine.cpp
+++ lib/CodeGen/LLVMTargetMachine.cpp
@@ -253,3 +253,12 @@
 
   return false; // success!
 }
+
+bool LLVMTargetMachine::useAA(const Function &F) const {
+  return getSubtargetImpl(F)->useAA();
+}
+
+const TargetLowering *
+LLVMTargetMachine::getTargetLowering(const Function &F) const {
+  return getSubtargetImpl(F)->getTargetLowering();
+}
Index: lib/CodeGen/MachineFunction.cpp
===================================================================
--- lib/CodeGen/MachineFunction.cpp
+++ lib/CodeGen/MachineFunction.cpp
@@ -94,7 +94,7 @@
   return STI->getFrameLowering()->getStackAlignment();
 }
 
-MachineFunction::MachineFunction(const Function *F, const TargetMachine &TM,
+MachineFunction::MachineFunction(const Function *F, const LLVMTargetMachine &TM,
                                  unsigned FunctionNum, MachineModuleInfo &mmi)
     : Fn(F), Target(TM), STI(TM.getSubtargetImpl(*F)), Ctx(mmi.getContext()),
       MMI(mmi) {
Index: lib/CodeGen/MachineModuleInfo.cpp
===================================================================
--- lib/CodeGen/MachineModuleInfo.cpp
+++ lib/CodeGen/MachineModuleInfo.cpp
@@ -195,7 +195,7 @@
   Map->UpdateForRAUWBlock(cast<BasicBlock>(getValPtr()), cast<BasicBlock>(V2));
 }
 
-MachineModuleInfo::MachineModuleInfo(const TargetMachine *TM)
+MachineModuleInfo::MachineModuleInfo(const LLVMTargetMachine *TM)
   : ImmutablePass(ID), TM(*TM),
     Context(TM->getMCAsmInfo(), TM->getMCRegisterInfo(),
             TM->getObjFileLowering(), nullptr, false) {
Index: lib/CodeGen/PrologEpilogInserter.cpp
===================================================================
--- lib/CodeGen/PrologEpilogInserter.cpp
+++ lib/CodeGen/PrologEpilogInserter.cpp
@@ -167,7 +167,7 @@
 ///
 bool PEI::runOnMachineFunction(MachineFunction &Fn) {
   if (!SpillCalleeSavedRegisters) {
-    const TargetMachine &TM = Fn.getTarget();
+    const LLVMTargetMachine &TM = Fn.getTarget();
     if (!TM.usesPhysRegsForPEI()) {
       SpillCalleeSavedRegisters = [](MachineFunction &, RegScavenger *,
                                      unsigned &, unsigned &, const MBBVector &,
Index: lib/CodeGen/RegUsageInfoCollector.cpp
===================================================================
--- lib/CodeGen/RegUsageInfoCollector.cpp
+++ lib/CodeGen/RegUsageInfoCollector.cpp
@@ -81,7 +81,7 @@
 bool RegUsageInfoCollector::runOnMachineFunction(MachineFunction &MF) {
   MachineRegisterInfo *MRI = &MF.getRegInfo();
   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
-  const TargetMachine &TM = MF.getTarget();
+  const LLVMTargetMachine &TM = MF.getTarget();
 
   DEBUG(dbgs() << " -------------------- " << getPassName()
                << " -------------------- \n");
Index: lib/CodeGen/SafeStack.cpp
===================================================================
--- lib/CodeGen/SafeStack.cpp
+++ lib/CodeGen/SafeStack.cpp
@@ -782,8 +782,6 @@
 }
 
 class SafeStackLegacyPass : public FunctionPass {
-  const TargetMachine *TM = nullptr;
-
 public:
   static char ID; // Pass identification, replacement for typeid..
 
@@ -812,8 +810,9 @@
       return false;
     }
 
-    TM = &getAnalysis<TargetPassConfig>().getTM<TargetMachine>();
-    auto *TL = TM->getSubtargetImpl(F)->getTargetLowering();
+    const LLVMTargetMachine &TM =
+      getAnalysis<TargetPassConfig>().getTM<LLVMTargetMachine>();
+    auto *TL = TM.getSubtargetImpl(F)->getTargetLowering();
     if (!TL)
       report_fatal_error("TargetLowering instance is required");
 
Index: lib/CodeGen/SelectionDAG/SelectionDAG.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -893,7 +893,7 @@
 }
 
 // EntryNode could meaningfully have debug info if we can find it...
-SelectionDAG::SelectionDAG(const TargetMachine &tm, CodeGenOpt::Level OL)
+SelectionDAG::SelectionDAG(const LLVMTargetMachine &tm, CodeGenOpt::Level OL)
     : TM(tm), OptLevel(OL),
       EntryNode(ISD::EntryToken, 0, DebugLoc(), getVTList(MVT::Other)),
       Root(getEntryNode()) {
Index: lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -298,7 +298,7 @@
 // SelectionDAGISel code
 //===----------------------------------------------------------------------===//
 
-SelectionDAGISel::SelectionDAGISel(TargetMachine &tm,
+SelectionDAGISel::SelectionDAGISel(LLVMTargetMachine &tm,
                                    CodeGenOpt::Level OL) :
   MachineFunctionPass(ID), TM(tm),
   FuncInfo(new FunctionLoweringInfo()),
Index: lib/CodeGen/SelectionDAG/TargetLowering.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -36,8 +36,8 @@
 #include <cctype>
 using namespace llvm;
 
-/// NOTE: The TargetMachine owns TLOF.
-TargetLowering::TargetLowering(const TargetMachine &tm)
+/// NOTE: The LLVMTargetMachine owns TLOF.
+TargetLowering::TargetLowering(const LLVMTargetMachine &tm)
   : TargetLoweringBase(tm) {}
 
 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
@@ -317,9 +317,8 @@
   return MCSymbolRefExpr::create(MF->getJTISymbol(JTI, Ctx), Ctx);
 }
 
-bool
-TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
-  const TargetMachine &TM = getTargetMachine();
+bool TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
+  const LLVMTargetMachine &TM = getTargetMachine();
   const GlobalValue *GV = GA->getGlobal();
 
   // If the address is not even local to this DSO we will have to load it from
Index: lib/CodeGen/StackProtector.cpp
===================================================================
--- lib/CodeGen/StackProtector.cpp
+++ lib/CodeGen/StackProtector.cpp
@@ -106,7 +106,7 @@
   DominatorTreeWrapperPass *DTWP =
       getAnalysisIfAvailable<DominatorTreeWrapperPass>();
   DT = DTWP ? &DTWP->getDomTree() : nullptr;
-  TM = &getAnalysis<TargetPassConfig>().getTM<TargetMachine>();
+  TM = &getAnalysis<TargetPassConfig>().getTM<LLVMTargetMachine>();
   Trip = TM->getTargetTriple();
   TLI = TM->getSubtargetImpl(Fn)->getTargetLowering();
   HasPrologue = false;
Index: lib/CodeGen/TargetLoweringBase.cpp
===================================================================
--- lib/CodeGen/TargetLoweringBase.cpp
+++ lib/CodeGen/TargetLoweringBase.cpp
@@ -486,8 +486,8 @@
   CCs[RTLIB::O_PPCF128] = ISD::SETEQ;
 }
 
-/// NOTE: The TargetMachine owns TLOF.
-TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm) : TM(tm) {
+/// NOTE: The LLVMTargetMachine owns TLOF.
+TargetLoweringBase::TargetLoweringBase(const LLVMTargetMachine &tm) : TM(tm) {
   initActions();
 
   // Perform these initializations only once.
Index: lib/LTO/UpdateCompilerUsed.cpp
===================================================================
--- lib/LTO/UpdateCompilerUsed.cpp
+++ lib/LTO/UpdateCompilerUsed.cpp
@@ -73,9 +73,7 @@
     SmallPtrSet<const TargetLowering *, 1> TLSet;
 
     for (const Function &F : TheModule) {
-      const TargetLowering *Lowering =
-          TM.getSubtargetImpl(F)->getTargetLowering();
-
+      const TargetLowering *Lowering = TM.getTargetLowering(F);
       if (Lowering && TLSet.insert(Lowering).second)
         // TargetLowering has info on library calls that CodeGen expects to be
         // available, both from the C runtime and compiler-rt.
Index: lib/Target/AArch64/AArch64AsmPrinter.cpp
===================================================================
--- lib/Target/AArch64/AArch64AsmPrinter.cpp
+++ lib/Target/AArch64/AArch64AsmPrinter.cpp
@@ -65,7 +65,7 @@
   const AArch64Subtarget *STI;
 
 public:
-  AArch64AsmPrinter(TargetMachine &TM, std::unique_ptr<MCStreamer> Streamer)
+  AArch64AsmPrinter(LLVMTargetMachine &TM, std::unique_ptr<MCStreamer> Streamer)
       : AsmPrinter(TM, std::move(Streamer)), MCInstLowering(OutContext, *this),
         SM(*this) {}
 
Index: lib/Target/AArch64/AArch64ISelLowering.h
===================================================================
--- lib/Target/AArch64/AArch64ISelLowering.h
+++ lib/Target/AArch64/AArch64ISelLowering.h
@@ -239,7 +239,7 @@
 
 class AArch64TargetLowering : public TargetLowering {
 public:
-  explicit AArch64TargetLowering(const TargetMachine &TM,
+  explicit AArch64TargetLowering(const LLVMTargetMachine &TM,
                                  const AArch64Subtarget &STI);
 
   /// Selects the correct CCAssignFn for a given CallingConvention value.
Index: lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- lib/Target/AArch64/AArch64ISelLowering.cpp
+++ lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -116,7 +116,7 @@
 /// Value type used for condition codes.
 static const MVT MVT_CC = MVT::i32;
 
-AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
+AArch64TargetLowering::AArch64TargetLowering(const LLVMTargetMachine &TM,
                                              const AArch64Subtarget &STI)
     : TargetLowering(TM), Subtarget(&STI) {
   // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
Index: lib/Target/AArch64/AArch64Subtarget.h
===================================================================
--- lib/Target/AArch64/AArch64Subtarget.h
+++ lib/Target/AArch64/AArch64Subtarget.h
@@ -155,7 +155,7 @@
   /// This constructor initializes the data members to match that
   /// of the specified triple.
   AArch64Subtarget(const Triple &TT, const std::string &CPU,
-                   const std::string &FS, const TargetMachine &TM,
+                   const std::string &FS, const LLVMTargetMachine &TM,
                    bool LittleEndian);
 
   const AArch64SelectionDAGInfo *getSelectionDAGInfo() const override {
Index: lib/Target/AArch64/AArch64Subtarget.cpp
===================================================================
--- lib/Target/AArch64/AArch64Subtarget.cpp
+++ lib/Target/AArch64/AArch64Subtarget.cpp
@@ -147,7 +147,8 @@
 
 AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
                                    const std::string &FS,
-                                   const TargetMachine &TM, bool LittleEndian)
+                                   const LLVMTargetMachine &TM,
+                                   bool LittleEndian)
     : AArch64GenSubtargetInfo(TT, CPU, FS),
       ReserveX18(TT.isOSDarwin() || TT.isOSWindows()), IsLittle(LittleEndian),
       TargetTriple(TT), FrameLowering(),
Index: lib/Target/AArch64/AArch64TargetTransformInfo.cpp
===================================================================
--- lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -26,7 +26,7 @@
 
 bool AArch64TTIImpl::areInlineCompatible(const Function *Caller,
                                          const Function *Callee) const {
-  const TargetMachine &TM = getTLI()->getTargetMachine();
+  const LLVMTargetMachine &TM = getTLI()->getTargetMachine();
 
   const FeatureBitset &CallerBits =
       TM.getSubtargetImpl(*Caller)->getFeatureBits();
Index: lib/Target/AMDGPU/AMDGPU.h
===================================================================
--- lib/Target/AMDGPU/AMDGPU.h
+++ lib/Target/AMDGPU/AMDGPU.h
@@ -19,12 +19,12 @@
 class AMDGPUTargetMachine;
 class FunctionPass;
 class GCNTargetMachine;
+class LLVMTargetMachine;
+class Module;
 class ModulePass;
 class Pass;
-class Target;
-class TargetMachine;
 class PassRegistry;
-class Module;
+class Target;
 
 // R600 Passes
 FunctionPass *createR600VectorRegMerger();
@@ -34,7 +34,8 @@
 FunctionPass *createR600Packetizer();
 FunctionPass *createR600ControlFlowFinalizer();
 FunctionPass *createAMDGPUCFGStructurizerPass();
-FunctionPass *createR600ISelDag(TargetMachine *TM, CodeGenOpt::Level OptLevel);
+FunctionPass *createR600ISelDag(LLVMTargetMachine *TM,
+                                CodeGenOpt::Level OptLevel);
 
 // SI Passes
 FunctionPass *createSIAnnotateControlFlowPass();
@@ -140,7 +141,7 @@
 
 Pass *createAMDGPUStructurizeCFGPass();
 FunctionPass *createAMDGPUISelDag(
-  TargetMachine *TM = nullptr,
+  LLVMTargetMachine *TM = nullptr,
   CodeGenOpt::Level OptLevel = CodeGenOpt::Default);
 ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true);
 ModulePass *createAMDGPUOpenCLImageTypeLoweringPass();
@@ -250,7 +251,7 @@
 namespace llvm {
 namespace AMDGPU {
 AMDGPUAS getAMDGPUAS(const Module &M);
-AMDGPUAS getAMDGPUAS(const TargetMachine &TM);
+AMDGPUAS getAMDGPUAS(const LLVMTargetMachine &TM);
 AMDGPUAS getAMDGPUAS(Triple T);
 } // namespace AMDGPU
 } // namespace llvm
Index: lib/Target/AMDGPU/AMDGPUAnnotateKernelFeatures.cpp
===================================================================
--- lib/Target/AMDGPU/AMDGPUAnnotateKernelFeatures.cpp
+++ lib/Target/AMDGPU/AMDGPUAnnotateKernelFeatures.cpp
@@ -45,7 +45,7 @@
 
 class AMDGPUAnnotateKernelFeatures : public CallGraphSCCPass {
 private:
-  const TargetMachine *TM = nullptr;
+  const LLVMTargetMachine *TM = nullptr;
   AMDGPUAS AS;
 
   bool addFeatureAttributes(Function &F);
@@ -319,7 +319,7 @@
     report_fatal_error("TargetMachine is required");
 
   AS = AMDGPU::getAMDGPUAS(CG.getModule());
-  TM = &TPC->getTM<TargetMachine>();
+  TM = &TPC->getTM<LLVMTargetMachine>();
   return false;
 }
 
Index: lib/Target/AMDGPU/AMDGPUAsmPrinter.h
===================================================================
--- lib/Target/AMDGPU/AMDGPUAsmPrinter.h
+++ lib/Target/AMDGPU/AMDGPUAsmPrinter.h
@@ -133,7 +133,7 @@
                                   uint64_t CodeSize);
 
 public:
-  explicit AMDGPUAsmPrinter(TargetMachine &TM,
+  explicit AMDGPUAsmPrinter(LLVMTargetMachine &TM,
                             std::unique_ptr<MCStreamer> Streamer);
 
   StringRef getPassName() const override;
Index: lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
===================================================================
--- lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+++ lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
@@ -79,9 +79,10 @@
 }
 
 static AsmPrinter *
-createAMDGPUAsmPrinterPass(TargetMachine &tm,
+createAMDGPUAsmPrinterPass(TargetMachine &TM,
                            std::unique_ptr<MCStreamer> &&Streamer) {
-  return new AMDGPUAsmPrinter(tm, std::move(Streamer));
+  LLVMTargetMachine &LLVMTM = static_cast<LLVMTargetMachine&>(TM);
+  return new AMDGPUAsmPrinter(LLVMTM, std::move(Streamer));
 }
 
 extern "C" void LLVMInitializeAMDGPUAsmPrinter() {
@@ -91,7 +92,7 @@
                                      createAMDGPUAsmPrinterPass);
 }
 
-AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM,
+AMDGPUAsmPrinter::AMDGPUAsmPrinter(LLVMTargetMachine &TM,
                                    std::unique_ptr<MCStreamer> Streamer)
   : AsmPrinter(TM, std::move(Streamer)) {
     AMDGPUASI = static_cast<AMDGPUTargetMachine*>(&TM)->getAMDGPUAS();
Index: lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
===================================================================
--- lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
+++ lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
@@ -540,7 +540,7 @@
   if (!TPC)
     return false;
 
-  const TargetMachine &TM = TPC->getTM<TargetMachine>();
+  const LLVMTargetMachine &TM = TPC->getTM<LLVMTargetMachine>();
   ST = &TM.getSubtarget<SISubtarget>(F);
   DA = &getAnalysis<DivergenceAnalysis>();
   HasUnsafeFPMath = hasUnsafeFPMath(F);
Index: lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
===================================================================
--- lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -71,7 +71,7 @@
   AMDGPUAS AMDGPUASI;
 
 public:
-  explicit AMDGPUDAGToDAGISel(TargetMachine *TM = nullptr,
+  explicit AMDGPUDAGToDAGISel(LLVMTargetMachine *TM = nullptr,
                               CodeGenOpt::Level OptLevel = CodeGenOpt::Default)
     : SelectionDAGISel(*TM, OptLevel) {
     AMDGPUASI = AMDGPU::getAMDGPUAS(*TM);
@@ -221,7 +221,7 @@
 
 class R600DAGToDAGISel : public AMDGPUDAGToDAGISel {
 public:
-  explicit R600DAGToDAGISel(TargetMachine *TM, CodeGenOpt::Level OptLevel) :
+  explicit R600DAGToDAGISel(LLVMTargetMachine *TM, CodeGenOpt::Level OptLevel) :
       AMDGPUDAGToDAGISel(TM, OptLevel) {}
 
   void Select(SDNode *N) override;
@@ -242,14 +242,14 @@
 
 /// \brief This pass converts a legalized DAG into a AMDGPU-specific
 // DAG, ready for instruction scheduling.
-FunctionPass *llvm::createAMDGPUISelDag(TargetMachine *TM,
+FunctionPass *llvm::createAMDGPUISelDag(LLVMTargetMachine *TM,
                                         CodeGenOpt::Level OptLevel) {
   return new AMDGPUDAGToDAGISel(TM, OptLevel);
 }
 
 /// \brief This pass converts a legalized DAG into a R600-specific
 // DAG, ready for instruction scheduling.
-FunctionPass *llvm::createR600ISelDag(TargetMachine *TM,
+FunctionPass *llvm::createR600ISelDag(LLVMTargetMachine *TM,
                                       CodeGenOpt::Level OptLevel) {
   return new R600DAGToDAGISel(TM, OptLevel);
 }
Index: lib/Target/AMDGPU/AMDGPUISelLowering.h
===================================================================
--- lib/Target/AMDGPU/AMDGPUISelLowering.h
+++ lib/Target/AMDGPU/AMDGPUISelLowering.h
@@ -120,7 +120,7 @@
   void analyzeFormalArgumentsCompute(CCState &State,
                               const SmallVectorImpl<ISD::InputArg> &Ins) const;
 public:
-  AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI);
+  AMDGPUTargetLowering(const LLVMTargetMachine &TM, const AMDGPUSubtarget &STI);
 
   bool mayIgnoreSignedZero(SDValue Op) const {
     if (getTargetMachine().Options.NoSignedZerosFPMath)
Index: lib/Target/AMDGPU/AMDGPUISelLowering.cpp
===================================================================
--- lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -151,7 +151,7 @@
   return false;
 }
 
-AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
+AMDGPUTargetLowering::AMDGPUTargetLowering(const LLVMTargetMachine &TM,
                                            const AMDGPUSubtarget &STI)
     : TargetLowering(TM), Subtarget(&STI) {
   AMDGPUASI = AMDGPU::getAMDGPUAS(TM);
Index: lib/Target/AMDGPU/AMDGPULowerIntrinsics.cpp
===================================================================
--- lib/Target/AMDGPU/AMDGPULowerIntrinsics.cpp
+++ lib/Target/AMDGPU/AMDGPULowerIntrinsics.cpp
@@ -116,7 +116,7 @@
   if (!TPC)
     return false;
 
-  const TargetMachine &TM = TPC->getTM<TargetMachine>();
+  const LLVMTargetMachine &TM = TPC->getTM<LLVMTargetMachine>();
   const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>(F);
   bool Changed = false;
 
Index: lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
===================================================================
--- lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+++ lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
@@ -68,7 +68,7 @@
 // FIXME: This can create globals so should be a module pass.
 class AMDGPUPromoteAlloca : public FunctionPass {
 private:
-  const TargetMachine *TM;
+  const LLVMTargetMachine *TM;
   Module *Mod = nullptr;
   const DataLayout *DL = nullptr;
   AMDGPUAS AS;
@@ -139,7 +139,7 @@
     return false;
 
   if (auto *TPC = getAnalysisIfAvailable<TargetPassConfig>())
-    TM = &TPC->getTM<TargetMachine>();
+    TM = &TPC->getTM<LLVMTargetMachine>();
   else
     return false;
 
Index: lib/Target/AMDGPU/AMDGPUSubtarget.h
===================================================================
--- lib/Target/AMDGPU/AMDGPUSubtarget.h
+++ lib/Target/AMDGPU/AMDGPUSubtarget.h
@@ -179,7 +179,7 @@
 
 public:
   AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
-                  const TargetMachine &TM);
+                  const LLVMTargetMachine &TM);
   ~AMDGPUSubtarget() override;
 
   AMDGPUSubtarget &initializeSubtargetDependencies(const Triple &TT,
@@ -614,7 +614,7 @@
 
 public:
   R600Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
-                const TargetMachine &TM);
+                const LLVMTargetMachine &TM);
 
   const R600InstrInfo *getInstrInfo() const override {
     return &InstrInfo;
@@ -659,7 +659,7 @@
 
 public:
   SISubtarget(const Triple &TT, StringRef CPU, StringRef FS,
-              const TargetMachine &TM);
+              const LLVMTargetMachine &TM);
 
   const SIInstrInfo *getInstrInfo() const override {
     return &InstrInfo;
Index: lib/Target/AMDGPU/AMDGPUSubtarget.cpp
===================================================================
--- lib/Target/AMDGPU/AMDGPUSubtarget.cpp
+++ lib/Target/AMDGPU/AMDGPUSubtarget.cpp
@@ -91,7 +91,7 @@
 }
 
 AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
-                                 const TargetMachine &TM)
+                                 const LLVMTargetMachine &TM)
   : AMDGPUGenSubtargetInfo(TT, GPU, FS),
     TargetTriple(TT),
     Gen(TT.getArch() == Triple::amdgcn ? SOUTHERN_ISLANDS : R600),
@@ -332,14 +332,14 @@
 }
 
 R600Subtarget::R600Subtarget(const Triple &TT, StringRef GPU, StringRef FS,
-                             const TargetMachine &TM) :
+                             const LLVMTargetMachine &TM) :
   AMDGPUSubtarget(TT, GPU, FS, TM),
   InstrInfo(*this),
   FrameLowering(TargetFrameLowering::StackGrowsUp, getStackAlignment(), 0),
   TLInfo(TM, *this) {}
 
 SISubtarget::SISubtarget(const Triple &TT, StringRef GPU, StringRef FS,
-                         const TargetMachine &TM)
+                         const LLVMTargetMachine &TM)
     : AMDGPUSubtarget(TT, GPU, FS, TM), InstrInfo(*this),
       FrameLowering(TargetFrameLowering::StackGrowsUp, getStackAlignment(), 0),
       TLInfo(TM, *this) {
Index: lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
===================================================================
--- lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+++ lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
@@ -577,7 +577,7 @@
 
 bool AMDGPUTTIImpl::areInlineCompatible(const Function *Caller,
                                         const Function *Callee) const {
-  const TargetMachine &TM = getTLI()->getTargetMachine();
+  const LLVMTargetMachine &TM = getTLI()->getTargetMachine();
   const FeatureBitset &CallerBits =
     TM.getSubtargetImpl(*Caller)->getFeatureBits();
   const FeatureBitset &CalleeBits =
Index: lib/Target/AMDGPU/R600ISelLowering.h
===================================================================
--- lib/Target/AMDGPU/R600ISelLowering.h
+++ lib/Target/AMDGPU/R600ISelLowering.h
@@ -24,7 +24,7 @@
 
 class R600TargetLowering final : public AMDGPUTargetLowering {
 public:
-  R600TargetLowering(const TargetMachine &TM, const R600Subtarget &STI);
+  R600TargetLowering(const LLVMTargetMachine &TM, const R600Subtarget &STI);
 
   const R600Subtarget *getSubtarget() const;
 
Index: lib/Target/AMDGPU/R600ISelLowering.cpp
===================================================================
--- lib/Target/AMDGPU/R600ISelLowering.cpp
+++ lib/Target/AMDGPU/R600ISelLowering.cpp
@@ -50,7 +50,7 @@
 
 using namespace llvm;
 
-R600TargetLowering::R600TargetLowering(const TargetMachine &TM,
+R600TargetLowering::R600TargetLowering(const LLVMTargetMachine &TM,
                                        const R600Subtarget &STI)
     : AMDGPUTargetLowering(TM, STI), Gen(STI.getGeneration()) {
   addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass);
Index: lib/Target/AMDGPU/SIISelLowering.h
===================================================================
--- lib/Target/AMDGPU/SIISelLowering.h
+++ lib/Target/AMDGPU/SIISelLowering.h
@@ -144,7 +144,7 @@
   bool shouldEmitPCReloc(const GlobalValue *GV) const;
 
 public:
-  SITargetLowering(const TargetMachine &tm, const SISubtarget &STI);
+  SITargetLowering(const LLVMTargetMachine &tm, const SISubtarget &STI);
 
   const SISubtarget *getSubtarget() const;
 
Index: lib/Target/AMDGPU/SIISelLowering.cpp
===================================================================
--- lib/Target/AMDGPU/SIISelLowering.cpp
+++ lib/Target/AMDGPU/SIISelLowering.cpp
@@ -104,7 +104,7 @@
   llvm_unreachable("Cannot allocate sgpr");
 }
 
-SITargetLowering::SITargetLowering(const TargetMachine &TM,
+SITargetLowering::SITargetLowering(const LLVMTargetMachine &TM,
                                    const SISubtarget &STI)
     : AMDGPUTargetLowering(TM, STI) {
   addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
Index: lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
===================================================================
--- lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -839,7 +839,7 @@
   return AS;
 }
 
-AMDGPUAS getAMDGPUAS(const TargetMachine &M) {
+AMDGPUAS getAMDGPUAS(const LLVMTargetMachine &M) {
   return getAMDGPUAS(M.getTargetTriple());
 }
 
Index: lib/Target/ARM/ARMAsmPrinter.h
===================================================================
--- lib/Target/ARM/ARMAsmPrinter.h
+++ lib/Target/ARM/ARMAsmPrinter.h
@@ -67,7 +67,7 @@
   SmallPtrSet<const GlobalVariable*,2> EmittedPromotedGlobalLabels;
 
 public:
-  explicit ARMAsmPrinter(TargetMachine &TM,
+  explicit ARMAsmPrinter(LLVMTargetMachine &TM,
                          std::unique_ptr<MCStreamer> Streamer);
 
   StringRef getPassName() const override {
Index: lib/Target/ARM/ARMAsmPrinter.cpp
===================================================================
--- lib/Target/ARM/ARMAsmPrinter.cpp
+++ lib/Target/ARM/ARMAsmPrinter.cpp
@@ -56,7 +56,7 @@
 
 #define DEBUG_TYPE "asm-printer"
 
-ARMAsmPrinter::ARMAsmPrinter(TargetMachine &TM,
+ARMAsmPrinter::ARMAsmPrinter(LLVMTargetMachine &TM,
                              std::unique_ptr<MCStreamer> Streamer)
     : AsmPrinter(TM, std::move(Streamer)), AFI(nullptr), MCP(nullptr),
       InConstantPool(false), OptimizationGoals(-1) {}
Index: lib/Target/ARM/ARMISelLowering.h
===================================================================
--- lib/Target/ARM/ARMISelLowering.h
+++ lib/Target/ARM/ARMISelLowering.h
@@ -42,11 +42,11 @@
 class GlobalValue;
 class InstrItineraryData;
 class Instruction;
+class LLVMTargetMachine;
 class MachineBasicBlock;
 class MachineInstr;
 class SelectionDAG;
 class TargetLibraryInfo;
-class TargetMachine;
 class TargetRegisterInfo;
 class VectorType;
 
@@ -268,7 +268,7 @@
 
   class ARMTargetLowering : public TargetLowering {
   public:
-    explicit ARMTargetLowering(const TargetMachine &TM,
+    explicit ARMTargetLowering(const LLVMTargetMachine &TM,
                                const ARMSubtarget &STI);
 
     unsigned getJumpTableEncoding() const override;
Index: lib/Target/ARM/ARMISelLowering.cpp
===================================================================
--- lib/Target/ARM/ARMISelLowering.cpp
+++ lib/Target/ARM/ARMISelLowering.cpp
@@ -220,7 +220,7 @@
   addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
 }
 
-ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
+ARMTargetLowering::ARMTargetLowering(const LLVMTargetMachine &TM,
                                      const ARMSubtarget &STI)
     : TargetLowering(TM), Subtarget(&STI) {
   RegInfo = Subtarget->getRegisterInfo();
Index: lib/Target/ARM/ARMTargetObjectFile.cpp
===================================================================
--- lib/Target/ARM/ARMTargetObjectFile.cpp
+++ lib/Target/ARM/ARMTargetObjectFile.cpp
@@ -66,9 +66,12 @@
 
 static bool isExecuteOnlyFunction(const GlobalObject *GO, SectionKind SK,
                                   const TargetMachine &TM) {
-  if (const Function *F = dyn_cast<Function>(GO))
-    if (TM.getSubtarget<ARMSubtarget>(*F).genExecuteOnly() && SK.isText())
+  if (const Function *F = dyn_cast<Function>(GO)) {
+    const ARMBaseTargetMachine &ARM_TM =
+      static_cast<const ARMBaseTargetMachine &>(TM);
+    if (ARM_TM.getSubtarget<ARMSubtarget>(*F).genExecuteOnly() && SK.isText())
       return true;
+  }
   return false;
 }
 
Index: lib/Target/ARM/ARMTargetTransformInfo.cpp
===================================================================
--- lib/Target/ARM/ARMTargetTransformInfo.cpp
+++ lib/Target/ARM/ARMTargetTransformInfo.cpp
@@ -38,7 +38,7 @@
 
 bool ARMTTIImpl::areInlineCompatible(const Function *Caller,
                                      const Function *Callee) const {
-  const TargetMachine &TM = getTLI()->getTargetMachine();
+  const LLVMTargetMachine &TM = getTLI()->getTargetMachine();
   const FeatureBitset &CallerBits =
       TM.getSubtargetImpl(*Caller)->getFeatureBits();
   const FeatureBitset &CalleeBits =
Index: lib/Target/BPF/BPFAsmPrinter.cpp
===================================================================
--- lib/Target/BPF/BPFAsmPrinter.cpp
+++ lib/Target/BPF/BPFAsmPrinter.cpp
@@ -35,7 +35,7 @@
 namespace {
 class BPFAsmPrinter : public AsmPrinter {
 public:
-  explicit BPFAsmPrinter(TargetMachine &TM,
+  explicit BPFAsmPrinter(LLVMTargetMachine &TM,
                          std::unique_ptr<MCStreamer> Streamer)
       : AsmPrinter(TM, std::move(Streamer)) {}
 
Index: lib/Target/BPF/BPFISelLowering.h
===================================================================
--- lib/Target/BPF/BPFISelLowering.h
+++ lib/Target/BPF/BPFISelLowering.h
@@ -34,7 +34,8 @@
 
 class BPFTargetLowering : public TargetLowering {
 public:
-  explicit BPFTargetLowering(const TargetMachine &TM, const BPFSubtarget &STI);
+  explicit BPFTargetLowering(const LLVMTargetMachine &TM,
+                             const BPFSubtarget &STI);
 
   // Provide custom lowering hooks for some operations.
   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
Index: lib/Target/BPF/BPFISelLowering.cpp
===================================================================
--- lib/Target/BPF/BPFISelLowering.cpp
+++ lib/Target/BPF/BPFISelLowering.cpp
@@ -51,7 +51,7 @@
       DiagnosticInfoUnsupported(*MF.getFunction(), Str, DL.getDebugLoc()));
 }
 
-BPFTargetLowering::BPFTargetLowering(const TargetMachine &TM,
+BPFTargetLowering::BPFTargetLowering(const LLVMTargetMachine &TM,
                                      const BPFSubtarget &STI)
     : TargetLowering(TM) {
 
Index: lib/Target/BPF/BPFSubtarget.h
===================================================================
--- lib/Target/BPF/BPFSubtarget.h
+++ lib/Target/BPF/BPFSubtarget.h
@@ -51,7 +51,7 @@
   // This constructor initializes the data members to match that
   // of the specified triple.
   BPFSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
-               const TargetMachine &TM);
+               const LLVMTargetMachine &TM);
 
   BPFSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
 
Index: lib/Target/BPF/BPFSubtarget.cpp
===================================================================
--- lib/Target/BPF/BPFSubtarget.cpp
+++ lib/Target/BPF/BPFSubtarget.cpp
@@ -49,7 +49,7 @@
 }
 
 BPFSubtarget::BPFSubtarget(const Triple &TT, const std::string &CPU,
-                           const std::string &FS, const TargetMachine &TM)
+                           const std::string &FS, const LLVMTargetMachine &TM)
     : BPFGenSubtargetInfo(TT, CPU, FS), InstrInfo(),
       FrameLowering(initializeSubtargetDependencies(CPU, FS)),
       TLInfo(TM, *this) {}
Index: lib/Target/Hexagon/HexagonAsmPrinter.h
===================================================================
--- lib/Target/Hexagon/HexagonAsmPrinter.h
+++ lib/Target/Hexagon/HexagonAsmPrinter.h
@@ -25,13 +25,13 @@
 class MachineInstr;
 class MCInst;
 class raw_ostream;
-class TargetMachine;
+class LLVMTargetMachine;
 
   class HexagonAsmPrinter : public AsmPrinter {
     const HexagonSubtarget *Subtarget = nullptr;
 
   public:
-    explicit HexagonAsmPrinter(TargetMachine &TM,
+    explicit HexagonAsmPrinter(LLVMTargetMachine &TM,
                                std::unique_ptr<MCStreamer> Streamer);
 
     bool runOnMachineFunction(MachineFunction &Fn) override {
Index: lib/Target/Hexagon/HexagonAsmPrinter.cpp
===================================================================
--- lib/Target/Hexagon/HexagonAsmPrinter.cpp
+++ lib/Target/Hexagon/HexagonAsmPrinter.cpp
@@ -76,7 +76,7 @@
   return Pair;
 }
 
-HexagonAsmPrinter::HexagonAsmPrinter(TargetMachine &TM,
+HexagonAsmPrinter::HexagonAsmPrinter(LLVMTargetMachine &TM,
                                      std::unique_ptr<MCStreamer> Streamer)
     : AsmPrinter(TM, std::move(Streamer)) {}
 
Index: lib/Target/Hexagon/HexagonISelLowering.h
===================================================================
--- lib/Target/Hexagon/HexagonISelLowering.h
+++ lib/Target/Hexagon/HexagonISelLowering.h
@@ -86,7 +86,7 @@
     void promoteLdStType(MVT VT, MVT PromotedLdStVT);
 
   public:
-    explicit HexagonTargetLowering(const TargetMachine &TM,
+    explicit HexagonTargetLowering(const LLVMTargetMachine &TM,
                                    const HexagonSubtarget &ST);
 
     /// IsEligibleForTailCallOptimization - Check whether the call is eligible
Index: lib/Target/Hexagon/HexagonISelLowering.cpp
===================================================================
--- lib/Target/Hexagon/HexagonISelLowering.cpp
+++ lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -1704,7 +1704,7 @@
 // TargetLowering Implementation
 //===----------------------------------------------------------------------===//
 
-HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
+HexagonTargetLowering::HexagonTargetLowering(const LLVMTargetMachine &TM,
                                              const HexagonSubtarget &ST)
     : TargetLowering(TM), HTM(static_cast<const HexagonTargetMachine&>(TM)),
       Subtarget(ST) {
Index: lib/Target/Hexagon/HexagonSubtarget.h
===================================================================
--- lib/Target/Hexagon/HexagonSubtarget.h
+++ lib/Target/Hexagon/HexagonSubtarget.h
@@ -36,10 +36,10 @@
 
 namespace llvm {
 
+class LLVMTargetMachine;
 class MachineInstr;
 class SDep;
 class SUnit;
-class TargetMachine;
 class Triple;
 
 class HexagonSubtarget : public HexagonGenSubtargetInfo {
@@ -84,7 +84,7 @@
 
 public:
   HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
-                   const TargetMachine &TM);
+                   const LLVMTargetMachine &TM);
 
   /// getInstrItins - Return the instruction itineraries based on subtarget
   /// selection.
Index: lib/Target/Hexagon/HexagonSubtarget.cpp
===================================================================
--- lib/Target/Hexagon/HexagonSubtarget.cpp
+++ lib/Target/Hexagon/HexagonSubtarget.cpp
@@ -99,7 +99,7 @@
 
 
 HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU,
-                                   StringRef FS, const TargetMachine &TM)
+                                   StringRef FS, const LLVMTargetMachine &TM)
     : HexagonGenSubtargetInfo(TT, CPU, FS),
       CPUString(Hexagon_MC::selectHexagonCPU(TT, CPU)),
       InstrInfo(initializeSubtargetDependencies(CPU, FS)),
Index: lib/Target/Lanai/LanaiAsmPrinter.cpp
===================================================================
--- lib/Target/Lanai/LanaiAsmPrinter.cpp
+++ lib/Target/Lanai/LanaiAsmPrinter.cpp
@@ -41,7 +41,7 @@
 namespace {
 class LanaiAsmPrinter : public AsmPrinter {
 public:
-  explicit LanaiAsmPrinter(TargetMachine &TM,
+  explicit LanaiAsmPrinter(LLVMTargetMachine &TM,
                            std::unique_ptr<MCStreamer> Streamer)
       : AsmPrinter(TM, std::move(Streamer)) {}
 
Index: lib/Target/Lanai/LanaiISelLowering.h
===================================================================
--- lib/Target/Lanai/LanaiISelLowering.h
+++ lib/Target/Lanai/LanaiISelLowering.h
@@ -67,7 +67,7 @@
 
 class LanaiTargetLowering : public TargetLowering {
 public:
-  LanaiTargetLowering(const TargetMachine &TM, const LanaiSubtarget &STI);
+  LanaiTargetLowering(const LLVMTargetMachine &TM, const LanaiSubtarget &STI);
 
   // LowerOperation - Provide custom lowering hooks for some operations.
   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
Index: lib/Target/Lanai/LanaiISelLowering.cpp
===================================================================
--- lib/Target/Lanai/LanaiISelLowering.cpp
+++ lib/Target/Lanai/LanaiISelLowering.cpp
@@ -71,7 +71,7 @@
              "multiplication instead of calling library function [default=14]"),
     cl::init(14));
 
-LanaiTargetLowering::LanaiTargetLowering(const TargetMachine &TM,
+LanaiTargetLowering::LanaiTargetLowering(const LLVMTargetMachine &TM,
                                          const LanaiSubtarget &STI)
     : TargetLowering(TM) {
   // Set up the register classes.
Index: lib/Target/Lanai/LanaiSubtarget.h
===================================================================
--- lib/Target/Lanai/LanaiSubtarget.h
+++ lib/Target/Lanai/LanaiSubtarget.h
@@ -33,7 +33,7 @@
   // This constructor initializes the data members to match that
   // of the specified triple.
   LanaiSubtarget(const Triple &TargetTriple, StringRef Cpu,
-                 StringRef FeatureString, const TargetMachine &TM,
+                 StringRef FeatureString, const LLVMTargetMachine &TM,
                  const TargetOptions &Options, CodeModel::Model CodeModel,
                  CodeGenOpt::Level OptLevel);
 
Index: lib/Target/Lanai/LanaiSubtarget.cpp
===================================================================
--- lib/Target/Lanai/LanaiSubtarget.cpp
+++ lib/Target/Lanai/LanaiSubtarget.cpp
@@ -38,7 +38,8 @@
 }
 
 LanaiSubtarget::LanaiSubtarget(const Triple &TargetTriple, StringRef Cpu,
-                               StringRef FeatureString, const TargetMachine &TM,
+                               StringRef FeatureString,
+                               const LLVMTargetMachine &TM,
                                const TargetOptions & /*Options*/,
                                CodeModel::Model /*CodeModel*/,
                                CodeGenOpt::Level /*OptLevel*/)
Index: lib/Target/MSP430/MSP430AsmPrinter.cpp
===================================================================
--- lib/Target/MSP430/MSP430AsmPrinter.cpp
+++ lib/Target/MSP430/MSP430AsmPrinter.cpp
@@ -39,7 +39,8 @@
 namespace {
   class MSP430AsmPrinter : public AsmPrinter {
   public:
-    MSP430AsmPrinter(TargetMachine &TM, std::unique_ptr<MCStreamer> Streamer)
+    MSP430AsmPrinter(LLVMTargetMachine &TM,
+                     std::unique_ptr<MCStreamer> Streamer)
         : AsmPrinter(TM, std::move(Streamer)) {}
 
     StringRef getPassName() const override { return "MSP430 Assembly Printer"; }
Index: lib/Target/MSP430/MSP430ISelLowering.h
===================================================================
--- lib/Target/MSP430/MSP430ISelLowering.h
+++ lib/Target/MSP430/MSP430ISelLowering.h
@@ -69,7 +69,7 @@
   class MSP430Subtarget;
   class MSP430TargetLowering : public TargetLowering {
   public:
-    explicit MSP430TargetLowering(const TargetMachine &TM,
+    explicit MSP430TargetLowering(const LLVMTargetMachine &TM,
                                   const MSP430Subtarget &STI);
 
     MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
Index: lib/Target/MSP430/MSP430ISelLowering.cpp
===================================================================
--- lib/Target/MSP430/MSP430ISelLowering.cpp
+++ lib/Target/MSP430/MSP430ISelLowering.cpp
@@ -38,7 +38,7 @@
 
 #define DEBUG_TYPE "msp430-lower"
 
-MSP430TargetLowering::MSP430TargetLowering(const TargetMachine &TM,
+MSP430TargetLowering::MSP430TargetLowering(const LLVMTargetMachine &TM,
                                            const MSP430Subtarget &STI)
     : TargetLowering(TM) {
 
Index: lib/Target/MSP430/MSP430Subtarget.h
===================================================================
--- lib/Target/MSP430/MSP430Subtarget.h
+++ lib/Target/MSP430/MSP430Subtarget.h
@@ -49,7 +49,7 @@
   /// of the specified triple.
   ///
   MSP430Subtarget(const Triple &TT, const std::string &CPU,
-                  const std::string &FS, const TargetMachine &TM);
+                  const std::string &FS, const LLVMTargetMachine &TM);
 
   MSP430Subtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
 
Index: lib/Target/MSP430/MSP430Subtarget.cpp
===================================================================
--- lib/Target/MSP430/MSP430Subtarget.cpp
+++ lib/Target/MSP430/MSP430Subtarget.cpp
@@ -57,6 +57,7 @@
 }
 
 MSP430Subtarget::MSP430Subtarget(const Triple &TT, const std::string &CPU,
-                                 const std::string &FS, const TargetMachine &TM)
+                                 const std::string &FS,
+                                 const LLVMTargetMachine &TM)
     : MSP430GenSubtargetInfo(TT, CPU, FS), FrameLowering(),
       InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this) {}
Index: lib/Target/Mips/MipsAsmPrinter.h
===================================================================
--- lib/Target/Mips/MipsAsmPrinter.h
+++ lib/Target/Mips/MipsAsmPrinter.h
@@ -122,7 +122,7 @@
   const MipsFunctionInfo *MipsFI;
   MipsMCInstLower MCInstLowering;
 
-  explicit MipsAsmPrinter(TargetMachine &TM,
+  explicit MipsAsmPrinter(LLVMTargetMachine &TM,
                           std::unique_ptr<MCStreamer> Streamer)
       : AsmPrinter(TM, std::move(Streamer)), MCInstLowering(*this) {}
 
Index: lib/Target/NVPTX/NVPTXAsmPrinter.h
===================================================================
--- lib/Target/NVPTX/NVPTXAsmPrinter.h
+++ lib/Target/NVPTX/NVPTXAsmPrinter.h
@@ -335,7 +335,7 @@
   bool EmitGeneric;
 
 public:
-  NVPTXAsmPrinter(TargetMachine &TM, std::unique_ptr<MCStreamer> Streamer)
+  NVPTXAsmPrinter(LLVMTargetMachine &TM, std::unique_ptr<MCStreamer> Streamer)
       : AsmPrinter(TM, std::move(Streamer)),
         EmitGeneric(static_cast<NVPTXTargetMachine &>(TM).getDrvInterface() ==
                     NVPTX::CUDA) {}
Index: lib/Target/NVPTX/NVPTXAsmPrinter.cpp
===================================================================
--- lib/Target/NVPTX/NVPTXAsmPrinter.cpp
+++ lib/Target/NVPTX/NVPTXAsmPrinter.cpp
@@ -259,7 +259,7 @@
 
 void NVPTXAsmPrinter::lowerImageHandleSymbol(unsigned Index, MCOperand &MCOp) {
   // Ewwww
-  TargetMachine &TM = const_cast<TargetMachine&>(MF->getTarget());
+  LLVMTargetMachine &TM = const_cast<LLVMTargetMachine&>(MF->getTarget());
   NVPTXTargetMachine &nvTM = static_cast<NVPTXTargetMachine&>(TM);
   const NVPTXMachineFunctionInfo *MFI = MF->getInfo<NVPTXMachineFunctionInfo>();
   const char *Sym = MFI->getImageHandleSymbol(Index);
Index: lib/Target/PowerPC/PPCAsmPrinter.cpp
===================================================================
--- lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -81,7 +81,7 @@
   StackMaps SM;
 
 public:
-  explicit PPCAsmPrinter(TargetMachine &TM,
+  explicit PPCAsmPrinter(LLVMTargetMachine &TM,
                          std::unique_ptr<MCStreamer> Streamer)
       : AsmPrinter(TM, std::move(Streamer)), SM(*this) {}
 
@@ -122,7 +122,7 @@
   /// PPCLinuxAsmPrinter - PowerPC assembly printer, customized for Linux
   class PPCLinuxAsmPrinter : public PPCAsmPrinter {
   public:
-    explicit PPCLinuxAsmPrinter(TargetMachine &TM,
+    explicit PPCLinuxAsmPrinter(LLVMTargetMachine &TM,
                                 std::unique_ptr<MCStreamer> Streamer)
         : PPCAsmPrinter(TM, std::move(Streamer)) {}
 
@@ -144,7 +144,7 @@
   /// OS X
   class PPCDarwinAsmPrinter : public PPCAsmPrinter {
   public:
-    explicit PPCDarwinAsmPrinter(TargetMachine &TM,
+    explicit PPCDarwinAsmPrinter(LLVMTargetMachine &TM,
                                  std::unique_ptr<MCStreamer> Streamer)
         : PPCAsmPrinter(TM, std::move(Streamer)) {}
 
@@ -1595,11 +1595,12 @@
 /// Darwin assembler can deal with.
 ///
 static AsmPrinter *
-createPPCAsmPrinterPass(TargetMachine &tm,
+createPPCAsmPrinterPass(TargetMachine &TM,
                         std::unique_ptr<MCStreamer> &&Streamer) {
-  if (tm.getTargetTriple().isMacOSX())
-    return new PPCDarwinAsmPrinter(tm, std::move(Streamer));
-  return new PPCLinuxAsmPrinter(tm, std::move(Streamer));
+  LLVMTargetMachine &LLVMTM = static_cast<LLVMTargetMachine&>(TM);
+  if (LLVMTM.getTargetTriple().isMacOSX())
+    return new PPCDarwinAsmPrinter(LLVMTM, std::move(Streamer));
+  return new PPCLinuxAsmPrinter(LLVMTM, std::move(Streamer));
 }
 
 // Force static initialization.
Index: lib/Target/Sparc/SparcAsmPrinter.cpp
===================================================================
--- lib/Target/Sparc/SparcAsmPrinter.cpp
+++ lib/Target/Sparc/SparcAsmPrinter.cpp
@@ -42,7 +42,7 @@
           *OutStreamer->getTargetStreamer());
     }
   public:
-    explicit SparcAsmPrinter(TargetMachine &TM,
+    explicit SparcAsmPrinter(LLVMTargetMachine &TM,
                              std::unique_ptr<MCStreamer> Streamer)
         : AsmPrinter(TM, std::move(Streamer)) {}
 
Index: lib/Target/Sparc/SparcISelLowering.h
===================================================================
--- lib/Target/Sparc/SparcISelLowering.h
+++ lib/Target/Sparc/SparcISelLowering.h
@@ -57,7 +57,7 @@
   class SparcTargetLowering : public TargetLowering {
     const SparcSubtarget *Subtarget;
   public:
-    SparcTargetLowering(const TargetMachine &TM, const SparcSubtarget &STI);
+    SparcTargetLowering(const LLVMTargetMachine &TM, const SparcSubtarget &STI);
     SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
     
     bool useSoftFloat() const override;
Index: lib/Target/Sparc/SparcISelLowering.cpp
===================================================================
--- lib/Target/Sparc/SparcISelLowering.cpp
+++ lib/Target/Sparc/SparcISelLowering.cpp
@@ -1447,7 +1447,7 @@
   }
 }
 
-SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
+SparcTargetLowering::SparcTargetLowering(const LLVMTargetMachine &TM,
                                          const SparcSubtarget &STI)
     : TargetLowering(TM), Subtarget(&STI) {
   MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());
Index: lib/Target/Sparc/SparcSubtarget.h
===================================================================
--- lib/Target/Sparc/SparcSubtarget.h
+++ lib/Target/Sparc/SparcSubtarget.h
@@ -59,7 +59,8 @@
 
 public:
   SparcSubtarget(const Triple &TT, const std::string &CPU,
-                 const std::string &FS, const TargetMachine &TM, bool is64bit);
+                 const std::string &FS, const LLVMTargetMachine &TM,
+                 bool is64bit);
 
   const SparcInstrInfo *getInstrInfo() const override { return &InstrInfo; }
   const TargetFrameLowering *getFrameLowering() const override {
Index: lib/Target/Sparc/SparcSubtarget.cpp
===================================================================
--- lib/Target/Sparc/SparcSubtarget.cpp
+++ lib/Target/Sparc/SparcSubtarget.cpp
@@ -63,8 +63,8 @@
 }
 
 SparcSubtarget::SparcSubtarget(const Triple &TT, const std::string &CPU,
-                               const std::string &FS, const TargetMachine &TM,
-                               bool is64Bit)
+                               const std::string &FS,
+                               const LLVMTargetMachine &TM, bool is64Bit)
     : SparcGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT), Is64Bit(is64Bit),
       InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
       FrameLowering(*this) {}
Index: lib/Target/SystemZ/SystemZAsmPrinter.h
===================================================================
--- lib/Target/SystemZ/SystemZAsmPrinter.h
+++ lib/Target/SystemZ/SystemZAsmPrinter.h
@@ -23,7 +23,7 @@
 
 class LLVM_LIBRARY_VISIBILITY SystemZAsmPrinter : public AsmPrinter {
 public:
-  SystemZAsmPrinter(TargetMachine &TM, std::unique_ptr<MCStreamer> Streamer)
+  SystemZAsmPrinter(LLVMTargetMachine &TM, std::unique_ptr<MCStreamer> Streamer)
       : AsmPrinter(TM, std::move(Streamer)) {}
 
   // Override AsmPrinter.
Index: lib/Target/SystemZ/SystemZISelLowering.h
===================================================================
--- lib/Target/SystemZ/SystemZISelLowering.h
+++ lib/Target/SystemZ/SystemZISelLowering.h
@@ -364,7 +364,7 @@
 
 class SystemZTargetLowering : public TargetLowering {
 public:
-  explicit SystemZTargetLowering(const TargetMachine &TM,
+  explicit SystemZTargetLowering(const LLVMTargetMachine &TM,
                                  const SystemZSubtarget &STI);
 
   // Override TargetLowering.
Index: lib/Target/SystemZ/SystemZISelLowering.cpp
===================================================================
--- lib/Target/SystemZ/SystemZISelLowering.cpp
+++ lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -84,7 +84,7 @@
   return Op;
 }
 
-SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
+SystemZTargetLowering::SystemZTargetLowering(const LLVMTargetMachine &TM,
                                              const SystemZSubtarget &STI)
     : TargetLowering(TM), Subtarget(STI) {
   MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());
Index: lib/Target/SystemZ/SystemZSubtarget.h
===================================================================
--- lib/Target/SystemZ/SystemZSubtarget.h
+++ lib/Target/SystemZ/SystemZSubtarget.h
@@ -75,7 +75,7 @@
                                                     StringRef FS);
 public:
   SystemZSubtarget(const Triple &TT, const std::string &CPU,
-                   const std::string &FS, const TargetMachine &TM);
+                   const std::string &FS, const LLVMTargetMachine &TM);
 
   const TargetFrameLowering *getFrameLowering() const override {
     return &FrameLowering;
Index: lib/Target/SystemZ/SystemZSubtarget.cpp
===================================================================
--- lib/Target/SystemZ/SystemZSubtarget.cpp
+++ lib/Target/SystemZ/SystemZSubtarget.cpp
@@ -34,7 +34,7 @@
 
 SystemZSubtarget::SystemZSubtarget(const Triple &TT, const std::string &CPU,
                                    const std::string &FS,
-                                   const TargetMachine &TM)
+                                   const LLVMTargetMachine &TM)
     : SystemZGenSubtargetInfo(TT, CPU, FS), HasDistinctOps(false),
       HasLoadStoreOnCond(false), HasHighWord(false), HasFPExtension(false),
       HasPopulationCount(false), HasMessageSecurityAssist3(false),
Index: lib/Target/X86/X86AsmPrinter.h
===================================================================
--- lib/Target/X86/X86AsmPrinter.h
+++ lib/Target/X86/X86AsmPrinter.h
@@ -100,7 +100,7 @@
   void EmitXRayTable();
 
 public:
-  explicit X86AsmPrinter(TargetMachine &TM,
+  explicit X86AsmPrinter(LLVMTargetMachine &TM,
                          std::unique_ptr<MCStreamer> Streamer)
       : AsmPrinter(TM, std::move(Streamer)), SM(*this), FM(*this) {}
 
Index: lib/Target/X86/X86Subtarget.h
===================================================================
--- lib/Target/X86/X86Subtarget.h
+++ lib/Target/X86/X86Subtarget.h
@@ -79,7 +79,7 @@
   /// Which PIC style to use
   PICStyles::Style PICStyle;
 
-  const TargetMachine &TM;
+  const LLVMTargetMachine &TM;
 
   /// SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
   X86SSEEnum X86SSELevel;
Index: lib/Target/X86/X86TargetTransformInfo.cpp
===================================================================
--- lib/Target/X86/X86TargetTransformInfo.cpp
+++ lib/Target/X86/X86TargetTransformInfo.cpp
@@ -2522,7 +2522,7 @@
 
 bool X86TTIImpl::areInlineCompatible(const Function *Caller,
                                      const Function *Callee) const {
-  const TargetMachine &TM = getTLI()->getTargetMachine();
+  const LLVMTargetMachine &TM = getTLI()->getTargetMachine();
 
   // Work this as a subsetting of subtarget features.
   const FeatureBitset &CallerBits =
Index: lib/Target/XCore/XCoreAsmPrinter.cpp
===================================================================
--- lib/Target/XCore/XCoreAsmPrinter.cpp
+++ lib/Target/XCore/XCoreAsmPrinter.cpp
@@ -54,7 +54,7 @@
     XCoreTargetStreamer &getTargetStreamer();
 
   public:
-    explicit XCoreAsmPrinter(TargetMachine &TM,
+    explicit XCoreAsmPrinter(LLVMTargetMachine &TM,
                              std::unique_ptr<MCStreamer> Streamer)
         : AsmPrinter(TM, std::move(Streamer)), MCInstLowering(*this) {}
 
Index: lib/Target/XCore/XCoreISelLowering.h
===================================================================
--- lib/Target/XCore/XCoreISelLowering.h
+++ lib/Target/XCore/XCoreISelLowering.h
@@ -93,7 +93,7 @@
   class XCoreTargetLowering : public TargetLowering
   {
   public:
-    explicit XCoreTargetLowering(const TargetMachine &TM,
+    explicit XCoreTargetLowering(const LLVMTargetMachine &TM,
                                  const XCoreSubtarget &Subtarget);
 
     using TargetLowering::isZExtFree;
@@ -141,7 +141,7 @@
     }
 
   private:
-    const TargetMachine &TM;
+    const LLVMTargetMachine &TM;
     const XCoreSubtarget &Subtarget;
 
     // Lower Operand helpers
Index: lib/Target/XCore/XCoreISelLowering.cpp
===================================================================
--- lib/Target/XCore/XCoreISelLowering.cpp
+++ lib/Target/XCore/XCoreISelLowering.cpp
@@ -70,7 +70,7 @@
   return nullptr;
 }
 
-XCoreTargetLowering::XCoreTargetLowering(const TargetMachine &TM,
+XCoreTargetLowering::XCoreTargetLowering(const LLVMTargetMachine &TM,
                                          const XCoreSubtarget &Subtarget)
     : TargetLowering(TM), TM(TM), Subtarget(Subtarget) {
 
Index: lib/Target/XCore/XCoreSubtarget.h
===================================================================
--- lib/Target/XCore/XCoreSubtarget.h
+++ lib/Target/XCore/XCoreSubtarget.h
@@ -41,7 +41,7 @@
   /// of the specified triple.
   ///
   XCoreSubtarget(const Triple &TT, const std::string &CPU,
-                 const std::string &FS, const TargetMachine &TM);
+                 const std::string &FS, const LLVMTargetMachine &TM);
 
   /// ParseSubtargetFeatures - Parses features string setting specified 
   /// subtarget options.  Definition of function is auto generated by tblgen.
Index: lib/Target/XCore/XCoreSubtarget.cpp
===================================================================
--- lib/Target/XCore/XCoreSubtarget.cpp
+++ lib/Target/XCore/XCoreSubtarget.cpp
@@ -26,6 +26,7 @@
 void XCoreSubtarget::anchor() { }
 
 XCoreSubtarget::XCoreSubtarget(const Triple &TT, const std::string &CPU,
-                               const std::string &FS, const TargetMachine &TM)
+                               const std::string &FS,
+                               const LLVMTargetMachine &TM)
     : XCoreGenSubtargetInfo(TT, CPU, FS), InstrInfo(), FrameLowering(*this),
       TLInfo(TM, *this), TSInfo() {}
Index: lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp
===================================================================
--- lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp
+++ lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp
@@ -972,7 +972,7 @@
   if (LowerGEP) {
     // As currently BasicAA does not analyze ptrtoint/inttoptr, do not lower to
     // arithmetic operations if the target uses alias analysis in codegen.
-    if (TM && TM->getSubtargetImpl(*GEP->getParent()->getParent())->useAA())
+    if (TM && TM->useAA(*GEP->getParent()->getParent()))
       lowerToSingleIndexGEPs(GEP, AccumulativeByteOffset);
     else
       lowerToArithmetics(GEP, AccumulativeByteOffset);
Index: unittests/MI/LiveIntervalTest.cpp
===================================================================
--- unittests/MI/LiveIntervalTest.cpp
+++ unittests/MI/LiveIntervalTest.cpp
@@ -37,7 +37,7 @@
 /// Create a TargetMachine. As we lack a dedicated always available target for
 /// unittests, we go for "AMDGPU" to be able to test normal and subregister
 /// liveranges.
-std::unique_ptr<TargetMachine> createTargetMachine() {
+std::unique_ptr<LLVMTargetMachine> createTargetMachine() {
   Triple TargetTriple("amdgcn--");
   std::string Error;
   const Target *T = TargetRegistry::lookupTarget("", TargetTriple, Error);
@@ -45,13 +45,15 @@
     return nullptr;
 
   TargetOptions Options;
-  return std::unique_ptr<TargetMachine>(T->createTargetMachine(
-      "AMDGPU", "", "", Options, None, None, CodeGenOpt::Aggressive));
+  TargetMachine *TM = T->createTargetMachine("AMDGPU", "", "", Options, None,
+                                             None, CodeGenOpt::Aggressive);
+  return
+    std::unique_ptr<LLVMTargetMachine>(static_cast<LLVMTargetMachine*>(TM));
 }
 
 std::unique_ptr<Module> parseMIR(LLVMContext &Context,
     legacy::PassManagerBase &PM, std::unique_ptr<MIRParser> &MIR,
-    const TargetMachine &TM, StringRef MIRCode, const char *FuncName) {
+    const LLVMTargetMachine &TM, StringRef MIRCode, const char *FuncName) {
   SMDiagnostic Diagnostic;
   std::unique_ptr<MemoryBuffer> MBuffer = MemoryBuffer::getMemBuffer(MIRCode);
   MIR = createMIRParser(std::move(MBuffer), Context);
@@ -130,7 +132,7 @@
 
 static void liveIntervalTest(StringRef MIRFunc, LiveIntervalTest T) {
   LLVMContext Context;
-  std::unique_ptr<TargetMachine> TM = createTargetMachine();
+  std::unique_ptr<LLVMTargetMachine> TM = createTargetMachine();
   // This test is designed for the X86 backend; stop if it is not available.
   if (!TM)
     return;
Index: unittests/Target/AArch64/InstSizes.cpp
===================================================================
--- unittests/Target/AArch64/InstSizes.cpp
+++ unittests/Target/AArch64/InstSizes.cpp
@@ -10,7 +10,7 @@
 using namespace llvm;
 
 namespace {
-std::unique_ptr<TargetMachine> createTargetMachine() {
+std::unique_ptr<LLVMTargetMachine> createTargetMachine() {
   auto TT(Triple::normalize("aarch64--"));
   std::string CPU("generic");
   std::string FS("");
@@ -22,11 +22,13 @@
   std::string Error;
   const Target *TheTarget = TargetRegistry::lookupTarget(TT, Error);
 
-  return std::unique_ptr<TargetMachine>(TheTarget->createTargetMachine(
-      TT, CPU, FS, TargetOptions(), None, None, CodeGenOpt::Default));
+  TargetMachine *TM = TheTarget->createTargetMachine(
+      TT, CPU, FS, TargetOptions(), None, None, CodeGenOpt::Default);
+  return
+    std::unique_ptr<LLVMTargetMachine>(static_cast<LLVMTargetMachine*>(TM));
 }
 
-std::unique_ptr<AArch64InstrInfo> createInstrInfo(TargetMachine *TM) {
+std::unique_ptr<AArch64InstrInfo> createInstrInfo(LLVMTargetMachine *TM) {
   AArch64Subtarget ST(TM->getTargetTriple(), TM->getTargetCPU(),
                       TM->getTargetFeatureString(), *TM, /* isLittle */ false);
   return llvm::make_unique<AArch64InstrInfo>(ST);
@@ -37,7 +39,7 @@
 /// TODO: Some of this might be useful for other architectures as well - extract
 ///       the platform-independent parts somewhere they can be reused.
 void runChecks(
-    TargetMachine *TM, AArch64InstrInfo *II, const StringRef InputIRSnippet,
+    LLVMTargetMachine *TM, AArch64InstrInfo *II, const StringRef InputIRSnippet,
     const StringRef InputMIRSnippet,
     std::function<void(AArch64InstrInfo &, MachineFunction &)> Checks) {
   LLVMContext Context;
@@ -78,7 +80,7 @@
 } // anonymous namespace
 
 TEST(InstSizes, STACKMAP) {
-  std::unique_ptr<TargetMachine> TM = createTargetMachine();
+  std::unique_ptr<LLVMTargetMachine> TM = createTargetMachine();
   ASSERT_TRUE(TM);
   std::unique_ptr<AArch64InstrInfo> II = createInstrInfo(TM.get());
 
@@ -93,7 +95,7 @@
 }
 
 TEST(InstSizes, PATCHPOINT) {
-  std::unique_ptr<TargetMachine> TM = createTargetMachine();
+  std::unique_ptr<LLVMTargetMachine> TM = createTargetMachine();
   std::unique_ptr<AArch64InstrInfo> II = createInstrInfo(TM.get());
 
   runChecks(TM.get(), II.get(), "",
@@ -108,7 +110,7 @@
 }
 
 TEST(InstSizes, TLSDESC_CALLSEQ) {
-  std::unique_ptr<TargetMachine> TM = createTargetMachine();
+  std::unique_ptr<LLVMTargetMachine> TM = createTargetMachine();
   std::unique_ptr<AArch64InstrInfo> II = createInstrInfo(TM.get());
 
   runChecks(