Index: llvm/trunk/include/llvm/DebugInfo/CodeView/CodeView.h =================================================================== --- llvm/trunk/include/llvm/DebugInfo/CodeView/CodeView.h +++ llvm/trunk/include/llvm/DebugInfo/CodeView/CodeView.h @@ -505,55 +505,9 @@ // Corresponds to CV_HREG_e enum. enum class RegisterId : uint16_t { - Unknown = 0, - VFrame = 30006, - AL = 1, - CL = 2, - DL = 3, - BL = 4, - AH = 5, - CH = 6, - DH = 7, - BH = 8, - AX = 9, - CX = 10, - DX = 11, - BX = 12, - SP = 13, - BP = 14, - SI = 15, - DI = 16, - EAX = 17, - ECX = 18, - EDX = 19, - EBX = 20, - ESP = 21, - EBP = 22, - ESI = 23, - EDI = 24, - ES = 25, - CS = 26, - SS = 27, - DS = 28, - FS = 29, - GS = 30, - IP = 31, - RAX = 328, - RBX = 329, - RCX = 330, - RDX = 331, - RSI = 332, - RDI = 333, - RBP = 334, - RSP = 335, - R8 = 336, - R9 = 337, - R10 = 338, - R11 = 339, - R12 = 340, - R13 = 341, - R14 = 342, - R15 = 343, +#define CV_REGISTER(name, value) name = value, +#include "CodeViewRegisters.def" +#undef CV_REGISTER }; /// These values correspond to the THUNK_ORDINAL enumeration. Index: llvm/trunk/include/llvm/DebugInfo/CodeView/CodeViewRegisters.def =================================================================== --- llvm/trunk/include/llvm/DebugInfo/CodeView/CodeViewRegisters.def +++ llvm/trunk/include/llvm/DebugInfo/CodeView/CodeViewRegisters.def @@ -0,0 +1,268 @@ +//===-- CodeViewRegisters.def - CodeView registers --------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// See CV_HREG_e in cvconst.h. This should match the constants there. +// +//===----------------------------------------------------------------------===// + +#ifndef CV_REGISTER +#define CV_REGISTER(name, value) +#endif + +// This currently only contains the "register subset shraed by all processor +// types" (ERR etc.) and the x86 registers. + +CV_REGISTER(ERR, 30000) +CV_REGISTER(TEB, 30001) +CV_REGISTER(TIMER, 30002) +CV_REGISTER(EFAD1, 30003) +CV_REGISTER(EFAD2, 30004) +CV_REGISTER(EFAD3, 30005) +CV_REGISTER(VFRAME, 30006) +CV_REGISTER(HANDLE, 30007) +CV_REGISTER(PARAMS, 30008) +CV_REGISTER(LOCALS, 30009) +CV_REGISTER(TID, 30010) +CV_REGISTER(ENV, 30011) +CV_REGISTER(CMDLN, 30012) + +CV_REGISTER(NONE, 0) +CV_REGISTER(AL, 1) +CV_REGISTER(CL, 2) +CV_REGISTER(DL, 3) +CV_REGISTER(BL, 4) +CV_REGISTER(AH, 5) +CV_REGISTER(CH, 6) +CV_REGISTER(DH, 7) +CV_REGISTER(BH, 8) +CV_REGISTER(AX, 9) +CV_REGISTER(CX, 10) +CV_REGISTER(DX, 11) +CV_REGISTER(BX, 12) +CV_REGISTER(SP, 13) +CV_REGISTER(BP, 14) +CV_REGISTER(SI, 15) +CV_REGISTER(DI, 16) +CV_REGISTER(EAX, 17) +CV_REGISTER(ECX, 18) +CV_REGISTER(EDX, 19) +CV_REGISTER(EBX, 20) +CV_REGISTER(ESP, 21) +CV_REGISTER(EBP, 22) +CV_REGISTER(ESI, 23) +CV_REGISTER(EDI, 24) +CV_REGISTER(ES, 25) +CV_REGISTER(CS, 26) +CV_REGISTER(SS, 27) +CV_REGISTER(DS, 28) +CV_REGISTER(FS, 29) +CV_REGISTER(GS, 30) +CV_REGISTER(IP, 31) +CV_REGISTER(FLAGS, 32) +CV_REGISTER(EIP, 33) +CV_REGISTER(EFLAGS, 34) +CV_REGISTER(TEMP, 40) +CV_REGISTER(TEMPH, 41) +CV_REGISTER(QUOTE, 42) +CV_REGISTER(PCDR3, 43) +CV_REGISTER(PCDR4, 44) +CV_REGISTER(PCDR5, 45) +CV_REGISTER(PCDR6, 46) +CV_REGISTER(PCDR7, 47) +CV_REGISTER(CR0, 80) +CV_REGISTER(CR1, 81) +CV_REGISTER(CR2, 82) +CV_REGISTER(CR3, 83) +CV_REGISTER(CR4, 84) +CV_REGISTER(DR0, 90) +CV_REGISTER(DR1, 91) +CV_REGISTER(DR2, 92) +CV_REGISTER(DR3, 93) +CV_REGISTER(DR4, 94) +CV_REGISTER(DR5, 95) +CV_REGISTER(DR6, 96) +CV_REGISTER(DR7, 97) +CV_REGISTER(GDTR, 110) +CV_REGISTER(GDTL, 111) +CV_REGISTER(IDTR, 112) +CV_REGISTER(IDTL, 113) +CV_REGISTER(LDTR, 114) +CV_REGISTER(TR, 115) + +CV_REGISTER(PSEUDO1, 116) +CV_REGISTER(PSEUDO2, 117) +CV_REGISTER(PSEUDO3, 118) +CV_REGISTER(PSEUDO4, 119) +CV_REGISTER(PSEUDO5, 120) +CV_REGISTER(PSEUDO6, 121) +CV_REGISTER(PSEUDO7, 122) +CV_REGISTER(PSEUDO8, 123) +CV_REGISTER(PSEUDO9, 124) + +CV_REGISTER(ST0, 128) +CV_REGISTER(ST1, 129) +CV_REGISTER(ST2, 130) +CV_REGISTER(ST3, 131) +CV_REGISTER(ST4, 132) +CV_REGISTER(ST5, 133) +CV_REGISTER(ST6, 134) +CV_REGISTER(ST7, 135) +CV_REGISTER(CTRL, 136) +CV_REGISTER(STAT, 137) +CV_REGISTER(TAG, 138) +CV_REGISTER(FPIP, 139) +CV_REGISTER(FPCS, 140) +CV_REGISTER(FPDO, 141) +CV_REGISTER(FPDS, 142) +CV_REGISTER(ISEM, 143) +CV_REGISTER(FPEIP, 144) +CV_REGISTER(FPEDO, 145) + +CV_REGISTER(MM0, 146) +CV_REGISTER(MM1, 147) +CV_REGISTER(MM2, 148) +CV_REGISTER(MM3, 149) +CV_REGISTER(MM4, 150) +CV_REGISTER(MM5, 151) +CV_REGISTER(MM6, 152) +CV_REGISTER(MM7, 153) + +CV_REGISTER(XMM0, 154) +CV_REGISTER(XMM1, 155) +CV_REGISTER(XMM2, 156) +CV_REGISTER(XMM3, 157) +CV_REGISTER(XMM4, 158) +CV_REGISTER(XMM5, 159) +CV_REGISTER(XMM6, 160) +CV_REGISTER(XMM7, 161) + +CV_REGISTER(MXCSR, 211) + +CV_REGISTER(EDXEAX, 212) + +CV_REGISTER(EMM0L, 220) +CV_REGISTER(EMM1L, 221) +CV_REGISTER(EMM2L, 222) +CV_REGISTER(EMM3L, 223) +CV_REGISTER(EMM4L, 224) +CV_REGISTER(EMM5L, 225) +CV_REGISTER(EMM6L, 226) +CV_REGISTER(EMM7L, 227) + +CV_REGISTER(EMM0H, 228) +CV_REGISTER(EMM1H, 229) +CV_REGISTER(EMM2H, 230) +CV_REGISTER(EMM3H, 231) +CV_REGISTER(EMM4H, 232) +CV_REGISTER(EMM5H, 233) +CV_REGISTER(EMM6H, 234) +CV_REGISTER(EMM7H, 235) + +CV_REGISTER(MM00, 236) +CV_REGISTER(MM01, 237) +CV_REGISTER(MM10, 238) +CV_REGISTER(MM11, 239) +CV_REGISTER(MM20, 240) +CV_REGISTER(MM21, 241) +CV_REGISTER(MM30, 242) +CV_REGISTER(MM31, 243) +CV_REGISTER(MM40, 244) +CV_REGISTER(MM41, 245) +CV_REGISTER(MM50, 246) +CV_REGISTER(MM51, 247) +CV_REGISTER(MM60, 248) +CV_REGISTER(MM61, 249) +CV_REGISTER(MM70, 250) +CV_REGISTER(MM71, 251) + +CV_REGISTER(BND0, 396) +CV_REGISTER(BND1, 397) +CV_REGISTER(BND2, 398) + + +CV_REGISTER(XMM8, 252) +CV_REGISTER(XMM9, 253) +CV_REGISTER(XMM10, 254) +CV_REGISTER(XMM11, 255) +CV_REGISTER(XMM12, 256) +CV_REGISTER(XMM13, 257) +CV_REGISTER(XMM14, 258) +CV_REGISTER(XMM15, 259) + + +CV_REGISTER(SIL, 324) +CV_REGISTER(DIL, 325) +CV_REGISTER(BPL, 326) +CV_REGISTER(SPL, 327) + +CV_REGISTER(RAX, 328) +CV_REGISTER(RBX, 329) +CV_REGISTER(RCX, 330) +CV_REGISTER(RDX, 331) +CV_REGISTER(RSI, 332) +CV_REGISTER(RDI, 333) +CV_REGISTER(RBP, 334) +CV_REGISTER(RSP, 335) + +CV_REGISTER(R8, 336) +CV_REGISTER(R9, 337) +CV_REGISTER(R10, 338) +CV_REGISTER(R11, 339) +CV_REGISTER(R12, 340) +CV_REGISTER(R13, 341) +CV_REGISTER(R14, 342) +CV_REGISTER(R15, 343) + +CV_REGISTER(R8B, 344) +CV_REGISTER(R9B, 345) +CV_REGISTER(R10B, 346) +CV_REGISTER(R11B, 347) +CV_REGISTER(R12B, 348) +CV_REGISTER(R13B, 349) +CV_REGISTER(R14B, 350) +CV_REGISTER(R15B, 351) + +CV_REGISTER(R8W, 352) +CV_REGISTER(R9W, 353) +CV_REGISTER(R10W, 354) +CV_REGISTER(R11W, 355) +CV_REGISTER(R12W, 356) +CV_REGISTER(R13W, 357) +CV_REGISTER(R14W, 358) +CV_REGISTER(R15W, 359) + +CV_REGISTER(R8D, 360) +CV_REGISTER(R9D, 361) +CV_REGISTER(R10D, 362) +CV_REGISTER(R11D, 363) +CV_REGISTER(R12D, 364) +CV_REGISTER(R13D, 365) +CV_REGISTER(R14D, 366) +CV_REGISTER(R15D, 367) + + +// cvconst.h defines both CV_REG_YMM0 (252) and CV_AMD64_YMM0 (368). Keep the +// original prefix to distinguish them. + +CV_REGISTER(AMD64_YMM0, 368) +CV_REGISTER(AMD64_YMM1, 369) +CV_REGISTER(AMD64_YMM2, 370) +CV_REGISTER(AMD64_YMM3, 371) +CV_REGISTER(AMD64_YMM4, 372) +CV_REGISTER(AMD64_YMM5, 373) +CV_REGISTER(AMD64_YMM6, 374) +CV_REGISTER(AMD64_YMM7, 375) +CV_REGISTER(AMD64_YMM8, 376) +CV_REGISTER(AMD64_YMM9, 377) +CV_REGISTER(AMD64_YMM10, 378) +CV_REGISTER(AMD64_YMM11, 379) +CV_REGISTER(AMD64_YMM12, 380) +CV_REGISTER(AMD64_YMM13, 381) +CV_REGISTER(AMD64_YMM14, 382) +CV_REGISTER(AMD64_YMM15, 383) Index: llvm/trunk/include/llvm/module.modulemap =================================================================== --- llvm/trunk/include/llvm/module.modulemap +++ llvm/trunk/include/llvm/module.modulemap @@ -123,6 +123,7 @@ module * { export * } // These are intended for (repeated) textual inclusion. + textual header "DebugInfo/CodeView/CodeViewRegisters.def" textual header "DebugInfo/CodeView/CodeViewTypes.def" textual header "DebugInfo/CodeView/CodeViewSymbols.def" } Index: llvm/trunk/lib/DebugInfo/CodeView/EnumTables.cpp =================================================================== --- llvm/trunk/lib/DebugInfo/CodeView/EnumTables.cpp +++ llvm/trunk/lib/DebugInfo/CodeView/EnumTables.cpp @@ -33,55 +33,9 @@ }; static const EnumEntry RegisterNames[] = { - CV_ENUM_CLASS_ENT(RegisterId, Unknown), - CV_ENUM_CLASS_ENT(RegisterId, VFrame), - CV_ENUM_CLASS_ENT(RegisterId, AL), - CV_ENUM_CLASS_ENT(RegisterId, CL), - CV_ENUM_CLASS_ENT(RegisterId, DL), - CV_ENUM_CLASS_ENT(RegisterId, BL), - CV_ENUM_CLASS_ENT(RegisterId, AH), - CV_ENUM_CLASS_ENT(RegisterId, CH), - CV_ENUM_CLASS_ENT(RegisterId, DH), - CV_ENUM_CLASS_ENT(RegisterId, BH), - CV_ENUM_CLASS_ENT(RegisterId, AX), - CV_ENUM_CLASS_ENT(RegisterId, CX), - CV_ENUM_CLASS_ENT(RegisterId, DX), - CV_ENUM_CLASS_ENT(RegisterId, BX), - CV_ENUM_CLASS_ENT(RegisterId, SP), - CV_ENUM_CLASS_ENT(RegisterId, BP), - CV_ENUM_CLASS_ENT(RegisterId, SI), - CV_ENUM_CLASS_ENT(RegisterId, DI), - CV_ENUM_CLASS_ENT(RegisterId, EAX), - CV_ENUM_CLASS_ENT(RegisterId, ECX), - CV_ENUM_CLASS_ENT(RegisterId, EDX), - CV_ENUM_CLASS_ENT(RegisterId, EBX), - CV_ENUM_CLASS_ENT(RegisterId, ESP), - CV_ENUM_CLASS_ENT(RegisterId, EBP), - CV_ENUM_CLASS_ENT(RegisterId, ESI), - CV_ENUM_CLASS_ENT(RegisterId, EDI), - CV_ENUM_CLASS_ENT(RegisterId, ES), - CV_ENUM_CLASS_ENT(RegisterId, CS), - CV_ENUM_CLASS_ENT(RegisterId, SS), - CV_ENUM_CLASS_ENT(RegisterId, DS), - CV_ENUM_CLASS_ENT(RegisterId, FS), - CV_ENUM_CLASS_ENT(RegisterId, GS), - CV_ENUM_CLASS_ENT(RegisterId, IP), - CV_ENUM_CLASS_ENT(RegisterId, RAX), - CV_ENUM_CLASS_ENT(RegisterId, RBX), - CV_ENUM_CLASS_ENT(RegisterId, RCX), - CV_ENUM_CLASS_ENT(RegisterId, RDX), - CV_ENUM_CLASS_ENT(RegisterId, RSI), - CV_ENUM_CLASS_ENT(RegisterId, RDI), - CV_ENUM_CLASS_ENT(RegisterId, RBP), - CV_ENUM_CLASS_ENT(RegisterId, RSP), - CV_ENUM_CLASS_ENT(RegisterId, R8), - CV_ENUM_CLASS_ENT(RegisterId, R9), - CV_ENUM_CLASS_ENT(RegisterId, R10), - CV_ENUM_CLASS_ENT(RegisterId, R11), - CV_ENUM_CLASS_ENT(RegisterId, R12), - CV_ENUM_CLASS_ENT(RegisterId, R13), - CV_ENUM_CLASS_ENT(RegisterId, R14), - CV_ENUM_CLASS_ENT(RegisterId, R15), +#define CV_REGISTER(name, val) CV_ENUM_CLASS_ENT(RegisterId, name), +#include "llvm/DebugInfo/CodeView/CodeViewRegisters.def" +#undef CV_REGISTER }; static const EnumEntry PublicSymFlagNames[] = { Index: llvm/trunk/lib/DebugInfo/PDB/PDBExtras.cpp =================================================================== --- llvm/trunk/lib/DebugInfo/PDB/PDBExtras.cpp +++ llvm/trunk/lib/DebugInfo/PDB/PDBExtras.cpp @@ -94,55 +94,11 @@ raw_ostream &llvm::pdb::operator<<(raw_ostream &OS, const codeview::RegisterId &Reg) { switch (Reg) { - CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, AL, OS) - CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, CL, OS) - CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, DL, OS) - CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, BL, OS) - CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, AH, OS) - CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, CH, OS) - CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, DH, OS) - CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, BH, OS) - CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, AX, OS) - CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, CX, OS) - CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, DX, OS) - CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, BX, OS) - CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, SP, OS) - CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, BP, OS) - CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, SI, OS) - CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, DI, OS) - CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, EAX, OS) - CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, ECX, OS) - CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, EDX, OS) - CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, EBX, OS) - CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, ESP, OS) - CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, EBP, OS) - CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, ESI, OS) - CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, EDI, OS) - CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, ES, OS) - CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, CS, OS) - CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, SS, OS) - CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, DS, OS) - CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, FS, OS) - CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, GS, OS) - CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, IP, OS) - CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, RAX, OS) - CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, RBX, OS) - CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, RCX, OS) - CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, RDX, OS) - CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, RSI, OS) - CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, RDI, OS) - CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, RBP, OS) - CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, RSP, OS) - CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, R8, OS) - CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, R9, OS) - CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, R10, OS) - CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, R11, OS) - CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, R12, OS) - CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, R13, OS) - CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, R14, OS) - CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, R15, OS) - default: - OS << static_cast(Reg); +#define CV_REGISTER(name, val) case codeview::RegisterId::name: OS << #name; break; +#include "llvm/DebugInfo/CodeView/CodeViewRegisters.def" +#undef CV_REGISTER + default: + OS << static_cast(Reg); } return OS; } Index: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp =================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp @@ -16,6 +16,7 @@ #include "InstPrinter/X86IntelInstPrinter.h" #include "X86MCAsmInfo.h" #include "llvm/ADT/Triple.h" +#include "llvm/DebugInfo/CodeView/CodeView.h" #include "llvm/MC/MCInstrAnalysis.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" @@ -72,52 +73,128 @@ MRI->mapLLVMRegToSEHReg(Reg, SEH); } - // These CodeView registers are numbered sequentially starting at value 1. - static const MCPhysReg LowCVRegs[] = { - X86::AL, X86::CL, X86::DL, X86::BL, X86::AH, X86::CH, - X86::DH, X86::BH, X86::AX, X86::CX, X86::DX, X86::BX, - X86::SP, X86::BP, X86::SI, X86::DI, X86::EAX, X86::ECX, - X86::EDX, X86::EBX, X86::ESP, X86::EBP, X86::ESI, X86::EDI, + // Mapping from CodeView to MC register id. + static const struct { + codeview::RegisterId CVReg; + MCPhysReg Reg; + } RegMap[] = { + { codeview::RegisterId::AL, X86::AL}, + { codeview::RegisterId::CL, X86::CL}, + { codeview::RegisterId::DL, X86::DL}, + { codeview::RegisterId::BL, X86::BL}, + { codeview::RegisterId::AH, X86::AH}, + { codeview::RegisterId::CH, X86::CH}, + { codeview::RegisterId::DH, X86::DH}, + { codeview::RegisterId::BH, X86::BH}, + { codeview::RegisterId::AX, X86::AX}, + { codeview::RegisterId::CX, X86::CX}, + { codeview::RegisterId::DX, X86::DX}, + { codeview::RegisterId::BX, X86::BX}, + { codeview::RegisterId::SP, X86::SP}, + { codeview::RegisterId::BP, X86::BP}, + { codeview::RegisterId::SI, X86::SI}, + { codeview::RegisterId::DI, X86::DI}, + { codeview::RegisterId::EAX, X86::EAX}, + { codeview::RegisterId::ECX, X86::ECX}, + { codeview::RegisterId::EDX, X86::EDX}, + { codeview::RegisterId::EBX, X86::EBX}, + { codeview::RegisterId::ESP, X86::ESP}, + { codeview::RegisterId::EBP, X86::EBP}, + { codeview::RegisterId::ESI, X86::ESI}, + { codeview::RegisterId::EDI, X86::EDI}, + + { codeview::RegisterId::EFLAGS, X86::EFLAGS}, + + { codeview::RegisterId::ST0, X86::FP0}, + { codeview::RegisterId::ST1, X86::FP1}, + { codeview::RegisterId::ST2, X86::FP2}, + { codeview::RegisterId::ST3, X86::FP3}, + { codeview::RegisterId::ST4, X86::FP4}, + { codeview::RegisterId::ST5, X86::FP5}, + { codeview::RegisterId::ST6, X86::FP6}, + { codeview::RegisterId::ST7, X86::FP7}, + + { codeview::RegisterId::XMM0, X86::XMM0}, + { codeview::RegisterId::XMM1, X86::XMM1}, + { codeview::RegisterId::XMM2, X86::XMM2}, + { codeview::RegisterId::XMM3, X86::XMM3}, + { codeview::RegisterId::XMM4, X86::XMM4}, + { codeview::RegisterId::XMM5, X86::XMM5}, + { codeview::RegisterId::XMM6, X86::XMM6}, + { codeview::RegisterId::XMM7, X86::XMM7}, + + { codeview::RegisterId::XMM8, X86::XMM8}, + { codeview::RegisterId::XMM9, X86::XMM9}, + { codeview::RegisterId::XMM10, X86::XMM10}, + { codeview::RegisterId::XMM11, X86::XMM11}, + { codeview::RegisterId::XMM12, X86::XMM12}, + { codeview::RegisterId::XMM13, X86::XMM13}, + { codeview::RegisterId::XMM14, X86::XMM14}, + { codeview::RegisterId::XMM15, X86::XMM15}, + + { codeview::RegisterId::SIL, X86::SIL}, + { codeview::RegisterId::DIL, X86::DIL}, + { codeview::RegisterId::BPL, X86::BPL}, + { codeview::RegisterId::SPL, X86::SPL}, + { codeview::RegisterId::RAX, X86::RAX}, + { codeview::RegisterId::RBX, X86::RBX}, + { codeview::RegisterId::RCX, X86::RCX}, + { codeview::RegisterId::RDX, X86::RDX}, + { codeview::RegisterId::RSI, X86::RSI}, + { codeview::RegisterId::RDI, X86::RDI}, + { codeview::RegisterId::RBP, X86::RBP}, + { codeview::RegisterId::RSP, X86::RSP}, + { codeview::RegisterId::R8, X86::R8}, + { codeview::RegisterId::R9, X86::R9}, + { codeview::RegisterId::R10, X86::R10}, + { codeview::RegisterId::R11, X86::R11}, + { codeview::RegisterId::R12, X86::R12}, + { codeview::RegisterId::R13, X86::R13}, + { codeview::RegisterId::R14, X86::R14}, + { codeview::RegisterId::R15, X86::R15}, + { codeview::RegisterId::R8B, X86::R8B}, + { codeview::RegisterId::R9B, X86::R9B}, + { codeview::RegisterId::R10B, X86::R10B}, + { codeview::RegisterId::R11B, X86::R11B}, + { codeview::RegisterId::R12B, X86::R12B}, + { codeview::RegisterId::R13B, X86::R13B}, + { codeview::RegisterId::R14B, X86::R14B}, + { codeview::RegisterId::R15B, X86::R15B}, + { codeview::RegisterId::R8W, X86::R8W}, + { codeview::RegisterId::R9W, X86::R9W}, + { codeview::RegisterId::R10W, X86::R10W}, + { codeview::RegisterId::R11W, X86::R11W}, + { codeview::RegisterId::R12W, X86::R12W}, + { codeview::RegisterId::R13W, X86::R13W}, + { codeview::RegisterId::R14W, X86::R14W}, + { codeview::RegisterId::R15W, X86::R15W}, + { codeview::RegisterId::R8D, X86::R8D}, + { codeview::RegisterId::R9D, X86::R9D}, + { codeview::RegisterId::R10D, X86::R10D}, + { codeview::RegisterId::R11D, X86::R11D}, + { codeview::RegisterId::R12D, X86::R12D}, + { codeview::RegisterId::R13D, X86::R13D}, + { codeview::RegisterId::R14D, X86::R14D}, + { codeview::RegisterId::R15D, X86::R15D}, + { codeview::RegisterId::AMD64_YMM0, X86::YMM0}, + { codeview::RegisterId::AMD64_YMM1, X86::YMM1}, + { codeview::RegisterId::AMD64_YMM2, X86::YMM2}, + { codeview::RegisterId::AMD64_YMM3, X86::YMM3}, + { codeview::RegisterId::AMD64_YMM4, X86::YMM4}, + { codeview::RegisterId::AMD64_YMM5, X86::YMM5}, + { codeview::RegisterId::AMD64_YMM6, X86::YMM6}, + { codeview::RegisterId::AMD64_YMM7, X86::YMM7}, + { codeview::RegisterId::AMD64_YMM8, X86::YMM8}, + { codeview::RegisterId::AMD64_YMM9, X86::YMM9}, + { codeview::RegisterId::AMD64_YMM10, X86::YMM10}, + { codeview::RegisterId::AMD64_YMM11, X86::YMM11}, + { codeview::RegisterId::AMD64_YMM12, X86::YMM12}, + { codeview::RegisterId::AMD64_YMM13, X86::YMM13}, + { codeview::RegisterId::AMD64_YMM14, X86::YMM14}, + { codeview::RegisterId::AMD64_YMM15, X86::YMM15}, }; - unsigned CVLowRegStart = 1; - for (unsigned I = 0; I < array_lengthof(LowCVRegs); ++I) - MRI->mapLLVMRegToCVReg(LowCVRegs[I], I + CVLowRegStart); - - MRI->mapLLVMRegToCVReg(X86::EFLAGS, 34); - - // The x87 registers start at 128 and are numbered sequentially. - unsigned FP0Start = 128; - for (unsigned I = 0; I < 8; ++I) - MRI->mapLLVMRegToCVReg(X86::FP0 + I, FP0Start + I); - - // The low 8 XMM registers start at 154 and are numbered sequentially. - unsigned CVXMM0Start = 154; - for (unsigned I = 0; I < 8; ++I) - MRI->mapLLVMRegToCVReg(X86::XMM0 + I, CVXMM0Start + I); - - // The high 8 XMM registers start at 252 and are numbered sequentially. - unsigned CVXMM8Start = 252; - for (unsigned I = 0; I < 8; ++I) - MRI->mapLLVMRegToCVReg(X86::XMM8 + I, CVXMM8Start + I); - - // FIXME: XMM16 and above from AVX512 not yet documented. - - // AMD64 registers start at 324 and count up. - unsigned CVX64RegStart = 324; - static const MCPhysReg CVX64Regs[] = { - X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::RAX, X86::RBX, - X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBP, X86::RSP, - X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, - X86::R14, X86::R15, X86::R8B, X86::R9B, X86::R10B, X86::R11B, - X86::R12B, X86::R13B, X86::R14B, X86::R15B, X86::R8W, X86::R9W, - X86::R10W, X86::R11W, X86::R12W, X86::R13W, X86::R14W, X86::R15W, - X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R12D, X86::R13D, - X86::R14D, X86::R15D, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, - X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, - X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, - }; - for (unsigned I = 0; I < array_lengthof(CVX64Regs); ++I) - MRI->mapLLVMRegToCVReg(CVX64Regs[I], CVX64RegStart + I); + for (unsigned I = 0; I < array_lengthof(RegMap); ++I) + MRI->mapLLVMRegToCVReg(RegMap[I].Reg, static_cast(RegMap[I].CVReg)); } MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const Triple &TT, Index: llvm/trunk/test/DebugInfo/COFF/fp-stack.ll =================================================================== --- llvm/trunk/test/DebugInfo/COFF/fp-stack.ll +++ llvm/trunk/test/DebugInfo/COFF/fp-stack.ll @@ -12,7 +12,7 @@ ; ASM: .cv_def_range Lfunc_begin0 Lfunc_end0, "A\021\200\000\000\000" ; OBJ: DefRangeRegisterSym { -; OBJ: Register: 0x80 +; OBJ: Register: ST0 (0x80) ; OBJ: MayHaveNoName: 0 ; OBJ: LocalVariableAddrRange { ; OBJ: OffsetStart: .text+0x0 Index: llvm/trunk/tools/llvm-pdbutil/MinimalSymbolDumper.cpp =================================================================== --- llvm/trunk/tools/llvm-pdbutil/MinimalSymbolDumper.cpp +++ llvm/trunk/tools/llvm-pdbutil/MinimalSymbolDumper.cpp @@ -287,56 +287,11 @@ static std::string formatRegisterId(RegisterId Id) { switch (Id) { - RETURN_CASE(RegisterId, VFrame, "vframe"); - RETURN_CASE(RegisterId, AL, "al"); - RETURN_CASE(RegisterId, CL, "cl"); - RETURN_CASE(RegisterId, DL, "dl"); - RETURN_CASE(RegisterId, BL, "bl"); - RETURN_CASE(RegisterId, AH, "ah"); - RETURN_CASE(RegisterId, CH, "ch"); - RETURN_CASE(RegisterId, DH, "dh"); - RETURN_CASE(RegisterId, BH, "bh"); - RETURN_CASE(RegisterId, AX, "ax"); - RETURN_CASE(RegisterId, CX, "cx"); - RETURN_CASE(RegisterId, DX, "dx"); - RETURN_CASE(RegisterId, BX, "bx"); - RETURN_CASE(RegisterId, SP, "sp"); - RETURN_CASE(RegisterId, BP, "bp"); - RETURN_CASE(RegisterId, SI, "si"); - RETURN_CASE(RegisterId, DI, "di"); - RETURN_CASE(RegisterId, EAX, "eax"); - RETURN_CASE(RegisterId, ECX, "ecx"); - RETURN_CASE(RegisterId, EDX, "edx"); - RETURN_CASE(RegisterId, EBX, "ebx"); - RETURN_CASE(RegisterId, ESP, "esp"); - RETURN_CASE(RegisterId, EBP, "ebp"); - RETURN_CASE(RegisterId, ESI, "esi"); - RETURN_CASE(RegisterId, EDI, "edi"); - RETURN_CASE(RegisterId, ES, "es"); - RETURN_CASE(RegisterId, CS, "cs"); - RETURN_CASE(RegisterId, SS, "ss"); - RETURN_CASE(RegisterId, DS, "ds"); - RETURN_CASE(RegisterId, FS, "fs"); - RETURN_CASE(RegisterId, GS, "gs"); - RETURN_CASE(RegisterId, IP, "ip"); - RETURN_CASE(RegisterId, RAX, "rax"); - RETURN_CASE(RegisterId, RBX, "rbx"); - RETURN_CASE(RegisterId, RCX, "rcx"); - RETURN_CASE(RegisterId, RDX, "rdx"); - RETURN_CASE(RegisterId, RSI, "rsi"); - RETURN_CASE(RegisterId, RDI, "rdi"); - RETURN_CASE(RegisterId, RBP, "rbp"); - RETURN_CASE(RegisterId, RSP, "rsp"); - RETURN_CASE(RegisterId, R8, "r8"); - RETURN_CASE(RegisterId, R9, "r9"); - RETURN_CASE(RegisterId, R10, "r10"); - RETURN_CASE(RegisterId, R11, "r11"); - RETURN_CASE(RegisterId, R12, "r12"); - RETURN_CASE(RegisterId, R13, "r13"); - RETURN_CASE(RegisterId, R14, "r14"); - RETURN_CASE(RegisterId, R15, "r15"); - default: - return formatUnknownEnum(Id); +#define CV_REGISTER(name, val) RETURN_CASE(RegisterId, name, #name) +#include "llvm/DebugInfo/CodeView/CodeViewRegisters.def" +#undef CV_REGISTER + default: + return formatUnknownEnum(Id); } }