Index: cmake/config-ix.cmake =================================================================== --- cmake/config-ix.cmake +++ cmake/config-ix.cmake @@ -269,7 +269,6 @@ add_definitions( -D_GNU_SOURCE ) endif() # This check requires _GNU_SOURCE -check_library_exists(c sched_getaffinity "" HAVE_SCHED_GETAFFINITY) if(HAVE_LIBPTHREAD) check_library_exists(pthread pthread_getname_np "" HAVE_PTHREAD_GETNAME_NP) check_library_exists(pthread pthread_setname_np "" HAVE_PTHREAD_SETNAME_NP) Index: docs/AMDGPUUsage.rst =================================================================== --- docs/AMDGPUUsage.rst +++ docs/AMDGPUUsage.rst @@ -359,71 +359,47 @@ .. table:: AMDGPU ELF Header :name: amdgpu-elf-header-table - ========================== =============================== + ========================== ========================= Field Value - ========================== =============================== + ========================== ========================= ``e_ident[EI_CLASS]`` ``ELFCLASS64`` ``e_ident[EI_DATA]`` ``ELFDATA2LSB`` - ``e_ident[EI_OSABI]`` ``ELFOSABI_AMDGPU_HSA`` or - ``ELFOSABI_AMDGPU_PAL`` or - ``ELFOSABI_AMDGPU_MESA3D`` - ``e_ident[EI_ABIVERSION]`` ``ELFABIVERSION_AMDGPU_HSA`` or - ``ELFABIVERSION_AMDGPU_PAL`` or - ``ELFABIVERSION_AMDGPU_MESA3D`` + ``e_ident[EI_OSABI]`` ``ELFOSABI_AMDGPU_HSA`` + ``e_ident[EI_ABIVERSION]`` ``ELFABIVERSION_AMDGPU_HSA`` ``e_type`` ``ET_REL`` or ``ET_DYN`` ``e_machine`` ``EM_AMDGPU`` ``e_entry`` 0 ``e_flags`` 0 - ========================== =============================== + ========================== ========================= .. .. table:: AMDGPU ELF Header Enumeration Values :name: amdgpu-elf-header-enumeration-values-table - =============================== ===== - Name Value - =============================== ===== - ``EM_AMDGPU`` 224 - ``ELFOSABI_AMDGPU_HSA`` 64 - ``ELFOSABI_AMDGPU_PAL`` 65 - ``ELFOSABI_AMDGPU_MESA3D`` 66 - ``ELFABIVERSION_AMDGPU_HSA`` 1 - ``ELFABIVERSION_AMDGPU_PAL`` 0 - ``ELFABIVERSION_AMDGPU_MESA3D`` 0 - =============================== ===== + ============================ ===== + Name Value + ============================ ===== + ``EM_AMDGPU`` 224 + ``ELFOSABI_AMDGPU_HSA`` 64 + ``ELFABIVERSION_AMDGPU_HSA`` 1 + ============================ ===== ``e_ident[EI_CLASS]`` - The ELF class is always ``ELFCLASS64``. The AMDGPU backend only supports 64 - bit applications. + The ELF class is always ``ELFCLASS64``. The AMDGPU backend only supports 64 bit + applications. ``e_ident[EI_DATA]`` All AMDGPU targets use ELFDATA2LSB for little-endian byte ordering. ``e_ident[EI_OSABI]`` - One of the following AMD GPU architecture specific OS ABIs: - - * ``ELFOSABI_AMDGPU_HSA`` is used to specify that the code object conforms to - the AMD HSA runtime ABI [HSA]_. - - * ``ELFOSABI_AMDGPU_PAL`` is used to specify that the code object conforms to - the AMD PAL runtime ABI. - - * ``ELFOSABI_AMDGPU_MESA3D`` is used to specify that the code object conforms - to the AMD MESA runtime ABI. + The AMD GPU architecture specific OS ABI of ``ELFOSABI_AMDGPU_HSA`` is used to + specify that the code object conforms to the AMD HSA runtime ABI [HSA]_. ``e_ident[EI_ABIVERSION]`` - The ABI version of the AMD GPU architecture specific OS ABI to which the code - object conforms: - - * ``ELFABIVERSION_AMDGPU_HSA`` is used to specify the version of AMD HSA - runtime ABI. - - * ``ELFABIVERSION_AMDGPU_PAL`` is used to specify the version of AMD PAL - runtime ABI. - - * ``ELFABIVERSION_AMDGPU_MESA3D`` is used to specify the version of AMD MESA - runtime ABI. + The AMD GPU architecture specific OS ABI version of + ``ELFABIVERSION_AMDGPU_HSA`` is used to specify the version of AMD HSA runtime + ABI to which the code object conforms. ``e_type`` Can be one of the following values: Index: include/llvm/Analysis/ConstantFolding.h =================================================================== --- include/llvm/Analysis/ConstantFolding.h +++ include/llvm/Analysis/ConstantFolding.h @@ -79,12 +79,6 @@ Constant *ConstantFoldBinaryOpOperands(unsigned Opcode, Constant *LHS, Constant *RHS, const DataLayout &DL); -/// \brief Attempt to constant fold a select instruction with the specified -/// operands. The constant result is returned if successful; if not, null is -/// returned. -Constant *ConstantFoldSelectInstruction(Constant *Cond, Constant *V1, - Constant *V2); - /// \brief Attempt to constant fold a cast with the specified operand. If it /// fails, it returns a constant expression of the specified operand. Constant *ConstantFoldCastOperand(unsigned Opcode, Constant *C, Type *DestTy, Index: include/llvm/Analysis/SparsePropagation.h =================================================================== --- include/llvm/Analysis/SparsePropagation.h +++ include/llvm/Analysis/SparsePropagation.h @@ -30,19 +30,22 @@ class Instruction; class PHINode; class raw_ostream; -template class SparseSolver; +class SparseSolver; class TerminatorInst; class Value; template class SmallVectorImpl; /// AbstractLatticeFunction - This class is implemented by the dataflow instance -/// to specify what the lattice values are and how they handle merges etc. This -/// gives the client the power to compute lattice values from instructions, -/// constants, etc. The current requirement is that lattice values must be -/// copyable. At the moment, nothing tries to avoid copying. - +/// to specify what the lattice values are and how they handle merges etc. +/// This gives the client the power to compute lattice values from instructions, +/// constants, etc. The requirement is that lattice values must all fit into +/// a void*. If a void* is not sufficient, the implementation should use this +/// pointer to be a pointer into a uniquing set or something. +/// +class AbstractLatticeFunction { +public: + using LatticeVal = void *; -template class AbstractLatticeFunction { private: LatticeVal UndefVal, OverdefinedVal, UntrackedVal; @@ -78,8 +81,7 @@ /// GetConstant - If the specified lattice value is representable as an LLVM /// constant value, return it. Otherwise return null. The returned value /// must be in the same LLVM type as Val. - virtual Constant *GetConstant(LatticeVal LV, Value *Val, - SparseSolver &SS) { + virtual Constant *GetConstant(LatticeVal LV, Value *Val, SparseSolver &SS) { return nullptr; } @@ -98,8 +100,7 @@ /// ComputeInstructionState - Given an instruction and a vector of its operand /// values, compute the result value of the instruction. - virtual LatticeVal ComputeInstructionState(Instruction &I, - SparseSolver &SS) { + virtual LatticeVal ComputeInstructionState(Instruction &I, SparseSolver &SS) { return getOverdefinedVal(); // always safe, never useful. } @@ -109,11 +110,12 @@ /// SparseSolver - This class is a general purpose solver for Sparse Conditional /// Propagation with a programmable lattice function. -template class SparseSolver { +class SparseSolver { + using LatticeVal = AbstractLatticeFunction::LatticeVal; /// LatticeFunc - This is the object that knows the lattice and how to do /// compute transfer functions. - AbstractLatticeFunction *LatticeFunc; + AbstractLatticeFunction *LatticeFunc; DenseMap ValueState; // The state each value is in. SmallPtrSet BBExecutable; // The bbs that are executable. @@ -128,7 +130,7 @@ std::set KnownFeasibleEdges; public: - explicit SparseSolver(AbstractLatticeFunction *Lattice) + explicit SparseSolver(AbstractLatticeFunction *Lattice) : LatticeFunc(Lattice) {} SparseSolver(const SparseSolver &) = delete; SparseSolver &operator=(const SparseSolver &) = delete; @@ -141,18 +143,18 @@ /// getLatticeState - Return the LatticeVal object that corresponds to the /// value. If an value is not in the map, it is returned as untracked, - /// unlike the getValueState method. + /// unlike the getOrInitValueState method. LatticeVal getLatticeState(Value *V) const { - auto I = ValueState.find(V); + DenseMap::const_iterator I = ValueState.find(V); return I != ValueState.end() ? I->second : LatticeFunc->getUntrackedVal(); } - /// getValueState - Return the LatticeVal object that corresponds to the + /// getOrInitValueState - Return the LatticeVal object that corresponds to the /// value, initializing the value's state if it hasn't been entered into the /// map yet. This function is necessary because not all values should start /// out in the underdefined state... Arguments should be overdefined, and /// constants should be marked as constants. - LatticeVal getValueState(Value *V); + LatticeVal getOrInitValueState(Value *V); /// isEdgeFeasible - Return true if the control flow edge from the 'From' /// basic block to the 'To' basic block is currently feasible. If Index: include/llvm/BinaryFormat/ELF.h =================================================================== --- include/llvm/BinaryFormat/ELF.h +++ include/llvm/BinaryFormat/ELF.h @@ -335,33 +335,31 @@ // OS ABI identification. enum { - ELFOSABI_NONE = 0, // UNIX System V ABI - ELFOSABI_HPUX = 1, // HP-UX operating system - ELFOSABI_NETBSD = 2, // NetBSD - ELFOSABI_GNU = 3, // GNU/Linux - ELFOSABI_LINUX = 3, // Historical alias for ELFOSABI_GNU. - ELFOSABI_HURD = 4, // GNU/Hurd - ELFOSABI_SOLARIS = 6, // Solaris - ELFOSABI_AIX = 7, // AIX - ELFOSABI_IRIX = 8, // IRIX - ELFOSABI_FREEBSD = 9, // FreeBSD - ELFOSABI_TRU64 = 10, // TRU64 UNIX - ELFOSABI_MODESTO = 11, // Novell Modesto - ELFOSABI_OPENBSD = 12, // OpenBSD - ELFOSABI_OPENVMS = 13, // OpenVMS - ELFOSABI_NSK = 14, // Hewlett-Packard Non-Stop Kernel - ELFOSABI_AROS = 15, // AROS - ELFOSABI_FENIXOS = 16, // FenixOS - ELFOSABI_CLOUDABI = 17, // Nuxi CloudABI - ELFOSABI_FIRST_ARCH = 64, // First architecture-specific OS ABI - ELFOSABI_AMDGPU_HSA = 64, // AMD HSA runtime - ELFOSABI_AMDGPU_PAL = 65, // AMD PAL runtime - ELFOSABI_AMDGPU_MESA3D = 66, // AMD GCN GPUs (GFX6+) for MESA runtime - ELFOSABI_ARM = 97, // ARM - ELFOSABI_C6000_ELFABI = 64, // Bare-metal TMS320C6000 - ELFOSABI_C6000_LINUX = 65, // Linux TMS320C6000 - ELFOSABI_STANDALONE = 255, // Standalone (embedded) application - ELFOSABI_LAST_ARCH = 255 // Last Architecture-specific OS ABI + ELFOSABI_NONE = 0, // UNIX System V ABI + ELFOSABI_HPUX = 1, // HP-UX operating system + ELFOSABI_NETBSD = 2, // NetBSD + ELFOSABI_GNU = 3, // GNU/Linux + ELFOSABI_LINUX = 3, // Historical alias for ELFOSABI_GNU. + ELFOSABI_HURD = 4, // GNU/Hurd + ELFOSABI_SOLARIS = 6, // Solaris + ELFOSABI_AIX = 7, // AIX + ELFOSABI_IRIX = 8, // IRIX + ELFOSABI_FREEBSD = 9, // FreeBSD + ELFOSABI_TRU64 = 10, // TRU64 UNIX + ELFOSABI_MODESTO = 11, // Novell Modesto + ELFOSABI_OPENBSD = 12, // OpenBSD + ELFOSABI_OPENVMS = 13, // OpenVMS + ELFOSABI_NSK = 14, // Hewlett-Packard Non-Stop Kernel + ELFOSABI_AROS = 15, // AROS + ELFOSABI_FENIXOS = 16, // FenixOS + ELFOSABI_CLOUDABI = 17, // Nuxi CloudABI + ELFOSABI_FIRST_ARCH = 64, // First architecture-specific OS ABI + ELFOSABI_AMDGPU_HSA = 64, // AMD HSA runtime + ELFOSABI_C6000_ELFABI = 64, // Bare-metal TMS320C6000 + ELFOSABI_C6000_LINUX = 65, // Linux TMS320C6000 + ELFOSABI_ARM = 97, // ARM + ELFOSABI_STANDALONE = 255, // Standalone (embedded) application + ELFOSABI_LAST_ARCH = 255 // Last Architecture-specific OS ABI }; #define ELF_RELOC(name, value) name = value, Index: include/llvm/Config/config.h.cmake =================================================================== --- include/llvm/Config/config.h.cmake +++ include/llvm/Config/config.h.cmake @@ -185,9 +185,6 @@ /* Define to 1 if you have the `setenv' function. */ #cmakedefine HAVE_SETENV ${HAVE_SETENV} -/* Define to 1 if you have the `sched_getaffinity' function. */ -#cmakedefine HAVE_SCHED_GETAFFINITY ${HAVE_SCHED_GETAFFINITY} - /* Define to 1 if you have the `setrlimit' function. */ #cmakedefine HAVE_SETRLIMIT ${HAVE_SETRLIMIT} Index: include/llvm/DebugInfo/CodeView/CodeView.h =================================================================== --- include/llvm/DebugInfo/CodeView/CodeView.h +++ include/llvm/DebugInfo/CodeView/CodeView.h @@ -505,9 +505,55 @@ // Corresponds to CV_HREG_e enum. enum class RegisterId : uint16_t { -#define CV_REGISTER(name, value) name = value, -#include "CodeViewRegisters.def" -#undef CV_REGISTER + Unknown = 0, + VFrame = 30006, + AL = 1, + CL = 2, + DL = 3, + BL = 4, + AH = 5, + CH = 6, + DH = 7, + BH = 8, + AX = 9, + CX = 10, + DX = 11, + BX = 12, + SP = 13, + BP = 14, + SI = 15, + DI = 16, + EAX = 17, + ECX = 18, + EDX = 19, + EBX = 20, + ESP = 21, + EBP = 22, + ESI = 23, + EDI = 24, + ES = 25, + CS = 26, + SS = 27, + DS = 28, + FS = 29, + GS = 30, + IP = 31, + RAX = 328, + RBX = 329, + RCX = 330, + RDX = 331, + RSI = 332, + RDI = 333, + RBP = 334, + RSP = 335, + R8 = 336, + R9 = 337, + R10 = 338, + R11 = 339, + R12 = 340, + R13 = 341, + R14 = 342, + R15 = 343, }; /// These values correspond to the THUNK_ORDINAL enumeration. Index: include/llvm/DebugInfo/CodeView/CodeViewRegisters.def =================================================================== --- include/llvm/DebugInfo/CodeView/CodeViewRegisters.def +++ /dev/null @@ -1,268 +0,0 @@ -//===-- CodeViewRegisters.def - CodeView registers --------------*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// See CV_HREG_e in cvconst.h. This should match the constants there. -// -//===----------------------------------------------------------------------===// - -#ifndef CV_REGISTER -#define CV_REGISTER(name, value) -#endif - -// This currently only contains the "register subset shraed by all processor -// types" (ERR etc.) and the x86 registers. - -CV_REGISTER(ERR, 30000) -CV_REGISTER(TEB, 30001) -CV_REGISTER(TIMER, 30002) -CV_REGISTER(EFAD1, 30003) -CV_REGISTER(EFAD2, 30004) -CV_REGISTER(EFAD3, 30005) -CV_REGISTER(VFRAME, 30006) -CV_REGISTER(HANDLE, 30007) -CV_REGISTER(PARAMS, 30008) -CV_REGISTER(LOCALS, 30009) -CV_REGISTER(TID, 30010) -CV_REGISTER(ENV, 30011) -CV_REGISTER(CMDLN, 30012) - -CV_REGISTER(NONE, 0) -CV_REGISTER(AL, 1) -CV_REGISTER(CL, 2) -CV_REGISTER(DL, 3) -CV_REGISTER(BL, 4) -CV_REGISTER(AH, 5) -CV_REGISTER(CH, 6) -CV_REGISTER(DH, 7) -CV_REGISTER(BH, 8) -CV_REGISTER(AX, 9) -CV_REGISTER(CX, 10) -CV_REGISTER(DX, 11) -CV_REGISTER(BX, 12) -CV_REGISTER(SP, 13) -CV_REGISTER(BP, 14) -CV_REGISTER(SI, 15) -CV_REGISTER(DI, 16) -CV_REGISTER(EAX, 17) -CV_REGISTER(ECX, 18) -CV_REGISTER(EDX, 19) -CV_REGISTER(EBX, 20) -CV_REGISTER(ESP, 21) -CV_REGISTER(EBP, 22) -CV_REGISTER(ESI, 23) -CV_REGISTER(EDI, 24) -CV_REGISTER(ES, 25) -CV_REGISTER(CS, 26) -CV_REGISTER(SS, 27) -CV_REGISTER(DS, 28) -CV_REGISTER(FS, 29) -CV_REGISTER(GS, 30) -CV_REGISTER(IP, 31) -CV_REGISTER(FLAGS, 32) -CV_REGISTER(EIP, 33) -CV_REGISTER(EFLAGS, 34) -CV_REGISTER(TEMP, 40) -CV_REGISTER(TEMPH, 41) -CV_REGISTER(QUOTE, 42) -CV_REGISTER(PCDR3, 43) -CV_REGISTER(PCDR4, 44) -CV_REGISTER(PCDR5, 45) -CV_REGISTER(PCDR6, 46) -CV_REGISTER(PCDR7, 47) -CV_REGISTER(CR0, 80) -CV_REGISTER(CR1, 81) -CV_REGISTER(CR2, 82) -CV_REGISTER(CR3, 83) -CV_REGISTER(CR4, 84) -CV_REGISTER(DR0, 90) -CV_REGISTER(DR1, 91) -CV_REGISTER(DR2, 92) -CV_REGISTER(DR3, 93) -CV_REGISTER(DR4, 94) -CV_REGISTER(DR5, 95) -CV_REGISTER(DR6, 96) -CV_REGISTER(DR7, 97) -CV_REGISTER(GDTR, 110) -CV_REGISTER(GDTL, 111) -CV_REGISTER(IDTR, 112) -CV_REGISTER(IDTL, 113) -CV_REGISTER(LDTR, 114) -CV_REGISTER(TR, 115) - -CV_REGISTER(PSEUDO1, 116) -CV_REGISTER(PSEUDO2, 117) -CV_REGISTER(PSEUDO3, 118) -CV_REGISTER(PSEUDO4, 119) -CV_REGISTER(PSEUDO5, 120) -CV_REGISTER(PSEUDO6, 121) -CV_REGISTER(PSEUDO7, 122) -CV_REGISTER(PSEUDO8, 123) -CV_REGISTER(PSEUDO9, 124) - -CV_REGISTER(ST0, 128) -CV_REGISTER(ST1, 129) -CV_REGISTER(ST2, 130) -CV_REGISTER(ST3, 131) -CV_REGISTER(ST4, 132) -CV_REGISTER(ST5, 133) -CV_REGISTER(ST6, 134) -CV_REGISTER(ST7, 135) -CV_REGISTER(CTRL, 136) -CV_REGISTER(STAT, 137) -CV_REGISTER(TAG, 138) -CV_REGISTER(FPIP, 139) -CV_REGISTER(FPCS, 140) -CV_REGISTER(FPDO, 141) -CV_REGISTER(FPDS, 142) -CV_REGISTER(ISEM, 143) -CV_REGISTER(FPEIP, 144) -CV_REGISTER(FPEDO, 145) - -CV_REGISTER(MM0, 146) -CV_REGISTER(MM1, 147) -CV_REGISTER(MM2, 148) -CV_REGISTER(MM3, 149) -CV_REGISTER(MM4, 150) -CV_REGISTER(MM5, 151) -CV_REGISTER(MM6, 152) -CV_REGISTER(MM7, 153) - -CV_REGISTER(XMM0, 154) -CV_REGISTER(XMM1, 155) -CV_REGISTER(XMM2, 156) -CV_REGISTER(XMM3, 157) -CV_REGISTER(XMM4, 158) -CV_REGISTER(XMM5, 159) -CV_REGISTER(XMM6, 160) -CV_REGISTER(XMM7, 161) - -CV_REGISTER(MXCSR, 211) - -CV_REGISTER(EDXEAX, 212) - -CV_REGISTER(EMM0L, 220) -CV_REGISTER(EMM1L, 221) -CV_REGISTER(EMM2L, 222) -CV_REGISTER(EMM3L, 223) -CV_REGISTER(EMM4L, 224) -CV_REGISTER(EMM5L, 225) -CV_REGISTER(EMM6L, 226) -CV_REGISTER(EMM7L, 227) - -CV_REGISTER(EMM0H, 228) -CV_REGISTER(EMM1H, 229) -CV_REGISTER(EMM2H, 230) -CV_REGISTER(EMM3H, 231) -CV_REGISTER(EMM4H, 232) -CV_REGISTER(EMM5H, 233) -CV_REGISTER(EMM6H, 234) -CV_REGISTER(EMM7H, 235) - -CV_REGISTER(MM00, 236) -CV_REGISTER(MM01, 237) -CV_REGISTER(MM10, 238) -CV_REGISTER(MM11, 239) -CV_REGISTER(MM20, 240) -CV_REGISTER(MM21, 241) -CV_REGISTER(MM30, 242) -CV_REGISTER(MM31, 243) -CV_REGISTER(MM40, 244) -CV_REGISTER(MM41, 245) -CV_REGISTER(MM50, 246) -CV_REGISTER(MM51, 247) -CV_REGISTER(MM60, 248) -CV_REGISTER(MM61, 249) -CV_REGISTER(MM70, 250) -CV_REGISTER(MM71, 251) - -CV_REGISTER(BND0, 396) -CV_REGISTER(BND1, 397) -CV_REGISTER(BND2, 398) - - -CV_REGISTER(XMM8, 252) -CV_REGISTER(XMM9, 253) -CV_REGISTER(XMM10, 254) -CV_REGISTER(XMM11, 255) -CV_REGISTER(XMM12, 256) -CV_REGISTER(XMM13, 257) -CV_REGISTER(XMM14, 258) -CV_REGISTER(XMM15, 259) - - -CV_REGISTER(SIL, 324) -CV_REGISTER(DIL, 325) -CV_REGISTER(BPL, 326) -CV_REGISTER(SPL, 327) - -CV_REGISTER(RAX, 328) -CV_REGISTER(RBX, 329) -CV_REGISTER(RCX, 330) -CV_REGISTER(RDX, 331) -CV_REGISTER(RSI, 332) -CV_REGISTER(RDI, 333) -CV_REGISTER(RBP, 334) -CV_REGISTER(RSP, 335) - -CV_REGISTER(R8, 336) -CV_REGISTER(R9, 337) -CV_REGISTER(R10, 338) -CV_REGISTER(R11, 339) -CV_REGISTER(R12, 340) -CV_REGISTER(R13, 341) -CV_REGISTER(R14, 342) -CV_REGISTER(R15, 343) - -CV_REGISTER(R8B, 344) -CV_REGISTER(R9B, 345) -CV_REGISTER(R10B, 346) -CV_REGISTER(R11B, 347) -CV_REGISTER(R12B, 348) -CV_REGISTER(R13B, 349) -CV_REGISTER(R14B, 350) -CV_REGISTER(R15B, 351) - -CV_REGISTER(R8W, 352) -CV_REGISTER(R9W, 353) -CV_REGISTER(R10W, 354) -CV_REGISTER(R11W, 355) -CV_REGISTER(R12W, 356) -CV_REGISTER(R13W, 357) -CV_REGISTER(R14W, 358) -CV_REGISTER(R15W, 359) - -CV_REGISTER(R8D, 360) -CV_REGISTER(R9D, 361) -CV_REGISTER(R10D, 362) -CV_REGISTER(R11D, 363) -CV_REGISTER(R12D, 364) -CV_REGISTER(R13D, 365) -CV_REGISTER(R14D, 366) -CV_REGISTER(R15D, 367) - - -// cvconst.h defines both CV_REG_YMM0 (252) and CV_AMD64_YMM0 (368). Keep the -// original prefix to distinguish them. - -CV_REGISTER(AMD64_YMM0, 368) -CV_REGISTER(AMD64_YMM1, 369) -CV_REGISTER(AMD64_YMM2, 370) -CV_REGISTER(AMD64_YMM3, 371) -CV_REGISTER(AMD64_YMM4, 372) -CV_REGISTER(AMD64_YMM5, 373) -CV_REGISTER(AMD64_YMM6, 374) -CV_REGISTER(AMD64_YMM7, 375) -CV_REGISTER(AMD64_YMM8, 376) -CV_REGISTER(AMD64_YMM9, 377) -CV_REGISTER(AMD64_YMM10, 378) -CV_REGISTER(AMD64_YMM11, 379) -CV_REGISTER(AMD64_YMM12, 380) -CV_REGISTER(AMD64_YMM13, 381) -CV_REGISTER(AMD64_YMM14, 382) -CV_REGISTER(AMD64_YMM15, 383) Index: include/llvm/IR/DIBuilder.h =================================================================== --- include/llvm/IR/DIBuilder.h +++ include/llvm/IR/DIBuilder.h @@ -74,17 +74,6 @@ /// Create an \a temporary node and track it in \a UnresolvedNodes. void trackIfUnresolved(MDNode *N); - /// Internal helper for insertDeclare. - Instruction *insertDeclare(llvm::Value *Storage, DILocalVariable *VarInfo, - DIExpression *Expr, const DILocation *DL, - BasicBlock *InsertBB, Instruction *InsertBefore); - - /// Internal helper for insertDbgValueIntrinsic. - Instruction * - insertDbgValueIntrinsic(llvm::Value *Val, DILocalVariable *VarInfo, - DIExpression *Expr, const DILocation *DL, - BasicBlock *InsertBB, Instruction *InsertBefore); - public: /// Construct a builder for a module. /// Index: include/llvm/IR/InstrTypes.h =================================================================== --- include/llvm/IR/InstrTypes.h +++ include/llvm/IR/InstrTypes.h @@ -789,14 +789,6 @@ Type *IntPtrTy ///< Integer type corresponding to Ptr types ); - /// @brief Determine if the described cast is a no-op cast. - static bool isNoopCast( - Instruction::CastOps Opcode, ///< Opcode of cast - Type *SrcTy, ///< SrcTy of cast - Type *DstTy, ///< DstTy of cast - const DataLayout &DL ///< DataLayout to get the Int Ptr type from. - ); - /// @brief Determine if this cast is a no-op cast. bool isNoopCast( Type *IntPtrTy ///< Integer type corresponding to pointer Index: include/llvm/MC/MCParser/MCTargetAsmParser.h =================================================================== --- include/llvm/MC/MCParser/MCTargetAsmParser.h +++ include/llvm/MC/MCParser/MCTargetAsmParser.h @@ -132,139 +132,6 @@ MatchOperand_ParseFail // operand matched but had errors }; -// When matching of an assembly instruction fails, there may be multiple -// encodings that are close to being a match. It's often ambiguous which one -// the programmer intended to use, so we want to report an error which mentions -// each of these "near-miss" encodings. This struct contains information about -// one such encoding, and why it did not match the parsed instruction. -class NearMissInfo { -public: - enum NearMissKind { - NoNearMiss, - NearMissOperand, - NearMissFeature, - NearMissPredicate, - NearMissTooFewOperands, - }; - - // The encoding is valid for the parsed assembly string. This is only used - // internally to the table-generated assembly matcher. - static NearMissInfo getSuccess() { return NearMissInfo(); } - - // The instruction encoding is not valid because it requires some target - // features that are not currently enabled. MissingFeatures has a bit set for - // each feature that the encoding needs but which is not enabled. - static NearMissInfo getMissedFeature(uint64_t MissingFeatures) { - NearMissInfo Result; - Result.Kind = NearMissFeature; - Result.Features = MissingFeatures; - return Result; - } - - // The instruction encoding is not valid because the target-specific - // predicate function returned an error code. FailureCode is the - // target-specific error code returned by the predicate. - static NearMissInfo getMissedPredicate(unsigned FailureCode) { - NearMissInfo Result; - Result.Kind = NearMissPredicate; - Result.PredicateError = FailureCode; - return Result; - } - - // The instruction encoding is not valid because one (and only one) parsed - // operand is not of the correct type. OperandError is the error code - // relating to the operand class expected by the encoding. OperandClass is - // the type of the expected operand. Opcode is the opcode of the encoding. - // OperandIndex is the index into the parsed operand list. - static NearMissInfo getMissedOperand(unsigned OperandError, - unsigned OperandClass, unsigned Opcode, - unsigned OperandIndex) { - NearMissInfo Result; - Result.Kind = NearMissOperand; - Result.MissedOperand.Error = OperandError; - Result.MissedOperand.Class = OperandClass; - Result.MissedOperand.Opcode = Opcode; - Result.MissedOperand.Index = OperandIndex; - return Result; - } - - // The instruction encoding is not valid because it expects more operands - // than were parsed. OperandClass is the class of the expected operand that - // was not provided. Opcode is the instruction encoding. - static NearMissInfo getTooFewOperands(unsigned OperandClass, - unsigned Opcode) { - NearMissInfo Result; - Result.Kind = NearMissTooFewOperands; - Result.TooFewOperands.Class = OperandClass; - Result.TooFewOperands.Opcode = Opcode; - return Result; - } - - operator bool() const { return Kind != NoNearMiss; } - - NearMissKind getKind() const { return Kind; } - - // Feature flags required by the instruction, that the current target does - // not have. - uint64_t getFeatures() const { - assert(Kind == NearMissFeature); - return Features; - } - // Error code returned by the target predicate when validating this - // instruction encoding. - unsigned getPredicateError() const { - assert(Kind == NearMissPredicate); - return PredicateError; - } - // MatchClassKind of the operand that we expected to see. - unsigned getOperandClass() const { - assert(Kind == NearMissOperand || Kind == NearMissTooFewOperands); - return MissedOperand.Class; - } - // Opcode of the encoding we were trying to match. - unsigned getOpcode() const { - assert(Kind == NearMissOperand || Kind == NearMissTooFewOperands); - return MissedOperand.Opcode; - } - // Error code returned when validating the operand. - unsigned getOperandError() const { - assert(Kind == NearMissOperand); - return MissedOperand.Error; - } - // Index of the actual operand we were trying to match in the list of parsed - // operands. - unsigned getOperandIndex() const { - assert(Kind == NearMissOperand); - return MissedOperand.Index; - } - -private: - NearMissKind Kind; - - // These two structs share a common prefix, so we can safely rely on the fact - // that they overlap in the union. - struct MissedOpInfo { - unsigned Class; - unsigned Opcode; - unsigned Error; - unsigned Index; - }; - - struct TooFewOperandsInfo { - unsigned Class; - unsigned Opcode; - }; - - union { - uint64_t Features; - unsigned PredicateError; - MissedOpInfo MissedOperand; - TooFewOperandsInfo TooFewOperands; - }; - - NearMissInfo() : Kind(NoNearMiss) {} -}; - /// MCTargetAsmParser - Generic interface to target specific assembly parsers. class MCTargetAsmParser : public MCAsmParserExtension { public: @@ -273,7 +140,6 @@ Match_MissingFeature, Match_MnemonicFail, Match_Success, - Match_NearMisses, FIRST_TARGET_MATCH_RESULT_TY }; Index: include/llvm/Object/ELFObjectFile.h =================================================================== --- include/llvm/Object/ELFObjectFile.h +++ include/llvm/Object/ELFObjectFile.h @@ -995,7 +995,9 @@ case ELF::EM_WEBASSEMBLY: return "ELF64-wasm"; case ELF::EM_AMDGPU: - return "ELF64-amdgpu"; + return (EF.getHeader()->e_ident[ELF::EI_OSABI] == ELF::ELFOSABI_AMDGPU_HSA + && IsLittleEndian) ? + "ELF64-amdgpu-hsacobj" : "ELF64-amdgpu"; case ELF::EM_BPF: return "ELF64-BPF"; default: @@ -1064,13 +1066,10 @@ } case ELF::EM_AMDGPU: - if (EF.getHeader()->e_ident[ELF::EI_CLASS] != ELF::ELFCLASS64) - return Triple::UnknownArch; - if (!IsLittleEndian) - return Triple::UnknownArch; - - // TODO: Determine r600/amdgcn architecture based e_flags. - return Triple::amdgcn; + return (EF.getHeader()->e_ident[ELF::EI_CLASS] == ELF::ELFCLASS64 + && EF.getHeader()->e_ident[ELF::EI_OSABI] == ELF::ELFOSABI_AMDGPU_HSA + && IsLittleEndian) ? + Triple::amdgcn : Triple::UnknownArch; case ELF::EM_BPF: return IsLittleEndian ? Triple::bpfel : Triple::bpfeb; Index: include/llvm/Support/GenericDomTree.h =================================================================== --- include/llvm/Support/GenericDomTree.h +++ include/llvm/Support/GenericDomTree.h @@ -637,12 +637,11 @@ assert(Node && "Removing node that isn't in dominator tree."); assert(Node->getChildren().empty() && "Node is not a leaf node."); - DFSInfoValid = false; - // Remove node from immediate dominator's children list. DomTreeNodeBase *IDom = Node->getIDom(); if (IDom) { - const auto I = find(IDom->Children, Node); + typename std::vector *>::iterator I = + find(IDom->Children, Node); assert(I != IDom->Children.end() && "Not in immediate dominator children set!"); // I am no longer your child... @@ -703,25 +702,28 @@ return; } + unsigned DFSNum = 0; + SmallVector *, typename DomTreeNodeBase::const_iterator>, 32> WorkStack; const DomTreeNodeBase *ThisRoot = getRootNode(); - assert((!Parent || ThisRoot) && "Empty constructed DomTree"); + if (!ThisRoot) return; - // Both dominators and postdominators have a single root node. In the case - // case of PostDominatorTree, this node is a virtual root. - WorkStack.push_back({ThisRoot, ThisRoot->begin()}); - - unsigned DFSNum = 0; + // Even in the case of multiple exits that form the post dominator root + // nodes, do not iterate over all exits, but start from the virtual root + // node. Otherwise bbs, that are not post dominated by any exit but by the + // virtual root node, will never be assigned a DFS number. + WorkStack.push_back(std::make_pair(ThisRoot, ThisRoot->begin())); ThisRoot->DFSNumIn = DFSNum++; while (!WorkStack.empty()) { const DomTreeNodeBase *Node = WorkStack.back().first; - const auto ChildIt = WorkStack.back().second; + typename DomTreeNodeBase::const_iterator ChildIt = + WorkStack.back().second; // If we visited all of the children of this node, "recurse" back up the // stack setting the DFOutNum. @@ -733,7 +735,7 @@ const DomTreeNodeBase *Child = *ChildIt; ++WorkStack.back().second; - WorkStack.push_back({Child, Child->begin()}); + WorkStack.push_back(std::make_pair(Child, Child->begin())); Child->DFSNumIn = DFSNum++; } } Index: include/llvm/Support/GenericDomTreeConstruction.h =================================================================== --- include/llvm/Support/GenericDomTreeConstruction.h +++ include/llvm/Support/GenericDomTreeConstruction.h @@ -1349,102 +1349,6 @@ return true; } - // Check if the computed DFS numbers are correct. Note that DFS info may not - // be valid, and when that is the case, we don't verify the numbers. - static bool VerifyDFSNumbers(const DomTreeT &DT) { - if (!DT.DFSInfoValid || !DT.Parent) - return true; - - const NodePtr RootBB = IsPostDom ? nullptr : DT.getRoots()[0]; - const TreeNodePtr Root = DT.getNode(RootBB); - - auto PrintNodeAndDFSNums = [](const TreeNodePtr TN) { - errs() << BlockNamePrinter(TN) << " {" << TN->getDFSNumIn() << ", " - << TN->getDFSNumOut() << '}'; - }; - - // Verify the root's DFS In number. Although DFS numbering would also work - // if we started from some other value, we assume 0-based numbering. - if (Root->getDFSNumIn() != 0) { - errs() << "DFSIn number for the tree root is not:\n\t"; - PrintNodeAndDFSNums(Root); - errs() << '\n'; - errs().flush(); - return false; - } - - // For each tree node verify if children's DFS numbers cover their parent's - // DFS numbers with no gaps. - for (const auto &NodeToTN : DT.DomTreeNodes) { - const TreeNodePtr Node = NodeToTN.second.get(); - - // Handle tree leaves. - if (Node->getChildren().empty()) { - if (Node->getDFSNumIn() + 1 != Node->getDFSNumOut()) { - errs() << "Tree leaf should have DFSOut = DFSIn + 1:\n\t"; - PrintNodeAndDFSNums(Node); - errs() << '\n'; - errs().flush(); - return false; - } - - continue; - } - - // Make a copy and sort it such that it is possible to check if there are - // no gaps between DFS numbers of adjacent children. - SmallVector Children(Node->begin(), Node->end()); - std::sort(Children.begin(), Children.end(), - [](const TreeNodePtr Ch1, const TreeNodePtr Ch2) { - return Ch1->getDFSNumIn() < Ch2->getDFSNumIn(); - }); - - auto PrintChildrenError = [Node, &Children, PrintNodeAndDFSNums]( - const TreeNodePtr FirstCh, const TreeNodePtr SecondCh) { - assert(FirstCh); - - errs() << "Incorrect DFS numbers for:\n\tParent "; - PrintNodeAndDFSNums(Node); - - errs() << "\n\tChild "; - PrintNodeAndDFSNums(FirstCh); - - if (SecondCh) { - errs() << "\n\tSecond child "; - PrintNodeAndDFSNums(SecondCh); - } - - errs() << "\nAll children: "; - for (const TreeNodePtr Ch : Children) { - PrintNodeAndDFSNums(Ch); - errs() << ", "; - } - - errs() << '\n'; - errs().flush(); - }; - - if (Children.front()->getDFSNumIn() != Node->getDFSNumIn() + 1) { - PrintChildrenError(Children.front(), nullptr); - return false; - } - - if (Children.back()->getDFSNumOut() + 1 != Node->getDFSNumOut()) { - PrintChildrenError(Children.back(), nullptr); - return false; - } - - for (size_t i = 0, e = Children.size() - 1; i != e; ++i) { - if (Children[i]->getDFSNumOut() + 1 != Children[i + 1]->getDFSNumIn()) { - PrintChildrenError(Children[i], Children[i + 1]); - return false; - } - } - } - - return true; - } - // Checks if for every edge From -> To in the graph // NCD(From, To) == IDom(To) or To. bool verifyNCD(const DomTreeT &DT) { @@ -1617,8 +1521,7 @@ SemiNCAInfo SNCA(nullptr); return SNCA.verifyRoots(DT) && SNCA.verifyReachability(DT) && SNCA.VerifyLevels(DT) && SNCA.verifyNCD(DT) && - SNCA.verifyParentProperty(DT) && SNCA.verifySiblingProperty(DT) && - SNCA.VerifyDFSNumbers(DT); + SNCA.verifyParentProperty(DT) && SNCA.verifySiblingProperty(DT); } } // namespace DomTreeBuilder Index: include/llvm/Support/ThreadPool.h =================================================================== --- include/llvm/Support/ThreadPool.h +++ include/llvm/Support/ThreadPool.h @@ -38,8 +38,8 @@ using TaskTy = std::function; using PackagedTaskTy = std::packaged_task; - /// Construct a pool with the number of threads found by - /// hardware_concurrency(). + /// Construct a pool with the number of core available on the system (or + /// whatever the value returned by std::thread::hardware_concurrency() is). ThreadPool(); /// Construct a pool of \p ThreadCount threads Index: include/llvm/Support/Threading.h =================================================================== --- include/llvm/Support/Threading.h +++ include/llvm/Support/Threading.h @@ -131,14 +131,6 @@ /// Returns 1 when LLVM is configured with LLVM_ENABLE_THREADS=OFF unsigned heavyweight_hardware_concurrency(); - /// Get the number of threads that the current program can execute - /// concurrently. On some systems std::thread::hardware_concurrency() returns - /// the total number of cores, without taking affinity into consideration. - /// Returns 1 when LLVM is configured with LLVM_ENABLE_THREADS=OFF. - /// Fallback to std::thread::hardware_concurrency() if sched_getaffinity is - /// not available. - unsigned hardware_concurrency(); - /// \brief Return the current thread id, as used in various OS system calls. /// Note that not all platforms guarantee that the value returned will be /// unique across the entire system, so portable code should not assume Index: include/llvm/Target/Target.td =================================================================== --- include/llvm/Target/Target.td +++ include/llvm/Target/Target.td @@ -677,10 +677,6 @@ // diagnostic. The target AsmParser maps these codes to text. string DiagnosticType = ""; - /// A diagnostic message to emit when an invalid value is provided for this - /// operand. - string DiagnosticString = ""; - /// Set to 1 if this operand is optional and not always required. Typically, /// the AsmParser will emit an error when it finishes parsing an /// instruction if it hasn't matched all the operands yet. However, this @@ -1130,14 +1126,6 @@ // HasMnemonicFirst - Set to false if target instructions don't always // start with a mnemonic as the first token. bit HasMnemonicFirst = 1; - - // ReportMultipleNearMisses - - // When 0, the assembly matcher reports an error for one encoding or operand - // that did not match the parsed instruction. - // When 1, the assmebly matcher returns a list of encodings that were close - // to matching the parsed instruction, so to allow more detailed error - // messages. - bit ReportMultipleNearMisses = 0; } def DefaultAsmParser : AsmParser; Index: include/llvm/module.modulemap =================================================================== --- include/llvm/module.modulemap +++ include/llvm/module.modulemap @@ -123,7 +123,6 @@ module * { export * } // These are intended for (repeated) textual inclusion. - textual header "DebugInfo/CodeView/CodeViewRegisters.def" textual header "DebugInfo/CodeView/CodeViewTypes.def" textual header "DebugInfo/CodeView/CodeViewSymbols.def" } Index: lib/Analysis/InlineCost.cpp =================================================================== --- lib/Analysis/InlineCost.cpp +++ lib/Analysis/InlineCost.cpp @@ -172,7 +172,6 @@ void accumulateSROACost(DenseMap::iterator CostIt, int InstructionCost); bool isGEPFree(GetElementPtrInst &GEP); - bool canFoldInboundsGEP(GetElementPtrInst &I); bool accumulateGEPOffset(GEPOperator &GEP, APInt &Offset); bool simplifyCallSite(Function *F, CallSite CS); template @@ -432,34 +431,40 @@ return true; } -/// \brief Check we can fold GEPs of constant-offset call site argument pointers. -/// This requires target data and inbounds GEPs. -/// -/// \return true if the specified GEP can be folded. -bool CallAnalyzer::canFoldInboundsGEP(GetElementPtrInst &I) { - // Check if we have a base + offset for the pointer. - std::pair BaseAndOffset = - ConstantOffsetPtrs.lookup(I.getPointerOperand()); - if (!BaseAndOffset.first) - return false; - - // Check if the offset of this GEP is constant, and if so accumulate it - // into Offset. - if (!accumulateGEPOffset(cast(I), BaseAndOffset.second)) - return false; - - // Add the result as a new mapping to Base + Offset. - ConstantOffsetPtrs[&I] = BaseAndOffset; - - return true; -} - bool CallAnalyzer::visitGetElementPtr(GetElementPtrInst &I) { Value *SROAArg; DenseMap::iterator CostIt; bool SROACandidate = lookupSROAArgAndCost(I.getPointerOperand(), SROAArg, CostIt); + // Try to fold GEPs of constant-offset call site argument pointers. This + // requires target data and inbounds GEPs. + if (I.isInBounds()) { + // Check if we have a base + offset for the pointer. + Value *Ptr = I.getPointerOperand(); + std::pair BaseAndOffset = ConstantOffsetPtrs.lookup(Ptr); + if (BaseAndOffset.first) { + // Check if the offset of this GEP is constant, and if so accumulate it + // into Offset. + if (!accumulateGEPOffset(cast(I), BaseAndOffset.second)) { + // Non-constant GEPs aren't folded, and disable SROA. + if (SROACandidate) + disableSROA(CostIt); + return isGEPFree(I); + } + + // Add the result as a new mapping to Base + Offset. + ConstantOffsetPtrs[&I] = BaseAndOffset; + + // Also handle SROA candidates here, we already know that the GEP is + // all-constant indexed. + if (SROACandidate) + SROAArgValues[&I] = SROAArg; + + return true; + } + } + // Lambda to check whether a GEP's indices are all constant. auto IsGEPOffsetConstant = [&](GetElementPtrInst &GEP) { for (User::op_iterator I = GEP.idx_begin(), E = GEP.idx_end(); I != E; ++I) @@ -468,7 +473,7 @@ return true; }; - if ((I.isInBounds() && canFoldInboundsGEP(I)) || IsGEPOffsetConstant(I)) { + if (IsGEPOffsetConstant(I)) { if (SROACandidate) SROAArgValues[&I] = SROAArg; Index: lib/Analysis/InstructionSimplify.cpp =================================================================== --- lib/Analysis/InstructionSimplify.cpp +++ lib/Analysis/InstructionSimplify.cpp @@ -3580,9 +3580,6 @@ // select true, X, Y -> X // select false, X, Y -> Y if (Constant *CB = dyn_cast(CondVal)) { - if (Constant *CT = dyn_cast(TrueVal)) - if (Constant *CF = dyn_cast(FalseVal)) - return ConstantFoldSelectInstruction(CB, CT, CF); if (CB->isAllOnesValue()) return TrueVal; if (CB->isNullValue()) Index: lib/Analysis/Lint.cpp =================================================================== --- lib/Analysis/Lint.cpp +++ lib/Analysis/Lint.cpp @@ -683,7 +683,7 @@ if (Instruction::isCast(CE->getOpcode())) { if (CastInst::isNoopCast(Instruction::CastOps(CE->getOpcode()), CE->getOperand(0)->getType(), CE->getType(), - *DL)) + DL->getIntPtrType(V->getType()))) return findValueImpl(CE->getOperand(0), OffsetOk, Visited); } else if (CE->getOpcode() == Instruction::ExtractValue) { ArrayRef Indices = CE->getIndices(); Index: lib/Analysis/SparsePropagation.cpp =================================================================== --- lib/Analysis/SparsePropagation.cpp +++ lib/Analysis/SparsePropagation.cpp @@ -36,13 +36,10 @@ // AbstractLatticeFunction Implementation //===----------------------------------------------------------------------===// -template -AbstractLatticeFunction::~AbstractLatticeFunction() = default; +AbstractLatticeFunction::~AbstractLatticeFunction() = default; /// PrintValue - Render the specified lattice value to the specified stream. -template -void AbstractLatticeFunction::PrintValue(LatticeVal V, - raw_ostream &OS) { +void AbstractLatticeFunction::PrintValue(LatticeVal V, raw_ostream &OS) { if (V == UndefVal) OS << "undefined"; else if (V == OverdefinedVal) @@ -57,14 +54,13 @@ // SparseSolver Implementation //===----------------------------------------------------------------------===// -/// getValueState - Return the LatticeVal object that corresponds to the +/// getOrInitValueState - Return the LatticeVal object that corresponds to the /// value, initializing the value's state if it hasn't been entered into the /// map yet. This function is necessary because not all values should start /// out in the underdefined state... Arguments should be overdefined, and /// constants should be marked as constants. -template -LatticeVal SparseSolver::getValueState(Value *V) { - auto I = ValueState.find(V); +SparseSolver::LatticeVal SparseSolver::getOrInitValueState(Value *V) { + DenseMap::iterator I = ValueState.find(V); if (I != ValueState.end()) return I->second; // Common case, in the map LatticeVal LV; @@ -89,9 +85,8 @@ /// UpdateState - When the state for some instruction is potentially updated, /// this function notices and adds I to the worklist if needed. -template -void SparseSolver::UpdateState(Instruction &Inst, LatticeVal V) { - auto I = ValueState.find(&Inst); +void SparseSolver::UpdateState(Instruction &Inst, LatticeVal V) { + DenseMap::iterator I = ValueState.find(&Inst); if (I != ValueState.end() && I->second == V) return; // No change. @@ -102,8 +97,7 @@ /// MarkBlockExecutable - This method can be used by clients to mark all of /// the blocks that are known to be intrinsically live in the processed unit. -template -void SparseSolver::MarkBlockExecutable(BasicBlock *BB) { +void SparseSolver::MarkBlockExecutable(BasicBlock *BB) { DEBUG(dbgs() << "Marking Block Executable: " << BB->getName() << "\n"); BBExecutable.insert(BB); // Basic block is executable! BBWorkList.push_back(BB); // Add the block to the work list! @@ -111,9 +105,7 @@ /// markEdgeExecutable - Mark a basic block as executable, adding it to the BB /// work list if it is not already executable... -template -void SparseSolver::markEdgeExecutable(BasicBlock *Source, - BasicBlock *Dest) { +void SparseSolver::markEdgeExecutable(BasicBlock *Source, BasicBlock *Dest) { if (!KnownFeasibleEdges.insert(Edge(Source, Dest)).second) return; // This edge is already known to be executable! @@ -133,9 +125,9 @@ /// getFeasibleSuccessors - Return a vector of booleans to indicate which /// successors are reachable from a given terminator instruction. -template -void SparseSolver::getFeasibleSuccessors( - TerminatorInst &TI, SmallVectorImpl &Succs, bool AggressiveUndef) { +void SparseSolver::getFeasibleSuccessors(TerminatorInst &TI, + SmallVectorImpl &Succs, + bool AggressiveUndef) { Succs.resize(TI.getNumSuccessors()); if (TI.getNumSuccessors() == 0) return; @@ -147,7 +139,7 @@ LatticeVal BCValue; if (AggressiveUndef) - BCValue = getValueState(BI->getCondition()); + BCValue = getOrInitValueState(BI->getCondition()); else BCValue = getLatticeState(BI->getCondition()); @@ -189,7 +181,7 @@ SwitchInst &SI = cast(TI); LatticeVal SCValue; if (AggressiveUndef) - SCValue = getValueState(SI.getCondition()); + SCValue = getOrInitValueState(SI.getCondition()); else SCValue = getLatticeState(SI.getCondition()); @@ -216,9 +208,8 @@ /// isEdgeFeasible - Return true if the control flow edge from the 'From' /// basic block to the 'To' basic block is currently feasible... -template -bool SparseSolver::isEdgeFeasible(BasicBlock *From, BasicBlock *To, - bool AggressiveUndef) { +bool SparseSolver::isEdgeFeasible(BasicBlock *From, BasicBlock *To, + bool AggressiveUndef) { SmallVector SuccFeasible; TerminatorInst *TI = From->getTerminator(); getFeasibleSuccessors(*TI, SuccFeasible, AggressiveUndef); @@ -230,8 +221,7 @@ return false; } -template -void SparseSolver::visitTerminatorInst(TerminatorInst &TI) { +void SparseSolver::visitTerminatorInst(TerminatorInst &TI) { SmallVector SuccFeasible; getFeasibleSuccessors(TI, SuccFeasible, true); @@ -243,8 +233,7 @@ markEdgeExecutable(BB, TI.getSuccessor(i)); } -template -void SparseSolver::visitPHINode(PHINode &PN) { +void SparseSolver::visitPHINode(PHINode &PN) { // The lattice function may store more information on a PHINode than could be // computed from its incoming values. For example, SSI form stores its sigma // functions as PHINodes with a single incoming value. @@ -255,7 +244,7 @@ return; } - LatticeVal PNIV = getValueState(&PN); + LatticeVal PNIV = getOrInitValueState(&PN); LatticeVal Overdefined = LatticeFunc->getOverdefinedVal(); // If this value is already overdefined (common) just return. @@ -278,7 +267,7 @@ continue; // Merge in this value. - LatticeVal OpVal = getValueState(PN.getIncomingValue(i)); + LatticeVal OpVal = getOrInitValueState(PN.getIncomingValue(i)); if (OpVal != PNIV) PNIV = LatticeFunc->MergeValues(PNIV, OpVal); @@ -290,8 +279,7 @@ UpdateState(PN, PNIV); } -template -void SparseSolver::visitInst(Instruction &I) { +void SparseSolver::visitInst(Instruction &I) { // PHIs are handled by the propagation logic, they are never passed into the // transfer functions. if (PHINode *PN = dyn_cast(&I)) @@ -307,7 +295,7 @@ visitTerminatorInst(*TI); } -template void SparseSolver::Solve(Function &F) { +void SparseSolver::Solve(Function &F) { MarkBlockExecutable(&F.getEntryBlock()); // Process the work lists until they are empty! @@ -343,8 +331,7 @@ } } -template -void SparseSolver::Print(Function &F, raw_ostream &OS) const { +void SparseSolver::Print(Function &F, raw_ostream &OS) const { OS << "\nFUNCTION: " << F.getName() << "\n"; for (auto &BB : F) { if (!BBExecutable.count(&BB)) Index: lib/CodeGen/CodeGenPrepare.cpp =================================================================== --- lib/CodeGen/CodeGenPrepare.cpp +++ lib/CodeGen/CodeGenPrepare.cpp @@ -2676,68 +2676,16 @@ struct ExtAddrMode : public TargetLowering::AddrMode { Value *BaseReg = nullptr; Value *ScaledReg = nullptr; - Value *OriginalValue = nullptr; - - enum FieldName { - NoField = 0x00, - BaseRegField = 0x01, - BaseGVField = 0x02, - BaseOffsField = 0x04, - ScaledRegField = 0x08, - ScaleField = 0x10, - MultipleFields = 0xff - }; ExtAddrMode() = default; void print(raw_ostream &OS) const; void dump() const; - FieldName compare(const ExtAddrMode &other) { - // First check that the types are the same on each field, as differing types - // is something we can't cope with later on. - if (BaseReg && other.BaseReg && - BaseReg->getType() != other.BaseReg->getType()) - return MultipleFields; - if (BaseGV && other.BaseGV && - BaseGV->getType() != other.BaseGV->getType()) - return MultipleFields; - if (ScaledReg && other.ScaledReg && - ScaledReg->getType() != other.ScaledReg->getType()) - return MultipleFields; - - // Check each field to see if it differs. - unsigned Result = NoField; - if (BaseReg != other.BaseReg) - Result |= BaseRegField; - if (BaseGV != other.BaseGV) - Result |= BaseGVField; - if (BaseOffs != other.BaseOffs) - Result |= BaseOffsField; - if (ScaledReg != other.ScaledReg) - Result |= ScaledRegField; - // Don't count 0 as being a different scale, because that actually means - // unscaled (which will already be counted by having no ScaledReg). - if (Scale && other.Scale && Scale != other.Scale) - Result |= ScaleField; - - if (countPopulation(Result) > 1) - return MultipleFields; - else - return static_cast(Result); - } - - // AddrModes with a base reg or gv where the reg/gv is just the original - // value are trivial. - bool isTrivial() { - bool Trivial = (BaseGV && BaseGV == OriginalValue) || - (BaseReg && BaseReg == OriginalValue); - // If the AddrMode is trivial it shouldn't have an offset or be scaled. - if (Trivial) { - assert(BaseOffs == 0); - assert(Scale == 0); - } - return Trivial; + bool operator==(const ExtAddrMode& O) const { + return (BaseReg == O.BaseReg) && (ScaledReg == O.ScaledReg) && + (BaseGV == O.BaseGV) && (BaseOffs == O.BaseOffs) && + (HasBaseReg == O.HasBaseReg) && (Scale == O.Scale); } }; @@ -3354,92 +3302,6 @@ Value *PromotedOperand) const; }; -/// \brief A helper class for combining addressing modes. -class AddressingModeCombiner { -private: - /// The addressing modes we've collected. - SmallVector AddrModes; - - /// The field in which the AddrModes differ, when we have more than one. - ExtAddrMode::FieldName DifferentField = ExtAddrMode::NoField; - - /// Are the AddrModes that we have all just equal to their original values? - bool AllAddrModesTrivial = true; - -public: - /// \brief Get the combined AddrMode - const ExtAddrMode &getAddrMode() const { - return AddrModes[0]; - } - - /// \brief Add a new AddrMode if it's compatible with the AddrModes we already - /// have. - /// \return True iff we succeeded in doing so. - bool addNewAddrMode(ExtAddrMode &NewAddrMode) { - // Take note of if we have any non-trivial AddrModes, as we need to detect - // when all AddrModes are trivial as then we would introduce a phi or select - // which just duplicates what's already there. - AllAddrModesTrivial = AllAddrModesTrivial && NewAddrMode.isTrivial(); - - // If this is the first addrmode then everything is fine. - if (AddrModes.empty()) { - AddrModes.emplace_back(NewAddrMode); - return true; - } - - // Figure out how different this is from the other address modes, which we - // can do just by comparing against the first one given that we only care - // about the cumulative difference. - ExtAddrMode::FieldName ThisDifferentField = - AddrModes[0].compare(NewAddrMode); - if (DifferentField == ExtAddrMode::NoField) - DifferentField = ThisDifferentField; - else if (DifferentField != ThisDifferentField) - DifferentField = ExtAddrMode::MultipleFields; - - // If this AddrMode is the same as all the others then everything is fine - // (which should only happen when there is actually only one AddrMode). - if (DifferentField == ExtAddrMode::NoField) { - assert(AddrModes.size() == 1); - return true; - } - - // If NewAddrMode differs in only one dimension then we can handle it by - // inserting a phi/select later on. - if (DifferentField != ExtAddrMode::MultipleFields) { - AddrModes.emplace_back(NewAddrMode); - return true; - } - - // We couldn't combine NewAddrMode with the rest, so return failure. - AddrModes.clear(); - return false; - } - - /// \brief Combine the addressing modes we've collected into a single - /// addressing mode. - /// \return True iff we successfully combined them or we only had one so - /// didn't need to combine them anyway. - bool combineAddrModes() { - // If we have no AddrModes then they can't be combined. - if (AddrModes.size() == 0) - return false; - - // A single AddrMode can trivially be combined. - if (AddrModes.size() == 1) - return true; - - // If the AddrModes we collected are all just equal to the value they are - // derived from then combining them wouldn't do anything useful. - if (AllAddrModesTrivial) - return false; - - // TODO: Combine multiple AddrModes by inserting a select or phi for the - // field in which the AddrModes differ. - return false; - } -}; - } // end anonymous namespace /// Try adding ScaleReg*Scale to the current addressing mode. @@ -4527,12 +4389,13 @@ SmallPtrSet Visited; worklist.push_back(Addr); - // Use a worklist to iteratively look through PHI and select nodes, and - // ensure that the addressing mode obtained from the non-PHI/select roots of - // the graph are compatible. - bool PhiOrSelectSeen = false; + // Use a worklist to iteratively look through PHI nodes, and ensure that + // the addressing mode obtained from the non-PHI roots of the graph + // are equivalent. + bool AddrModeFound = false; + bool PhiSeen = false; SmallVector AddrModeInsts; - AddressingModeCombiner AddrModes; + ExtAddrMode AddrMode; TypePromotionTransaction TPT(RemovedInsts); TypePromotionTransaction::ConstRestorationPt LastKnownGood = TPT.getRestorationPoint(); @@ -4556,14 +4419,7 @@ if (PHINode *P = dyn_cast(V)) { for (Value *IncValue : P->incoming_values()) worklist.push_back(IncValue); - PhiOrSelectSeen = true; - continue; - } - // Similar for select. - if (SelectInst *SI = dyn_cast(V)) { - worklist.push_back(SI->getFalseValue()); - worklist.push_back(SI->getTrueValue()); - PhiOrSelectSeen = true; + PhiSeen = true; continue; } @@ -4574,29 +4430,30 @@ ExtAddrMode NewAddrMode = AddressingModeMatcher::Match( V, AccessTy, AddrSpace, MemoryInst, AddrModeInsts, *TLI, *TRI, InsertedInsts, PromotedInsts, TPT); - NewAddrMode.OriginalValue = V; - if (!AddrModes.addNewAddrMode(NewAddrMode)) - break; + if (!AddrModeFound) { + AddrModeFound = true; + AddrMode = NewAddrMode; + continue; + } + if (NewAddrMode == AddrMode) + continue; + + AddrModeFound = false; + break; } - // Try to combine the AddrModes we've collected. If we couldn't collect any, - // or we have multiple but either couldn't combine them or combining them - // wouldn't do anything useful, bail out now. - if (!AddrModes.combineAddrModes()) { + // If the addressing mode couldn't be determined, or if multiple different + // ones were determined, bail out now. + if (!AddrModeFound) { TPT.rollback(LastKnownGood); return false; } TPT.commit(); - // Get the combined AddrMode (or the only AddrMode, if we only had one). - ExtAddrMode AddrMode = AddrModes.getAddrMode(); - // If all the instructions matched are already in this BB, don't do anything. - // If we saw a Phi node then it is not local definitely, and if we saw a select - // then we want to push the address calculation past it even if it's already - // in this BB. - if (!PhiOrSelectSeen && none_of(AddrModeInsts, [&](Value *V) { + // If we saw Phi node then it is not local definitely. + if (!PhiSeen && none_of(AddrModeInsts, [&](Value *V) { return IsNonLocalValue(V, MemoryInst->getParent()); })) { DEBUG(dbgs() << "CGP: Found local addrmode: " << AddrMode << "\n"); Index: lib/CodeGen/GlobalISel/LegalizerHelper.cpp =================================================================== --- lib/CodeGen/GlobalISel/LegalizerHelper.cpp +++ lib/CodeGen/GlobalISel/LegalizerHelper.cpp @@ -396,50 +396,6 @@ MI.eraseFromParent(); return Legalized; } - case TargetOpcode::G_OR: { - // Legalize bitwise operation: - // A = BinOp B, C - // into: - // B1, ..., BN = G_UNMERGE_VALUES B - // C1, ..., CN = G_UNMERGE_VALUES C - // A1 = BinOp B1, C2 - // ... - // AN = BinOp BN, CN - // A = G_MERGE_VALUES A1, ..., AN - unsigned NarrowSize = NarrowTy.getSizeInBits(); - int NumParts = - MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() / NarrowSize; - - // List the registers where the destination will be scattered. - SmallVector DstRegs; - // List the registers where the first argument will be split. - SmallVector SrcsReg1; - // List the registers where the second argument will be split. - SmallVector SrcsReg2; - // Create all the temporary registers. - for (int i = 0; i < NumParts; ++i) { - unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy); - unsigned SrcReg1 = MRI.createGenericVirtualRegister(NarrowTy); - unsigned SrcReg2 = MRI.createGenericVirtualRegister(NarrowTy); - - DstRegs.push_back(DstReg); - SrcsReg1.push_back(SrcReg1); - SrcsReg2.push_back(SrcReg2); - } - // Explode the big arguments into smaller chunks. - MIRBuilder.buildUnmerge(SrcsReg1, MI.getOperand(1).getReg()); - MIRBuilder.buildUnmerge(SrcsReg2, MI.getOperand(2).getReg()); - - // Do the operation on each small part. - for (int i = 0; i < NumParts; ++i) - MIRBuilder.buildOr(DstRegs[i], SrcsReg1[i], SrcsReg2[i]); - - // Gather the destination registers into the final destination. - unsigned DstReg = MI.getOperand(0).getReg(); - MIRBuilder.buildMerge(DstReg, DstRegs); - MI.eraseFromParent(); - return Legalized; - } } } Index: lib/CodeGen/GlobalISel/LegalizerInfo.cpp =================================================================== --- lib/CodeGen/GlobalISel/LegalizerInfo.cpp +++ lib/CodeGen/GlobalISel/LegalizerInfo.cpp @@ -48,7 +48,6 @@ DefaultActions[TargetOpcode::G_ADD] = NarrowScalar; DefaultActions[TargetOpcode::G_LOAD] = NarrowScalar; DefaultActions[TargetOpcode::G_STORE] = NarrowScalar; - DefaultActions[TargetOpcode::G_OR] = NarrowScalar; DefaultActions[TargetOpcode::G_BRCOND] = WidenScalar; DefaultActions[TargetOpcode::G_INSERT] = NarrowScalar; Index: lib/CodeGen/LiveDebugVariables.cpp =================================================================== --- lib/CodeGen/LiveDebugVariables.cpp +++ lib/CodeGen/LiveDebugVariables.cpp @@ -91,48 +91,8 @@ initializeLiveDebugVariablesPass(*PassRegistry::getPassRegistry()); } -enum : unsigned { UndefLocNo = ~0U }; - -/// Describes a location by number along with some flags about the original -/// usage of the location. -class DbgValueLocation { -public: - DbgValueLocation(unsigned LocNo, bool WasIndirect) - : LocNo(LocNo), WasIndirect(WasIndirect) { - static_assert(sizeof(*this) == sizeof(unsigned), "bad bitfield packing"); - assert(locNo() == LocNo && "location truncation"); - } - - DbgValueLocation() : LocNo(0), WasIndirect(0) {} - - unsigned locNo() const { - // Fix up the undef location number, which gets truncated. - return LocNo == INT_MAX ? UndefLocNo : LocNo; - } - bool wasIndirect() const { return WasIndirect; } - bool isUndef() const { return locNo() == UndefLocNo; } - - DbgValueLocation changeLocNo(unsigned NewLocNo) const { - return DbgValueLocation(NewLocNo, WasIndirect); - } - - friend inline bool operator==(const DbgValueLocation &LHS, - const DbgValueLocation &RHS) { - return LHS.LocNo == RHS.LocNo && LHS.WasIndirect == RHS.WasIndirect; - } - - friend inline bool operator!=(const DbgValueLocation &LHS, - const DbgValueLocation &RHS) { - return !(LHS == RHS); - } - -private: - unsigned LocNo : 31; - unsigned WasIndirect : 1; -}; - /// LocMap - Map of where a user value is live, and its location. -using LocMap = IntervalMap; +using LocMap = IntervalMap; namespace { @@ -150,6 +110,7 @@ class UserValue { const DILocalVariable *Variable; ///< The debug info variable we are part of. const DIExpression *Expression; ///< Any complex address expression. + bool IsIndirect; ///< true if this is a register-indirect+offset value. DebugLoc dl; ///< The debug location for the variable. This is ///< used by dwarf writer to find lexical scope. UserValue *leader; ///< Equivalence class leader. @@ -167,7 +128,7 @@ /// insertDebugValue - Insert a DBG_VALUE into MBB at Idx for LocNo. void insertDebugValue(MachineBasicBlock *MBB, SlotIndex Idx, - DbgValueLocation Loc, bool Spilled, LiveIntervals &LIS, + unsigned LocNo, bool Spilled, LiveIntervals &LIS, const TargetInstrInfo &TII); /// splitLocation - Replace OldLocNo ranges with NewRegs ranges where NewRegs @@ -177,10 +138,10 @@ public: /// UserValue - Create a new UserValue. - UserValue(const DILocalVariable *var, const DIExpression *expr, DebugLoc L, - LocMap::Allocator &alloc) - : Variable(var), Expression(expr), dl(std::move(L)), leader(this), - locInts(alloc) {} + UserValue(const DILocalVariable *var, const DIExpression *expr, bool i, + DebugLoc L, LocMap::Allocator &alloc) + : Variable(var), Expression(expr), IsIndirect(i), dl(std::move(L)), + leader(this), locInts(alloc) {} /// getLeader - Get the leader of this value's equivalence class. UserValue *getLeader() { @@ -195,12 +156,13 @@ /// match - Does this UserValue match the parameters? bool match(const DILocalVariable *Var, const DIExpression *Expr, - const DILocation *IA) const { - // FIXME: The fragment should be part of the equivalence class, but not - // other things in the expression like stack values. - return Var == Variable && Expr == Expression && dl->getInlinedAt() == IA; + const DILocation *IA, bool indirect) const { + return Var == Variable && Expr == Expression && dl->getInlinedAt() == IA && + indirect == IsIndirect; } + enum : unsigned { UndefLocNo = ~0U }; + /// merge - Merge equivalence classes. static UserValue *merge(UserValue *L1, UserValue *L2) { L2 = L2->getLeader(); @@ -249,15 +211,14 @@ void mapVirtRegs(LDVImpl *LDV); /// addDef - Add a definition point to this value. - void addDef(SlotIndex Idx, const MachineOperand &LocMO, bool IsIndirect) { - DbgValueLocation Loc(getLocationNo(LocMO), IsIndirect); + void addDef(SlotIndex Idx, const MachineOperand &LocMO) { // Add a singular (Idx,Idx) -> Loc mapping. LocMap::iterator I = locInts.find(Idx); if (!I.valid() || I.start() != Idx) - I.insert(Idx, Idx.getNextSlot(), Loc); + I.insert(Idx, Idx.getNextSlot(), getLocationNo(LocMO)); else // A later DBG_VALUE at the same SlotIndex overrides the old location. - I.setValue(Loc); + I.setValue(getLocationNo(LocMO)); } /// extendDef - Extend the current definition as far as possible down. @@ -265,12 +226,12 @@ /// range of VNI. /// End points where VNI is no longer live are added to Kills. /// @param Idx Starting point for the definition. - /// @param Loc Location number to propagate. + /// @param LocNo Location number to propagate. /// @param LR Restrict liveness to where LR has the value VNI. May be null. /// @param VNI When LR is not null, this is the value to restrict to. /// @param Kills Append end points of VNI's live range to Kills. /// @param LIS Live intervals analysis. - void extendDef(SlotIndex Idx, DbgValueLocation Loc, + void extendDef(SlotIndex Idx, unsigned LocNo, LiveRange *LR, const VNInfo *VNI, SmallVectorImpl *Kills, LiveIntervals &LIS); @@ -280,14 +241,13 @@ /// points, and add defs if possible. /// @param LI Scan for copies of the value in LI->reg. /// @param LocNo Location number of LI->reg. - /// @param WasIndirect Indicates if the original use of LI->reg was indirect /// @param Kills Points where the range of LocNo could be extended. /// @param NewDefs Append (Idx, LocNo) of inserted defs here. - void addDefsFromCopies( - LiveInterval *LI, unsigned LocNo, bool WasIndirect, - const SmallVectorImpl &Kills, - SmallVectorImpl> &NewDefs, - MachineRegisterInfo &MRI, LiveIntervals &LIS); + void addDefsFromCopies(LiveInterval *LI, unsigned LocNo, + const SmallVectorImpl &Kills, + SmallVectorImpl> &NewDefs, + MachineRegisterInfo &MRI, + LiveIntervals &LIS); /// computeIntervals - Compute the live intervals of all locations after /// collecting all their def points. @@ -342,7 +302,7 @@ /// getUserValue - Find or create a UserValue. UserValue *getUserValue(const DILocalVariable *Var, const DIExpression *Expr, - const DebugLoc &DL); + bool IsIndirect, const DebugLoc &DL); /// lookupVirtReg - Find the EC leader for VirtReg or null. UserValue *lookupVirtReg(unsigned VirtReg); @@ -440,13 +400,10 @@ OS << "\"\t"; for (LocMap::const_iterator I = locInts.begin(); I.valid(); ++I) { OS << " [" << I.start() << ';' << I.stop() << "):"; - if (I.value().isUndef()) + if (I.value() == UndefLocNo) OS << "undef"; - else { - OS << I.value().locNo(); - if (I.value().wasIndirect()) - OS << " ind"; - } + else + OS << I.value(); } for (unsigned i = 0, e = locations.size(); i != e; ++i) { OS << " Loc" << i << '='; @@ -470,18 +427,19 @@ } UserValue *LDVImpl::getUserValue(const DILocalVariable *Var, - const DIExpression *Expr, const DebugLoc &DL) { + const DIExpression *Expr, bool IsIndirect, + const DebugLoc &DL) { UserValue *&Leader = userVarMap[Var]; if (Leader) { UserValue *UV = Leader->getLeader(); Leader = UV; for (; UV; UV = UV->getNext()) - if (UV->match(Var, Expr, DL->getInlinedAt())) + if (UV->match(Var, Expr, DL->getInlinedAt(), IsIndirect)) return UV; } userValues.push_back( - llvm::make_unique(Var, Expr, DL, allocator)); + llvm::make_unique(Var, Expr, IsIndirect, DL, allocator)); UserValue *UV = userValues.back().get(); Leader = UserValue::merge(Leader, UV); return UV; @@ -508,15 +466,15 @@ return false; } - // Get or create the UserValue for (variable,offset) here. + // Get or create the UserValue for (variable,offset). bool IsIndirect = MI.getOperand(1).isImm(); if (IsIndirect) assert(MI.getOperand(1).getImm() == 0 && "DBG_VALUE with nonzero offset"); const DILocalVariable *Var = MI.getDebugVariable(); const DIExpression *Expr = MI.getDebugExpression(); - UserValue *UV = - getUserValue(Var, Expr, MI.getDebugLoc()); - UV->addDef(Idx, MI.getOperand(0), IsIndirect); + //here. + UserValue *UV = getUserValue(Var, Expr, IsIndirect, MI.getDebugLoc()); + UV->addDef(Idx, MI.getOperand(0)); return true; } @@ -551,7 +509,7 @@ /// We only propagate DBG_VALUES locally here. LiveDebugValues performs a /// data-flow analysis to propagate them beyond basic block boundaries. -void UserValue::extendDef(SlotIndex Idx, DbgValueLocation Loc, LiveRange *LR, +void UserValue::extendDef(SlotIndex Idx, unsigned LocNo, LiveRange *LR, const VNInfo *VNI, SmallVectorImpl *Kills, LiveIntervals &LIS) { SlotIndex Start = Idx; @@ -578,7 +536,7 @@ if (I.valid() && I.start() <= Start) { // Stop when meeting a different location or an already extended interval. Start = Start.getNextSlot(); - if (I.value() != Loc || I.stop() != Start) + if (I.value() != LocNo || I.stop() != Start) return; // This is a one-slot placeholder. Just skip it. ++I; @@ -594,14 +552,14 @@ Kills->push_back(Stop); if (Start < Stop) - I.insert(Start, Stop, Loc); + I.insert(Start, Stop, LocNo); } -void UserValue::addDefsFromCopies( - LiveInterval *LI, unsigned LocNo, bool WasIndirect, - const SmallVectorImpl &Kills, - SmallVectorImpl> &NewDefs, - MachineRegisterInfo &MRI, LiveIntervals &LIS) { +void +UserValue::addDefsFromCopies(LiveInterval *LI, unsigned LocNo, + const SmallVectorImpl &Kills, + SmallVectorImpl> &NewDefs, + MachineRegisterInfo &MRI, LiveIntervals &LIS) { if (Kills.empty()) return; // Don't track copies from physregs, there are too many uses. @@ -628,7 +586,7 @@ // it, or we are looking at a wrong value of LI. SlotIndex Idx = LIS.getInstructionIndex(*MI); LocMap::iterator I = locInts.find(Idx.getRegSlot(true)); - if (!I.valid() || I.value().locNo() != LocNo) + if (!I.valid() || I.value() != LocNo) continue; if (!LIS.hasInterval(DstReg)) @@ -661,9 +619,8 @@ MachineInstr *CopyMI = LIS.getInstructionFromIndex(DstVNI->def); assert(CopyMI && CopyMI->isCopy() && "Bad copy value"); unsigned LocNo = getLocationNo(CopyMI->getOperand(0)); - DbgValueLocation NewLoc(LocNo, WasIndirect); - I.insert(Idx, Idx.getNextSlot(), NewLoc); - NewDefs.push_back(std::make_pair(Idx, NewLoc)); + I.insert(Idx, Idx.getNextSlot(), LocNo); + NewDefs.push_back(std::make_pair(Idx, LocNo)); break; } } @@ -672,37 +629,36 @@ void UserValue::computeIntervals(MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, LiveIntervals &LIS, LexicalScopes &LS) { - SmallVector, 16> Defs; + SmallVector, 16> Defs; // Collect all defs to be extended (Skipping undefs). for (LocMap::const_iterator I = locInts.begin(); I.valid(); ++I) - if (!I.value().isUndef()) + if (I.value() != UndefLocNo) Defs.push_back(std::make_pair(I.start(), I.value())); // Extend all defs, and possibly add new ones along the way. for (unsigned i = 0; i != Defs.size(); ++i) { SlotIndex Idx = Defs[i].first; - DbgValueLocation Loc = Defs[i].second; - const MachineOperand &LocMO = locations[Loc.locNo()]; + unsigned LocNo = Defs[i].second; + const MachineOperand &Loc = locations[LocNo]; - if (!LocMO.isReg()) { - extendDef(Idx, Loc, nullptr, nullptr, nullptr, LIS); + if (!Loc.isReg()) { + extendDef(Idx, LocNo, nullptr, nullptr, nullptr, LIS); continue; } // Register locations are constrained to where the register value is live. - if (TargetRegisterInfo::isVirtualRegister(LocMO.getReg())) { + if (TargetRegisterInfo::isVirtualRegister(Loc.getReg())) { LiveInterval *LI = nullptr; const VNInfo *VNI = nullptr; - if (LIS.hasInterval(LocMO.getReg())) { - LI = &LIS.getInterval(LocMO.getReg()); + if (LIS.hasInterval(Loc.getReg())) { + LI = &LIS.getInterval(Loc.getReg()); VNI = LI->getVNInfoAt(Idx); } SmallVector Kills; - extendDef(Idx, Loc, LI, VNI, &Kills, LIS); + extendDef(Idx, LocNo, LI, VNI, &Kills, LIS); if (LI) - addDefsFromCopies(LI, Loc.locNo(), Loc.wasIndirect(), Kills, Defs, MRI, - LIS); + addDefsFromCopies(LI, LocNo, Kills, Defs, MRI, LIS); continue; } @@ -716,7 +672,7 @@ // Erase all the undefs. for (LocMap::iterator I = locInts.begin(); I.valid();) - if (I.value().isUndef()) + if (I.value() == UndefLocNo) I.erase(); else ++I; @@ -746,7 +702,7 @@ // I.stop() >= PrevEnd. Check for overlap. if (PrevEnd && I.start() < PrevEnd) { SlotIndex IStop = I.stop(); - DbgValueLocation Loc = I.value(); + unsigned LocNo = I.value(); // Stop overlaps previous end - trim the end of the interval to // the scope range. @@ -757,7 +713,7 @@ // current) range create a new interval for the remainder (which // may be further trimmed). if (RStart < IStop) - I.insert(RStart, IStop, Loc); + I.insert(RStart, IStop, LocNo); } // Advance I so that I.stop() >= RStart, and check for overlap. @@ -884,7 +840,7 @@ break; // Now LII->end > LocMapI.start(). Do we have an overlap? - if (LocMapI.value().locNo() == OldLocNo && LII->start < LocMapI.stop()) { + if (LocMapI.value() == OldLocNo && LII->start < LocMapI.stop()) { // Overlapping correct location. Allocate NewLocNo now. if (NewLocNo == UndefLocNo) { MachineOperand MO = MachineOperand::CreateReg(LI->reg, false); @@ -895,7 +851,6 @@ SlotIndex LStart = LocMapI.start(); SlotIndex LStop = LocMapI.stop(); - DbgValueLocation OldLoc = LocMapI.value(); // Trim LocMapI down to the LII overlap. if (LStart < LII->start) @@ -904,17 +859,17 @@ LocMapI.setStopUnchecked(LII->end); // Change the value in the overlap. This may trigger coalescing. - LocMapI.setValue(OldLoc.changeLocNo(NewLocNo)); + LocMapI.setValue(NewLocNo); // Re-insert any removed OldLocNo ranges. if (LStart < LocMapI.start()) { - LocMapI.insert(LStart, LocMapI.start(), OldLoc); + LocMapI.insert(LStart, LocMapI.start(), OldLocNo); ++LocMapI; assert(LocMapI.valid() && "Unexpected coalescing"); } if (LStop > LocMapI.stop()) { ++LocMapI; - LocMapI.insert(LII->end, LStop, OldLoc); + LocMapI.insert(LII->end, LStop, OldLocNo); --LocMapI; } } @@ -937,14 +892,14 @@ locations.erase(locations.begin() + OldLocNo); LocMapI.goToBegin(); while (LocMapI.valid()) { - DbgValueLocation v = LocMapI.value(); - if (v.locNo() == OldLocNo) { + unsigned v = LocMapI.value(); + if (v == OldLocNo) { DEBUG(dbgs() << "Erasing [" << LocMapI.start() << ';' << LocMapI.stop() << ")\n"); LocMapI.erase(); } else { - if (v.locNo() > OldLocNo) - LocMapI.setValueUnchecked(v.changeLocNo(v.locNo() - 1)); + if (v > OldLocNo) + LocMapI.setValueUnchecked(v-1); ++LocMapI; } } @@ -1048,9 +1003,8 @@ // DBG_VALUE intervals with different vregs that were allocated to the same // physical register. for (LocMap::iterator I = locInts.begin(); I.valid(); ++I) { - DbgValueLocation Loc = I.value(); - unsigned NewLocNo = LocNoMap[Loc.locNo()]; - I.setValueUnchecked(Loc.changeLocNo(NewLocNo)); + unsigned NewLocNo = LocNoMap[I.value()]; + I.setValueUnchecked(NewLocNo); I.setStart(I.start()); } } @@ -1080,11 +1034,11 @@ } void UserValue::insertDebugValue(MachineBasicBlock *MBB, SlotIndex Idx, - DbgValueLocation Loc, bool Spilled, + unsigned LocNo, bool Spilled, LiveIntervals &LIS, const TargetInstrInfo &TII) { MachineBasicBlock::iterator I = findInsertLocation(MBB, Idx, LIS); - MachineOperand &MO = locations[Loc.locNo()]; + MachineOperand &Loc = locations[LocNo]; ++NumInsertedDebugValues; assert(cast(Variable) @@ -1094,20 +1048,18 @@ // If the location was spilled, the new DBG_VALUE will be indirect. If the // original DBG_VALUE was indirect, we need to add DW_OP_deref to indicate // that the original virtual register was a pointer. + bool NewIndirect = IsIndirect || Spilled; const DIExpression *Expr = Expression; - bool IsIndirect = Loc.wasIndirect(); - if (Spilled) { - if (IsIndirect) - Expr = DIExpression::prepend(Expr, DIExpression::WithDeref); - IsIndirect = true; - } + if (Spilled && IsIndirect) + Expr = DIExpression::prepend(Expr, DIExpression::WithDeref); - assert((!Spilled || MO.isFI()) && "a spilled location must be a frame index"); + assert((!Spilled || Loc.isFI()) && + "a spilled location must be a frame index"); MachineInstrBuilder MIB = BuildMI(*MBB, I, getDebugLoc(), TII.get(TargetOpcode::DBG_VALUE)) - .add(MO); - if (IsIndirect) + .add(Loc); + if (NewIndirect) MIB.addImm(0U); else MIB.addReg(0U, RegState::Debug); @@ -1122,8 +1074,8 @@ for (LocMap::const_iterator I = locInts.begin(); I.valid();) { SlotIndex Start = I.start(); SlotIndex Stop = I.stop(); - DbgValueLocation Loc = I.value(); - bool Spilled = !Loc.isUndef() ? SpilledLocations.test(Loc.locNo()) : false; + unsigned LocNo = I.value(); + bool Spilled = LocNo != UndefLocNo ? SpilledLocations.test(LocNo) : false; // If the interval start was trimmed to the lexical scope insert the // DBG_VALUE at the previous index (otherwise it appears after the @@ -1131,12 +1083,12 @@ if (trimmedDefs.count(Start)) Start = Start.getPrevIndex(); - DEBUG(dbgs() << "\t[" << Start << ';' << Stop << "):" << Loc.locNo()); + DEBUG(dbgs() << "\t[" << Start << ';' << Stop << "):" << LocNo); MachineFunction::iterator MBB = LIS.getMBBFromIndex(Start)->getIterator(); SlotIndex MBBEnd = LIS.getMBBEndIdx(&*MBB); DEBUG(dbgs() << " BB#" << MBB->getNumber() << '-' << MBBEnd); - insertDebugValue(&*MBB, Start, Loc, Spilled, LIS, TII); + insertDebugValue(&*MBB, Start, LocNo, Spilled, LIS, TII); // This interval may span multiple basic blocks. // Insert a DBG_VALUE into each one. while(Stop > MBBEnd) { @@ -1146,7 +1098,7 @@ break; MBBEnd = LIS.getMBBEndIdx(&*MBB); DEBUG(dbgs() << " BB#" << MBB->getNumber() << '-' << MBBEnd); - insertDebugValue(&*MBB, Start, Loc, Spilled, LIS, TII); + insertDebugValue(&*MBB, Start, LocNo, Spilled, LIS, TII); } DEBUG(dbgs() << '\n'); if (MBB == MFEnd) Index: lib/CodeGen/MachineOutliner.cpp =================================================================== --- lib/CodeGen/MachineOutliner.cpp +++ lib/CodeGen/MachineOutliner.cpp @@ -146,30 +146,17 @@ /// function. std::vector Sequence; + /// The number of instructions this function would save. + unsigned Benefit = 0; + /// Contains all target-specific information for this \p OutlinedFunction. TargetInstrInfo::MachineOutlinerInfo MInfo; - /// \brief Return the number of instructions it would take to outline this - /// function. - unsigned getOutliningCost() { - return (OccurrenceCount * MInfo.CallOverhead) + Sequence.size() + - MInfo.FrameOverhead; - } - - /// \brief Return the number of instructions that would be saved by outlining - /// this function. - unsigned getBenefit() { - unsigned NotOutlinedCost = OccurrenceCount * Sequence.size(); - unsigned OutlinedCost = getOutliningCost(); - return (NotOutlinedCost < OutlinedCost) ? 0 - : NotOutlinedCost - OutlinedCost; - } - OutlinedFunction(unsigned Name, unsigned OccurrenceCount, - const std::vector &Sequence, + const std::vector &Sequence, unsigned Benefit, TargetInstrInfo::MachineOutlinerInfo &MInfo) : Name(Name), OccurrenceCount(OccurrenceCount), Sequence(Sequence), - MInfo(MInfo) {} + Benefit(Benefit), MInfo(MInfo) {} }; /// Represents an undefined index in the suffix tree. @@ -857,6 +844,7 @@ std::vector &FunctionList) { CandidateList.clear(); FunctionList.clear(); + unsigned FnIdx = 0; unsigned MaxLen = 0; // FIXME: Visit internal nodes instead of leaves. @@ -903,8 +891,7 @@ MachineBasicBlock::iterator EndIt = Mapper.InstrList[M->SuffixIdx + StringLen - 1]; - CandidatesForRepeatedSeq.emplace_back(M->SuffixIdx, StringLen, - FunctionList.size()); + CandidatesForRepeatedSeq.emplace_back(M->SuffixIdx, StringLen, FnIdx); RepeatedSequenceLocs.emplace_back(std::make_pair(StartIt, EndIt)); // Never visit this leaf again. @@ -912,20 +899,16 @@ } } - // We've found something we might want to outline. - // Create an OutlinedFunction to store it and check if it'd be beneficial - // to outline. + unsigned SequenceOverhead = StringLen; TargetInstrInfo::MachineOutlinerInfo MInfo = TII.getOutlininingCandidateInfo(RepeatedSequenceLocs); - std::vector Seq; - for (unsigned i = Leaf->SuffixIdx; i < Leaf->SuffixIdx + StringLen; i++) - Seq.push_back(ST.Str[i]); - OutlinedFunction OF(FunctionList.size(), Parent.OccurrenceCount, Seq, - MInfo); - unsigned Benefit = OF.getBenefit(); + + unsigned OutliningCost = + (MInfo.CallOverhead * Parent.OccurrenceCount) + MInfo.FrameOverhead; + unsigned NotOutliningCost = SequenceOverhead * Parent.OccurrenceCount; // Is it better to outline this candidate than not? - if (Benefit < 1) { + if (NotOutliningCost <= OutliningCost) { // Outlining this candidate would take more instructions than not // outlining. // Emit a remark explaining why we didn't outline this candidate. @@ -940,9 +923,9 @@ << " from " << NV("NumOccurrences", RepeatedSequenceLocs.size()) << " locations." << " Instructions from outlining all occurrences (" - << NV("OutliningCost", OF.getOutliningCost()) << ")" + << NV("OutliningCost", OutliningCost) << ")" << " >= Unoutlined instruction count (" - << NV("NotOutliningCost", StringLen * OF.OccurrenceCount) << ")" + << NV("NotOutliningCost", NotOutliningCost) << ")" << " (Also found at: "; // Tell the user the other places the candidate was found. @@ -960,6 +943,8 @@ continue; } + unsigned Benefit = NotOutliningCost - OutliningCost; + if (StringLen > MaxLen) MaxLen = StringLen; @@ -971,9 +956,16 @@ CandidateList.push_back(C); } - FunctionList.push_back(OF); + // Save the function for the new candidate sequence. + std::vector CandidateSequence; + for (unsigned i = Leaf->SuffixIdx; i < Leaf->SuffixIdx + StringLen; i++) + CandidateSequence.push_back(ST.Str[i]); + + FunctionList.emplace_back(FnIdx, CandidatesForRepeatedSeq.size(), + CandidateSequence, Benefit, MInfo); // Move to the next function. + FnIdx++; Parent.IsInTree = false; } @@ -998,7 +990,7 @@ // pruning steps. OutlinedFunction &F = FunctionList[C.FunctionIdx]; - if (F.OccurrenceCount < 2 || F.getBenefit() < 1) { + if (F.OccurrenceCount < 2 || F.Benefit < 1) { assert(F.OccurrenceCount > 0 && "Can't remove OutlinedFunction with no occurrences!"); F.OccurrenceCount--; @@ -1021,13 +1013,20 @@ "Can't remove OutlinedFunction with no occurrences!"); F.OccurrenceCount--; + // Remove the call overhead from the removed sequence. + F.Benefit += C.MInfo.CallOverhead; + + // Add back one instance of the sequence. + F.Benefit = + (F.Sequence.size() > F.Benefit) ? 0 : F.Benefit - F.Sequence.size(); + // Remove C from the CandidateList. C.InCandidateList = false; DEBUG(dbgs() << "- Removed a Candidate \n"; dbgs() << "--- Num fns left for candidate: " << F.OccurrenceCount << "\n"; - dbgs() << "--- Candidate's functions's benefit: " << F.getBenefit() + dbgs() << "--- Candidate's functions's benefit: " << F.Benefit << "\n";); }; @@ -1188,7 +1187,7 @@ OutlinedFunction &OF = FunctionList[C.FunctionIdx]; // Was its OutlinedFunction made unbeneficial during pruneOverlaps? - if (OF.OccurrenceCount < 2 || OF.getBenefit() < 1) + if (OF.OccurrenceCount < 2 || OF.Benefit < 1) continue; // If not, then outline it. Index: lib/CodeGen/MachineScheduler.cpp =================================================================== --- lib/CodeGen/MachineScheduler.cpp +++ lib/CodeGen/MachineScheduler.cpp @@ -1962,18 +1962,16 @@ if (SchedModel->hasInstrSchedModel() && SU->hasReservedResource) { const MCSchedClassDesc *SC = DAG->getSchedClass(SU); - for (const MCWriteProcResEntry &PE : - make_range(SchedModel->getWriteProcResBegin(SC), - SchedModel->getWriteProcResEnd(SC))) { - unsigned ResIdx = PE.ProcResourceIdx; - unsigned Cycles = PE.Cycles; - unsigned NRCycle = getNextResourceCycle(ResIdx, Cycles); + for (TargetSchedModel::ProcResIter + PI = SchedModel->getWriteProcResBegin(SC), + PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) { + unsigned NRCycle = getNextResourceCycle(PI->ProcResourceIdx, PI->Cycles); if (NRCycle > CurrCycle) { #ifndef NDEBUG - MaxObservedStall = std::max(Cycles, MaxObservedStall); + MaxObservedStall = std::max(PI->Cycles, MaxObservedStall); #endif DEBUG(dbgs() << " SU(" << SU->NodeNum << ") " - << SchedModel->getResourceName(ResIdx) + << SchedModel->getResourceName(PI->ProcResourceIdx) << "=" << NRCycle << "c\n"); return true; } Index: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp =================================================================== --- lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -408,7 +408,6 @@ } SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) { - DEBUG(dbgs() << "Optimizing float store operations\n"); // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' // FIXME: We shouldn't do this for TargetConstantFP's. // FIXME: move this to the DAG Combiner! Note that we can't regress due @@ -467,174 +466,172 @@ } void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) { - StoreSDNode *ST = cast(Node); - SDValue Chain = ST->getChain(); - SDValue Ptr = ST->getBasePtr(); - SDLoc dl(Node); - - unsigned Alignment = ST->getAlignment(); - MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags(); - AAMDNodes AAInfo = ST->getAAInfo(); - - if (!ST->isTruncatingStore()) { - DEBUG(dbgs() << "Legalizing store operation\n"); - if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) { - ReplaceNode(ST, OptStore); - return; - } - - SDValue Value = ST->getValue(); - MVT VT = Value.getSimpleValueType(); - switch (TLI.getOperationAction(ISD::STORE, VT)) { - default: llvm_unreachable("This action is not supported yet!"); - case TargetLowering::Legal: { - // If this is an unaligned store and the target doesn't support it, - // expand it. - EVT MemVT = ST->getMemoryVT(); - unsigned AS = ST->getAddressSpace(); - unsigned Align = ST->getAlignment(); - const DataLayout &DL = DAG.getDataLayout(); - if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align)) { - DEBUG(dbgs() << "Expanding unsupported unaligned store\n"); - SDValue Result = TLI.expandUnalignedStore(ST, DAG); - ReplaceNode(SDValue(ST, 0), Result); - } else - DEBUG(dbgs() << "Legal store\n"); - break; - } - case TargetLowering::Custom: { - DEBUG(dbgs() << "Trying custom lowering\n"); - SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG); - if (Res && Res != SDValue(Node, 0)) - ReplaceNode(SDValue(Node, 0), Res); - return; - } - case TargetLowering::Promote: { - MVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT); - assert(NVT.getSizeInBits() == VT.getSizeInBits() && - "Can only promote stores to same size type"); - Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value); - SDValue Result = - DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(), - Alignment, MMOFlags, AAInfo); - ReplaceNode(SDValue(Node, 0), Result); - break; - } - } - return; - } - - DEBUG(dbgs() << "Legalizing truncating store operations\n"); - SDValue Value = ST->getValue(); - EVT StVT = ST->getMemoryVT(); - unsigned StWidth = StVT.getSizeInBits(); - auto &DL = DAG.getDataLayout(); - - if (StWidth != StVT.getStoreSizeInBits()) { - // Promote to a byte-sized store with upper bits zero if not - // storing an integral number of bytes. For example, promote - // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) - EVT NVT = EVT::getIntegerVT(*DAG.getContext(), - StVT.getStoreSizeInBits()); - Value = DAG.getZeroExtendInReg(Value, dl, StVT); - SDValue Result = - DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(), NVT, - Alignment, MMOFlags, AAInfo); - ReplaceNode(SDValue(Node, 0), Result); - } else if (StWidth & (StWidth - 1)) { - // If not storing a power-of-2 number of bits, expand as two stores. - assert(!StVT.isVector() && "Unsupported truncstore!"); - unsigned RoundWidth = 1 << Log2_32(StWidth); - assert(RoundWidth < StWidth); - unsigned ExtraWidth = StWidth - RoundWidth; - assert(ExtraWidth < RoundWidth); - assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && - "Store size not an integral number of bytes!"); - EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth); - EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth); - SDValue Lo, Hi; - unsigned IncrementSize; - - if (DL.isLittleEndian()) { - // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16) - // Store the bottom RoundWidth bits. - Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(), - RoundVT, Alignment, MMOFlags, AAInfo); + StoreSDNode *ST = cast(Node); + SDValue Chain = ST->getChain(); + SDValue Ptr = ST->getBasePtr(); + SDLoc dl(Node); + + unsigned Alignment = ST->getAlignment(); + MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags(); + AAMDNodes AAInfo = ST->getAAInfo(); + + if (!ST->isTruncatingStore()) { + if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) { + ReplaceNode(ST, OptStore); + return; + } - // Store the remaining ExtraWidth bits. - IncrementSize = RoundWidth / 8; - Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, - DAG.getConstant(IncrementSize, dl, - Ptr.getValueType())); - Hi = DAG.getNode( - ISD::SRL, dl, Value.getValueType(), Value, - DAG.getConstant(RoundWidth, dl, - TLI.getShiftAmountTy(Value.getValueType(), DL))); - Hi = DAG.getTruncStore( - Chain, dl, Hi, Ptr, - ST->getPointerInfo().getWithOffset(IncrementSize), ExtraVT, - MinAlign(Alignment, IncrementSize), MMOFlags, AAInfo); + { + SDValue Value = ST->getValue(); + MVT VT = Value.getSimpleValueType(); + switch (TLI.getOperationAction(ISD::STORE, VT)) { + default: llvm_unreachable("This action is not supported yet!"); + case TargetLowering::Legal: { + // If this is an unaligned store and the target doesn't support it, + // expand it. + EVT MemVT = ST->getMemoryVT(); + unsigned AS = ST->getAddressSpace(); + unsigned Align = ST->getAlignment(); + const DataLayout &DL = DAG.getDataLayout(); + if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align)) { + SDValue Result = TLI.expandUnalignedStore(ST, DAG); + ReplaceNode(SDValue(ST, 0), Result); + } + break; + } + case TargetLowering::Custom: { + SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG); + if (Res && Res != SDValue(Node, 0)) + ReplaceNode(SDValue(Node, 0), Res); + return; + } + case TargetLowering::Promote: { + MVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT); + assert(NVT.getSizeInBits() == VT.getSizeInBits() && + "Can only promote stores to same size type"); + Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value); + SDValue Result = + DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(), + Alignment, MMOFlags, AAInfo); + ReplaceNode(SDValue(Node, 0), Result); + break; + } + } + return; + } } else { - // Big endian - avoid unaligned stores. - // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X - // Store the top RoundWidth bits. - Hi = DAG.getNode( - ISD::SRL, dl, Value.getValueType(), Value, - DAG.getConstant(ExtraWidth, dl, - TLI.getShiftAmountTy(Value.getValueType(), DL))); - Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(), - RoundVT, Alignment, MMOFlags, AAInfo); - - // Store the remaining ExtraWidth bits. - IncrementSize = RoundWidth / 8; - Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, - DAG.getConstant(IncrementSize, dl, - Ptr.getValueType())); - Lo = DAG.getTruncStore( - Chain, dl, Value, Ptr, - ST->getPointerInfo().getWithOffset(IncrementSize), ExtraVT, - MinAlign(Alignment, IncrementSize), MMOFlags, AAInfo); - } + SDValue Value = ST->getValue(); + + EVT StVT = ST->getMemoryVT(); + unsigned StWidth = StVT.getSizeInBits(); + auto &DL = DAG.getDataLayout(); + + if (StWidth != StVT.getStoreSizeInBits()) { + // Promote to a byte-sized store with upper bits zero if not + // storing an integral number of bytes. For example, promote + // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) + EVT NVT = EVT::getIntegerVT(*DAG.getContext(), + StVT.getStoreSizeInBits()); + Value = DAG.getZeroExtendInReg(Value, dl, StVT); + SDValue Result = + DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(), NVT, + Alignment, MMOFlags, AAInfo); + ReplaceNode(SDValue(Node, 0), Result); + } else if (StWidth & (StWidth - 1)) { + // If not storing a power-of-2 number of bits, expand as two stores. + assert(!StVT.isVector() && "Unsupported truncstore!"); + unsigned RoundWidth = 1 << Log2_32(StWidth); + assert(RoundWidth < StWidth); + unsigned ExtraWidth = StWidth - RoundWidth; + assert(ExtraWidth < RoundWidth); + assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && + "Store size not an integral number of bytes!"); + EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth); + EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth); + SDValue Lo, Hi; + unsigned IncrementSize; + + if (DL.isLittleEndian()) { + // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16) + // Store the bottom RoundWidth bits. + Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(), + RoundVT, Alignment, MMOFlags, AAInfo); + + // Store the remaining ExtraWidth bits. + IncrementSize = RoundWidth / 8; + Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, + DAG.getConstant(IncrementSize, dl, + Ptr.getValueType())); + Hi = DAG.getNode( + ISD::SRL, dl, Value.getValueType(), Value, + DAG.getConstant(RoundWidth, dl, + TLI.getShiftAmountTy(Value.getValueType(), DL))); + Hi = DAG.getTruncStore( + Chain, dl, Hi, Ptr, + ST->getPointerInfo().getWithOffset(IncrementSize), ExtraVT, + MinAlign(Alignment, IncrementSize), MMOFlags, AAInfo); + } else { + // Big endian - avoid unaligned stores. + // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X + // Store the top RoundWidth bits. + Hi = DAG.getNode( + ISD::SRL, dl, Value.getValueType(), Value, + DAG.getConstant(ExtraWidth, dl, + TLI.getShiftAmountTy(Value.getValueType(), DL))); + Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(), + RoundVT, Alignment, MMOFlags, AAInfo); + + // Store the remaining ExtraWidth bits. + IncrementSize = RoundWidth / 8; + Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, + DAG.getConstant(IncrementSize, dl, + Ptr.getValueType())); + Lo = DAG.getTruncStore( + Chain, dl, Value, Ptr, + ST->getPointerInfo().getWithOffset(IncrementSize), ExtraVT, + MinAlign(Alignment, IncrementSize), MMOFlags, AAInfo); + } - // The order of the stores doesn't matter. - SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); - ReplaceNode(SDValue(Node, 0), Result); - } else { - switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) { - default: llvm_unreachable("This action is not supported yet!"); - case TargetLowering::Legal: { - EVT MemVT = ST->getMemoryVT(); - unsigned AS = ST->getAddressSpace(); - unsigned Align = ST->getAlignment(); - // If this is an unaligned store and the target doesn't support it, - // expand it. - if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align)) { - SDValue Result = TLI.expandUnalignedStore(ST, DAG); - ReplaceNode(SDValue(ST, 0), Result); + // The order of the stores doesn't matter. + SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); + ReplaceNode(SDValue(Node, 0), Result); + } else { + switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) { + default: llvm_unreachable("This action is not supported yet!"); + case TargetLowering::Legal: { + EVT MemVT = ST->getMemoryVT(); + unsigned AS = ST->getAddressSpace(); + unsigned Align = ST->getAlignment(); + // If this is an unaligned store and the target doesn't support it, + // expand it. + if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align)) { + SDValue Result = TLI.expandUnalignedStore(ST, DAG); + ReplaceNode(SDValue(ST, 0), Result); + } + break; + } + case TargetLowering::Custom: { + SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG); + if (Res && Res != SDValue(Node, 0)) + ReplaceNode(SDValue(Node, 0), Res); + return; + } + case TargetLowering::Expand: + assert(!StVT.isVector() && + "Vector Stores are handled in LegalizeVectorOps"); + + // TRUNCSTORE:i16 i32 -> STORE i16 + assert(TLI.isTypeLegal(StVT) && + "Do not know how to expand this store!"); + Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value); + SDValue Result = + DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(), + Alignment, MMOFlags, AAInfo); + ReplaceNode(SDValue(Node, 0), Result); + break; + } } - break; - } - case TargetLowering::Custom: { - SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG); - if (Res && Res != SDValue(Node, 0)) - ReplaceNode(SDValue(Node, 0), Res); - return; - } - case TargetLowering::Expand: - assert(!StVT.isVector() && - "Vector Stores are handled in LegalizeVectorOps"); - - // TRUNCSTORE:i16 i32 -> STORE i16 - assert(TLI.isTypeLegal(StVT) && - "Do not know how to expand this store!"); - Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value); - SDValue Result = - DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(), - Alignment, MMOFlags, AAInfo); - ReplaceNode(SDValue(Node, 0), Result); - break; } - } } void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) { @@ -646,7 +643,6 @@ ISD::LoadExtType ExtType = LD->getExtensionType(); if (ExtType == ISD::NON_EXTLOAD) { - DEBUG(dbgs() << "Legalizing non-extending load operation\n"); MVT VT = Node->getSimpleValueType(0); SDValue RVal = SDValue(Node, 0); SDValue RChain = SDValue(Node, 1); @@ -696,7 +692,6 @@ return; } - DEBUG(dbgs() << "Legalizing extending load operation\n"); EVT SrcVT = LD->getMemoryVT(); unsigned SrcWidth = SrcVT.getSizeInBits(); unsigned Alignment = LD->getAlignment(); @@ -1189,10 +1184,8 @@ } switch (Action) { case TargetLowering::Legal: - DEBUG(dbgs() << "Legal node: nothing to do\n"); return; case TargetLowering::Custom: - DEBUG(dbgs() << "Trying custom legalization\n"); // FIXME: The handling for custom lowering with multiple results is // a complete mess. if (SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG)) { @@ -1200,7 +1193,6 @@ return; if (Node->getNumValues() == 1) { - DEBUG(dbgs() << "Successfully custom legalized node\n"); // We can just directly replace this node with the lowered value. ReplaceNode(SDValue(Node, 0), Res); return; @@ -1209,11 +1201,9 @@ SmallVector ResultVals; for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) ResultVals.push_back(Res.getValue(i)); - DEBUG(dbgs() << "Successfully custom legalized node\n"); ReplaceNode(Node, ResultVals.data()); return; } - DEBUG(dbgs() << "Could not custom legalize node\n"); LLVM_FALLTHROUGH; case TargetLowering::Expand: if (ExpandNode(Node)) @@ -2020,13 +2010,10 @@ std::pair CallInfo = TLI.LowerCallTo(CLI); - if (!CallInfo.second.getNode()) { - DEBUG(dbgs() << "Created tailcall: "; DAG.getRoot().dump()); + if (!CallInfo.second.getNode()) // It's a tailcall, return the chain (which is the DAG root). return DAG.getRoot(); - } - DEBUG(dbgs() << "Created libcall: "; CallInfo.first.dump()); return CallInfo.first; } @@ -2312,10 +2299,9 @@ EVT DestVT, const SDLoc &dl) { // TODO: Should any fast-math-flags be set for the created nodes? - DEBUG(dbgs() << "Legalizing INT_TO_FP\n"); + if (Op0.getValueType() == MVT::i32 && TLI.isTypeLegal(MVT::f64)) { - DEBUG(dbgs() << "32-bit [signed|unsigned] integer to float/double " - "expansion\n"); + // simple 32-bit [signed|unsigned] integer to float/double expansion // Get the stack frame index of a 8 byte buffer. SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64); @@ -2380,7 +2366,6 @@ // and in all alternate rounding modes. // TODO: Generalize this for use with other types. if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) { - DEBUG(dbgs() << "Converting unsigned i64 to f64\n"); SDValue TwoP52 = DAG.getConstant(UINT64_C(0x4330000000000000), dl, MVT::i64); SDValue TwoP84PlusTwoP52 = @@ -2401,9 +2386,9 @@ return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub); } + // Implementation of unsigned i64 to f32. // TODO: Generalize this for use with other types. if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) { - DEBUG(dbgs() << "Converting unsigned i64 to f32\n"); // For unsigned conversions, convert them to signed conversions using the // algorithm from the x86_64 __floatundidf in compiler_rt. if (!isSigned) { @@ -2827,7 +2812,6 @@ } bool SelectionDAGLegalize::ExpandNode(SDNode *Node) { - DEBUG(dbgs() << "Trying to expand node\n"); SmallVector Results; SDLoc dl(Node); SDValue Tmp1, Tmp2, Tmp3, Tmp4; @@ -3285,7 +3269,6 @@ } break; case ISD::FP_TO_FP16: - DEBUG(dbgs() << "Legalizing FP_TO_FP16\n"); if (!TLI.useSoftFloat() && TM.Options.UnsafeFPMath) { SDValue Op = Node->getOperand(0); MVT SVT = Op.getSimpleValueType(); @@ -3894,18 +3877,14 @@ } // Replace the original node with the legalized result. - if (Results.empty()) { - DEBUG(dbgs() << "Cannot expand node\n"); + if (Results.empty()) return false; - } - DEBUG(dbgs() << "Succesfully expanded node\n"); ReplaceNode(Node, Results.data()); return true; } void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) { - DEBUG(dbgs() << "Trying to convert node to libcall\n"); SmallVector Results; SDLoc dl(Node); SDValue Tmp1, Tmp2, Tmp3, Tmp4; @@ -4160,11 +4139,8 @@ } // Replace the original node with the legalized result. - if (!Results.empty()) { - DEBUG(dbgs() << "Successfully converted node to libcall\n"); + if (!Results.empty()) ReplaceNode(Node, Results.data()); - } else - DEBUG(dbgs() << "Could not convert node to libcall\n"); } // Determine the vector type to use in place of an original scalar element when @@ -4178,7 +4154,6 @@ } void SelectionDAGLegalize::PromoteNode(SDNode *Node) { - DEBUG(dbgs() << "Trying to promote node\n"); SmallVector Results; MVT OVT = Node->getSimpleValueType(0); if (Node->getOpcode() == ISD::UINT_TO_FP || @@ -4614,11 +4589,8 @@ } // Replace the original node with the legalized result. - if (!Results.empty()) { - DEBUG(dbgs() << "Successfully promoted node\n"); + if (!Results.empty()) ReplaceNode(Node, Results.data()); - } else - DEBUG(dbgs() << "Could not promote node\n"); } /// This is the entry point for the file. Index: lib/CodeGen/TargetLoweringObjectFileImpl.cpp =================================================================== --- lib/CodeGen/TargetLoweringObjectFileImpl.cpp +++ lib/CodeGen/TargetLoweringObjectFileImpl.cpp @@ -1328,9 +1328,7 @@ MCSymbolRefExpr::create(TM.getSymbol(RHS), getContext()), getContext()); } -void TargetLoweringObjectFileWasm::InitializeWasm() { - StaticCtorSection = - getContext().getWasmSection(".init_array", wasm::WASM_SEC_DATA); - StaticDtorSection = - getContext().getWasmSection(".fini_array", wasm::WASM_SEC_DATA); +void +TargetLoweringObjectFileWasm::InitializeWasm() { + // TODO: Initialize StaticCtorSection and StaticDtorSection. } Index: lib/DebugInfo/CodeView/EnumTables.cpp =================================================================== --- lib/DebugInfo/CodeView/EnumTables.cpp +++ lib/DebugInfo/CodeView/EnumTables.cpp @@ -33,9 +33,55 @@ }; static const EnumEntry RegisterNames[] = { -#define CV_REGISTER(name, val) CV_ENUM_CLASS_ENT(RegisterId, name), -#include "llvm/DebugInfo/CodeView/CodeViewRegisters.def" -#undef CV_REGISTER + CV_ENUM_CLASS_ENT(RegisterId, Unknown), + CV_ENUM_CLASS_ENT(RegisterId, VFrame), + CV_ENUM_CLASS_ENT(RegisterId, AL), + CV_ENUM_CLASS_ENT(RegisterId, CL), + CV_ENUM_CLASS_ENT(RegisterId, DL), + CV_ENUM_CLASS_ENT(RegisterId, BL), + CV_ENUM_CLASS_ENT(RegisterId, AH), + CV_ENUM_CLASS_ENT(RegisterId, CH), + CV_ENUM_CLASS_ENT(RegisterId, DH), + CV_ENUM_CLASS_ENT(RegisterId, BH), + CV_ENUM_CLASS_ENT(RegisterId, AX), + CV_ENUM_CLASS_ENT(RegisterId, CX), + CV_ENUM_CLASS_ENT(RegisterId, DX), + CV_ENUM_CLASS_ENT(RegisterId, BX), + CV_ENUM_CLASS_ENT(RegisterId, SP), + CV_ENUM_CLASS_ENT(RegisterId, BP), + CV_ENUM_CLASS_ENT(RegisterId, SI), + CV_ENUM_CLASS_ENT(RegisterId, DI), + CV_ENUM_CLASS_ENT(RegisterId, EAX), + CV_ENUM_CLASS_ENT(RegisterId, ECX), + CV_ENUM_CLASS_ENT(RegisterId, EDX), + CV_ENUM_CLASS_ENT(RegisterId, EBX), + CV_ENUM_CLASS_ENT(RegisterId, ESP), + CV_ENUM_CLASS_ENT(RegisterId, EBP), + CV_ENUM_CLASS_ENT(RegisterId, ESI), + CV_ENUM_CLASS_ENT(RegisterId, EDI), + CV_ENUM_CLASS_ENT(RegisterId, ES), + CV_ENUM_CLASS_ENT(RegisterId, CS), + CV_ENUM_CLASS_ENT(RegisterId, SS), + CV_ENUM_CLASS_ENT(RegisterId, DS), + CV_ENUM_CLASS_ENT(RegisterId, FS), + CV_ENUM_CLASS_ENT(RegisterId, GS), + CV_ENUM_CLASS_ENT(RegisterId, IP), + CV_ENUM_CLASS_ENT(RegisterId, RAX), + CV_ENUM_CLASS_ENT(RegisterId, RBX), + CV_ENUM_CLASS_ENT(RegisterId, RCX), + CV_ENUM_CLASS_ENT(RegisterId, RDX), + CV_ENUM_CLASS_ENT(RegisterId, RSI), + CV_ENUM_CLASS_ENT(RegisterId, RDI), + CV_ENUM_CLASS_ENT(RegisterId, RBP), + CV_ENUM_CLASS_ENT(RegisterId, RSP), + CV_ENUM_CLASS_ENT(RegisterId, R8), + CV_ENUM_CLASS_ENT(RegisterId, R9), + CV_ENUM_CLASS_ENT(RegisterId, R10), + CV_ENUM_CLASS_ENT(RegisterId, R11), + CV_ENUM_CLASS_ENT(RegisterId, R12), + CV_ENUM_CLASS_ENT(RegisterId, R13), + CV_ENUM_CLASS_ENT(RegisterId, R14), + CV_ENUM_CLASS_ENT(RegisterId, R15), }; static const EnumEntry PublicSymFlagNames[] = { Index: lib/DebugInfo/PDB/PDBExtras.cpp =================================================================== --- lib/DebugInfo/PDB/PDBExtras.cpp +++ lib/DebugInfo/PDB/PDBExtras.cpp @@ -94,11 +94,56 @@ raw_ostream &llvm::pdb::operator<<(raw_ostream &OS, const codeview::RegisterId &Reg) { switch (Reg) { -#define CV_REGISTER(name, val) case codeview::RegisterId::name: OS << #name; return OS; -#include "llvm/DebugInfo/CodeView/CodeViewRegisters.def" -#undef CV_REGISTER + CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, AL, OS) + CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, CL, OS) + CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, DL, OS) + CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, BL, OS) + CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, AH, OS) + CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, CH, OS) + CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, DH, OS) + CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, BH, OS) + CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, AX, OS) + CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, CX, OS) + CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, DX, OS) + CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, BX, OS) + CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, SP, OS) + CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, BP, OS) + CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, SI, OS) + CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, DI, OS) + CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, EAX, OS) + CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, ECX, OS) + CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, EDX, OS) + CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, EBX, OS) + CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, ESP, OS) + CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, EBP, OS) + CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, ESI, OS) + CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, EDI, OS) + CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, ES, OS) + CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, CS, OS) + CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, SS, OS) + CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, DS, OS) + CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, FS, OS) + CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, GS, OS) + CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, IP, OS) + CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, RAX, OS) + CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, RBX, OS) + CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, RCX, OS) + CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, RDX, OS) + CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, RSI, OS) + CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, RDI, OS) + CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, RBP, OS) + CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, RSP, OS) + CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, R8, OS) + CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, R9, OS) + CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, R10, OS) + CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, R11, OS) + CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, R12, OS) + CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, R13, OS) + CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, R14, OS) + CASE_OUTPUT_ENUM_CLASS_NAME(codeview::RegisterId, R15, OS) + default: + OS << static_cast(Reg); } - OS << static_cast(Reg); return OS; } Index: lib/Fuzzer/FuzzerUtil.cpp =================================================================== --- lib/Fuzzer/FuzzerUtil.cpp +++ lib/Fuzzer/FuzzerUtil.cpp @@ -195,7 +195,15 @@ Printf(FallbackFMT, PC); } -unsigned NumberOfCpuCores() { return hardware_concurrency(); } +unsigned NumberOfCpuCores() { + unsigned N = std::thread::hardware_concurrency(); + if (!N) { + Printf("WARNING: std::thread::hardware_concurrency not well defined for " + "your platform. Assuming CPU count of 1.\n"); + N = 1; + } + return N; +} size_t SimpleFastHash(const uint8_t *Data, size_t Size) { size_t Res = 0; Index: lib/IR/DIBuilder.cpp =================================================================== --- lib/IR/DIBuilder.cpp +++ lib/IR/DIBuilder.cpp @@ -12,7 +12,6 @@ //===----------------------------------------------------------------------===// #include "llvm/IR/DIBuilder.h" -#include "llvm/IR/IRBuilder.h" #include "LLVMContextImpl.h" #include "llvm/ADT/STLExtras.h" #include "llvm/BinaryFormat/Dwarf.h" @@ -772,59 +771,16 @@ File, Line, Col); } -Instruction *DIBuilder::insertDeclare(Value *Storage, DILocalVariable *VarInfo, - DIExpression *Expr, const DILocation *DL, - Instruction *InsertBefore) { - return insertDeclare(Storage, VarInfo, Expr, DL, InsertBefore->getParent(), - InsertBefore); -} - -Instruction *DIBuilder::insertDeclare(Value *Storage, DILocalVariable *VarInfo, - DIExpression *Expr, const DILocation *DL, - BasicBlock *InsertAtEnd) { - // If this block already has a terminator then insert this intrinsic before - // the terminator. Otherwise, put it at the end of the block. - Instruction *InsertBefore = InsertAtEnd->getTerminator(); - return insertDeclare(Storage, VarInfo, Expr, DL, InsertAtEnd, InsertBefore); -} - -Instruction *DIBuilder::insertDbgValueIntrinsic(Value *V, - DILocalVariable *VarInfo, - DIExpression *Expr, - const DILocation *DL, - Instruction *InsertBefore) { - return insertDbgValueIntrinsic( - V, VarInfo, Expr, DL, InsertBefore ? InsertBefore->getParent() : nullptr, - InsertBefore); -} - -Instruction *DIBuilder::insertDbgValueIntrinsic(Value *V, - DILocalVariable *VarInfo, - DIExpression *Expr, - const DILocation *DL, - BasicBlock *InsertAtEnd) { - return insertDbgValueIntrinsic(V, VarInfo, Expr, DL, InsertAtEnd, nullptr); -} - -/// Return an IRBuilder for inserting dbg.declare and dbg.value intrinsics. This -/// abstracts over the various ways to specify an insert position. -static IRBuilder<> getIRBForDbgInsertion(const DILocation *DL, - BasicBlock *InsertBB, - Instruction *InsertBefore) { - IRBuilder<> B(DL->getContext()); - if (InsertBefore) - B.SetInsertPoint(InsertBefore); - else if (InsertBB) - B.SetInsertPoint(InsertBB); - B.SetCurrentDebugLocation(DL); - return B; -} - static Value *getDbgIntrinsicValueImpl(LLVMContext &VMContext, Value *V) { assert(V && "no value passed to dbg intrinsic"); return MetadataAsValue::get(VMContext, ValueAsMetadata::get(V)); } +static Instruction *withDebugLoc(Instruction *I, const DILocation *DL) { + I->setDebugLoc(const_cast(DL)); + return I; +} + static Function *getDeclareIntrin(Module &M) { return Intrinsic::getDeclaration(&M, UseDbgAddr ? Intrinsic::dbg_addr : Intrinsic::dbg_declare); @@ -832,7 +788,7 @@ Instruction *DIBuilder::insertDeclare(Value *Storage, DILocalVariable *VarInfo, DIExpression *Expr, const DILocation *DL, - BasicBlock *InsertBB, Instruction *InsertBefore) { + Instruction *InsertBefore) { assert(VarInfo && "empty or invalid DILocalVariable* passed to dbg.declare"); assert(DL && "Expected debug loc"); assert(DL->getScope()->getSubprogram() == @@ -846,14 +802,60 @@ Value *Args[] = {getDbgIntrinsicValueImpl(VMContext, Storage), MetadataAsValue::get(VMContext, VarInfo), MetadataAsValue::get(VMContext, Expr)}; + return withDebugLoc(CallInst::Create(DeclareFn, Args, "", InsertBefore), DL); +} - IRBuilder<> B = getIRBForDbgInsertion(DL, InsertBB, InsertBefore); - return B.CreateCall(DeclareFn, Args); +Instruction *DIBuilder::insertDeclare(Value *Storage, DILocalVariable *VarInfo, + DIExpression *Expr, const DILocation *DL, + BasicBlock *InsertAtEnd) { + assert(VarInfo && "empty or invalid DILocalVariable* passed to dbg.declare"); + assert(DL && "Expected debug loc"); + assert(DL->getScope()->getSubprogram() == + VarInfo->getScope()->getSubprogram() && + "Expected matching subprograms"); + if (!DeclareFn) + DeclareFn = getDeclareIntrin(M); + + trackIfUnresolved(VarInfo); + trackIfUnresolved(Expr); + Value *Args[] = {getDbgIntrinsicValueImpl(VMContext, Storage), + MetadataAsValue::get(VMContext, VarInfo), + MetadataAsValue::get(VMContext, Expr)}; + + // If this block already has a terminator then insert this intrinsic + // before the terminator. + if (TerminatorInst *T = InsertAtEnd->getTerminator()) + return withDebugLoc(CallInst::Create(DeclareFn, Args, "", T), DL); + return withDebugLoc(CallInst::Create(DeclareFn, Args, "", InsertAtEnd), DL); +} + +Instruction *DIBuilder::insertDbgValueIntrinsic(Value *V, + DILocalVariable *VarInfo, + DIExpression *Expr, + const DILocation *DL, + Instruction *InsertBefore) { + assert(V && "no value passed to dbg.value"); + assert(VarInfo && "empty or invalid DILocalVariable* passed to dbg.value"); + assert(DL && "Expected debug loc"); + assert(DL->getScope()->getSubprogram() == + VarInfo->getScope()->getSubprogram() && + "Expected matching subprograms"); + if (!ValueFn) + ValueFn = Intrinsic::getDeclaration(&M, Intrinsic::dbg_value); + + trackIfUnresolved(VarInfo); + trackIfUnresolved(Expr); + Value *Args[] = {getDbgIntrinsicValueImpl(VMContext, V), + MetadataAsValue::get(VMContext, VarInfo), + MetadataAsValue::get(VMContext, Expr)}; + return withDebugLoc(CallInst::Create(ValueFn, Args, "", InsertBefore), DL); } -Instruction *DIBuilder::insertDbgValueIntrinsic( - Value *V, DILocalVariable *VarInfo, DIExpression *Expr, - const DILocation *DL, BasicBlock *InsertBB, Instruction *InsertBefore) { +Instruction *DIBuilder::insertDbgValueIntrinsic(Value *V, + DILocalVariable *VarInfo, + DIExpression *Expr, + const DILocation *DL, + BasicBlock *InsertAtEnd) { assert(V && "no value passed to dbg.value"); assert(VarInfo && "empty or invalid DILocalVariable* passed to dbg.value"); assert(DL && "Expected debug loc"); @@ -869,8 +871,7 @@ MetadataAsValue::get(VMContext, VarInfo), MetadataAsValue::get(VMContext, Expr)}; - IRBuilder<> B = getIRBForDbgInsertion(DL, InsertBB, InsertBefore); - return B.CreateCall(ValueFn, Args); + return withDebugLoc(CallInst::Create(ValueFn, Args, "", InsertAtEnd), DL); } void DIBuilder::replaceVTableHolder(DICompositeType *&T, Index: lib/IR/Instructions.cpp =================================================================== --- lib/IR/Instructions.cpp +++ lib/IR/Instructions.cpp @@ -2325,30 +2325,22 @@ } } -/// @brief Determine if a cast is a no-op. -bool CastInst::isNoopCast(Instruction::CastOps Opcode, - Type *SrcTy, - Type *DestTy, - const DataLayout &DL) { - Type *PtrOpTy = nullptr; - if (Opcode == Instruction::PtrToInt) - PtrOpTy = SrcTy; - else if (Opcode == Instruction::IntToPtr) - PtrOpTy = DestTy; - - Type *IntPtrTy = PtrOpTy ? DL.getIntPtrType(PtrOpTy) : - DL.getIntPtrType(SrcTy->getContext(), 0); - - return isNoopCast(Opcode, SrcTy, DestTy, IntPtrTy); -} - /// @brief Determine if a cast is a no-op. bool CastInst::isNoopCast(Type *IntPtrTy) const { return isNoopCast(getOpcode(), getOperand(0)->getType(), getType(), IntPtrTy); } bool CastInst::isNoopCast(const DataLayout &DL) const { - return isNoopCast(getOpcode(), getOperand(0)->getType(), getType(), DL); + Type *PtrOpTy = nullptr; + if (getOpcode() == Instruction::PtrToInt) + PtrOpTy = getOperand(0)->getType(); + else if (getOpcode() == Instruction::IntToPtr) + PtrOpTy = getType(); + + Type *IntPtrTy = + PtrOpTy ? DL.getIntPtrType(PtrOpTy) : DL.getIntPtrType(getContext(), 0); + + return isNoopCast(getOpcode(), getOperand(0)->getType(), getType(), IntPtrTy); } /// This function determines if a pair of casts can be eliminated and what Index: lib/LTO/Caching.cpp =================================================================== --- lib/LTO/Caching.cpp +++ lib/LTO/Caching.cpp @@ -66,17 +66,15 @@ // Open the file first to avoid racing with a cache pruner. ErrorOr> MBOrErr = MemoryBuffer::getFile(TempFilename); - if (!MBOrErr) - report_fatal_error(Twine("Failed to open new cache file ") + - TempFilename + ": " + - MBOrErr.getError().message() + "\n"); // This is atomic on POSIX systems. if (auto EC = sys::fs::rename(TempFilename, EntryPath)) report_fatal_error(Twine("Failed to rename temporary file ") + - TempFilename + " to " + EntryPath + ": " + - EC.message() + "\n"); + TempFilename + ": " + EC.message() + "\n"); + if (!MBOrErr) + report_fatal_error(Twine("Failed to open cache file ") + EntryPath + + ": " + MBOrErr.getError().message() + "\n"); AddBuffer(Task, std::move(*MBOrErr), EntryPath); } }; Index: lib/MC/StringTableBuilder.cpp =================================================================== --- lib/MC/StringTableBuilder.cpp +++ lib/MC/StringTableBuilder.cpp @@ -82,29 +82,28 @@ // Three-way radix quicksort. This is much faster than std::sort with strcmp // because it does not compare characters that we already know the same. -static void multikey_qsort(std::vector &Vec, size_t Begin, - size_t End, int Pos) { +static void multikey_qsort(StringPair **Begin, StringPair **End, int Pos) { tailcall: if (End - Begin <= 1) return; - // Partition items so that items in [Begin, P) are greater than the pivot, + // Partition items. Items in [Begin, P) are greater than the pivot, // [P, Q) are the same as the pivot, and [Q, End) are less than the pivot. - int Pivot = charTailAt(Vec[Begin], Pos); - size_t P = Begin; - size_t Q = End; - for (size_t R = Begin + 1; R < Q;) { - int C = charTailAt(Vec[R], Pos); + int Pivot = charTailAt(*Begin, Pos); + StringPair **P = Begin; + StringPair **Q = End; + for (StringPair **R = Begin + 1; R < Q;) { + int C = charTailAt(*R, Pos); if (C > Pivot) - std::swap(Vec[P++], Vec[R++]); + std::swap(*P++, *R++); else if (C < Pivot) - std::swap(Vec[--Q], Vec[R]); + std::swap(*--Q, *R); else R++; } - multikey_qsort(Vec, Begin, P, Pos); - multikey_qsort(Vec, Q, End, Pos); + multikey_qsort(Begin, P, Pos); + multikey_qsort(Q, End, Pos); if (Pivot != -1) { // qsort(P, Q, Pos + 1), but with tail call optimization. Begin = P; @@ -134,7 +133,7 @@ if (!Strings.empty()) { // If we're optimizing, sort by name. If not, sort by previously assigned // offset. - multikey_qsort(Strings, 0, Strings.size(), 0); + multikey_qsort(&Strings[0], &Strings[0] + Strings.size(), 0); } initSize(); Index: lib/Object/ArchiveWriter.cpp =================================================================== --- lib/Object/ArchiveWriter.cpp +++ lib/Object/ArchiveWriter.cpp @@ -167,11 +167,11 @@ } static void -printBSDMemberHeader(raw_ostream &Out, uint64_t Pos, StringRef Name, +printBSDMemberHeader(raw_ostream &Out, StringRef Name, const sys::TimePoint &ModTime, unsigned UID, unsigned GID, unsigned Perms, unsigned Size) { - uint64_t PosAfterHeader = Pos + 60 + Name.size(); + uint64_t PosAfterHeader = Out.tell() + 60 + Name.size(); // Pad so that even 64 bit object files are aligned. unsigned Pad = OffsetToAlignment(PosAfterHeader, 8); unsigned NameWithPadding = Name.size() + Pad; @@ -179,6 +179,7 @@ printRestOfMemberHeader(Out, ModTime, UID, GID, Perms, NameWithPadding + Size); Out << Name; + assert(PosAfterHeader == Out.tell()); while (Pad--) Out.write(uint8_t(0)); } @@ -187,6 +188,21 @@ return Thin || Name.size() >= 16 || Name.contains('/'); } +static void +printMemberHeader(raw_ostream &Out, object::Archive::Kind Kind, bool Thin, + StringRef Name, + std::vector::iterator &StringMapIndexIter, + const sys::TimePoint &ModTime, + unsigned UID, unsigned GID, unsigned Perms, unsigned Size) { + if (isBSDLike(Kind)) + return printBSDMemberHeader(Out, Name, ModTime, UID, GID, Perms, Size); + if (!useStringTable(Thin, Name)) + return printGNUSmallMemberHeader(Out, Name, ModTime, UID, GID, Perms, Size); + Out << '/'; + printWithSpacePadding(Out, *StringMapIndexIter++, 15); + printRestOfMemberHeader(Out, ModTime, UID, GID, Perms, Size); +} + // Compute the relative path from From to To. static std::string computeRelativePath(StringRef From, StringRef To) { if (sys::path::is_absolute(From) || sys::path::is_absolute(To)) @@ -216,56 +232,41 @@ return Relative.str(); } -static void addToStringTable(raw_ostream &Out, StringRef ArcName, - const NewArchiveMember &M, bool Thin) { - StringRef ID = M.Buf->getBufferIdentifier(); - if (Thin) { - if (M.IsNew) - Out << computeRelativePath(ArcName, ID); - else - Out << ID; - } else - Out << M.MemberName; - Out << "/\n"; -} +static void writeStringTable(raw_fd_ostream &Out, StringRef ArcName, + ArrayRef Members, + std::vector &StringMapIndexes, + bool Thin) { + unsigned StartOffset = 0; + for (const NewArchiveMember &M : Members) { + StringRef Path = M.Buf->getBufferIdentifier(); + StringRef Name = M.MemberName; + if (!useStringTable(Thin, Name)) + continue; + if (StartOffset == 0) { + printWithSpacePadding(Out, "//", 58); + Out << "`\n"; + StartOffset = Out.tell(); + } + StringMapIndexes.push_back(Out.tell() - StartOffset); -static void printMemberHeader(raw_ostream &Out, uint64_t Pos, - raw_ostream &StringTable, - object::Archive::Kind Kind, bool Thin, - StringRef ArcName, const NewArchiveMember &M, - unsigned Size) { - if (isBSDLike(Kind)) - return printBSDMemberHeader(Out, Pos, M.MemberName, M.ModTime, M.UID, M.GID, - M.Perms, Size); - if (!useStringTable(Thin, M.MemberName)) - return printGNUSmallMemberHeader(Out, M.MemberName, M.ModTime, M.UID, M.GID, - M.Perms, Size); - Out << '/'; - uint64_t NamePos = StringTable.tell(); - addToStringTable(StringTable, ArcName, M, Thin); - printWithSpacePadding(Out, NamePos, 15); - printRestOfMemberHeader(Out, M.ModTime, M.UID, M.GID, M.Perms, Size); -} + if (Thin) { + if (M.IsNew) + Out << computeRelativePath(ArcName, Path); + else + Out << M.Buf->getBufferIdentifier(); + } else + Out << Name; -namespace { -struct MemberData { - std::vector Symbols; - std::string Header; - StringRef Data; - StringRef Padding; -}; -} // namespace - -static MemberData computeStringTable(StringRef Names) { - unsigned Size = Names.size(); - unsigned Pad = OffsetToAlignment(Size, 2); - std::string Header; - raw_string_ostream Out(Header); - printWithSpacePadding(Out, "//", 48); - printWithSpacePadding(Out, Size + Pad, 10); - Out << "`\n"; - Out.flush(); - return {{}, std::move(Header), Names, Pad ? "\n" : ""}; + Out << "/\n"; + } + if (StartOffset == 0) + return; + if (Out.tell() % 2) + Out << '\n'; + int Pos = Out.tell(); + Out.seek(StartOffset - 12); + printWithSpacePadding(Out, Pos - StartOffset, 10); + Out.seek(Pos); } static sys::TimePoint now(bool Deterministic) { @@ -288,137 +289,97 @@ return true; } -static void writeSymbolTable(raw_ostream &Out, object::Archive::Kind Kind, - bool Deterministic, ArrayRef Members, - StringRef StringTable) { - if (StringTable.empty()) - return; - - unsigned NumSyms = 0; - for (const MemberData &M : Members) - NumSyms += M.Symbols.size(); - - unsigned Size = 0; - Size += 4; // Number of entries - if (isBSDLike(Kind)) - Size += NumSyms * 8; // Table - else - Size += NumSyms * 4; // Table - if (isBSDLike(Kind)) - Size += 4; // byte count - Size += StringTable.size(); - // ld64 expects the members to be 8-byte aligned for 64-bit content and at - // least 4-byte aligned for 32-bit content. Opt for the larger encoding - // uniformly. - // We do this for all bsd formats because it simplifies aligning members. - unsigned Alignment = isBSDLike(Kind) ? 8 : 2; - unsigned Pad = OffsetToAlignment(Size, Alignment); - Size += Pad; - - if (isBSDLike(Kind)) - printBSDMemberHeader(Out, Out.tell(), "__.SYMDEF", now(Deterministic), 0, 0, - 0, Size); - else - printGNUSmallMemberHeader(Out, "", now(Deterministic), 0, 0, 0, Size); +// Returns the offset of the first reference to a member offset. +static Expected +writeSymbolTable(raw_fd_ostream &Out, object::Archive::Kind Kind, + ArrayRef Members, + std::vector &MemberOffsetRefs, bool Deterministic) { + unsigned HeaderStartOffset = 0; + unsigned BodyStartOffset = 0; + SmallString<128> NameBuf; + raw_svector_ostream NameOS(NameBuf); + LLVMContext Context; + for (unsigned MemberNum = 0, N = Members.size(); MemberNum < N; ++MemberNum) { + MemoryBufferRef MemberBuffer = Members[MemberNum].Buf->getMemBufferRef(); + Expected> ObjOrErr = + object::SymbolicFile::createSymbolicFile( + MemberBuffer, llvm::file_magic::unknown, &Context); + if (!ObjOrErr) { + // FIXME: check only for "not an object file" errors. + consumeError(ObjOrErr.takeError()); + continue; + } + object::SymbolicFile &Obj = *ObjOrErr.get(); - uint64_t Pos = Out.tell() + Size; + if (!HeaderStartOffset) { + HeaderStartOffset = Out.tell(); + if (isBSDLike(Kind)) + printBSDMemberHeader(Out, "__.SYMDEF", now(Deterministic), 0, 0, 0, 0); + else + printGNUSmallMemberHeader(Out, "", now(Deterministic), 0, 0, 0, 0); + BodyStartOffset = Out.tell(); + print32(Out, Kind, 0); // number of entries or bytes + } - if (isBSDLike(Kind)) - print32(Out, Kind, NumSyms * 8); - else - print32(Out, Kind, NumSyms); + for (const object::BasicSymbolRef &S : Obj.symbols()) { + if (!isArchiveSymbol(S)) + continue; - for (const MemberData &M : Members) { - for (unsigned StringOffset : M.Symbols) { + unsigned NameOffset = NameOS.tell(); + if (std::error_code EC = S.printName(NameOS)) + return errorCodeToError(EC); + NameOS << '\0'; + MemberOffsetRefs.push_back(MemberNum); if (isBSDLike(Kind)) - print32(Out, Kind, StringOffset); - print32(Out, Kind, Pos); // member offset + print32(Out, Kind, NameOffset); + print32(Out, Kind, 0); // member offset } - Pos += M.Header.size() + M.Data.size() + M.Padding.size(); } + if (HeaderStartOffset == 0) + return 0; + + // ld64 prefers the cctools type archive which pads its string table to a + // boundary of sizeof(int32_t). + if (isBSDLike(Kind)) + for (unsigned P = OffsetToAlignment(NameOS.tell(), sizeof(int32_t)); P--;) + NameOS << '\0'; + + StringRef StringTable = NameOS.str(); if (isBSDLike(Kind)) print32(Out, Kind, StringTable.size()); // byte count of the string table Out << StringTable; + // If there are no symbols, emit an empty symbol table, to satisfy Solaris + // tools, older versions of which expect a symbol table in a non-empty + // archive, regardless of whether there are any symbols in it. + if (StringTable.size() == 0) + print32(Out, Kind, 0); + // ld64 expects the members to be 8-byte aligned for 64-bit content and at + // least 4-byte aligned for 32-bit content. Opt for the larger encoding + // uniformly. + // We do this for all bsd formats because it simplifies aligning members. + unsigned Alignment = isBSDLike(Kind) ? 8 : 2; + unsigned Pad = OffsetToAlignment(Out.tell(), Alignment); while (Pad--) Out.write(uint8_t(0)); -} -static Expected> -getSymbols(MemoryBufferRef Buf, raw_ostream &SymNames, bool &HasObject) { - std::vector Ret; - LLVMContext Context; + // Patch up the size of the symbol table now that we know how big it is. + unsigned Pos = Out.tell(); + const unsigned MemberHeaderSize = 60; + Out.seek(HeaderStartOffset + 48); // offset of the size field. + printWithSpacePadding(Out, Pos - MemberHeaderSize - HeaderStartOffset, 10); - Expected> ObjOrErr = - object::SymbolicFile::createSymbolicFile(Buf, llvm::file_magic::unknown, - &Context); - if (!ObjOrErr) { - // FIXME: check only for "not an object file" errors. - consumeError(ObjOrErr.takeError()); - return Ret; - } + // Patch up the number of symbols. + Out.seek(BodyStartOffset); + unsigned NumSyms = MemberOffsetRefs.size(); + if (isBSDLike(Kind)) + print32(Out, Kind, NumSyms * 8); + else + print32(Out, Kind, NumSyms); - HasObject = true; - object::SymbolicFile &Obj = *ObjOrErr.get(); - for (const object::BasicSymbolRef &S : Obj.symbols()) { - if (!isArchiveSymbol(S)) - continue; - Ret.push_back(SymNames.tell()); - if (auto EC = S.printName(SymNames)) - return errorCodeToError(EC); - SymNames << '\0'; - } - return Ret; -} - -static Expected> -computeMemberData(raw_ostream &StringTable, raw_ostream &SymNames, - object::Archive::Kind Kind, bool Thin, StringRef ArcName, - ArrayRef NewMembers) { - static char PaddingData[8] = {'\n', '\n', '\n', '\n', '\n', '\n', '\n', '\n'}; - - // This ignores the symbol table, but we only need the value mod 8 and the - // symbol table is aligned to be a multiple of 8 bytes - uint64_t Pos = 0; - - std::vector Ret; - bool HasObject = false; - for (const NewArchiveMember &M : NewMembers) { - std::string Header; - raw_string_ostream Out(Header); - - MemoryBufferRef Buf = M.Buf->getMemBufferRef(); - StringRef Data = Thin ? "" : Buf.getBuffer(); - - // ld64 expects the members to be 8-byte aligned for 64-bit content and at - // least 4-byte aligned for 32-bit content. Opt for the larger encoding - // uniformly. This matches the behaviour with cctools and ensures that ld64 - // is happy with archives that we generate. - unsigned MemberPadding = Kind == object::Archive::K_DARWIN - ? OffsetToAlignment(Data.size(), 8) - : 0; - unsigned TailPadding = OffsetToAlignment(Data.size() + MemberPadding, 2); - StringRef Padding = StringRef(PaddingData, MemberPadding + TailPadding); - - printMemberHeader(Out, Pos, StringTable, Kind, Thin, ArcName, M, - Buf.getBufferSize() + MemberPadding); - Out.flush(); - - Expected> Symbols = - getSymbols(Buf, SymNames, HasObject); - if (auto E = Symbols.takeError()) - return std::move(E); - - Pos += Header.size() + Data.size() + Padding.size(); - Ret.push_back({std::move(*Symbols), std::move(Header), Data, Padding}); - } - // If there are no symbols, emit an empty symbol table, to satisfy Solaris - // tools, older versions of which expect a symbol table in a non-empty - // archive, regardless of whether there are any symbols in it. - if (HasObject && SymNames.tell() == 0) - SymNames << '\0' << '\0' << '\0'; - return Ret; + Out.seek(Pos); + return BodyStartOffset + 4; } Error llvm::writeArchive(StringRef ArcName, @@ -427,21 +388,6 @@ bool Deterministic, bool Thin, std::unique_ptr OldArchiveBuf) { assert((!Thin || !isBSDLike(Kind)) && "Only the gnu format has a thin mode"); - - SmallString<0> SymNamesBuf; - raw_svector_ostream SymNames(SymNamesBuf); - SmallString<0> StringTableBuf; - raw_svector_ostream StringTable(StringTableBuf); - - Expected> DataOrErr = - computeMemberData(StringTable, SymNames, Kind, Thin, ArcName, NewMembers); - if (Error E = DataOrErr.takeError()) - return E; - std::vector &Data = *DataOrErr; - - if (!StringTableBuf.empty()) - Data.insert(Data.begin(), computeStringTable(StringTableBuf)); - SmallString<128> TmpArchive; int TmpArchiveFD; if (auto EC = sys::fs::createUniqueFile(ArcName + ".temp-archive-%%%%%%%.a", @@ -455,11 +401,58 @@ else Out << "!\n"; - if (WriteSymtab) - writeSymbolTable(Out, Kind, Deterministic, Data, SymNamesBuf); + std::vector MemberOffsetRefs; + + unsigned MemberReferenceOffset = 0; + if (WriteSymtab) { + Expected MemberReferenceOffsetOrErr = writeSymbolTable( + Out, Kind, NewMembers, MemberOffsetRefs, Deterministic); + if (auto E = MemberReferenceOffsetOrErr.takeError()) + return E; + MemberReferenceOffset = MemberReferenceOffsetOrErr.get(); + } + + std::vector StringMapIndexes; + if (!isBSDLike(Kind)) + writeStringTable(Out, ArcName, NewMembers, StringMapIndexes, Thin); + + std::vector::iterator StringMapIndexIter = StringMapIndexes.begin(); + std::vector MemberOffset; + for (const NewArchiveMember &M : NewMembers) { + MemoryBufferRef File = M.Buf->getMemBufferRef(); + unsigned Padding = 0; + + unsigned Pos = Out.tell(); + MemberOffset.push_back(Pos); - for (const MemberData &M : Data) - Out << M.Header << M.Data << M.Padding; + // ld64 expects the members to be 8-byte aligned for 64-bit content and at + // least 4-byte aligned for 32-bit content. Opt for the larger encoding + // uniformly. This matches the behaviour with cctools and ensures that ld64 + // is happy with archives that we generate. + if (Kind == object::Archive::K_DARWIN) + Padding = OffsetToAlignment(M.Buf->getBufferSize(), 8); + + printMemberHeader(Out, Kind, Thin, M.MemberName, StringMapIndexIter, + M.ModTime, M.UID, M.GID, M.Perms, + M.Buf->getBufferSize() + Padding); + + if (!Thin) + Out << File.getBuffer(); + + while (Padding--) + Out << '\n'; + if (Out.tell() % 2) + Out << '\n'; + } + + if (MemberReferenceOffset) { + Out.seek(MemberReferenceOffset); + for (unsigned MemberNum : MemberOffsetRefs) { + if (isBSDLike(Kind)) + Out.seek(Out.tell() + 4); // skip over the string offset + print32(Out, Kind, MemberOffset[MemberNum]); + } + } Output.keep(); Out.close(); Index: lib/ObjectYAML/ELFYAML.cpp =================================================================== --- lib/ObjectYAML/ELFYAML.cpp +++ lib/ObjectYAML/ELFYAML.cpp @@ -260,12 +260,10 @@ ECase(ELFOSABI_AROS); ECase(ELFOSABI_FENIXOS); ECase(ELFOSABI_CLOUDABI); - ECase(ELFOSABI_AMDGPU_HSA); - ECase(ELFOSABI_AMDGPU_PAL); - ECase(ELFOSABI_AMDGPU_MESA3D); - ECase(ELFOSABI_ARM); ECase(ELFOSABI_C6000_ELFABI); + ECase(ELFOSABI_AMDGPU_HSA); ECase(ELFOSABI_C6000_LINUX); + ECase(ELFOSABI_ARM); ECase(ELFOSABI_STANDALONE); #undef ECase } @@ -361,14 +359,6 @@ BCase(EF_AVR_ARCH_XMEGA6); BCase(EF_AVR_ARCH_XMEGA7); break; - case ELF::EM_RISCV: - BCase(EF_RISCV_RVC); - BCaseMask(EF_RISCV_FLOAT_ABI_SOFT, EF_RISCV_FLOAT_ABI); - BCaseMask(EF_RISCV_FLOAT_ABI_SINGLE, EF_RISCV_FLOAT_ABI); - BCaseMask(EF_RISCV_FLOAT_ABI_DOUBLE, EF_RISCV_FLOAT_ABI); - BCaseMask(EF_RISCV_FLOAT_ABI_QUAD, EF_RISCV_FLOAT_ABI); - BCase(EF_RISCV_RVE); - break; case ELF::EM_AMDGPU: case ELF::EM_X86_64: break; @@ -460,7 +450,6 @@ BCase(SHF_OS_NONCONFORMING); BCase(SHF_GROUP); BCase(SHF_TLS); - BCase(SHF_COMPRESSED); switch (Object->Header.Machine) { case ELF::EM_ARM: BCase(SHF_ARM_PURECODE); Index: lib/Support/Parallel.cpp =================================================================== --- lib/Support/Parallel.cpp +++ lib/Support/Parallel.cpp @@ -9,7 +9,6 @@ #include "llvm/Support/Parallel.h" #include "llvm/Config/llvm-config.h" -#include "llvm/Support/Threading.h" #include #include @@ -71,7 +70,8 @@ /// in filo order. class ThreadPoolExecutor : public Executor { public: - explicit ThreadPoolExecutor(unsigned ThreadCount = hardware_concurrency()) + explicit ThreadPoolExecutor( + unsigned ThreadCount = std::thread::hardware_concurrency()) : Done(ThreadCount) { // Spawn all but one of the threads in another thread as spawning threads // can take a while. Index: lib/Support/ThreadPool.cpp =================================================================== --- lib/Support/ThreadPool.cpp +++ lib/Support/ThreadPool.cpp @@ -14,15 +14,14 @@ #include "llvm/Support/ThreadPool.h" #include "llvm/Config/llvm-config.h" -#include "llvm/Support/Threading.h" #include "llvm/Support/raw_ostream.h" using namespace llvm; #if LLVM_ENABLE_THREADS -// Default to hardware_concurrency -ThreadPool::ThreadPool() : ThreadPool(hardware_concurrency()) {} +// Default to std::thread::hardware_concurrency +ThreadPool::ThreadPool() : ThreadPool(std::thread::hardware_concurrency()) {} ThreadPool::ThreadPool(unsigned ThreadCount) : ActiveThreads(0), EnableFlag(true) { Index: lib/Support/Threading.cpp =================================================================== --- lib/Support/Threading.cpp +++ lib/Support/Threading.cpp @@ -47,8 +47,6 @@ unsigned llvm::heavyweight_hardware_concurrency() { return 1; } -unsigned llvm::hardware_concurrency() { return 1; } - uint64_t llvm::get_threadid() { return 0; } uint32_t llvm::get_max_thread_name_length() { return 0; } @@ -73,18 +71,6 @@ return NumPhysical; } -unsigned llvm::hardware_concurrency() { -#ifdef HAVE_SCHED_GETAFFINITY - cpu_set_t Set; - if (sched_getaffinity(0, sizeof(Set), &Set)) - return CPU_COUNT(&Set); -#endif - // Guard against std::thread::hardware_concurrency() returning 0. - if (unsigned Val = std::thread::hardware_concurrency()) - return Val; - return 1; -} - // Include the platform-specific parts of this class. #ifdef LLVM_ON_UNIX #include "Unix/Threading.inc" Index: lib/Target/AMDGPU/AMDGPU.td =================================================================== --- lib/Target/AMDGPU/AMDGPU.td +++ lib/Target/AMDGPU/AMDGPU.td @@ -724,28 +724,18 @@ def HasMadMix : Predicate<"Subtarget->hasMadMixInsts()">, AssemblerPredicate<"FeatureGFX9Insts">; - -// Exists to help track down where SubtargetPredicate isn't set rather -// than letting tablegen crash with an unhelpful error. -def InvalidPred : Predicate<"predicate not set on instruction or pattern">; - class PredicateControl { - Predicate SubtargetPredicate = InvalidPred; + Predicate SubtargetPredicate; Predicate SIAssemblerPredicate = isSICI; Predicate VIAssemblerPredicate = isVI; list AssemblerPredicates = []; Predicate AssemblerPredicate = TruePredicate; list OtherPredicates = []; - list Predicates = !listconcat([SubtargetPredicate, - AssemblerPredicate], + list Predicates = !listconcat([SubtargetPredicate, AssemblerPredicate], AssemblerPredicates, OtherPredicates); } -class AMDGPUPat : Pat, - PredicateControl; - - // Include AMDGPU TD files include "R600Schedule.td" include "SISchedule.td" Index: lib/Target/AMDGPU/AMDGPUAsmPrinter.h =================================================================== --- lib/Target/AMDGPU/AMDGPUAsmPrinter.h +++ lib/Target/AMDGPU/AMDGPUAsmPrinter.h @@ -112,12 +112,10 @@ SIProgramInfo CurrentProgramInfo; DenseMap CallGraphResourceInfo; - std::map PalMetadata; uint64_t getFunctionCodeSize(const MachineFunction &MF) const; SIFunctionResourceInfo analyzeResourceUsage(const MachineFunction &MF) const; - void readPalMetadata(Module &M); void getSIProgramInfo(SIProgramInfo &Out, const MachineFunction &MF); void getAmdKernelCode(amd_kernel_code_t &Out, const SIProgramInfo &KernelInfo, const MachineFunction &MF) const; @@ -129,7 +127,6 @@ /// can correctly setup the GPU state. void EmitProgramInfoR600(const MachineFunction &MF); void EmitProgramInfoSI(const MachineFunction &MF, const SIProgramInfo &KernelInfo); - void EmitPalMetadata(const MachineFunction &MF, const SIProgramInfo &KernelInfo); void emitCommonFunctionComments(uint32_t NumVGPR, uint32_t NumSGPR, uint32_t ScratchSize, Index: lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp =================================================================== --- lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp +++ lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp @@ -110,18 +110,12 @@ } void AMDGPUAsmPrinter::EmitStartOfAsmFile(Module &M) { - AMDGPU::IsaInfo::IsaVersion ISA = - AMDGPU::IsaInfo::getIsaVersion(getSTI()->getFeatureBits()); - - if (TM.getTargetTriple().getOS() == Triple::AMDPAL) { - readPalMetadata(M); - // AMDPAL wants an HSA_ISA .note. - getTargetStreamer().EmitDirectiveHSACodeObjectISA( - ISA.Major, ISA.Minor, ISA.Stepping, "AMD", "AMDGPU"); - } if (TM.getTargetTriple().getOS() != Triple::AMDHSA) return; + AMDGPU::IsaInfo::IsaVersion ISA = + AMDGPU::IsaInfo::getIsaVersion(getSTI()->getFeatureBits()); + getTargetStreamer().EmitDirectiveHSACodeObjectVersion(2, 1); getTargetStreamer().EmitDirectiveHSACodeObjectISA( ISA.Major, ISA.Minor, ISA.Stepping, "AMD", "AMDGPU"); @@ -129,17 +123,6 @@ } void AMDGPUAsmPrinter::EmitEndOfAsmFile(Module &M) { - if (TM.getTargetTriple().getOS() == Triple::AMDPAL) { - // Copy the PAL metadata from the map where we collected it into a vector, - // then write it as a .note. - std::vector Data; - for (auto i : PalMetadata) { - Data.push_back(i.first); - Data.push_back(i.second); - } - getTargetStreamer().EmitPalMetadata(Data); - } - if (TM.getTargetTriple().getOS() != Triple::AMDHSA) return; @@ -207,27 +190,6 @@ return AsmPrinter::doFinalization(M); } -// For the amdpal OS type, read the amdgpu.pal.metadata supplied by the -// frontend into our PalMetadata map, ready for per-function modification. It -// is a NamedMD containing an MDTuple containing a number of MDNodes each of -// which is an integer value, and each two integer values forms a key=value -// pair that we store as PalMetadata[key]=value in the map. -void AMDGPUAsmPrinter::readPalMetadata(Module &M) { - auto NamedMD = M.getNamedMetadata("amdgpu.pal.metadata"); - if (!NamedMD || !NamedMD->getNumOperands()) - return; - auto Tuple = dyn_cast(NamedMD->getOperand(0)); - if (!Tuple) - return; - for (unsigned I = 0, E = Tuple->getNumOperands() & -2; I != E; I += 2) { - auto Key = mdconst::dyn_extract(Tuple->getOperand(I)); - auto Val = mdconst::dyn_extract(Tuple->getOperand(I + 1)); - if (!Key || !Val) - continue; - PalMetadata[Key->getZExtValue()] = Val->getZExtValue(); - } -} - // Print comments that apply to both callable functions and entry points. void AMDGPUAsmPrinter::emitCommonFunctionComments( uint32_t NumVGPR, @@ -270,8 +232,6 @@ Info = analyzeResourceUsage(MF); } - if (STM.isAmdPalOS()) - EmitPalMetadata(MF, CurrentProgramInfo); if (!STM.isAmdHsaOS()) { EmitProgramInfoSI(MF, CurrentProgramInfo); } @@ -963,74 +923,6 @@ OutStreamer->EmitIntValue(MFI->getNumSpilledVGPRs(), 4); } -// This is the equivalent of EmitProgramInfoSI above, but for when the OS type -// is AMDPAL. It stores each compute/SPI register setting and other PAL -// metadata items into the PalMetadata map, combining with any provided by the -// frontend as LLVM metadata. Once all functions are written, PalMetadata is -// then written as a single block in the .note section. -void AMDGPUAsmPrinter::EmitPalMetadata(const MachineFunction &MF, - const SIProgramInfo &CurrentProgramInfo) { - const SIMachineFunctionInfo *MFI = MF.getInfo(); - // Given the calling convention, calculate the register number for rsrc1. In - // principle the register number could change in future hardware, but we know - // it is the same for gfx6-9 (except that LS and ES don't exist on gfx9), so - // we can use the same fixed value that .AMDGPU.config has for Mesa. Note - // that we use a register number rather than a byte offset, so we need to - // divide by 4. - unsigned Rsrc1Reg = getRsrcReg(MF.getFunction()->getCallingConv()) / 4; - unsigned Rsrc2Reg = Rsrc1Reg + 1; - // Also calculate the PAL metadata key for *S_SCRATCH_SIZE. It can be used - // with a constant offset to access any non-register shader-specific PAL - // metadata key. - unsigned ScratchSizeKey = AMDGPU::ElfNote::AMDGPU_PAL_METADATA_CS_SCRATCH_SIZE; - switch (MF.getFunction()->getCallingConv()) { - case CallingConv::AMDGPU_PS: - ScratchSizeKey = AMDGPU::ElfNote::AMDGPU_PAL_METADATA_PS_SCRATCH_SIZE; - break; - case CallingConv::AMDGPU_VS: - ScratchSizeKey = AMDGPU::ElfNote::AMDGPU_PAL_METADATA_VS_SCRATCH_SIZE; - break; - case CallingConv::AMDGPU_GS: - ScratchSizeKey = AMDGPU::ElfNote::AMDGPU_PAL_METADATA_GS_SCRATCH_SIZE; - break; - case CallingConv::AMDGPU_ES: - ScratchSizeKey = AMDGPU::ElfNote::AMDGPU_PAL_METADATA_ES_SCRATCH_SIZE; - break; - case CallingConv::AMDGPU_HS: - ScratchSizeKey = AMDGPU::ElfNote::AMDGPU_PAL_METADATA_HS_SCRATCH_SIZE; - break; - case CallingConv::AMDGPU_LS: - ScratchSizeKey = AMDGPU::ElfNote::AMDGPU_PAL_METADATA_LS_SCRATCH_SIZE; - break; - } - unsigned NumUsedVgprsKey = ScratchSizeKey - + AMDGPU::ElfNote::AMDGPU_PAL_METADATA_VS_NUM_USED_VGPRS - - AMDGPU::ElfNote::AMDGPU_PAL_METADATA_VS_SCRATCH_SIZE; - unsigned NumUsedSgprsKey = ScratchSizeKey - + AMDGPU::ElfNote::AMDGPU_PAL_METADATA_VS_NUM_USED_SGPRS - - AMDGPU::ElfNote::AMDGPU_PAL_METADATA_VS_SCRATCH_SIZE; - PalMetadata[NumUsedVgprsKey] = CurrentProgramInfo.NumVGPRsForWavesPerEU; - PalMetadata[NumUsedSgprsKey] = CurrentProgramInfo.NumSGPRsForWavesPerEU; - if (AMDGPU::isCompute(MF.getFunction()->getCallingConv())) { - PalMetadata[Rsrc1Reg] |= CurrentProgramInfo.ComputePGMRSrc1; - PalMetadata[Rsrc2Reg] |= CurrentProgramInfo.ComputePGMRSrc2; - // ScratchSize is in bytes, 16 aligned. - PalMetadata[ScratchSizeKey] |= alignTo(CurrentProgramInfo.ScratchSize, 16); - } else { - PalMetadata[Rsrc1Reg] |= S_00B028_VGPRS(CurrentProgramInfo.VGPRBlocks) - | S_00B028_SGPRS(CurrentProgramInfo.SGPRBlocks); - if (CurrentProgramInfo.ScratchBlocks > 0) - PalMetadata[Rsrc2Reg] |= S_00B84C_SCRATCH_EN(1); - // ScratchSize is in bytes, 16 aligned. - PalMetadata[ScratchSizeKey] |= alignTo(CurrentProgramInfo.ScratchSize, 16); - } - if (MF.getFunction()->getCallingConv() == CallingConv::AMDGPU_PS) { - PalMetadata[Rsrc2Reg] |= S_00B02C_EXTRA_LDS_SIZE(CurrentProgramInfo.LDSBlocks); - PalMetadata[R_0286CC_SPI_PS_INPUT_ENA / 4] |= MFI->getPSInputEnable(); - PalMetadata[R_0286D0_SPI_PS_INPUT_ADDR / 4] |= MFI->getPSInputAddr(); - } -} - // This is supposed to be log2(Size) static amd_element_byte_size_t getElementByteSizeValue(unsigned Size) { switch (Size) { Index: lib/Target/AMDGPU/AMDGPUInstructions.td =================================================================== --- lib/Target/AMDGPU/AMDGPUInstructions.td +++ lib/Target/AMDGPU/AMDGPUInstructions.td @@ -505,7 +505,7 @@ /* -------------------------------------- */ class POW_Common - : AMDGPUPat < + : Pat < (fpow f32:$src0, f32:$src1), (exp_ieee (mul f32:$src1, (log_ieee f32:$src0))) >; @@ -516,34 +516,30 @@ /* Extract element pattern */ class Extract_Element - : AMDGPUPat< + : Pat< (sub_type (extractelt vec_type:$src, sub_idx)), (EXTRACT_SUBREG $src, sub_reg) -> { - let SubtargetPredicate = TruePredicate; -} +>; /* Insert element pattern */ class Insert_Element - : AMDGPUPat < + : Pat < (insertelt vec_type:$vec, elem_type:$elem, sub_idx), (INSERT_SUBREG $vec, $elem, sub_reg) -> { - let SubtargetPredicate = TruePredicate; -} +>; // XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer // can handle COPY instructions. // bitconvert pattern -class BitConvert : AMDGPUPat < +class BitConvert : Pat < (dt (bitconvert (st rc:$src0))), (dt rc:$src0) >; // XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer // can handle COPY instructions. -class DwordAddrPat : AMDGPUPat < +class DwordAddrPat : Pat < (vt (AMDGPUdwordaddr (vt rc:$addr))), (vt rc:$addr) >; @@ -555,30 +551,30 @@ RegisterClass RC64> { // Definition from ISA doc: // (y & x) | (z & ~x) - def : AMDGPUPat < + def : Pat < (or (and i32:$y, i32:$x), (and i32:$z, (not i32:$x))), (BFI_INT $x, $y, $z) >; // SHA-256 Ch function // z ^ (x & (y ^ z)) - def : AMDGPUPat < + def : Pat < (xor i32:$z, (and i32:$x, (xor i32:$y, i32:$z))), (BFI_INT $x, $y, $z) >; - def : AMDGPUPat < + def : Pat < (fcopysign f32:$src0, f32:$src1), (BFI_INT (LoadImm32 (i32 0x7fffffff)), $src0, $src1) >; - def : AMDGPUPat < + def : Pat < (f32 (fcopysign f32:$src0, f64:$src1)), (BFI_INT (LoadImm32 (i32 0x7fffffff)), $src0, (i32 (EXTRACT_SUBREG $src1, sub1))) >; - def : AMDGPUPat < + def : Pat < (f64 (fcopysign f64:$src0, f64:$src1)), (REG_SEQUENCE RC64, (i32 (EXTRACT_SUBREG $src0, sub0)), sub0, @@ -587,7 +583,7 @@ (i32 (EXTRACT_SUBREG $src1, sub1))), sub1) >; - def : AMDGPUPat < + def : Pat < (f64 (fcopysign f64:$src0, f32:$src1)), (REG_SEQUENCE RC64, (i32 (EXTRACT_SUBREG $src0, sub0)), sub0, @@ -600,7 +596,7 @@ // SHA-256 Ma patterns // ((x & z) | (y & (x | z))) -> BFI_INT (XOR x, y), z, y -class SHA256MaPattern : AMDGPUPat < +class SHA256MaPattern : Pat < (or (and i32:$x, i32:$z), (and i32:$y, (or i32:$x, i32:$z))), (BFI_INT (XOR i32:$x, i32:$y), i32:$z, i32:$y) >; @@ -617,24 +613,24 @@ }]>; multiclass BFEPattern { - def : AMDGPUPat < + def : Pat < (i32 (and (i32 (srl i32:$src, i32:$rshift)), IMMZeroBasedBitfieldMask:$mask)), (UBFE $src, $rshift, (MOV (i32 (IMMPopCount $mask)))) >; - def : AMDGPUPat < + def : Pat < (srl (shl_oneuse i32:$src, (sub 32, i32:$width)), (sub 32, i32:$width)), (UBFE $src, (i32 0), $width) >; - def : AMDGPUPat < + def : Pat < (sra (shl_oneuse i32:$src, (sub 32, i32:$width)), (sub 32, i32:$width)), (SBFE $src, (i32 0), $width) >; } // rotr pattern -class ROTRPattern : AMDGPUPat < +class ROTRPattern : Pat < (rotr i32:$src0, i32:$src1), (BIT_ALIGN $src0, $src0, $src1) >; @@ -645,7 +641,7 @@ SDPatternOperator max, SDPatternOperator max_oneuse, SDPatternOperator min_oneuse, - ValueType vt = i32> : AMDGPUPat< + ValueType vt = i32> : Pat< (max (min_oneuse vt:$src0, vt:$src1), (min_oneuse (max_oneuse vt:$src0, vt:$src1), vt:$src2)), (med3Inst $src0, $src1, $src2) @@ -665,24 +661,24 @@ [{ (void)N; return TM.Options.NoNaNsFPMath; }] >; -class IMad24Pat : AMDGPUPat < +class IMad24Pat : Pat < (add (AMDGPUmul_i24 i32:$src0, i32:$src1), i32:$src2), !if(HasClamp, (Inst $src0, $src1, $src2, (i1 0)), (Inst $src0, $src1, $src2)) >; -class UMad24Pat : AMDGPUPat < +class UMad24Pat : Pat < (add (AMDGPUmul_u24 i32:$src0, i32:$src1), i32:$src2), !if(HasClamp, (Inst $src0, $src1, $src2, (i1 0)), (Inst $src0, $src1, $src2)) >; -class RcpPat : AMDGPUPat < +class RcpPat : Pat < (fdiv FP_ONE, vt:$src), (RcpInst $src) >; -class RsqPat : AMDGPUPat < +class RsqPat : Pat < (AMDGPUrcp (fsqrt vt:$src)), (RsqInst $src) >; Index: lib/Target/AMDGPU/AMDGPUPTNote.h =================================================================== --- lib/Target/AMDGPU/AMDGPUPTNote.h +++ lib/Target/AMDGPU/AMDGPUPTNote.h @@ -27,49 +27,16 @@ // TODO: Move this enum to include/llvm/Support so it can be used in tools? enum NoteType{ - NT_AMDGPU_HSA_RESERVED_0 = 0, NT_AMDGPU_HSA_CODE_OBJECT_VERSION = 1, NT_AMDGPU_HSA_HSAIL = 2, NT_AMDGPU_HSA_ISA = 3, NT_AMDGPU_HSA_PRODUCER = 4, NT_AMDGPU_HSA_PRODUCER_OPTIONS = 5, NT_AMDGPU_HSA_EXTENSION = 6, - NT_AMDGPU_HSA_RESERVED_7 = 7, - NT_AMDGPU_HSA_RESERVED_8 = 8, - NT_AMDGPU_HSA_RESERVED_9 = 9, NT_AMDGPU_HSA_CODE_OBJECT_METADATA = 10, - NT_AMD_AMDGPU_ISA = 11, - NT_AMDGPU_PAL_METADATA = 12, NT_AMDGPU_HSA_HLDEBUG_DEBUG = 101, NT_AMDGPU_HSA_HLDEBUG_TARGET = 102 }; - -enum NoteAmdGpuPalMetadataKey { - AMDGPU_PAL_METADATA_LS_NUM_USED_VGPRS = 0x10000015, - AMDGPU_PAL_METADATA_HS_NUM_USED_VGPRS = 0x10000016, - AMDGPU_PAL_METADATA_ES_NUM_USED_VGPRS = 0x10000017, - AMDGPU_PAL_METADATA_GS_NUM_USED_VGPRS = 0x10000018, - AMDGPU_PAL_METADATA_VS_NUM_USED_VGPRS = 0x10000019, - AMDGPU_PAL_METADATA_PS_NUM_USED_VGPRS = 0x1000001a, - AMDGPU_PAL_METADATA_CS_NUM_USED_VGPRS = 0x1000001b, - - AMDGPU_PAL_METADATA_LS_NUM_USED_SGPRS = 0x1000001c, - AMDGPU_PAL_METADATA_HS_NUM_USED_SGPRS = 0x1000001d, - AMDGPU_PAL_METADATA_ES_NUM_USED_SGPRS = 0x1000001e, - AMDGPU_PAL_METADATA_GS_NUM_USED_SGPRS = 0x1000001f, - AMDGPU_PAL_METADATA_VS_NUM_USED_SGPRS = 0x10000020, - AMDGPU_PAL_METADATA_PS_NUM_USED_SGPRS = 0x10000021, - AMDGPU_PAL_METADATA_CS_NUM_USED_SGPRS = 0x10000022, - - AMDGPU_PAL_METADATA_LS_SCRATCH_SIZE = 0x10000038, - AMDGPU_PAL_METADATA_HS_SCRATCH_SIZE = 0x10000039, - AMDGPU_PAL_METADATA_ES_SCRATCH_SIZE = 0x1000003a, - AMDGPU_PAL_METADATA_GS_SCRATCH_SIZE = 0x1000003b, - AMDGPU_PAL_METADATA_VS_SCRATCH_SIZE = 0x1000003c, - AMDGPU_PAL_METADATA_PS_SCRATCH_SIZE = 0x1000003d, - AMDGPU_PAL_METADATA_CS_SCRATCH_SIZE = 0x1000003e, -}; - } } Index: lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp =================================================================== --- lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -833,7 +833,6 @@ bool ParseDirectiveAMDKernelCodeT(); bool subtargetHasRegister(const MCRegisterInfo &MRI, unsigned RegNo) const; bool ParseDirectiveAMDGPUHsaKernel(); - bool ParseDirectivePalMetadata(); bool AddNextRegisterToList(unsigned& Reg, unsigned& RegWidth, RegisterKind RegKind, unsigned Reg1, unsigned RegNum); @@ -2494,21 +2493,6 @@ return false; } -bool AMDGPUAsmParser::ParseDirectivePalMetadata() { - std::vector Data; - for (;;) { - uint32_t Value; - if (ParseAsAbsoluteExpression(Value)) - return TokError("invalid value in .amdgpu_pal_metadata"); - Data.push_back(Value); - if (getLexer().isNot(AsmToken::Comma)) - break; - Lex(); - } - getTargetStreamer().EmitPalMetadata(Data); - return false; -} - bool AMDGPUAsmParser::ParseDirective(AsmToken DirectiveID) { StringRef IDVal = DirectiveID.getString(); @@ -2527,9 +2511,6 @@ if (IDVal == ".amdgpu_hsa_kernel") return ParseDirectiveAMDGPUHsaKernel(); - if (IDVal == ".amdgpu_pal_metadata") - return ParseDirectivePalMetadata(); - return true; } Index: lib/Target/AMDGPU/BUFInstructions.td =================================================================== --- lib/Target/AMDGPU/BUFInstructions.td +++ lib/Target/AMDGPU/BUFInstructions.td @@ -647,6 +647,8 @@ // MUBUF Instructions //===----------------------------------------------------------------------===// +let SubtargetPredicate = isGCN in { + defm BUFFER_LOAD_FORMAT_X : MUBUF_Pseudo_Loads < "buffer_load_format_x", VGPR_32 >; @@ -860,6 +862,8 @@ defm TBUFFER_STORE_FORMAT_XYZ : MTBUF_Pseudo_Stores <"tbuffer_store_format_xyz", VReg_128>; defm TBUFFER_STORE_FORMAT_XYZW : MTBUF_Pseudo_Stores <"tbuffer_store_format_xyzw", VReg_128>; +} // End let SubtargetPredicate = isGCN + let SubtargetPredicate = isCIVI in { //===----------------------------------------------------------------------===// @@ -878,8 +882,10 @@ // MUBUF Patterns //===----------------------------------------------------------------------===// +let Predicates = [isGCN] in { + // Offset in an 32-bit VGPR -def : GCNPat < +def : Pat < (SIload_constant v4i32:$sbase, i32:$voff), (BUFFER_LOAD_DWORD_OFFEN $voff, $sbase, (i32 0), 0, 0, 0, 0) >; @@ -891,7 +897,7 @@ multiclass MUBUF_LoadIntrinsicPat { - def : GCNPat< + def : Pat< (vt (name v4i32:$rsrc, 0, (MUBUFIntrinsicOffset i32:$soffset, i16:$offset), imm:$glc, imm:$slc)), @@ -899,7 +905,7 @@ (as_i1imm $glc), (as_i1imm $slc), 0) >; - def : GCNPat< + def : Pat< (vt (name v4i32:$rsrc, i32:$vindex, (MUBUFIntrinsicOffset i32:$soffset, i16:$offset), imm:$glc, imm:$slc)), @@ -907,7 +913,7 @@ (as_i1imm $glc), (as_i1imm $slc), 0) >; - def : GCNPat< + def : Pat< (vt (name v4i32:$rsrc, 0, (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset), imm:$glc, imm:$slc)), @@ -915,7 +921,7 @@ (as_i1imm $glc), (as_i1imm $slc), 0) >; - def : GCNPat< + def : Pat< (vt (name v4i32:$rsrc, i32:$vindex, (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset), imm:$glc, imm:$slc)), @@ -935,7 +941,7 @@ multiclass MUBUF_StoreIntrinsicPat { - def : GCNPat< + def : Pat< (name vt:$vdata, v4i32:$rsrc, 0, (MUBUFIntrinsicOffset i32:$soffset, i16:$offset), imm:$glc, imm:$slc), @@ -943,7 +949,7 @@ (as_i1imm $glc), (as_i1imm $slc), 0) >; - def : GCNPat< + def : Pat< (name vt:$vdata, v4i32:$rsrc, i32:$vindex, (MUBUFIntrinsicOffset i32:$soffset, i16:$offset), imm:$glc, imm:$slc), @@ -952,7 +958,7 @@ (as_i1imm $slc), 0) >; - def : GCNPat< + def : Pat< (name vt:$vdata, v4i32:$rsrc, 0, (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset), imm:$glc, imm:$slc), @@ -961,7 +967,7 @@ (as_i1imm $slc), 0) >; - def : GCNPat< + def : Pat< (name vt:$vdata, v4i32:$rsrc, i32:$vindex, (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset), imm:$glc, imm:$slc), @@ -985,7 +991,7 @@ //===----------------------------------------------------------------------===// multiclass BufferAtomicPatterns { - def : GCNPat< + def : Pat< (name i32:$vdata_in, v4i32:$rsrc, 0, (MUBUFIntrinsicOffset i32:$soffset, i16:$offset), imm:$slc), @@ -993,7 +999,7 @@ (as_i16imm $offset), (as_i1imm $slc)) >; - def : GCNPat< + def : Pat< (name i32:$vdata_in, v4i32:$rsrc, i32:$vindex, (MUBUFIntrinsicOffset i32:$soffset, i16:$offset), imm:$slc), @@ -1001,7 +1007,7 @@ (as_i16imm $offset), (as_i1imm $slc)) >; - def : GCNPat< + def : Pat< (name i32:$vdata_in, v4i32:$rsrc, 0, (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset), imm:$slc), @@ -1009,7 +1015,7 @@ (as_i16imm $offset), (as_i1imm $slc)) >; - def : GCNPat< + def : Pat< (name i32:$vdata_in, v4i32:$rsrc, i32:$vindex, (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset), imm:$slc), @@ -1031,7 +1037,7 @@ defm : BufferAtomicPatterns; defm : BufferAtomicPatterns; -def : GCNPat< +def : Pat< (int_amdgcn_buffer_atomic_cmpswap i32:$data, i32:$cmp, v4i32:$rsrc, 0, (MUBUFIntrinsicOffset i32:$soffset, i16:$offset), @@ -1043,7 +1049,7 @@ sub0) >; -def : GCNPat< +def : Pat< (int_amdgcn_buffer_atomic_cmpswap i32:$data, i32:$cmp, v4i32:$rsrc, i32:$vindex, (MUBUFIntrinsicOffset i32:$soffset, i16:$offset), @@ -1055,7 +1061,7 @@ sub0) >; -def : GCNPat< +def : Pat< (int_amdgcn_buffer_atomic_cmpswap i32:$data, i32:$cmp, v4i32:$rsrc, 0, (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset), @@ -1067,7 +1073,7 @@ sub0) >; -def : GCNPat< +def : Pat< (int_amdgcn_buffer_atomic_cmpswap i32:$data, i32:$cmp, v4i32:$rsrc, i32:$vindex, (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset), @@ -1082,7 +1088,7 @@ class MUBUFLoad_PatternADDR64 : GCNPat < + PatFrag constant_ld> : Pat < (vt (constant_ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, i16:$offset, i1:$glc, i1:$slc, i1:$tfe))), (Instr_ADDR64 $vaddr, $srsrc, $soffset, $offset, $glc, $slc, $tfe) @@ -1090,19 +1096,19 @@ multiclass MUBUFLoad_Atomic_Pattern { - def : GCNPat < + def : Pat < (vt (atomic_ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, i16:$offset, i1:$slc))), (Instr_ADDR64 $vaddr, $srsrc, $soffset, $offset, 0, $slc, 0) >; - def : GCNPat < + def : Pat < (vt (atomic_ld (MUBUFOffsetNoGLC v4i32:$rsrc, i32:$soffset, i16:$offset))), (Instr_OFFSET $rsrc, $soffset, (as_i16imm $offset), 0, 0, 0) >; } -let SubtargetPredicate = isSICI in { +let Predicates = [isSICI] in { def : MUBUFLoad_PatternADDR64 ; def : MUBUFLoad_PatternADDR64 ; def : MUBUFLoad_PatternADDR64 ; @@ -1110,19 +1116,19 @@ defm : MUBUFLoad_Atomic_Pattern ; defm : MUBUFLoad_Atomic_Pattern ; -} // End SubtargetPredicate = isSICI +} // End Predicates = [isSICI] multiclass MUBUFLoad_Pattern { - def : GCNPat < + def : Pat < (vt (ld (MUBUFOffset v4i32:$srsrc, i32:$soffset, i16:$offset, i1:$glc, i1:$slc, i1:$tfe))), (Instr_OFFSET $srsrc, $soffset, $offset, $glc, $slc, $tfe) >; } -let OtherPredicates = [Has16BitInsts] in { +let Predicates = [Has16BitInsts] in { defm : MUBUFLoad_Pattern ; defm : MUBUFLoad_Pattern ; @@ -1131,18 +1137,18 @@ defm : MUBUFLoad_Pattern ; -} // End OtherPredicates = [Has16BitInsts] +} // End Predicates = [Has16BitInsts] multiclass MUBUFScratchLoadPat { - def : GCNPat < + def : Pat < (vt (ld (MUBUFScratchOffen v4i32:$srsrc, i32:$vaddr, i32:$soffset, u16imm:$offset))), (InstrOffen $vaddr, $srsrc, $soffset, $offset, 0, 0, 0) >; - def : GCNPat < + def : Pat < (vt (ld (MUBUFScratchOffset v4i32:$srsrc, i32:$soffset, u16imm:$offset))), (InstrOffset $srsrc, $soffset, $offset, 0, 0, 0) >; @@ -1152,25 +1158,25 @@ multiclass MUBUFScratchLoadPat_Hi16 { - def : GCNPat < + def : Pat < (build_vector vt:$lo, (vt (ld (MUBUFScratchOffen v4i32:$srsrc, i32:$vaddr, i32:$soffset, u16imm:$offset)))), (v2i16 (InstrOffen $vaddr, $srsrc, $soffset, $offset, 0, 0, 0, $lo)) >; - def : GCNPat < + def : Pat < (build_vector f16:$lo, (f16 (bitconvert (vt (ld (MUBUFScratchOffen v4i32:$srsrc, i32:$vaddr, i32:$soffset, u16imm:$offset)))))), (v2f16 (InstrOffen $vaddr, $srsrc, $soffset, $offset, 0, 0, 0, $lo)) >; - def : GCNPat < + def : Pat < (build_vector vt:$lo, (vt (ld (MUBUFScratchOffset v4i32:$srsrc, i32:$soffset, u16imm:$offset)))), (v2i16 (InstrOffset $srsrc, $soffset, $offset, 0, 0, 0, $lo)) >; - def : GCNPat < + def : Pat < (build_vector f16:$lo, (f16 (bitconvert (vt (ld (MUBUFScratchOffset v4i32:$srsrc, i32:$soffset, u16imm:$offset)))))), (v2f16 (InstrOffset $srsrc, $soffset, $offset, 0, 0, 0, $lo)) >; @@ -1187,7 +1193,7 @@ defm : MUBUFScratchLoadPat ; defm : MUBUFScratchLoadPat ; -let OtherPredicates = [HasD16LoadStore] in { +let Predicates = [HasD16LoadStore] in { defm : MUBUFScratchLoadPat_Hi16; defm : MUBUFScratchLoadPat_Hi16; defm : MUBUFScratchLoadPat_Hi16; @@ -1200,7 +1206,7 @@ MUBUF_Pseudo idxen, MUBUF_Pseudo bothen> { - def : GCNPat < + def : Pat < (vt (int_SI_buffer_load_dword v4i32:$rsrc, (i32 imm), i32:$soffset, imm:$offset, 0, 0, imm:$glc, imm:$slc, imm:$tfe)), @@ -1208,7 +1214,7 @@ (as_i1imm $slc), (as_i1imm $tfe)) >; - def : GCNPat < + def : Pat < (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset, imm:$offset, 1, 0, imm:$glc, imm:$slc, imm:$tfe)), @@ -1216,7 +1222,7 @@ (as_i1imm $tfe)) >; - def : GCNPat < + def : Pat < (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset, imm:$offset, 0, 1, imm:$glc, imm:$slc, imm:$tfe)), @@ -1224,7 +1230,7 @@ (as_i1imm $slc), (as_i1imm $tfe)) >; - def : GCNPat < + def : Pat < (vt (int_SI_buffer_load_dword v4i32:$rsrc, v2i32:$vaddr, i32:$soffset, imm:$offset, 1, 1, imm:$glc, imm:$slc, imm:$tfe)), @@ -1243,27 +1249,27 @@ multiclass MUBUFStore_Atomic_Pattern { // Store follows atomic op convention so address is forst - def : GCNPat < + def : Pat < (atomic_st (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, i16:$offset, i1:$slc), vt:$val), (Instr_ADDR64 $val, $vaddr, $srsrc, $soffset, $offset, 0, $slc, 0) >; - def : GCNPat < + def : Pat < (atomic_st (MUBUFOffsetNoGLC v4i32:$rsrc, i32:$soffset, i16:$offset), vt:$val), (Instr_OFFSET $val, $rsrc, $soffset, (as_i16imm $offset), 0, 0, 0) >; } -let SubtargetPredicate = isSICI in { +let Predicates = [isSICI] in { defm : MUBUFStore_Atomic_Pattern ; defm : MUBUFStore_Atomic_Pattern ; -} // End Predicates = isSICI +} // End Predicates = [isSICI] multiclass MUBUFStore_Pattern { - def : GCNPat < + def : Pat < (st vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset, i16:$offset, i1:$glc, i1:$slc, i1:$tfe)), (Instr_OFFSET $vdata, $srsrc, $soffset, $offset, $glc, $slc, $tfe) @@ -1276,13 +1282,13 @@ multiclass MUBUFScratchStorePat { - def : GCNPat < + def : Pat < (st vt:$value, (MUBUFScratchOffen v4i32:$srsrc, i32:$vaddr, i32:$soffset, u16imm:$offset)), (InstrOffen $value, $vaddr, $srsrc, $soffset, $offset, 0, 0, 0) >; - def : GCNPat < + def : Pat < (st vt:$value, (MUBUFScratchOffset v4i32:$srsrc, i32:$soffset, u16imm:$offset)), (InstrOffset $value, $srsrc, $soffset, $offset, 0, 0, 0) @@ -1298,7 +1304,7 @@ defm : MUBUFScratchStorePat ; -let OtherPredicates = [HasD16LoadStore] in { +let Predicates = [HasD16LoadStore] in { // Hiding the extract high pattern in the PatFrag seems to not // automatically increase the complexity. let AddedComplexity = 1 in { @@ -1317,28 +1323,28 @@ multiclass MTBUF_LoadIntrinsicPat { - def : GCNPat< + def : Pat< (vt (name v4i32:$rsrc, 0, 0, i32:$soffset, imm:$offset, imm:$dfmt, imm:$nfmt, imm:$glc, imm:$slc)), (!cast(opcode # _OFFSET) $rsrc, $soffset, (as_i16imm $offset), (as_i8imm $dfmt), (as_i8imm $nfmt), (as_i1imm $glc), (as_i1imm $slc), 0) >; - def : GCNPat< + def : Pat< (vt (name v4i32:$rsrc, i32:$vindex, 0, i32:$soffset, imm:$offset, imm:$dfmt, imm:$nfmt, imm:$glc, imm:$slc)), (!cast(opcode # _IDXEN) $vindex, $rsrc, $soffset, (as_i16imm $offset), (as_i8imm $dfmt), (as_i8imm $nfmt), (as_i1imm $glc), (as_i1imm $slc), 0) >; - def : GCNPat< + def : Pat< (vt (name v4i32:$rsrc, 0, i32:$voffset, i32:$soffset, imm:$offset, imm:$dfmt, imm:$nfmt, imm:$glc, imm:$slc)), (!cast(opcode # _OFFEN) $voffset, $rsrc, $soffset, (as_i16imm $offset), (as_i8imm $dfmt), (as_i8imm $nfmt), (as_i1imm $glc), (as_i1imm $slc), 0) >; - def : GCNPat< + def : Pat< (vt (name v4i32:$rsrc, i32:$vindex, i32:$voffset, i32:$soffset, imm:$offset, imm:$dfmt, imm:$nfmt, imm:$glc, imm:$slc)), (!cast(opcode # _BOTHEN) @@ -1357,7 +1363,7 @@ multiclass MTBUF_StoreIntrinsicPat { - def : GCNPat< + def : Pat< (name vt:$vdata, v4i32:$rsrc, 0, 0, i32:$soffset, imm:$offset, imm:$dfmt, imm:$nfmt, imm:$glc, imm:$slc), (!cast(opcode # _OFFSET_exact) $vdata, $rsrc, $soffset, @@ -1366,7 +1372,7 @@ (as_i1imm $slc), 0) >; - def : GCNPat< + def : Pat< (name vt:$vdata, v4i32:$rsrc, i32:$vindex, 0, i32:$soffset, imm:$offset, imm:$dfmt, imm:$nfmt, imm:$glc, imm:$slc), (!cast(opcode # _IDXEN_exact) $vdata, $vindex, $rsrc, $soffset, @@ -1375,7 +1381,7 @@ (as_i1imm $slc), 0) >; - def : GCNPat< + def : Pat< (name vt:$vdata, v4i32:$rsrc, 0, i32:$voffset, i32:$soffset, imm:$offset, imm:$dfmt, imm:$nfmt, imm:$glc, imm:$slc), (!cast(opcode # _OFFEN_exact) $vdata, $voffset, $rsrc, $soffset, @@ -1384,7 +1390,7 @@ (as_i1imm $slc), 0) >; - def : GCNPat< + def : Pat< (name vt:$vdata, v4i32:$rsrc, i32:$vindex, i32:$voffset, i32:$soffset, imm:$offset, imm:$dfmt, imm:$nfmt, imm:$glc, imm:$slc), (!cast(opcode # _BOTHEN_exact) @@ -1404,6 +1410,8 @@ defm : MTBUF_StoreIntrinsicPat; defm : MTBUF_StoreIntrinsicPat; +} // End let Predicates = [isGCN] + //===----------------------------------------------------------------------===// // Target instructions, move to the appropriate target TD file //===----------------------------------------------------------------------===// Index: lib/Target/AMDGPU/CaymanInstructions.td =================================================================== --- lib/Target/AMDGPU/CaymanInstructions.td +++ lib/Target/AMDGPU/CaymanInstructions.td @@ -18,7 +18,7 @@ // Cayman Instructions //===----------------------------------------------------------------------===// -let SubtargetPredicate = isCayman in { +let Predicates = [isCayman] in { def MULADD_INT24_cm : R600_3OP <0x08, "MULADD_INT24", [(set i32:$dst, (AMDGPUmad_i24 i32:$src0, i32:$src1, i32:$src2))], VecALU @@ -57,21 +57,20 @@ // RECIP_UINT emulation for Cayman // The multiplication scales from [0,1] to the unsigned integer range -def : R600Pat < +def : Pat < (AMDGPUurecip i32:$src0), (FLT_TO_UINT_eg (MUL_IEEE (RECIP_IEEE_cm (UINT_TO_FLT_eg $src0)), (MOV_IMM_I32 CONST.FP_UINT_MAX_PLUS_1))) >; -def CF_END_CM : CF_CLAUSE_EG<32, (ins), "CF_END"> { + def CF_END_CM : CF_CLAUSE_EG<32, (ins), "CF_END"> { let ADDR = 0; let POP_COUNT = 0; let COUNT = 0; } - -def : R600Pat<(fsqrt f32:$src), (MUL R600_Reg32:$src, (RECIPSQRT_CLAMPED_cm $src))>; +def : Pat<(fsqrt f32:$src), (MUL R600_Reg32:$src, (RECIPSQRT_CLAMPED_cm $src))>; class RAT_STORE_DWORD mask> : CF_MEM_RAT_CACHELESS <0x14, 0, mask, @@ -180,43 +179,44 @@ //===----------------------------------------------------------------------===// // VTX Read from parameter memory space //===----------------------------------------------------------------------===// -def : R600Pat<(i32:$dst_gpr (vtx_id3_az_extloadi8 ADDRVTX_READ:$src_gpr)), +def : Pat<(i32:$dst_gpr (vtx_id3_az_extloadi8 ADDRVTX_READ:$src_gpr)), (VTX_READ_8_cm MEMxi:$src_gpr, 3)>; -def : R600Pat<(i32:$dst_gpr (vtx_id3_az_extloadi16 ADDRVTX_READ:$src_gpr)), +def : Pat<(i32:$dst_gpr (vtx_id3_az_extloadi16 ADDRVTX_READ:$src_gpr)), (VTX_READ_16_cm MEMxi:$src_gpr, 3)>; -def : R600Pat<(i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)), +def : Pat<(i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)), (VTX_READ_32_cm MEMxi:$src_gpr, 3)>; -def : R600Pat<(v2i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)), +def : Pat<(v2i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)), (VTX_READ_64_cm MEMxi:$src_gpr, 3)>; -def : R600Pat<(v4i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)), +def : Pat<(v4i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)), (VTX_READ_128_cm MEMxi:$src_gpr, 3)>; //===----------------------------------------------------------------------===// // VTX Read from constant memory space //===----------------------------------------------------------------------===// -def : R600Pat<(i32:$dst_gpr (vtx_id2_az_extloadi8 ADDRVTX_READ:$src_gpr)), +def : Pat<(i32:$dst_gpr (vtx_id2_az_extloadi8 ADDRVTX_READ:$src_gpr)), (VTX_READ_8_cm MEMxi:$src_gpr, 2)>; -def : R600Pat<(i32:$dst_gpr (vtx_id2_az_extloadi16 ADDRVTX_READ:$src_gpr)), +def : Pat<(i32:$dst_gpr (vtx_id2_az_extloadi16 ADDRVTX_READ:$src_gpr)), (VTX_READ_16_cm MEMxi:$src_gpr, 2)>; -def : R600Pat<(i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)), +def : Pat<(i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)), (VTX_READ_32_cm MEMxi:$src_gpr, 2)>; -def : R600Pat<(v2i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)), +def : Pat<(v2i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)), (VTX_READ_64_cm MEMxi:$src_gpr, 2)>; -def : R600Pat<(v4i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)), +def : Pat<(v4i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)), (VTX_READ_128_cm MEMxi:$src_gpr, 2)>; //===----------------------------------------------------------------------===// // VTX Read from global memory space //===----------------------------------------------------------------------===// -def : R600Pat<(i32:$dst_gpr (vtx_id1_az_extloadi8 ADDRVTX_READ:$src_gpr)), +def : Pat<(i32:$dst_gpr (vtx_id1_az_extloadi8 ADDRVTX_READ:$src_gpr)), (VTX_READ_8_cm MEMxi:$src_gpr, 1)>; -def : R600Pat<(i32:$dst_gpr (vtx_id1_az_extloadi16 ADDRVTX_READ:$src_gpr)), +def : Pat<(i32:$dst_gpr (vtx_id1_az_extloadi16 ADDRVTX_READ:$src_gpr)), (VTX_READ_16_cm MEMxi:$src_gpr, 1)>; -def : R600Pat<(i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)), +def : Pat<(i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)), (VTX_READ_32_cm MEMxi:$src_gpr, 1)>; -def : R600Pat<(v2i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)), +def : Pat<(v2i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)), (VTX_READ_64_cm MEMxi:$src_gpr, 1)>; -def : R600Pat<(v4i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)), +def : Pat<(v4i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)), (VTX_READ_128_cm MEMxi:$src_gpr, 1)>; -} // End let SubtargetPredicate = isCayman +} // End isCayman + Index: lib/Target/AMDGPU/DSInstructions.td =================================================================== --- lib/Target/AMDGPU/DSInstructions.td +++ lib/Target/AMDGPU/DSInstructions.td @@ -537,23 +537,25 @@ // DS Patterns //===----------------------------------------------------------------------===// -def : GCNPat < +let Predicates = [isGCN] in { + +def : Pat < (int_amdgcn_ds_swizzle i32:$src, imm:$offset16), (DS_SWIZZLE_B32 $src, (as_i16imm $offset16), (i1 0)) >; -class DSReadPat : GCNPat < +class DSReadPat : Pat < (vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset))), (inst $ptr, (as_i16imm $offset), (i1 0)) >; multiclass DSReadPat_Hi16 { - def : GCNPat < + def : Pat < (build_vector vt:$lo, (vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset)))), (v2i16 (inst $ptr, (as_i16imm $offset), (i1 0), $lo)) >; - def : GCNPat < + def : Pat < (build_vector f16:$lo, (f16 (bitconvert (vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset)))))), (v2f16 (inst $ptr, (as_i16imm $offset), (i1 0), $lo)) >; @@ -575,14 +577,14 @@ } // End AddedComplexity = 100 -def : GCNPat < +def : Pat < (v2i32 (load_local_m0 (DS64Bit4ByteAligned i32:$ptr, i8:$offset0, i8:$offset1))), (DS_READ2_B32 $ptr, $offset0, $offset1, (i1 0)) >; -let OtherPredicates = [HasD16LoadStore] in { +let Predicates = [HasD16LoadStore] in { let AddedComplexity = 100 in { defm : DSReadPat_Hi16; defm : DSReadPat_Hi16; @@ -590,7 +592,7 @@ } } -class DSWritePat : GCNPat < +class DSWritePat : Pat < (frag vt:$value, (DS1Addr1Offset i32:$ptr, i32:$offset)), (inst $ptr, $value, (as_i16imm $offset), (i1 0)) >; @@ -601,7 +603,7 @@ def : DSWritePat ; def : DSWritePat ; -let OtherPredicates = [HasD16LoadStore] in { +let Predicates = [HasD16LoadStore] in { def : DSWritePat ; def : DSWritePat ; } @@ -611,7 +613,7 @@ def : DSWritePat ; } // End AddedComplexity = 100 -def : GCNPat < +def : Pat < (store_local_m0 v2i32:$value, (DS64Bit4ByteAligned i32:$ptr, i8:$offset0, i8:$offset1)), (DS_WRITE2_B32 $ptr, (i32 (EXTRACT_SUBREG $value, sub0)), @@ -619,12 +621,12 @@ (i1 0)) >; -class DSAtomicRetPat : GCNPat < +class DSAtomicRetPat : Pat < (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$value), (inst $ptr, $value, (as_i16imm $offset), (i1 0)) >; -class DSAtomicCmpXChg : GCNPat < +class DSAtomicCmpXChg : Pat < (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$cmp, vt:$swap), (inst $ptr, $cmp, $swap, (as_i16imm $offset), (i1 0)) >; @@ -661,6 +663,8 @@ def : DSAtomicCmpXChg; +} // let Predicates = [isGCN] + //===----------------------------------------------------------------------===// // Real instructions //===----------------------------------------------------------------------===// Index: lib/Target/AMDGPU/EvergreenInstructions.td =================================================================== --- lib/Target/AMDGPU/EvergreenInstructions.td +++ lib/Target/AMDGPU/EvergreenInstructions.td @@ -15,28 +15,20 @@ def isEG : Predicate< "Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && " - "Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS && " + "Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && " "!Subtarget->hasCaymanISA()" >; def isEGorCayman : Predicate< "Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||" - "Subtarget->getGeneration() == AMDGPUSubtarget::NORTHERN_ISLANDS" + "Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS" >; -class EGPat : AMDGPUPat { - let SubtargetPredicate = isEG; -} - -class EGOrCaymanPat : AMDGPUPat { - let SubtargetPredicate = isEGorCayman; -} - //===----------------------------------------------------------------------===// // Evergreen / Cayman store instructions //===----------------------------------------------------------------------===// -let SubtargetPredicate = isEGorCayman in { +let Predicates = [isEGorCayman] in { class CF_MEM_RAT_CACHELESS rat_inst, bits<4> rat_id, bits<4> mask, dag ins, string name, list pattern> @@ -96,13 +88,13 @@ defm RAT_ATOMIC_INC_UINT : RAT_ATOMIC<18, 50, "ATOMIC_INC_UINT">; defm RAT_ATOMIC_DEC_UINT : RAT_ATOMIC<19, 51, "ATOMIC_DEC_UINT">; -} // End SubtargetPredicate = isEGorCayman +} // End let Predicates = [isEGorCayman] //===----------------------------------------------------------------------===// // Evergreen Only instructions //===----------------------------------------------------------------------===// -let SubtargetPredicate = isEG in { +let Predicates = [isEG] in { def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>; defm DIV_eg : DIV_Common; @@ -124,8 +116,7 @@ def COS_eg : COS_Common<0x8E>; def : POW_Common ; -def : EGPat<(fsqrt f32:$src), (MUL $src, (RECIPSQRT_CLAMPED_eg $src))>; -} // End SubtargetPredicate = isEG +def : Pat<(fsqrt f32:$src), (MUL $src, (RECIPSQRT_CLAMPED_eg $src))>; //===----------------------------------------------------------------------===// // Memory read/write instructions @@ -250,56 +241,58 @@ //===----------------------------------------------------------------------===// // VTX Read from parameter memory space //===----------------------------------------------------------------------===// -def : EGPat<(i32:$dst_gpr (vtx_id3_az_extloadi8 ADDRVTX_READ:$src_gpr)), +def : Pat<(i32:$dst_gpr (vtx_id3_az_extloadi8 ADDRVTX_READ:$src_gpr)), (VTX_READ_8_eg MEMxi:$src_gpr, 3)>; -def : EGPat<(i32:$dst_gpr (vtx_id3_az_extloadi16 ADDRVTX_READ:$src_gpr)), +def : Pat<(i32:$dst_gpr (vtx_id3_az_extloadi16 ADDRVTX_READ:$src_gpr)), (VTX_READ_16_eg MEMxi:$src_gpr, 3)>; -def : EGPat<(i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)), +def : Pat<(i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)), (VTX_READ_32_eg MEMxi:$src_gpr, 3)>; -def : EGPat<(v2i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)), +def : Pat<(v2i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)), (VTX_READ_64_eg MEMxi:$src_gpr, 3)>; -def : EGPat<(v4i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)), +def : Pat<(v4i32:$dst_gpr (vtx_id3_load ADDRVTX_READ:$src_gpr)), (VTX_READ_128_eg MEMxi:$src_gpr, 3)>; //===----------------------------------------------------------------------===// // VTX Read from constant memory space //===----------------------------------------------------------------------===// -def : EGPat<(i32:$dst_gpr (vtx_id2_az_extloadi8 ADDRVTX_READ:$src_gpr)), +def : Pat<(i32:$dst_gpr (vtx_id2_az_extloadi8 ADDRVTX_READ:$src_gpr)), (VTX_READ_8_eg MEMxi:$src_gpr, 2)>; -def : EGPat<(i32:$dst_gpr (vtx_id2_az_extloadi16 ADDRVTX_READ:$src_gpr)), +def : Pat<(i32:$dst_gpr (vtx_id2_az_extloadi16 ADDRVTX_READ:$src_gpr)), (VTX_READ_16_eg MEMxi:$src_gpr, 2)>; -def : EGPat<(i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)), +def : Pat<(i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)), (VTX_READ_32_eg MEMxi:$src_gpr, 2)>; -def : EGPat<(v2i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)), +def : Pat<(v2i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)), (VTX_READ_64_eg MEMxi:$src_gpr, 2)>; -def : EGPat<(v4i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)), +def : Pat<(v4i32:$dst_gpr (vtx_id2_load ADDRVTX_READ:$src_gpr)), (VTX_READ_128_eg MEMxi:$src_gpr, 2)>; //===----------------------------------------------------------------------===// // VTX Read from global memory space //===----------------------------------------------------------------------===// -def : EGPat<(i32:$dst_gpr (vtx_id1_az_extloadi8 ADDRVTX_READ:$src_gpr)), +def : Pat<(i32:$dst_gpr (vtx_id1_az_extloadi8 ADDRVTX_READ:$src_gpr)), (VTX_READ_8_eg MEMxi:$src_gpr, 1)>; -def : EGPat<(i32:$dst_gpr (vtx_id1_az_extloadi16 ADDRVTX_READ:$src_gpr)), +def : Pat<(i32:$dst_gpr (vtx_id1_az_extloadi16 ADDRVTX_READ:$src_gpr)), (VTX_READ_16_eg MEMxi:$src_gpr, 1)>; -def : EGPat<(i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)), +def : Pat<(i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)), (VTX_READ_32_eg MEMxi:$src_gpr, 1)>; -def : EGPat<(v2i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)), +def : Pat<(v2i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)), (VTX_READ_64_eg MEMxi:$src_gpr, 1)>; -def : EGPat<(v4i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)), +def : Pat<(v4i32:$dst_gpr (vtx_id1_load ADDRVTX_READ:$src_gpr)), (VTX_READ_128_eg MEMxi:$src_gpr, 1)>; +} // End Predicates = [isEG] + //===----------------------------------------------------------------------===// // Evergreen / Cayman Instructions //===----------------------------------------------------------------------===// -let SubtargetPredicate = isEGorCayman in { +let Predicates = [isEGorCayman] in { multiclass AtomicPat { // FIXME: Add _RTN version. We need per WI scratch location to store the old value // EXTRACT_SUBREG here is dummy, we know the node has no uses - def : EGOrCaymanPat<(i32 (node_noret i32:$ptr, i32:$data)), + def : Pat<(i32 (node_noret i32:$ptr, i32:$data)), (EXTRACT_SUBREG (inst_noret (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), $data, sub0), $ptr), sub1)>; } @@ -307,7 +300,7 @@ SDPatternOperator node_ret, SDPatternOperator node_noret, int C> { // FIXME: Add _RTN version. We need per WI scratch location to store the old value // EXTRACT_SUBREG here is dummy, we know the node has no uses - def : EGOrCaymanPat<(i32 (node_noret i32:$ptr, C)), + def : Pat<(i32 (node_noret i32:$ptr, C)), (EXTRACT_SUBREG (inst_noret (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), (MOV_IMM_I32 -1), sub0), $ptr), sub1)>; } @@ -315,7 +308,7 @@ // CMPSWAP is pattern is special // EXTRACT_SUBREG here is dummy, we know the node has no uses // FIXME: Add _RTN version. We need per WI scratch location to store the old value -def : EGOrCaymanPat<(i32 (atomic_cmp_swap_global_noret i32:$ptr, i32:$cmp, i32:$data)), +def : Pat<(i32 (atomic_cmp_swap_global_noret i32:$ptr, i32:$cmp, i32:$data)), (EXTRACT_SUBREG (RAT_ATOMIC_CMPXCHG_INT_NORET (INSERT_SUBREG (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), $cmp, sub3), @@ -402,11 +395,11 @@ VecALU >; -def : EGOrCaymanPat<(i32 (sext_inreg i32:$src, i1)), +def : Pat<(i32 (sext_inreg i32:$src, i1)), (BFE_INT_eg i32:$src, (i32 ZERO), (i32 ONE_INT))>; -def : EGOrCaymanPat<(i32 (sext_inreg i32:$src, i8)), +def : Pat<(i32 (sext_inreg i32:$src, i8)), (BFE_INT_eg i32:$src, (i32 ZERO), (MOV_IMM_I32 8))>; -def : EGOrCaymanPat<(i32 (sext_inreg i32:$src, i16)), +def : Pat<(i32 (sext_inreg i32:$src, i16)), (BFE_INT_eg i32:$src, (i32 ZERO), (MOV_IMM_I32 16))>; defm : BFIPatterns ; @@ -688,9 +681,9 @@ // XXX: Lowering SELECT_CC will sometimes generate fp_to_[su]int nodes, // which do not need to be truncated since the fp values are 0.0f or 1.0f. // We should look into handling these cases separately. -def : EGOrCaymanPat<(fp_to_sint f32:$src0), (FLT_TO_INT_eg (TRUNC $src0))>; +def : Pat<(fp_to_sint f32:$src0), (FLT_TO_INT_eg (TRUNC $src0))>; -def : EGOrCaymanPat<(fp_to_uint f32:$src0), (FLT_TO_UINT_eg (TRUNC $src0))>; +def : Pat<(fp_to_uint f32:$src0), (FLT_TO_UINT_eg (TRUNC $src0))>; // SHA-256 Patterns def : SHA256MaPattern ; Index: lib/Target/AMDGPU/FLATInstructions.td =================================================================== --- lib/Target/AMDGPU/FLATInstructions.td +++ lib/Target/AMDGPU/FLATInstructions.td @@ -625,63 +625,63 @@ //===----------------------------------------------------------------------===// // Patterns for global loads with no offset. -class FlatLoadPat : GCNPat < +class FlatLoadPat : Pat < (vt (node (FLATOffset i64:$vaddr, i16:$offset, i1:$slc))), (inst $vaddr, $offset, 0, $slc) >; multiclass FlatLoadPat_Hi16 { - def : GCNPat < + def : Pat < (build_vector vt:$elt0, (vt (node (FLATOffset i64:$vaddr, i16:$offset, i1:$slc)))), (v2i16 (inst $vaddr, $offset, 0, $slc, $elt0)) >; - def : GCNPat < + def : Pat < (build_vector f16:$elt0, (f16 (bitconvert (vt (node (FLATOffset i64:$vaddr, i16:$offset, i1:$slc)))))), (v2f16 (inst $vaddr, $offset, 0, $slc, $elt0)) >; } multiclass FlatSignedLoadPat_Hi16 { - def : GCNPat < + def : Pat < (build_vector vt:$elt0, (vt (node (FLATOffsetSigned i64:$vaddr, i16:$offset, i1:$slc)))), (v2i16 (inst $vaddr, $offset, 0, $slc, $elt0)) >; - def : GCNPat < + def : Pat < (build_vector f16:$elt0, (f16 (bitconvert (vt (node (FLATOffsetSigned i64:$vaddr, i16:$offset, i1:$slc)))))), (v2f16 (inst $vaddr, $offset, 0, $slc, $elt0)) >; } -class FlatLoadAtomicPat : GCNPat < +class FlatLoadAtomicPat : Pat < (vt (node (FLATAtomic i64:$vaddr, i16:$offset, i1:$slc))), (inst $vaddr, $offset, 0, $slc) >; -class FlatLoadSignedPat : GCNPat < +class FlatLoadSignedPat : Pat < (vt (node (FLATOffsetSigned i64:$vaddr, i16:$offset, i1:$slc))), (inst $vaddr, $offset, 0, $slc) >; -class FlatStorePat : GCNPat < +class FlatStorePat : Pat < (node vt:$data, (FLATOffset i64:$vaddr, i16:$offset, i1:$slc)), (inst $vaddr, $data, $offset, 0, $slc) >; -class FlatStoreSignedPat : GCNPat < +class FlatStoreSignedPat : Pat < (node vt:$data, (FLATOffsetSigned i64:$vaddr, i16:$offset, i1:$slc)), (inst $vaddr, $data, $offset, 0, $slc) >; -class FlatStoreAtomicPat : GCNPat < +class FlatStoreAtomicPat : Pat < // atomic store follows atomic binop convention so the address comes // first. (node (FLATAtomic i64:$vaddr, i16:$offset, i1:$slc), vt:$data), (inst $vaddr, $data, $offset, 0, $slc) >; -class FlatStoreSignedAtomicPat : GCNPat < +class FlatStoreSignedAtomicPat : Pat < // atomic store follows atomic binop convention so the address comes // first. (node (FLATSignedAtomic i64:$vaddr, i16:$offset, i1:$slc), vt:$data), @@ -689,18 +689,18 @@ >; class FlatAtomicPat : GCNPat < + ValueType data_vt = vt> : Pat < (vt (node (FLATAtomic i64:$vaddr, i16:$offset, i1:$slc), data_vt:$data)), (inst $vaddr, $data, $offset, $slc) >; class FlatSignedAtomicPat : GCNPat < + ValueType data_vt = vt> : Pat < (vt (node (FLATSignedAtomic i64:$vaddr, i16:$offset, i1:$slc), data_vt:$data)), (inst $vaddr, $data, $offset, $slc) >; -let OtherPredicates = [HasFlatAddressSpace] in { +let Predicates = [HasFlatAddressSpace] in { def : FlatLoadPat ; def : FlatLoadPat ; @@ -756,7 +756,7 @@ def : FlatStorePat ; def : FlatStorePat ; -let OtherPredicates = [HasD16LoadStore] in { + let Predicates = [HasD16LoadStore] in { def : FlatStorePat ; def : FlatStorePat ; @@ -767,9 +767,9 @@ } } -} // End OtherPredicates = [HasFlatAddressSpace] +} // End Predicates = [HasFlatAddressSpace] -let OtherPredicates = [HasFlatGlobalInsts], AddedComplexity = 10 in { +let Predicates = [HasFlatGlobalInsts], AddedComplexity = 10 in { def : FlatLoadSignedPat ; def : FlatLoadSignedPat ; @@ -794,7 +794,7 @@ def : FlatStoreSignedPat ; def : FlatStoreSignedPat ; -let OtherPredicates = [HasD16LoadStore] in { + let Predicates = [HasD16LoadStore] in { def : FlatStoreSignedPat ; def : FlatStoreSignedPat ; @@ -834,7 +834,7 @@ def : FlatSignedAtomicPat ; def : FlatSignedAtomicPat ; -} // End OtherPredicates = [HasFlatGlobalInsts] +} // End Predicates = [HasFlatGlobalInsts] //===----------------------------------------------------------------------===// Index: lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h =================================================================== --- lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h +++ lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h @@ -53,8 +53,6 @@ /// \returns True on success, false on failure. virtual bool EmitCodeObjectMetadata(StringRef YamlString) = 0; - - virtual bool EmitPalMetadata(ArrayRef Data) = 0; }; class AMDGPUTargetAsmStreamer final : public AMDGPUTargetStreamer { @@ -74,8 +72,6 @@ /// \returns True on success, false on failure. bool EmitCodeObjectMetadata(StringRef YamlString) override; - - bool EmitPalMetadata(ArrayRef data) override; }; class AMDGPUTargetELFStreamer final : public AMDGPUTargetStreamer { @@ -103,8 +99,6 @@ /// \returns True on success, false on failure. bool EmitCodeObjectMetadata(StringRef YamlString) override; - - bool EmitPalMetadata(ArrayRef data) override; }; } Index: lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp =================================================================== --- lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp +++ lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp @@ -112,14 +112,6 @@ return true; } -bool AMDGPUTargetAsmStreamer::EmitPalMetadata(ArrayRef Data) { - OS << "\t.amdgpu_pal_metadata"; - for (auto I = Data.begin(), E = Data.end(); I != E; ++I) - OS << (I == Data.begin() ? " 0x" : ",0x") << Twine::utohexstr(*I); - OS << "\n"; - return true; -} - //===----------------------------------------------------------------------===// // AMDGPUTargetELFStreamer //===----------------------------------------------------------------------===// @@ -238,16 +230,3 @@ return true; } - -bool AMDGPUTargetELFStreamer::EmitPalMetadata(ArrayRef Data) { - EmitAMDGPUNote( - MCConstantExpr::create(Data.size() * sizeof(uint32_t), getContext()), - ElfNote::NT_AMDGPU_PAL_METADATA, - [&](MCELFStreamer &OS){ - for (auto I : Data) - OS.EmitIntValue(I, sizeof(uint32_t)); - } - ); - return true; -} - Index: lib/Target/AMDGPU/MIMGInstructions.td =================================================================== --- lib/Target/AMDGPU/MIMGInstructions.td +++ lib/Target/AMDGPU/MIMGInstructions.td @@ -349,7 +349,7 @@ /********** ======================= **********/ // Image + sampler -class SampleRawPattern : GCNPat < +class SampleRawPattern : Pat < (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, i32:$dmask, i32:$unorm, i32:$r128, i32:$da, i32:$glc, i32:$slc, i32:$tfe, i32:$lwe), (opcode $addr, $rsrc, $sampler, @@ -371,7 +371,7 @@ // 2. Handle v4i32 rsrc type (Register Class for the instruction to be SReg_128). // 3. Add A16 support when we pass address of half type. multiclass AMDGCNSamplePattern { - def : GCNPat< + def : Pat< (dt (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, i32:$dmask, i1:$unorm, i1:$glc, i1:$slc, i1:$lwe, i1:$da)), (opcode $addr, $rsrc, $sampler, @@ -396,7 +396,7 @@ } // Image only -class ImagePattern : GCNPat < +class ImagePattern : Pat < (name vt:$addr, v8i32:$rsrc, imm:$dmask, imm:$unorm, imm:$r128, imm:$da, imm:$glc, imm:$slc, imm:$tfe, imm:$lwe), (opcode $addr, $rsrc, @@ -411,7 +411,7 @@ } multiclass ImageLoadPattern { - def : GCNPat < + def : Pat < (dt (name vt:$addr, v8i32:$rsrc, i32:$dmask, i1:$glc, i1:$slc, i1:$lwe, i1:$da)), (opcode $addr, $rsrc, @@ -434,7 +434,7 @@ } multiclass ImageStorePattern { - def : GCNPat < + def : Pat < (name dt:$data, vt:$addr, v8i32:$rsrc, i32:$dmask, i1:$glc, i1:$slc, i1:$lwe, i1:$da), (opcode $data, $addr, $rsrc, @@ -456,7 +456,7 @@ defm : ImageStoreDataPatterns(opcode # _V4), v4f32>; } -class ImageAtomicPattern : GCNPat < +class ImageAtomicPattern : Pat < (name i32:$vdata, vt:$addr, v8i32:$rsrc, imm:$r128, imm:$da, imm:$slc), (opcode $vdata, $addr, $rsrc, 1, 1, 1, (as_i1imm $slc), (as_i1imm $r128), 0, 0, (as_i1imm $da)) >; @@ -467,7 +467,7 @@ def : ImageAtomicPattern(opcode # _V4), v4i32>; } -class ImageAtomicCmpSwapPattern : GCNPat < +class ImageAtomicCmpSwapPattern : Pat < (int_amdgcn_image_atomic_cmpswap i32:$vsrc, i32:$vcmp, vt:$addr, v8i32:$rsrc, imm:$r128, imm:$da, imm:$slc), (EXTRACT_SUBREG @@ -584,34 +584,34 @@ defm : ImageAtomicPatterns; /* SIsample for simple 1D texture lookup */ -def : GCNPat < +def : Pat < (SIsample i32:$addr, v8i32:$rsrc, v4i32:$sampler, imm), (IMAGE_SAMPLE_V4_V1 $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 0) >; -class SamplePattern : GCNPat < +class SamplePattern : Pat < (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, imm), (opcode $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 0) >; -class SampleRectPattern : GCNPat < +class SampleRectPattern : Pat < (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_RECT), (opcode $addr, $rsrc, $sampler, 0xf, 1, 0, 0, 0, 0, 0, 0) >; -class SampleArrayPattern : GCNPat < +class SampleArrayPattern : Pat < (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_ARRAY), (opcode $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 1) >; class SampleShadowPattern : GCNPat < + ValueType vt> : Pat < (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_SHADOW), (opcode $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 0) >; class SampleShadowArrayPattern : GCNPat < + ValueType vt> : Pat < (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_SHADOW_ARRAY), (opcode $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 1) >; Index: lib/Target/AMDGPU/R600InstrFormats.td =================================================================== --- lib/Target/AMDGPU/R600InstrFormats.td +++ lib/Target/AMDGPU/R600InstrFormats.td @@ -11,18 +11,9 @@ // //===----------------------------------------------------------------------===// -def isR600 : Predicate<"Subtarget->getGeneration() <= R600Subtarget::R700">; - -def isR600toCayman : Predicate< - "Subtarget->getGeneration() <= R600Subtarget::NORTHERN_ISLANDS">; - -class R600Pat : AMDGPUPat { - let SubtargetPredicate = isR600toCayman; -} - class InstR600 pattern, - InstrItinClass itin = NoItinerary> - : AMDGPUInst , PredicateControl { + InstrItinClass itin> + : AMDGPUInst { field bits<64> Inst; bit Trig = 0; @@ -40,7 +31,6 @@ bit IsExport = 0; bit LDS_1A2D = 0; - let SubtargetPredicate = isR600toCayman; let Namespace = "AMDGPU"; let OutOperandList = outs; let InOperandList = ins; Index: lib/Target/AMDGPU/R600Instructions.td =================================================================== --- lib/Target/AMDGPU/R600Instructions.td +++ lib/Target/AMDGPU/R600Instructions.td @@ -15,13 +15,6 @@ include "R600Intrinsics.td" include "R600InstrFormats.td" -// FIXME: Should not be arbitrarily split from other R600 inst classes. -class R600WrapperInst pattern = []> : - AMDGPUInst, PredicateControl { - let SubtargetPredicate = isR600toCayman; -} - - class InstR600ISA pattern = []> : InstR600 { @@ -353,6 +346,12 @@ def vtx_id2_az_extloadi16 : LoadVtxId2 ; def vtx_id2_load : LoadVtxId2 ; +def isR600 : Predicate<"Subtarget->getGeneration() <= R600Subtarget::R700">; + +def isR600toCayman + : Predicate< + "Subtarget->getGeneration() <= R600Subtarget::NORTHERN_ISLANDS">; + //===----------------------------------------------------------------------===// // R600 SDNodes //===----------------------------------------------------------------------===// @@ -394,7 +393,7 @@ def TEXTURE_FETCH: SDNode<"AMDGPUISD::TEXTURE_FETCH", TEXTURE_FETCH_Type, []>; multiclass TexPattern TextureOp, Instruction inst, ValueType vt = v4f32> { -def : R600Pat<(TEXTURE_FETCH (i32 TextureOp), vt:$SRC_GPR, +def : Pat<(TEXTURE_FETCH (i32 TextureOp), vt:$SRC_GPR, (i32 imm:$srcx), (i32 imm:$srcy), (i32 imm:$srcz), (i32 imm:$srcw), (i32 imm:$offsetx), (i32 imm:$offsety), (i32 imm:$offsetz), (i32 imm:$DST_SEL_X), (i32 imm:$DST_SEL_Y), (i32 imm:$DST_SEL_Z), @@ -480,7 +479,7 @@ } multiclass ExportPattern cf_inst> { - def : R600Pat<(R600_EXPORT (v4f32 R600_Reg128:$src), (i32 imm:$base), (i32 imm:$type), + def : Pat<(R600_EXPORT (v4f32 R600_Reg128:$src), (i32 imm:$base), (i32 imm:$type), (i32 imm:$swz_x), (i32 imm:$swz_y), (i32 imm:$swz_z), (i32 imm:$swz_w)), (ExportInst R600_Reg128:$src, imm:$type, imm:$base, imm:$swz_x, imm:$swz_y, imm:$swz_z, imm:$swz_w, cf_inst, 0) @@ -491,22 +490,22 @@ multiclass SteamOutputExportPattern buf0inst, bits<8> buf1inst, bits<8> buf2inst, bits<8> buf3inst> { // Stream0 - def : R600Pat<(int_r600_store_stream_output (v4f32 R600_Reg128:$src), + def : Pat<(int_r600_store_stream_output (v4f32 R600_Reg128:$src), (i32 imm:$arraybase), (i32 0), (i32 imm:$mask)), (ExportInst R600_Reg128:$src, 0, imm:$arraybase, 4095, imm:$mask, buf0inst, 0)>; // Stream1 - def : R600Pat<(int_r600_store_stream_output (v4f32 R600_Reg128:$src), + def : Pat<(int_r600_store_stream_output (v4f32 R600_Reg128:$src), (i32 imm:$arraybase), (i32 1), (i32 imm:$mask)), (ExportInst $src, 0, imm:$arraybase, 4095, imm:$mask, buf1inst, 0)>; // Stream2 - def : R600Pat<(int_r600_store_stream_output (v4f32 R600_Reg128:$src), + def : Pat<(int_r600_store_stream_output (v4f32 R600_Reg128:$src), (i32 imm:$arraybase), (i32 2), (i32 imm:$mask)), (ExportInst $src, 0, imm:$arraybase, 4095, imm:$mask, buf2inst, 0)>; // Stream3 - def : R600Pat<(int_r600_store_stream_output (v4f32 R600_Reg128:$src), + def : Pat<(int_r600_store_stream_output (v4f32 R600_Reg128:$src), (i32 imm:$arraybase), (i32 3), (i32 imm:$mask)), (ExportInst $src, 0, imm:$arraybase, 4095, imm:$mask, buf3inst, 0)>; @@ -550,7 +549,7 @@ def KCACHE : InstFlag<"printKCache">; -class ALU_CLAUSE inst, string OpName> : R600WrapperInst <(outs), +class ALU_CLAUSE inst, string OpName> : AMDGPUInst <(outs), (ins i32imm:$ADDR, i32imm:$KCACHE_BANK0, i32imm:$KCACHE_BANK1, KCACHE:$KCACHE_MODE0, KCACHE:$KCACHE_MODE1, i32imm:$KCACHE_ADDR0, i32imm:$KCACHE_ADDR1, @@ -579,7 +578,7 @@ let Word0 = ADDR; } -class CF_CLAUSE_R600 inst, dag ins, string AsmPrint> : R600WrapperInst <(outs), +class CF_CLAUSE_R600 inst, dag ins, string AsmPrint> : AMDGPUInst <(outs), ins, AsmPrint, [] >, CF_WORD0_R600, CF_WORD1_R600 { field bits<64> Inst; bits<4> CNT; @@ -599,7 +598,7 @@ let Inst{63-32} = Word1; } -class CF_CLAUSE_EG inst, dag ins, string AsmPrint> : R600WrapperInst <(outs), +class CF_CLAUSE_EG inst, dag ins, string AsmPrint> : AMDGPUInst <(outs), ins, AsmPrint, [] >, CF_WORD0_EG, CF_WORD1_EG { field bits<64> Inst; @@ -622,7 +621,7 @@ def CF_ALU_BREAK : ALU_CLAUSE<14, "ALU_BREAK">; def CF_ALU_ELSE_AFTER : ALU_CLAUSE<15, "ALU_ELSE_AFTER">; -def FETCH_CLAUSE : R600WrapperInst <(outs), +def FETCH_CLAUSE : AMDGPUInst <(outs), (ins i32imm:$addr), "Fetch clause starting at $addr:", [] > { field bits<8> Inst; bits<8> num; @@ -630,7 +629,7 @@ let isCodeGenOnly = 1; } -def ALU_CLAUSE : R600WrapperInst <(outs), +def ALU_CLAUSE : AMDGPUInst <(outs), (ins i32imm:$addr), "ALU clause starting at $addr:", [] > { field bits<8> Inst; bits<8> num; @@ -638,7 +637,7 @@ let isCodeGenOnly = 1; } -def LITERALS : R600WrapperInst <(outs), +def LITERALS : AMDGPUInst <(outs), (ins LITERAL:$literal1, LITERAL:$literal2), "$literal1, $literal2", [] > { let isCodeGenOnly = 1; @@ -650,10 +649,12 @@ let Inst{63-32} = literal2; } -def PAD : R600WrapperInst <(outs), (ins), "PAD", [] > { +def PAD : AMDGPUInst <(outs), (ins), "PAD", [] > { field bits<64> Inst; } +let Predicates = [isR600toCayman] in { + //===----------------------------------------------------------------------===// // Common Instructions R600, R700, Evergreen, Cayman //===----------------------------------------------------------------------===// @@ -783,7 +784,7 @@ // Most DUMMY_CHAINs should be eliminated during legalization, but undef // values can sneak in some to selection. let isPseudo = 1, isCodeGenOnly = 1 in { -def DUMMY_CHAIN : R600WrapperInst < +def DUMMY_CHAIN : AMDGPUInst < (outs), (ins), "DUMMY_CHAIN", @@ -794,7 +795,7 @@ let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1 in { -class MOV_IMM : R600WrapperInst < +class MOV_IMM : AMDGPUInst < (outs R600_Reg32:$dst), (ins immType:$imm), "", @@ -804,20 +805,20 @@ } // end let isPseudo = 1, isCodeGenOnly = 1, usesCustomInserter = 1 def MOV_IMM_I32 : MOV_IMM; -def : R600Pat < +def : Pat < (imm:$val), (MOV_IMM_I32 imm:$val) >; def MOV_IMM_GLOBAL_ADDR : MOV_IMM; -def : R600Pat < +def : Pat < (AMDGPUconstdata_ptr tglobaladdr:$addr), (MOV_IMM_GLOBAL_ADDR tglobaladdr:$addr) >; def MOV_IMM_F32 : MOV_IMM; -def : R600Pat < +def : Pat < (fpimm:$val), (MOV_IMM_F32 fpimm:$val) >; @@ -1200,7 +1201,7 @@ // FIXME: Should be predicated on unsafe fp math. multiclass DIV_Common { -def : R600Pat< +def : Pat< (fdiv f32:$src0, f32:$src1), (MUL_IEEE $src0, (recip_ieee $src1)) >; @@ -1247,7 +1248,7 @@ defm DIV_r600 : DIV_Common; def : POW_Common ; - def : R600Pat<(fsqrt f32:$src), (MUL $src, (RECIPSQRT_CLAMPED_r600 $src))>; + def : Pat<(fsqrt f32:$src), (MUL $src, (RECIPSQRT_CLAMPED_r600 $src))>; def : RsqPat; def R600_ExportSwz : ExportSwzInst { @@ -1335,11 +1336,11 @@ // Hardcode channel to 0 // NOTE: LSHR is not available here. LSHR is per family instruction -def : R600Pat < +def : Pat < (i32 (load_private ADDRIndirect:$addr) ), (R600_RegisterLoad FRAMEri:$addr, (i32 0)) >; -def : R600Pat < +def : Pat < (store_private i32:$val, ADDRIndirect:$addr), (R600_RegisterStore i32:$val, FRAMEri:$addr, (i32 0)) >; @@ -1690,7 +1691,7 @@ def R600_INSERT_ELT_V4 : InsertVertical ; class ExtractVerticalPat : R600Pat < + ValueType scalar_ty> : Pat < (scalar_ty (extractelt vec_ty:$vec, i32:$index)), (inst $vec, $index) >; @@ -1701,7 +1702,7 @@ def : ExtractVerticalPat ; class InsertVerticalPat : R600Pat < + ValueType scalar_ty> : Pat < (vec_ty (insertelt vec_ty:$vec, scalar_ty:$value, i32:$index)), (inst $vec, $value, $index) >; @@ -1715,11 +1716,9 @@ // ISel Patterns //===----------------------------------------------------------------------===// -let SubtargetPredicate = isR600toCayman in { - // CND*_INT Patterns for f32 True / False values -class CND_INT_f32 : R600Pat < +class CND_INT_f32 : Pat < (selectcc i32:$src0, 0, f32:$src1, f32:$src2, cc), (cnd $src0, $src1, $src2) >; @@ -1729,18 +1728,18 @@ def : CND_INT_f32 ; //CNDGE_INT extra pattern -def : R600Pat < +def : Pat < (selectcc i32:$src0, -1, i32:$src1, i32:$src2, COND_SGT), (CNDGE_INT $src0, $src1, $src2) >; // KIL Patterns -def KILP : R600Pat < +def KILP : Pat < (int_AMDGPU_kilp), (MASK_WRITE (KILLGT (f32 ONE), (f32 ZERO))) >; -def KIL : R600Pat < +def KIL : Pat < (int_AMDGPU_kill f32:$src0), (MASK_WRITE (KILLGT (f32 ZERO), $src0)) >; @@ -1789,7 +1788,7 @@ // DWORDADDR pattern def : DwordAddrPat ; -} // End SubtargetPredicate = isR600toCayman +} // End isR600toCayman Predicate def getLDSNoRetOp : InstrMapping { let FilterClass = "R600_LDS_1A1D"; Index: lib/Target/AMDGPU/SIInsertSkips.cpp =================================================================== --- lib/Target/AMDGPU/SIInsertSkips.cpp +++ lib/Target/AMDGPU/SIInsertSkips.cpp @@ -132,16 +132,6 @@ I->getOpcode() == AMDGPU::S_CBRANCH_VCCZ) return true; - // V_READFIRSTLANE/V_READLANE destination register may be used as operand - // by some SALU instruction. If exec mask is zero vector instruction - // defining the register that is used by the scalar one is not executed - // and scalar instruction will operate on undefined data. For - // V_READFIRSTLANE/V_READLANE we should avoid predicated execution. - if ((I->getOpcode() == AMDGPU::V_READFIRSTLANE_B32) || - (I->getOpcode() == AMDGPU::V_READLANE_B32)) { - return true; - } - if (I->isInlineAsm()) { const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo(); const char *AsmStr = I->getOperand(0).getSymbolName(); Index: lib/Target/AMDGPU/SIInstrFormats.td =================================================================== --- lib/Target/AMDGPU/SIInstrFormats.td +++ lib/Target/AMDGPU/SIInstrFormats.td @@ -11,18 +11,9 @@ // //===----------------------------------------------------------------------===// -def isGCN : Predicate<"Subtarget->getGeneration() " - ">= SISubtarget::SOUTHERN_ISLANDS">, - AssemblerPredicate<"FeatureGCN">; -def isSI : Predicate<"Subtarget->getGeneration() " - "== SISubtarget::SOUTHERN_ISLANDS">, - AssemblerPredicate<"FeatureSouthernIslands">; - - class InstSI pattern = []> : AMDGPUInst, PredicateControl { - let SubtargetPredicate = isGCN; // Low bits - basic encoding information. field bit SALU = 0; Index: lib/Target/AMDGPU/SIInstructions.td =================================================================== --- lib/Target/AMDGPU/SIInstructions.td +++ lib/Target/AMDGPU/SIInstructions.td @@ -11,6 +11,13 @@ // that are not yet supported remain commented out. //===----------------------------------------------------------------------===// +def isGCN : Predicate<"Subtarget->getGeneration() " + ">= SISubtarget::SOUTHERN_ISLANDS">, + AssemblerPredicate<"FeatureGCN">; +def isSI : Predicate<"Subtarget->getGeneration() " + "== SISubtarget::SOUTHERN_ISLANDS">, + AssemblerPredicate<"FeatureSouthernIslands">; + def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">; def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">; def HasVGPRIndexMode : Predicate<"Subtarget->hasVGPRIndexMode()">, @@ -18,17 +25,14 @@ def HasMovrel : Predicate<"Subtarget->hasMovrel()">, AssemblerPredicate<"FeatureMovrel">; -class GCNPat : AMDGPUPat { - let SubtargetPredicate = isGCN; -} - - include "VOPInstructions.td" include "SOPInstructions.td" include "SMInstructions.td" include "FLATInstructions.td" include "BUFInstructions.td" +let SubtargetPredicate = isGCN in { + //===----------------------------------------------------------------------===// // EXP Instructions //===----------------------------------------------------------------------===// @@ -522,27 +526,30 @@ let Defs = [SCC]; } -def : GCNPat < +} // End SubtargetPredicate = isGCN + +let Predicates = [isGCN] in { +def : Pat < (AMDGPUinit_exec i64:$src), (SI_INIT_EXEC (as_i64imm $src)) >; -def : GCNPat < +def : Pat < (AMDGPUinit_exec_from_input i32:$input, i32:$shift), (SI_INIT_EXEC_FROM_INPUT (i32 $input), (as_i32imm $shift)) >; -def : GCNPat< +def : Pat< (AMDGPUtrap timm:$trapid), (S_TRAP $trapid) >; -def : GCNPat< +def : Pat< (AMDGPUelse i64:$src, bb:$target), (SI_ELSE $src, $target, 0) >; -def : GCNPat < +def : Pat < (int_AMDGPU_kilp), (SI_KILL (i32 0xbf800000)) >; @@ -551,7 +558,7 @@ // VOP1 Patterns //===----------------------------------------------------------------------===// -let SubtargetPredicate = isGCN, OtherPredicates = [UnsafeFPMath] in { +let Predicates = [UnsafeFPMath] in { //def : RcpPat; //defm : RsqPat; @@ -561,70 +568,70 @@ def : RsqPat; // Convert (x - floor(x)) to fract(x) -def : GCNPat < +def : Pat < (f32 (fsub (f32 (VOP3Mods f32:$x, i32:$mods)), (f32 (ffloor (f32 (VOP3Mods f32:$x, i32:$mods)))))), (V_FRACT_F32_e64 $mods, $x, DSTCLAMP.NONE, DSTOMOD.NONE) >; // Convert (x + (-floor(x))) to fract(x) -def : GCNPat < +def : Pat < (f64 (fadd (f64 (VOP3Mods f64:$x, i32:$mods)), (f64 (fneg (f64 (ffloor (f64 (VOP3Mods f64:$x, i32:$mods)))))))), (V_FRACT_F64_e64 $mods, $x, DSTCLAMP.NONE, DSTOMOD.NONE) >; -} // End SubtargetPredicate = isGCN, OtherPredicates = [UnsafeFPMath] +} // End Predicates = [UnsafeFPMath] // f16_to_fp patterns -def : GCNPat < +def : Pat < (f32 (f16_to_fp i32:$src0)), (V_CVT_F32_F16_e64 SRCMODS.NONE, $src0, DSTCLAMP.NONE, DSTOMOD.NONE) >; -def : GCNPat < +def : Pat < (f32 (f16_to_fp (and_oneuse i32:$src0, 0x7fff))), (V_CVT_F32_F16_e64 SRCMODS.ABS, $src0, DSTCLAMP.NONE, DSTOMOD.NONE) >; -def : GCNPat < +def : Pat < (f32 (f16_to_fp (or_oneuse i32:$src0, 0x8000))), (V_CVT_F32_F16_e64 SRCMODS.NEG_ABS, $src0, DSTCLAMP.NONE, DSTOMOD.NONE) >; -def : GCNPat < +def : Pat < (f32 (f16_to_fp (xor_oneuse i32:$src0, 0x8000))), (V_CVT_F32_F16_e64 SRCMODS.NEG, $src0, DSTCLAMP.NONE, DSTOMOD.NONE) >; -def : GCNPat < +def : Pat < (f64 (fpextend f16:$src)), (V_CVT_F64_F32_e32 (V_CVT_F32_F16_e32 $src)) >; // fp_to_fp16 patterns -def : GCNPat < +def : Pat < (i32 (AMDGPUfp_to_f16 (f32 (VOP3Mods f32:$src0, i32:$src0_modifiers)))), (V_CVT_F16_F32_e64 $src0_modifiers, f32:$src0, DSTCLAMP.NONE, DSTOMOD.NONE) >; -def : GCNPat < +def : Pat < (i32 (fp_to_sint f16:$src)), (V_CVT_I32_F32_e32 (V_CVT_F32_F16_e32 $src)) >; -def : GCNPat < +def : Pat < (i32 (fp_to_uint f16:$src)), (V_CVT_U32_F32_e32 (V_CVT_F32_F16_e32 $src)) >; -def : GCNPat < +def : Pat < (f16 (sint_to_fp i32:$src)), (V_CVT_F16_F32_e32 (V_CVT_F32_I32_e32 $src)) >; -def : GCNPat < +def : Pat < (f16 (uint_to_fp i32:$src)), (V_CVT_F16_F32_e32 (V_CVT_F32_U32_e32 $src)) >; @@ -634,7 +641,7 @@ //===----------------------------------------------------------------------===// multiclass FMADPat { - def : GCNPat < + def : Pat < (vt (fmad (VOP3NoMods vt:$src0), (VOP3NoMods vt:$src1), (VOP3NoMods vt:$src2))), @@ -646,7 +653,7 @@ defm : FMADPat ; defm : FMADPat ; -class FMADModsPat : GCNPat< +class FMADModsPat : Pat< (f32 (mad_opr (VOP3Mods f32:$src0, i32:$src0_mod), (VOP3Mods f32:$src1, i32:$src1_mod), (VOP3Mods f32:$src2, i32:$src2_mod))), @@ -657,7 +664,7 @@ def : FMADModsPat; multiclass SelectPat { - def : GCNPat < + def : Pat < (vt (select i1:$src0, vt:$src1, vt:$src2)), (inst $src2, $src1, $src0) >; @@ -668,7 +675,7 @@ defm : SelectPat ; defm : SelectPat ; -def : GCNPat < +def : Pat < (i32 (add (i32 (ctpop i32:$popcnt)), i32:$val)), (V_BCNT_U32_B32_e64 $popcnt, $val) >; @@ -741,8 +748,6 @@ >; } -let SubtargetPredicate = isGCN in { - // FIXME: Why do only some of these type combinations for SReg and // VReg? // 16-bit bitcast @@ -803,8 +808,6 @@ def : BitConvert ; def : BitConvert ; -} // End SubtargetPredicate = isGCN - /********** =================== **********/ /********** Src & Dst modifiers **********/ /********** =================== **********/ @@ -812,7 +815,7 @@ // If denormals are not enabled, it only impacts the compare of the // inputs. The output result is not flushed. -class ClampPat : GCNPat < +class ClampPat : Pat < (vt (AMDGPUclamp (VOP3Mods vt:$src0, i32:$src0_modifiers))), (inst i32:$src0_modifiers, vt:$src0, i32:$src0_modifiers, vt:$src0, DSTCLAMP.ENABLE, DSTOMOD.NONE) @@ -822,7 +825,7 @@ def : ClampPat; def : ClampPat; -def : GCNPat < +def : Pat < (v2f16 (AMDGPUclamp (VOP3PMods v2f16:$src0, i32:$src0_modifiers))), (V_PK_MAX_F16 $src0_modifiers, $src0, $src0_modifiers, $src0, DSTCLAMP.ENABLE) @@ -834,13 +837,13 @@ // Prevent expanding both fneg and fabs. -def : GCNPat < +def : Pat < (fneg (fabs f32:$src)), (S_OR_B32 $src, (S_MOV_B32(i32 0x80000000))) // Set sign bit >; // FIXME: Should use S_OR_B32 -def : GCNPat < +def : Pat < (fneg (fabs f64:$src)), (REG_SEQUENCE VReg_64, (i32 (EXTRACT_SUBREG f64:$src, sub0)), @@ -850,17 +853,17 @@ sub1) >; -def : GCNPat < +def : Pat < (fabs f32:$src), (V_AND_B32_e64 $src, (V_MOV_B32_e32 (i32 0x7fffffff))) >; -def : GCNPat < +def : Pat < (fneg f32:$src), (V_XOR_B32_e32 $src, (V_MOV_B32_e32 (i32 0x80000000))) >; -def : GCNPat < +def : Pat < (fabs f64:$src), (REG_SEQUENCE VReg_64, (i32 (EXTRACT_SUBREG f64:$src, sub0)), @@ -870,7 +873,7 @@ sub1) >; -def : GCNPat < +def : Pat < (fneg f64:$src), (REG_SEQUENCE VReg_64, (i32 (EXTRACT_SUBREG f64:$src, sub0)), @@ -880,18 +883,18 @@ sub1) >; -def : GCNPat < +def : Pat < (fcopysign f16:$src0, f16:$src1), (V_BFI_B32 (S_MOV_B32 (i32 0x00007fff)), $src0, $src1) >; -def : GCNPat < +def : Pat < (fcopysign f32:$src0, f16:$src1), (V_BFI_B32 (S_MOV_B32 (i32 0x7fffffff)), $src0, (V_LSHLREV_B32_e64 (i32 16), $src1)) >; -def : GCNPat < +def : Pat < (fcopysign f64:$src0, f16:$src1), (REG_SEQUENCE SReg_64, (i32 (EXTRACT_SUBREG $src0, sub0)), sub0, @@ -899,39 +902,39 @@ (V_LSHLREV_B32_e64 (i32 16), $src1)), sub1) >; -def : GCNPat < +def : Pat < (fcopysign f16:$src0, f32:$src1), (V_BFI_B32 (S_MOV_B32 (i32 0x00007fff)), $src0, (V_LSHRREV_B32_e64 (i32 16), $src1)) >; -def : GCNPat < +def : Pat < (fcopysign f16:$src0, f64:$src1), (V_BFI_B32 (S_MOV_B32 (i32 0x00007fff)), $src0, (V_LSHRREV_B32_e64 (i32 16), (EXTRACT_SUBREG $src1, sub1))) >; -def : GCNPat < +def : Pat < (fneg f16:$src), (V_XOR_B32_e32 $src, (V_MOV_B32_e32 (i32 0x00008000))) >; -def : GCNPat < +def : Pat < (fabs f16:$src), (V_AND_B32_e64 $src, (V_MOV_B32_e32 (i32 0x00007fff))) >; -def : GCNPat < +def : Pat < (fneg (fabs f16:$src)), (S_OR_B32 $src, (S_MOV_B32 (i32 0x00008000))) // Set sign bit >; -def : GCNPat < +def : Pat < (fneg v2f16:$src), (V_XOR_B32_e64 (S_MOV_B32 (i32 0x80008000)), $src) >; -def : GCNPat < +def : Pat < (fabs v2f16:$src), (V_AND_B32_e64 (S_MOV_B32 (i32 0x7fff7fff)), $src) >; @@ -940,7 +943,7 @@ // // fabs is not reported as free because there is modifier for it in // VOP3P instructions, so it is turned into the bit op. -def : GCNPat < +def : Pat < (fneg (v2f16 (bitconvert (and_oneuse i32:$src, 0x7fff7fff)))), (S_OR_B32 (S_MOV_B32 (i32 0x80008000)), $src) // Set sign bit >; @@ -949,17 +952,17 @@ /********** Immediate Patterns **********/ /********** ================== **********/ -def : GCNPat < +def : Pat < (VGPRImm<(i32 imm)>:$imm), (V_MOV_B32_e32 imm:$imm) >; -def : GCNPat < +def : Pat < (VGPRImm<(f32 fpimm)>:$imm), (V_MOV_B32_e32 (f32 (bitcast_fpimm_to_i32 $imm))) >; -def : GCNPat < +def : Pat < (i32 imm:$imm), (S_MOV_B32 imm:$imm) >; @@ -967,27 +970,27 @@ // FIXME: Workaround for ordering issue with peephole optimizer where // a register class copy interferes with immediate folding. Should // use s_mov_b32, which can be shrunk to s_movk_i32 -def : GCNPat < +def : Pat < (VGPRImm<(f16 fpimm)>:$imm), (V_MOV_B32_e32 (f16 (bitcast_fpimm_to_i32 $imm))) >; -def : GCNPat < +def : Pat < (f32 fpimm:$imm), (S_MOV_B32 (f32 (bitcast_fpimm_to_i32 $imm))) >; -def : GCNPat < +def : Pat < (f16 fpimm:$imm), (S_MOV_B32 (i32 (bitcast_fpimm_to_i32 $imm))) >; -def : GCNPat < +def : Pat < (i32 frameindex:$fi), (V_MOV_B32_e32 (i32 (frameindex_to_targetframeindex $fi))) >; -def : GCNPat < +def : Pat < (i64 InlineImm:$imm), (S_MOV_B64 InlineImm:$imm) >; @@ -995,12 +998,12 @@ // XXX - Should this use a s_cmp to set SCC? // Set to sign-extended 64-bit value (true = -1, false = 0) -def : GCNPat < +def : Pat < (i1 imm:$imm), (S_MOV_B64 (i64 (as_i64imm $imm))) >; -def : GCNPat < +def : Pat < (f64 InlineFPImm:$imm), (S_MOV_B64 (f64 (bitcast_fpimm_to_i64 InlineFPImm:$imm))) >; @@ -1009,16 +1012,14 @@ /********** Intrinsic Patterns **********/ /********** ================== **********/ -let SubtargetPredicate = isGCN in { def : POW_Common ; -} -def : GCNPat < +def : Pat < (i32 (sext i1:$src0)), (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src0) >; -class Ext32Pat : GCNPat < +class Ext32Pat : Pat < (i32 (ext i1:$src0)), (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src0) >; @@ -1027,7 +1028,7 @@ def : Ext32Pat ; // The multiplication scales from [0,1] to the unsigned integer range -def : GCNPat < +def : Pat < (AMDGPUurecip i32:$src0), (V_CVT_U32_F32_e32 (V_MUL_F32_e32 (i32 CONST.FP_UINT_MAX_PLUS_1), @@ -1038,21 +1039,17 @@ // VOP3 Patterns //===----------------------------------------------------------------------===// -let SubtargetPredicate = isGCN in { - def : IMad24Pat; def : UMad24Pat; defm : BFIPatterns ; def : ROTRPattern ; -} - -def : GCNPat<(i32 (trunc (srl i64:$src0, (and i32:$src1, (i32 31))))), +def : Pat<(i32 (trunc (srl i64:$src0, (and i32:$src1, (i32 31))))), (V_ALIGNBIT_B32 (i32 (EXTRACT_SUBREG (i64 $src0), sub1)), (i32 (EXTRACT_SUBREG (i64 $src0), sub0)), $src1)>; -def : GCNPat<(i32 (trunc (srl i64:$src0, (i32 ShiftAmt32Imm:$src1)))), +def : Pat<(i32 (trunc (srl i64:$src0, (i32 ShiftAmt32Imm:$src1)))), (V_ALIGNBIT_B32 (i32 (EXTRACT_SUBREG (i64 $src0), sub1)), (i32 (EXTRACT_SUBREG (i64 $src0), sub0)), $src1)>; @@ -1062,13 +1059,13 @@ multiclass SI_INDIRECT_Pattern { // Extract with offset - def : GCNPat< + def : Pat< (eltvt (extractelt vt:$src, (MOVRELOffset i32:$idx, (i32 imm:$offset)))), (!cast("SI_INDIRECT_SRC_"#VecSize) $src, $idx, imm:$offset) >; // Insert with offset - def : GCNPat< + def : Pat< (insertelt vt:$src, eltvt:$val, (MOVRELOffset i32:$idx, (i32 imm:$offset))), (!cast("SI_INDIRECT_DST_"#VecSize) $src, $idx, imm:$offset, $val) >; @@ -1088,14 +1085,14 @@ // SAD Patterns //===----------------------------------------------------------------------===// -def : GCNPat < +def : Pat < (add (sub_oneuse (umax i32:$src0, i32:$src1), (umin i32:$src0, i32:$src1)), i32:$src2), (V_SAD_U32 $src0, $src1, $src2, (i1 0)) >; -def : GCNPat < +def : Pat < (add (select_oneuse (i1 (setugt i32:$src0, i32:$src1)), (sub i32:$src0, i32:$src1), (sub i32:$src1, i32:$src0)), @@ -1107,51 +1104,51 @@ // Conversion Patterns //===----------------------------------------------------------------------===// -def : GCNPat<(i32 (sext_inreg i32:$src, i1)), +def : Pat<(i32 (sext_inreg i32:$src, i1)), (S_BFE_I32 i32:$src, (i32 65536))>; // 0 | 1 << 16 // Handle sext_inreg in i64 -def : GCNPat < +def : Pat < (i64 (sext_inreg i64:$src, i1)), (S_BFE_I64 i64:$src, (i32 0x10000)) // 0 | 1 << 16 >; -def : GCNPat < +def : Pat < (i16 (sext_inreg i16:$src, i1)), (S_BFE_I32 $src, (i32 0x00010000)) // 0 | 1 << 16 >; -def : GCNPat < +def : Pat < (i16 (sext_inreg i16:$src, i8)), (S_BFE_I32 $src, (i32 0x80000)) // 0 | 8 << 16 >; -def : GCNPat < +def : Pat < (i64 (sext_inreg i64:$src, i8)), (S_BFE_I64 i64:$src, (i32 0x80000)) // 0 | 8 << 16 >; -def : GCNPat < +def : Pat < (i64 (sext_inreg i64:$src, i16)), (S_BFE_I64 i64:$src, (i32 0x100000)) // 0 | 16 << 16 >; -def : GCNPat < +def : Pat < (i64 (sext_inreg i64:$src, i32)), (S_BFE_I64 i64:$src, (i32 0x200000)) // 0 | 32 << 16 >; -def : GCNPat < +def : Pat < (i64 (zext i32:$src)), (REG_SEQUENCE SReg_64, $src, sub0, (S_MOV_B32 (i32 0)), sub1) >; -def : GCNPat < +def : Pat < (i64 (anyext i32:$src)), (REG_SEQUENCE SReg_64, $src, sub0, (i32 (IMPLICIT_DEF)), sub1) >; -class ZExt_i64_i1_Pat : GCNPat < +class ZExt_i64_i1_Pat : Pat < (i64 (ext i1:$src)), (REG_SEQUENCE VReg_64, (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src), sub0, @@ -1164,20 +1161,20 @@ // FIXME: We need to use COPY_TO_REGCLASS to work-around the fact that // REG_SEQUENCE patterns don't support instructions with multiple outputs. -def : GCNPat < +def : Pat < (i64 (sext i32:$src)), (REG_SEQUENCE SReg_64, $src, sub0, (i32 (COPY_TO_REGCLASS (S_ASHR_I32 $src, (i32 31)), SReg_32_XM0)), sub1) >; -def : GCNPat < +def : Pat < (i64 (sext i1:$src)), (REG_SEQUENCE VReg_64, (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src), sub0, (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src), sub1) >; -class FPToI1Pat : GCNPat < +class FPToI1Pat : Pat < (i1 (fp_to_int (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)))), (i1 (Inst 0, (kone_type KOne), $src0_modifiers, $src0, DSTCLAMP.NONE)) >; @@ -1193,37 +1190,37 @@ // 64-bit comparisons. When legalizing SGPR copies, instructions // resulting in the copies from SCC to these instructions will be // moved to the VALU. -def : GCNPat < +def : Pat < (i1 (and i1:$src0, i1:$src1)), (S_AND_B64 $src0, $src1) >; -def : GCNPat < +def : Pat < (i1 (or i1:$src0, i1:$src1)), (S_OR_B64 $src0, $src1) >; -def : GCNPat < +def : Pat < (i1 (xor i1:$src0, i1:$src1)), (S_XOR_B64 $src0, $src1) >; -def : GCNPat < +def : Pat < (f32 (sint_to_fp i1:$src)), (V_CNDMASK_B32_e64 (i32 0), (i32 CONST.FP32_NEG_ONE), $src) >; -def : GCNPat < +def : Pat < (f32 (uint_to_fp i1:$src)), (V_CNDMASK_B32_e64 (i32 0), (i32 CONST.FP32_ONE), $src) >; -def : GCNPat < +def : Pat < (f64 (sint_to_fp i1:$src)), (V_CVT_F64_I32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src)) >; -def : GCNPat < +def : Pat < (f64 (uint_to_fp i1:$src)), (V_CVT_F64_U32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src)) >; @@ -1231,87 +1228,103 @@ //===----------------------------------------------------------------------===// // Miscellaneous Patterns //===----------------------------------------------------------------------===// -def : GCNPat < +def : Pat < (i32 (AMDGPUfp16_zext f16:$src)), (COPY $src) >; -def : GCNPat < +def : Pat < (i32 (trunc i64:$a)), (EXTRACT_SUBREG $a, sub0) >; -def : GCNPat < +def : Pat < (i1 (trunc i32:$a)), (V_CMP_EQ_U32_e64 (S_AND_B32 (i32 1), $a), (i32 1)) >; -def : GCNPat < +def : Pat < (i1 (trunc i16:$a)), (V_CMP_EQ_U32_e64 (S_AND_B32 (i32 1), $a), (i32 1)) >; -def : GCNPat < +def : Pat < (i1 (trunc i64:$a)), (V_CMP_EQ_U32_e64 (S_AND_B32 (i32 1), (i32 (EXTRACT_SUBREG $a, sub0))), (i32 1)) >; -def : GCNPat < +def : Pat < (i32 (bswap i32:$a)), (V_BFI_B32 (S_MOV_B32 (i32 0x00ff00ff)), (V_ALIGNBIT_B32 $a, $a, (i32 24)), (V_ALIGNBIT_B32 $a, $a, (i32 8))) >; -let OtherPredicates = [NoFP16Denormals] in { -def : GCNPat< +multiclass BFMPatterns { + def : Pat < + (vt (shl (vt (add (vt (shl 1, vt:$a)), -1)), vt:$b)), + (BFM $a, $b) + >; + + def : Pat < + (vt (add (vt (shl 1, vt:$a)), -1)), + (BFM $a, (MOV (i32 0))) + >; +} + +defm : BFMPatterns ; +// FIXME: defm : BFMPatterns ; +defm : BFEPattern ; + +let Predicates = [NoFP16Denormals] in { +def : Pat< (fcanonicalize (f16 (VOP3Mods f16:$src, i32:$src_mods))), (V_MUL_F16_e64 0, (i32 CONST.FP16_ONE), $src_mods, $src, 0, 0) >; -def : GCNPat< +def : Pat< (fcanonicalize (v2f16 (VOP3PMods v2f16:$src, i32:$src_mods))), (V_PK_MUL_F16 0, (i32 CONST.V2FP16_ONE), $src_mods, $src, DSTCLAMP.NONE) >; } -let OtherPredicates = [FP16Denormals] in { -def : GCNPat< +let Predicates = [FP16Denormals] in { +def : Pat< (fcanonicalize (f16 (VOP3Mods f16:$src, i32:$src_mods))), (V_MAX_F16_e64 $src_mods, $src, $src_mods, $src, 0, 0) >; -def : GCNPat< +def : Pat< (fcanonicalize (v2f16 (VOP3PMods v2f16:$src, i32:$src_mods))), (V_PK_MAX_F16 $src_mods, $src, $src_mods, $src, DSTCLAMP.NONE) >; } -let OtherPredicates = [NoFP32Denormals] in { -def : GCNPat< +let Predicates = [NoFP32Denormals] in { +def : Pat< (fcanonicalize (f32 (VOP3Mods f32:$src, i32:$src_mods))), (V_MUL_F32_e64 0, (i32 CONST.FP32_ONE), $src_mods, $src, 0, 0) >; } -let OtherPredicates = [FP32Denormals] in { -def : GCNPat< +let Predicates = [FP32Denormals] in { +def : Pat< (fcanonicalize (f32 (VOP3Mods f32:$src, i32:$src_mods))), (V_MAX_F32_e64 $src_mods, $src, $src_mods, $src, 0, 0) >; } -let OtherPredicates = [NoFP64Denormals] in { -def : GCNPat< +let Predicates = [NoFP64Denormals] in { +def : Pat< (fcanonicalize (f64 (VOP3Mods f64:$src, i32:$src_mods))), (V_MUL_F64 0, CONST.FP64_ONE, $src_mods, $src, 0, 0) >; } -let OtherPredicates = [FP64Denormals] in { -def : GCNPat< +let Predicates = [FP64Denormals] in { +def : Pat< (fcanonicalize (f64 (VOP3Mods f64:$src, i32:$src_mods))), (V_MAX_F64 $src_mods, $src, $src_mods, $src, 0, 0) >; @@ -1319,7 +1332,7 @@ // Allow integer inputs -class ExpPattern : GCNPat< +class ExpPattern : Pat< (node (i8 timm:$tgt), (i8 timm:$en), vt:$src0, vt:$src1, vt:$src2, vt:$src3, (i1 timm:$compr), (i1 timm:$vm)), (Inst i8:$tgt, vt:$src0, vt:$src1, vt:$src2, vt:$src3, i1:$vm, i1:$compr, i8:$en) >; @@ -1327,43 +1340,43 @@ def : ExpPattern; def : ExpPattern; -def : GCNPat < +def : Pat < (v2i16 (build_vector i16:$src0, i16:$src1)), (v2i16 (S_PACK_LL_B32_B16 $src0, $src1)) >; // COPY_TO_REGCLASS is workaround tablegen bug from multiple outputs // from S_LSHL_B32's multiple outputs from implicit scc def. -def : GCNPat < +def : Pat < (v2i16 (build_vector (i16 0), i16:$src1)), (v2i16 (COPY_TO_REGCLASS (S_LSHL_B32 i16:$src1, (i16 16)), SReg_32_XM0)) >; // With multiple uses of the shift, this will duplicate the shift and // increase register pressure. -def : GCNPat < +def : Pat < (v2i16 (build_vector i16:$src0, (i16 (trunc (srl_oneuse i32:$src1, (i32 16)))))), (v2i16 (S_PACK_LH_B32_B16 i16:$src0, i32:$src1)) >; -def : GCNPat < +def : Pat < (v2i16 (build_vector (i16 (trunc (srl_oneuse i32:$src0, (i32 16)))), (i16 (trunc (srl_oneuse i32:$src1, (i32 16)))))), (v2i16 (S_PACK_HH_B32_B16 $src0, $src1)) >; // TODO: Should source modifiers be matched to v_pack_b32_f16? -def : GCNPat < +def : Pat < (v2f16 (build_vector f16:$src0, f16:$src1)), (v2f16 (S_PACK_LL_B32_B16 $src0, $src1)) >; -// def : GCNPat < +// def : Pat < // (v2f16 (scalar_to_vector f16:$src0)), // (COPY $src0) // >; -// def : GCNPat < +// def : Pat < // (v2i16 (scalar_to_vector i16:$src0)), // (COPY $src0) // >; @@ -1372,7 +1385,7 @@ // Fract Patterns //===----------------------------------------------------------------------===// -let SubtargetPredicate = isSI in { +let Predicates = [isSI] in { // V_FRACT is buggy on SI, so the F32 version is never used and (x-floor(x)) is // used instead. However, SI doesn't have V_FLOOR_F64, so the most efficient @@ -1381,7 +1394,7 @@ // fract(x) = isnan(x) ? x : min(V_FRACT(x), 0.99999999999999999) // Convert floor(x) to (x - fract(x)) -def : GCNPat < +def : Pat < (f64 (ffloor (f64 (VOP3Mods f64:$x, i32:$mods)))), (V_ADD_F64 $mods, @@ -1399,7 +1412,7 @@ DSTCLAMP.NONE, DSTOMOD.NONE) >; -} // End SubtargetPredicates = isSI +} // End Predicates = [isSI] //============================================================================// // Miscellaneous Optimization Patterns @@ -1408,41 +1421,20 @@ // Undo sub x, c -> add x, -c canonicalization since c is more likely // an inline immediate than -c. // TODO: Also do for 64-bit. -def : GCNPat< +def : Pat< (add i32:$src0, (i32 NegSubInlineConst32:$src1)), (S_SUB_I32 $src0, NegSubInlineConst32:$src1) >; - -multiclass BFMPatterns { - def : GCNPat < - (vt (shl (vt (add (vt (shl 1, vt:$a)), -1)), vt:$b)), - (BFM $a, $b) - >; - - def : GCNPat < - (vt (add (vt (shl 1, vt:$a)), -1)), - (BFM $a, (MOV (i32 0))) - >; -} - -let SubtargetPredicate = isGCN in { - -defm : BFMPatterns ; -// FIXME: defm : BFMPatterns ; - -defm : BFEPattern ; def : SHA256MaPattern ; def : IntMed3Pat; def : IntMed3Pat; -} - // This matches 16 permutations of // max(min(x, y), min(max(x, y), z)) class FPMed3Pat : GCNPat< + Instruction med3Inst> : Pat< (fmaxnum (fminnum_oneuse (VOP3Mods_nnan vt:$src0, i32:$src0_mods), (VOP3Mods_nnan vt:$src1, i32:$src1_mods)), (fminnum_oneuse (fmaxnum_oneuse (VOP3Mods_nnan vt:$src0, i32:$src0_mods), @@ -1452,7 +1444,7 @@ >; class FP16Med3Pat : GCNPat< + Instruction med3Inst> : Pat< (fmaxnum (fminnum_oneuse (VOP3Mods_nnan vt:$src0, i32:$src0_mods), (VOP3Mods_nnan vt:$src1, i32:$src1_mods)), (fminnum_oneuse (fmaxnum_oneuse (VOP3Mods_nnan vt:$src0, i32:$src0_mods), @@ -1465,7 +1457,7 @@ SDPatternOperator max, SDPatternOperator max_oneuse, SDPatternOperator min_oneuse, - ValueType vt = i32> : GCNPat< + ValueType vt = i32> : Pat< (max (min_oneuse vt:$src0, vt:$src1), (min_oneuse (max_oneuse vt:$src0, vt:$src1), vt:$src2)), (med3Inst SRCMODS.NONE, $src0, SRCMODS.NONE, $src1, SRCMODS.NONE, $src2, DSTCLAMP.NONE) @@ -1473,7 +1465,7 @@ def : FPMed3Pat; -let OtherPredicates = [isGFX9] in { +let Predicates = [isGFX9] in { def : FP16Med3Pat; def : Int16Med3Pat; def : Int16Med3Pat; @@ -1506,7 +1498,6 @@ // gfx9 made a mess of add instruction names. The existing add // instructions add _co added to the names, and their old names were // repurposed to a version without carry out. -// TODO: Do we need SubtargetPredicates for MnemonicAliases? let Predicates = [HasAddNoCarryInsts] in { defm : NoCarryAlias<"v_add_u32", V_ADD_U32_e32_vi, V_ADD_U32_e64_vi, V_ADD_I32_e32_vi, V_ADD_I32_e64_vi>; @@ -1522,3 +1513,5 @@ def : MnemonicAlias<"v_sub_u32", "v_sub_i32">; def : MnemonicAlias<"v_subrev_u32", "v_subrev_i32">; } + +} // End isGCN predicate Index: lib/Target/AMDGPU/SMInstructions.td =================================================================== --- lib/Target/AMDGPU/SMInstructions.td +++ lib/Target/AMDGPU/SMInstructions.td @@ -241,23 +241,25 @@ def SMRDBufferImm32 : ComplexPattern; def SMRDBufferSgpr : ComplexPattern; +let Predicates = [isGCN] in { + multiclass SMRD_Pattern { // 1. IMM offset - def : GCNPat < + def : Pat < (smrd_load (SMRDImm i64:$sbase, i32:$offset)), (vt (!cast(Instr#"_IMM") $sbase, $offset, 0)) >; // 2. SGPR offset - def : GCNPat < + def : Pat < (smrd_load (SMRDSgpr i64:$sbase, i32:$offset)), (vt (!cast(Instr#"_SGPR") $sbase, $offset, 0)) >; } -let OtherPredicates = [isSICI] in { -def : GCNPat < +let Predicates = [isSICI] in { +def : Pat < (i64 (readcyclecounter)), (S_MEMTIME) >; @@ -275,27 +277,29 @@ defm : SMRD_Pattern <"S_LOAD_DWORDX16", v16i32>; // 1. Offset as an immediate -def SM_LOAD_PATTERN : GCNPat < // name this pattern to reuse AddedComplexity on CI +def SM_LOAD_PATTERN : Pat < // name this pattern to reuse AddedComplexity on CI (SIload_constant v4i32:$sbase, (SMRDBufferImm i32:$offset)), (S_BUFFER_LOAD_DWORD_IMM $sbase, $offset, 0) >; // 2. Offset loaded in an 32bit SGPR -def : GCNPat < +def : Pat < (SIload_constant v4i32:$sbase, (SMRDBufferSgpr i32:$offset)), (S_BUFFER_LOAD_DWORD_SGPR $sbase, $offset, 0) >; } // End let AddedComplexity = 100 -let OtherPredicates = [isVI] in { +} // let Predicates = [isGCN] + +let Predicates = [isVI] in { -def : GCNPat < +def : Pat < (i64 (readcyclecounter)), (S_MEMREALTIME) >; -} // let OtherPredicates = [isVI] +} // let Predicates = [isVI] //===----------------------------------------------------------------------===// @@ -504,10 +508,10 @@ let AddedComplexity = SM_LOAD_PATTERN.AddedComplexity in { -class SMRD_Pattern_ci : GCNPat < +class SMRD_Pattern_ci : Pat < (smrd_load (SMRDImm32 i64:$sbase, i32:$offset)), (vt (!cast(Instr#"_IMM_ci") $sbase, $offset, 0))> { - let OtherPredicates = [isCIOnly]; + let Predicates = [isCIOnly]; } def : SMRD_Pattern_ci <"S_LOAD_DWORD", i32>; @@ -516,10 +520,10 @@ def : SMRD_Pattern_ci <"S_LOAD_DWORDX8", v8i32>; def : SMRD_Pattern_ci <"S_LOAD_DWORDX16", v16i32>; -def : GCNPat < +def : Pat < (SIload_constant v4i32:$sbase, (SMRDBufferImm32 i32:$offset)), (S_BUFFER_LOAD_DWORD_IMM_ci $sbase, $offset, 0)> { - let OtherPredicates = [isCI]; // should this be isCIOnly? + let Predicates = [isCI]; // should this be isCIOnly? } } // End let AddedComplexity = SM_LOAD_PATTERN.AddedComplexity Index: lib/Target/AMDGPU/SOPInstructions.td =================================================================== --- lib/Target/AMDGPU/SOPInstructions.td +++ lib/Target/AMDGPU/SOPInstructions.td @@ -948,10 +948,12 @@ } } +let Predicates = [isGCN] in { + //===----------------------------------------------------------------------===// // S_GETREG_B32 Intrinsic Pattern. //===----------------------------------------------------------------------===// -def : GCNPat < +def : Pat < (int_amdgcn_s_getreg imm:$simm16), (S_GETREG_B32 (as_i16imm $simm16)) >; @@ -960,25 +962,25 @@ // SOP1 Patterns //===----------------------------------------------------------------------===// -def : GCNPat < +def : Pat < (i64 (ctpop i64:$src)), (i64 (REG_SEQUENCE SReg_64, (i32 (COPY_TO_REGCLASS (S_BCNT1_I32_B64 $src), SReg_32)), sub0, (S_MOV_B32 (i32 0)), sub1)) >; -def : GCNPat < +def : Pat < (i32 (smax i32:$x, (i32 (ineg i32:$x)))), (S_ABS_I32 $x) >; -def : GCNPat < +def : Pat < (i16 imm:$imm), (S_MOV_B32 imm:$imm) >; // Same as a 32-bit inreg -def : GCNPat< +def : Pat< (i32 (sext i16:$src)), (S_SEXT_I32_I16 $src) >; @@ -990,7 +992,7 @@ // V_ADD_I32_e32/S_ADD_U32 produces carry in VCC/SCC. For the vector // case, the sgpr-copies pass will fix this to use the vector version. -def : GCNPat < +def : Pat < (i32 (addc i32:$src0, i32:$src1)), (S_ADD_U32 $src0, $src1) >; @@ -998,20 +1000,20 @@ // FIXME: We need to use COPY_TO_REGCLASS to work-around the fact that // REG_SEQUENCE patterns don't support instructions with multiple // outputs. -def : GCNPat< +def : Pat< (i64 (zext i16:$src)), (REG_SEQUENCE SReg_64, (i32 (COPY_TO_REGCLASS (S_AND_B32 $src, (S_MOV_B32 (i32 0xffff))), SGPR_32)), sub0, (S_MOV_B32 (i32 0)), sub1) >; -def : GCNPat < +def : Pat < (i64 (sext i16:$src)), (REG_SEQUENCE SReg_64, (i32 (S_SEXT_I32_I16 $src)), sub0, (i32 (COPY_TO_REGCLASS (S_ASHR_I32 (i32 (S_SEXT_I32_I16 $src)), (S_MOV_B32 (i32 31))), SGPR_32)), sub1) >; -def : GCNPat< +def : Pat< (i32 (zext i16:$src)), (S_AND_B32 (S_MOV_B32 (i32 0xffff)), $src) >; @@ -1022,11 +1024,13 @@ // SOPP Patterns //===----------------------------------------------------------------------===// -def : GCNPat < +def : Pat < (int_amdgcn_s_waitcnt i32:$simm16), (S_WAITCNT (as_i16imm $simm16)) >; +} // End isGCN predicate + //===----------------------------------------------------------------------===// // Real target instructions, move this to the appropriate subtarget TD file Index: lib/Target/AMDGPU/VOP1Instructions.td =================================================================== --- lib/Target/AMDGPU/VOP1Instructions.td +++ lib/Target/AMDGPU/VOP1Instructions.td @@ -361,14 +361,14 @@ } -let OtherPredicates = [Has16BitInsts] in { +let Predicates = [Has16BitInsts] in { -def : GCNPat< +def : Pat< (f32 (f16_to_fp i16:$src)), (V_CVT_F32_F16_e32 $src) >; -def : GCNPat< +def : Pat< (i16 (AMDGPUfp_to_f16 f32:$src)), (V_CVT_F16_F32_e32 $src) >; @@ -653,9 +653,9 @@ def V_MOVRELD_B32_V8 : V_MOVRELD_B32_pseudo; def V_MOVRELD_B32_V16 : V_MOVRELD_B32_pseudo; -let OtherPredicates = [isVI] in { +let Predicates = [isVI] in { -def : GCNPat < +def : Pat < (i32 (int_amdgcn_mov_dpp i32:$src, imm:$dpp_ctrl, imm:$row_mask, imm:$bank_mask, imm:$bound_ctrl)), (V_MOV_B32_dpp $src, $src, (as_i32imm $dpp_ctrl), @@ -663,7 +663,7 @@ (as_i1imm $bound_ctrl)) >; -def : GCNPat < +def : Pat < (i32 (int_amdgcn_update_dpp i32:$old, i32:$src, imm:$dpp_ctrl, imm:$row_mask, imm:$bank_mask, imm:$bound_ctrl)), (V_MOV_B32_dpp $old, $src, (as_i32imm $dpp_ctrl), @@ -671,26 +671,26 @@ (as_i1imm $bound_ctrl)) >; -def : GCNPat< +def : Pat< (i32 (anyext i16:$src)), (COPY $src) >; -def : GCNPat< +def : Pat< (i64 (anyext i16:$src)), (REG_SEQUENCE VReg_64, (i32 (COPY $src)), sub0, (V_MOV_B32_e32 (i32 0)), sub1) >; -def : GCNPat< +def : Pat< (i16 (trunc i32:$src)), (COPY $src) >; -def : GCNPat < +def : Pat < (i16 (trunc i64:$src)), (EXTRACT_SUBREG $src, sub0) >; -} // End OtherPredicates = [isVI] +} // End Predicates = [isVI] Index: lib/Target/AMDGPU/VOP2Instructions.td =================================================================== --- lib/Target/AMDGPU/VOP2Instructions.td +++ lib/Target/AMDGPU/VOP2Instructions.td @@ -408,12 +408,12 @@ } // End SubtargetPredicate = isGCN -def : GCNPat< +def : Pat< (AMDGPUadde i32:$src0, i32:$src1, i1:$src2), (V_ADDC_U32_e64 $src0, $src1, $src2) >; -def : GCNPat< +def : Pat< (AMDGPUsube i32:$src0, i32:$src1, i1:$src2), (V_SUBB_U32_e64 $src0, $src1, $src2) >; @@ -469,17 +469,17 @@ // Note: 16-bit instructions produce a 0 result in the high 16-bits. multiclass Arithmetic_i16_Pats { -def : GCNPat< +def : Pat< (op i16:$src0, i16:$src1), (inst $src0, $src1) >; -def : GCNPat< +def : Pat< (i32 (zext (op i16:$src0, i16:$src1))), (inst $src0, $src1) >; -def : GCNPat< +def : Pat< (i64 (zext (op i16:$src0, i16:$src1))), (REG_SEQUENCE VReg_64, (inst $src0, $src1), sub0, @@ -490,18 +490,18 @@ multiclass Bits_OpsRev_i16_Pats { -def : GCNPat< +def : Pat< (op i16:$src0, i16:$src1), (inst $src1, $src0) >; -def : GCNPat< +def : Pat< (i32 (zext (op i16:$src0, i16:$src1))), (inst $src1, $src0) >; -def : GCNPat< +def : Pat< (i64 (zext (op i16:$src0, i16:$src1))), (REG_SEQUENCE VReg_64, (inst $src1, $src0), sub0, @@ -509,7 +509,7 @@ >; } -class ZExt_i16_i1_Pat : GCNPat < +class ZExt_i16_i1_Pat : Pat < (i16 (ext i1:$src)), (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src) >; @@ -524,17 +524,17 @@ defm : Arithmetic_i16_Pats; defm : Arithmetic_i16_Pats; -def : GCNPat < +def : Pat < (and i16:$src0, i16:$src1), (V_AND_B32_e64 $src0, $src1) >; -def : GCNPat < +def : Pat < (or i16:$src0, i16:$src1), (V_OR_B32_e64 $src0, $src1) >; -def : GCNPat < +def : Pat < (xor i16:$src0, i16:$src1), (V_XOR_B32_e64 $src0, $src1) >; @@ -546,7 +546,7 @@ def : ZExt_i16_i1_Pat; def : ZExt_i16_i1_Pat; -def : GCNPat < +def : Pat < (i16 (sext i1:$src)), (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src) >; @@ -554,7 +554,7 @@ // Undo sub x, c -> add x, -c canonicalization since c is more likely // an inline immediate than -c. // TODO: Also do for 64-bit. -def : GCNPat< +def : Pat< (add i16:$src0, (i16 NegSubInlineConst16:$src1)), (V_SUB_U16_e64 $src0, NegSubInlineConst16:$src1) >; Index: lib/Target/AMDGPU/VOP3Instructions.td =================================================================== --- lib/Target/AMDGPU/VOP3Instructions.td +++ lib/Target/AMDGPU/VOP3Instructions.td @@ -450,17 +450,17 @@ multiclass Ternary_i16_Pats { -def : GCNPat < +def : Pat< (op2 (op1 i16:$src0, i16:$src1), i16:$src2), (inst i16:$src0, i16:$src1, i16:$src2, (i1 0)) >; -def : GCNPat< +def : Pat< (i32 (op3 (op2 (op1 i16:$src0, i16:$src1), i16:$src2))), (inst i16:$src0, i16:$src1, i16:$src2, (i1 0)) >; -def : GCNPat< +def : Pat< (i64 (op3 (op2 (op1 i16:$src0, i16:$src1), i16:$src2))), (REG_SEQUENCE VReg_64, (inst i16:$src0, i16:$src1, i16:$src2, (i1 0)), sub0, @@ -528,7 +528,7 @@ ret1)); } -class IntClampPat : GCNPat< +class IntClampPat : Pat< getClampPat.ret, getClampRes.ret >; Index: lib/Target/AMDGPU/VOP3PInstructions.td =================================================================== --- lib/Target/AMDGPU/VOP3PInstructions.td +++ lib/Target/AMDGPU/VOP3PInstructions.td @@ -82,9 +82,9 @@ } } -let OtherPredicates = [HasMadMix] in { +let Predicates = [HasMadMix] in { -def : GCNPat < +def : Pat < (f16 (fpround (fmad (f32 (VOP3PMadMixMods f16:$src0, i32:$src0_modifiers)), (f32 (VOP3PMadMixMods f16:$src1, i32:$src1_modifiers)), (f32 (VOP3PMadMixMods f16:$src2, i32:$src2_modifiers))))), @@ -98,7 +98,7 @@ // FIXME: Special case handling for maxhi (especially for clamp) // because dealing with the write to high half of the register is // difficult. -def : GCNPat < +def : Pat < (build_vector f16:$elt0, (fpround (fmad (f32 (VOP3PMadMixMods f16:$src0, i32:$src0_modifiers)), (f32 (VOP3PMadMixMods f16:$src1, i32:$src1_modifiers)), (f32 (VOP3PMadMixMods f16:$src2, i32:$src2_modifiers))))), @@ -109,7 +109,7 @@ $elt0)) >; -def : GCNPat < +def : Pat < (build_vector f16:$elt0, (AMDGPUclamp (fpround (fmad (f32 (VOP3PMadMixMods f16:$src0, i32:$src0_modifiers)), @@ -122,7 +122,7 @@ $elt0)) >; -def : GCNPat < +def : Pat < (AMDGPUclamp (build_vector (fpround (fmad (f32 (VOP3PMadMixMods f16:$lo_src0, i32:$lo_src0_modifiers)), (f32 (VOP3PMadMixMods f16:$lo_src1, i32:$lo_src1_modifiers)), Index: lib/Target/AMDGPU/VOPCInstructions.td =================================================================== --- lib/Target/AMDGPU/VOPCInstructions.td +++ lib/Target/AMDGPU/VOPCInstructions.td @@ -607,7 +607,9 @@ // V_ICMPIntrinsic Pattern. //===----------------------------------------------------------------------===// -class ICMP_Pattern : GCNPat < +let Predicates = [isGCN] in { + +class ICMP_Pattern : Pat < (AMDGPUsetcc vt:$src0, vt:$src1, cond), (inst $src0, $src1) >; @@ -634,7 +636,7 @@ def : ICMP_Pattern ; def : ICMP_Pattern ; -class FCMP_Pattern : GCNPat < +class FCMP_Pattern : Pat < (i64 (AMDGPUsetcc (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)), (vt (VOP3Mods vt:$src1, i32:$src1_modifiers)), cond)), (inst $src0_modifiers, $src0, $src1_modifiers, $src1, @@ -669,6 +671,8 @@ def : FCMP_Pattern ; def : FCMP_Pattern ; +} // End Predicates = [isGCN] + //===----------------------------------------------------------------------===// // Target //===----------------------------------------------------------------------===// Index: lib/Target/ARM/ARM.td =================================================================== --- lib/Target/ARM/ARM.td +++ lib/Target/ARM/ARM.td @@ -1022,10 +1022,6 @@ bit isMCAsmWriter = 1; } -def ARMAsmParser : AsmParser { - bit ReportMultipleNearMisses = 1; -} - def ARMAsmParserVariant : AsmParserVariant { int Variant = 0; string Name = "ARM"; @@ -1036,6 +1032,5 @@ // Pull in Instruction Info. let InstructionSet = ARMInstrInfo; let AssemblyWriters = [ARMAsmWriter]; - let AssemblyParsers = [ARMAsmParser]; let AssemblyParserVariants = [ARMAsmParserVariant]; } Index: lib/Target/ARM/ARMISelLowering.cpp =================================================================== --- lib/Target/ARM/ARMISelLowering.cpp +++ lib/Target/ARM/ARMISelLowering.cpp @@ -7781,7 +7781,6 @@ } SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { - DEBUG(dbgs() << "Lowering node: "; Op.dump()); switch (Op.getOpcode()) { default: llvm_unreachable("Don't know how to custom lower this!"); case ISD::WRITE_REGISTER: return LowerWRITE_REGISTER(Op, DAG); Index: lib/Target/ARM/ARMInstrFormats.td =================================================================== --- lib/Target/ARM/ARMInstrFormats.td +++ lib/Target/ARM/ARMInstrFormats.td @@ -2573,18 +2573,18 @@ } // Operand types for complex instructions -class ComplexRotationOperand +class ComplexRotationOperand : AsmOperandClass { let PredicateMethod = "isComplexRotation<" # Angle # ", " # Remainder # ">"; - let DiagnosticString = "complex rotation must be " # Diag; + let DiagnosticType = "InvalidComplexRotation" # Type; let Name = "ComplexRotation" # Type; } def complexrotateop : Operand { - let ParserMatchClass = ComplexRotationOperand<90, 0, "Even", "0, 90, 180 or 270">; + let ParserMatchClass = ComplexRotationOperand<90, 0, "Even">; let PrintMethod = "printComplexRotationOp<90, 0>"; } def complexrotateopodd : Operand { - let ParserMatchClass = ComplexRotationOperand<180, 90, "Odd", "90 or 270">; + let ParserMatchClass = ComplexRotationOperand<180, 90, "Odd">; let PrintMethod = "printComplexRotationOp<180, 90>"; } Index: lib/Target/ARM/ARMInstrInfo.td =================================================================== --- lib/Target/ARM/ARMInstrInfo.td +++ lib/Target/ARM/ARMInstrInfo.td @@ -460,13 +460,12 @@ class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; let PredicateMethod = "isImmediate<" # Low # "," # High # ">"; - let DiagnosticString = "immediate operand must be in the range [" # Low # "," # High # "]"; + let DiagnosticType = "ImmRange" # Low # "_" # High; } class ImmAsmOperandMinusOne : AsmOperandClass { let PredicateMethod = "isImmediate<" # Low # "," # High # ">"; let DiagnosticType = "ImmRange" # Low # "_" # High; - let DiagnosticString = "immediate operand must be in the range [" # Low # "," # High # "]"; } // Operands that are part of a memory addressing mode. @@ -755,6 +754,7 @@ /// imm0_15 predicate - Immediate in the range [0,15]. def Imm0_15AsmOperand: ImmAsmOperand<0,15> { let Name = "Imm0_15"; + let DiagnosticType = "ImmRange0_15"; } def imm0_15 : Operand, ImmLeaf= 0 && Imm < 16; @@ -789,6 +789,7 @@ /// imm0_239 predicate - Immediate in the range [0,239]. def Imm0_239AsmOperand : ImmAsmOperand<0,239> { let Name = "Imm0_239"; + let DiagnosticType = "ImmRange0_239"; } def imm0_239 : Operand, ImmLeaf= 0 && Imm < 240; }]> { let ParserMatchClass = Imm0_239AsmOperand; @@ -835,10 +836,7 @@ } /// imm24b - True if the 32-bit immediate is encodable in 24 bits. -def Imm24bitAsmOperand: ImmAsmOperand<0,0xffffff> { - let Name = "Imm24bit"; - let DiagnosticString = "immediate operand must be in the range [0,0xffffff]"; -} +def Imm24bitAsmOperand: ImmAsmOperand<0,0xffffff> { let Name = "Imm24bit"; } def imm24b : Operand, ImmLeaf= 0 && Imm <= 0xffffff; }]> { @@ -1131,7 +1129,7 @@ // VLD/VST instructions and checking the alignment is not specified. def AddrMode6AlignNoneAsmOperand : AsmOperandClass { let Name = "AlignedMemoryNone"; - let DiagnosticString = "alignment must be omitted"; + let DiagnosticType = "AlignedMemoryRequiresNone"; } def addrmode6alignNone : AddrMode6Align { // The alignment specifier can only be omitted. @@ -1142,7 +1140,7 @@ // VLD/VST instructions and checking the alignment value. def AddrMode6Align16AsmOperand : AsmOperandClass { let Name = "AlignedMemory16"; - let DiagnosticString = "alignment must be 16 or omitted"; + let DiagnosticType = "AlignedMemoryRequires16"; } def addrmode6align16 : AddrMode6Align { // The alignment specifier can only be 16 or omitted. @@ -1153,7 +1151,7 @@ // VLD/VST instructions and checking the alignment value. def AddrMode6Align32AsmOperand : AsmOperandClass { let Name = "AlignedMemory32"; - let DiagnosticString = "alignment must be 32 or omitted"; + let DiagnosticType = "AlignedMemoryRequires32"; } def addrmode6align32 : AddrMode6Align { // The alignment specifier can only be 32 or omitted. @@ -1164,7 +1162,7 @@ // VLD/VST instructions and checking the alignment value. def AddrMode6Align64AsmOperand : AsmOperandClass { let Name = "AlignedMemory64"; - let DiagnosticString = "alignment must be 64 or omitted"; + let DiagnosticType = "AlignedMemoryRequires64"; } def addrmode6align64 : AddrMode6Align { // The alignment specifier can only be 64 or omitted. @@ -1175,7 +1173,7 @@ // for VLD/VST instructions and checking the alignment value. def AddrMode6Align64or128AsmOperand : AsmOperandClass { let Name = "AlignedMemory64or128"; - let DiagnosticString = "alignment must be 64, 128 or omitted"; + let DiagnosticType = "AlignedMemoryRequires64or128"; } def addrmode6align64or128 : AddrMode6Align { // The alignment specifier can only be 64, 128 or omitted. @@ -1186,7 +1184,7 @@ // encoding for VLD/VST instructions and checking the alignment value. def AddrMode6Align64or128or256AsmOperand : AsmOperandClass { let Name = "AlignedMemory64or128or256"; - let DiagnosticString = "alignment must be 64, 128, 256 or omitted"; + let DiagnosticType = "AlignedMemoryRequires64or128or256"; } def addrmode6align64or128or256 : AddrMode6Align { // The alignment specifier can only be 64, 128, 256 or omitted. @@ -1217,7 +1215,7 @@ // VLD-dup instruction and checking the alignment is not specified. def AddrMode6dupAlignNoneAsmOperand : AsmOperandClass { let Name = "DupAlignedMemoryNone"; - let DiagnosticString = "alignment must be omitted"; + let DiagnosticType = "DupAlignedMemoryRequiresNone"; } def addrmode6dupalignNone : AddrMode6DupAlign { // The alignment specifier can only be omitted. @@ -1228,7 +1226,7 @@ // instruction and checking the alignment value. def AddrMode6dupAlign16AsmOperand : AsmOperandClass { let Name = "DupAlignedMemory16"; - let DiagnosticString = "alignment must be 16 or omitted"; + let DiagnosticType = "DupAlignedMemoryRequires16"; } def addrmode6dupalign16 : AddrMode6DupAlign { // The alignment specifier can only be 16 or omitted. @@ -1239,7 +1237,7 @@ // instruction and checking the alignment value. def AddrMode6dupAlign32AsmOperand : AsmOperandClass { let Name = "DupAlignedMemory32"; - let DiagnosticString = "alignment must be 32 or omitted"; + let DiagnosticType = "DupAlignedMemoryRequires32"; } def addrmode6dupalign32 : AddrMode6DupAlign { // The alignment specifier can only be 32 or omitted. @@ -1250,7 +1248,7 @@ // instructions and checking the alignment value. def AddrMode6dupAlign64AsmOperand : AsmOperandClass { let Name = "DupAlignedMemory64"; - let DiagnosticString = "alignment must be 64 or omitted"; + let DiagnosticType = "DupAlignedMemoryRequires64"; } def addrmode6dupalign64 : AddrMode6DupAlign { // The alignment specifier can only be 64 or omitted. @@ -1261,7 +1259,7 @@ // for VLD instructions and checking the alignment value. def AddrMode6dupAlign64or128AsmOperand : AsmOperandClass { let Name = "DupAlignedMemory64or128"; - let DiagnosticString = "alignment must be 64, 128 or omitted"; + let DiagnosticType = "DupAlignedMemoryRequires64or128"; } def addrmode6dupalign64or128 : AddrMode6DupAlign { // The alignment specifier can only be 64, 128 or omitted. Index: lib/Target/ARM/AsmParser/ARMAsmParser.cpp =================================================================== --- lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -17,7 +17,6 @@ #include "llvm/ADT/APInt.h" #include "llvm/ADT/None.h" #include "llvm/ADT/STLExtras.h" -#include "llvm/ADT/SmallSet.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringMap.h" #include "llvm/ADT/StringRef.h" @@ -85,11 +84,6 @@ static cl::opt AddBuildAttributes("arm-add-build-attributes", cl::init(false)); -cl::opt -DevDiags("arm-asm-parser-dev-diags", cl::init(false), - cl::desc("Use extended diagnostics, which include implementation " - "details useful for development")); - enum VectorLaneTy { NoLanes, AllLanes, IndexedLane }; class UnwindContext { @@ -614,21 +608,8 @@ uint64_t &ErrorInfo, bool MatchingInlineAsm) override; unsigned MatchInstruction(OperandVector &Operands, MCInst &Inst, - SmallVectorImpl &NearMisses, - bool MatchingInlineAsm, bool &EmitInITBlock, - MCStreamer &Out); - - struct NearMissMessage { - SMLoc Loc; - SmallString<128> Message; - }; - - void FilterNearMisses(SmallVectorImpl &NearMissesIn, - SmallVectorImpl &NearMissesOut, - SMLoc IDLoc, OperandVector &Operands); - void ReportNearMisses(SmallVectorImpl &NearMisses, SMLoc IDLoc, - OperandVector &Operands); - + uint64_t &ErrorInfo, bool MatchingInlineAsm, + bool &EmitInITBlock, MCStreamer &Out); void onLabelParsed(MCSymbol *Symbol) override; }; @@ -3406,13 +3387,13 @@ /// parse for a specific register type. bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) { MCAsmParser &Parser = getParser(); - SMLoc RegStartLoc = Parser.getTok().getLoc(); - SMLoc RegEndLoc = Parser.getTok().getEndLoc(); + const AsmToken &RegTok = Parser.getTok(); int RegNo = tryParseRegister(); if (RegNo == -1) return true; - Operands.push_back(ARMOperand::CreateReg(RegNo, RegStartLoc, RegEndLoc)); + Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(), + RegTok.getEndLoc())); const AsmToken &ExclaimTok = Parser.getTok(); if (ExclaimTok.is(AsmToken::Exclaim)) { @@ -8928,19 +8909,19 @@ } unsigned ARMAsmParser::MatchInstruction(OperandVector &Operands, MCInst &Inst, - SmallVectorImpl &NearMisses, + uint64_t &ErrorInfo, bool MatchingInlineAsm, bool &EmitInITBlock, MCStreamer &Out) { // If we can't use an implicit IT block here, just match as normal. if (inExplicitITBlock() || !isThumbTwo() || !useImplicitITThumb()) - return MatchInstructionImpl(Operands, Inst, &NearMisses, MatchingInlineAsm); + return MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm); // Try to match the instruction in an extension of the current IT block (if // there is one). if (inImplicitITBlock()) { extendImplicitITBlock(ITState.Cond); - if (MatchInstructionImpl(Operands, Inst, nullptr, MatchingInlineAsm) == + if (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm) == Match_Success) { // The match succeded, but we still have to check that the instruction is // valid in this implicit IT block. @@ -8966,7 +8947,7 @@ // Finish the current IT block, and try to match outside any IT block. flushPendingInstructions(Out); unsigned PlainMatchResult = - MatchInstructionImpl(Operands, Inst, &NearMisses, MatchingInlineAsm); + MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm); if (PlainMatchResult == Match_Success) { const MCInstrDesc &MCID = MII.get(Inst.getOpcode()); if (MCID.isPredicable()) { @@ -8993,7 +8974,7 @@ // condition, so we create an IT block with a dummy condition, and fix it up // once we know the actual condition. startImplicitITBlock(); - if (MatchInstructionImpl(Operands, Inst, nullptr, MatchingInlineAsm) == + if (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm) == Match_Success) { const MCInstrDesc &MCID = MII.get(Inst.getOpcode()); if (MCID.isPredicable()) { @@ -9023,10 +9004,16 @@ unsigned MatchResult; bool PendConditionalInstruction = false; - SmallVector NearMisses; - MatchResult = MatchInstruction(Operands, Inst, NearMisses, MatchingInlineAsm, + MatchResult = MatchInstruction(Operands, Inst, ErrorInfo, MatchingInlineAsm, PendConditionalInstruction, Out); + SMLoc ErrorLoc; + if (ErrorInfo < Operands.size()) { + ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc(); + if (ErrorLoc == SMLoc()) + ErrorLoc = IDLoc; + } + switch (MatchResult) { case Match_Success: // Context sensitive operand constraints aren't handled by the matcher, @@ -9074,9 +9061,33 @@ Out.EmitInstruction(Inst, getSTI()); } return false; - case Match_NearMisses: - ReportNearMisses(NearMisses, IDLoc, Operands); - return true; + case Match_MissingFeature: { + assert(ErrorInfo && "Unknown missing feature!"); + // Special case the error message for the very common case where only + // a single subtarget feature is missing (Thumb vs. ARM, e.g.). + std::string Msg = "instruction requires:"; + uint64_t Mask = 1; + for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) { + if (ErrorInfo & Mask) { + Msg += " "; + Msg += getSubtargetFeatureName(ErrorInfo & Mask); + } + Mask <<= 1; + } + return Error(IDLoc, Msg); + } + case Match_InvalidOperand: { + SMLoc ErrorLoc = IDLoc; + if (ErrorInfo != ~0ULL) { + if (ErrorInfo >= Operands.size()) + return Error(IDLoc, "too few operands for instruction"); + + ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc(); + if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; + } + + return Error(ErrorLoc, "invalid operand for instruction"); + } case Match_MnemonicFail: { uint64_t FBS = ComputeAvailableFeatures(getSTI().getFeatureBits()); std::string Suggestion = ARMMnemonicSpellCheck( @@ -9084,6 +9095,104 @@ return Error(IDLoc, "invalid instruction" + Suggestion, ((ARMOperand &)*Operands[0]).getLocRange()); } + case Match_RequiresNotITBlock: + return Error(IDLoc, "flag setting instruction only valid outside IT block"); + case Match_RequiresITBlock: + return Error(IDLoc, "instruction only valid inside IT block"); + case Match_RequiresV6: + return Error(IDLoc, "instruction variant requires ARMv6 or later"); + case Match_RequiresThumb2: + return Error(IDLoc, "instruction variant requires Thumb2"); + case Match_RequiresV8: + return Error(IDLoc, "instruction variant requires ARMv8 or later"); + case Match_RequiresFlagSetting: + return Error(IDLoc, "no flag-preserving variant of this instruction available"); + case Match_ImmRange0_1: + return Error(ErrorLoc, "immediate operand must be in the range [0,1]"); + case Match_ImmRange0_3: + return Error(ErrorLoc, "immediate operand must be in the range [0,3]"); + case Match_ImmRange0_7: + return Error(ErrorLoc, "immediate operand must be in the range [0,7]"); + case Match_ImmRange0_15: + return Error(ErrorLoc, "immediate operand must be in the range [0,15]"); + case Match_ImmRange0_31: + return Error(ErrorLoc, "immediate operand must be in the range [0,31]"); + case Match_ImmRange0_32: + return Error(ErrorLoc, "immediate operand must be in the range [0,32]"); + case Match_ImmRange0_63: + return Error(ErrorLoc, "immediate operand must be in the range [0,63]"); + case Match_ImmRange0_239: + return Error(ErrorLoc, "immediate operand must be in the range [0,239]"); + case Match_ImmRange0_255: + return Error(ErrorLoc, "immediate operand must be in the range [0,255]"); + case Match_ImmRange0_4095: + return Error(ErrorLoc, "immediate operand must be in the range [0,4095]"); + case Match_ImmRange0_65535: + return Error(ErrorLoc, "immediate operand must be in the range [0,65535]"); + case Match_ImmRange1_7: + return Error(ErrorLoc, "immediate operand must be in the range [1,7]"); + case Match_ImmRange1_8: + return Error(ErrorLoc, "immediate operand must be in the range [1,8]"); + case Match_ImmRange1_15: + return Error(ErrorLoc, "immediate operand must be in the range [1,15]"); + case Match_ImmRange1_16: + return Error(ErrorLoc, "immediate operand must be in the range [1,16]"); + case Match_ImmRange1_31: + return Error(ErrorLoc, "immediate operand must be in the range [1,31]"); + case Match_ImmRange1_32: + return Error(ErrorLoc, "immediate operand must be in the range [1,32]"); + case Match_ImmRange1_64: + return Error(ErrorLoc, "immediate operand must be in the range [1,64]"); + case Match_ImmRange8_8: + return Error(ErrorLoc, "immediate operand must be 8."); + case Match_ImmRange16_16: + return Error(ErrorLoc, "immediate operand must be 16."); + case Match_ImmRange32_32: + return Error(ErrorLoc, "immediate operand must be 32."); + case Match_ImmRange256_65535: + return Error(ErrorLoc, "immediate operand must be in the range [255,65535]"); + case Match_ImmRange0_16777215: + return Error(ErrorLoc, "immediate operand must be in the range [0,0xffffff]"); + case Match_AlignedMemoryRequiresNone: + case Match_DupAlignedMemoryRequiresNone: + case Match_AlignedMemoryRequires16: + case Match_DupAlignedMemoryRequires16: + case Match_AlignedMemoryRequires32: + case Match_DupAlignedMemoryRequires32: + case Match_AlignedMemoryRequires64: + case Match_DupAlignedMemoryRequires64: + case Match_AlignedMemoryRequires64or128: + case Match_DupAlignedMemoryRequires64or128: + case Match_AlignedMemoryRequires64or128or256: + { + SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getAlignmentLoc(); + if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; + switch (MatchResult) { + default: + llvm_unreachable("Missing Match_Aligned type"); + case Match_AlignedMemoryRequiresNone: + case Match_DupAlignedMemoryRequiresNone: + return Error(ErrorLoc, "alignment must be omitted"); + case Match_AlignedMemoryRequires16: + case Match_DupAlignedMemoryRequires16: + return Error(ErrorLoc, "alignment must be 16 or omitted"); + case Match_AlignedMemoryRequires32: + case Match_DupAlignedMemoryRequires32: + return Error(ErrorLoc, "alignment must be 32 or omitted"); + case Match_AlignedMemoryRequires64: + case Match_DupAlignedMemoryRequires64: + return Error(ErrorLoc, "alignment must be 64 or omitted"); + case Match_AlignedMemoryRequires64or128: + case Match_DupAlignedMemoryRequires64or128: + return Error(ErrorLoc, "alignment must be 64, 128 or omitted"); + case Match_AlignedMemoryRequires64or128or256: + return Error(ErrorLoc, "alignment must be 64, 128, 256 or omitted"); + } + } + case Match_InvalidComplexRotationEven: + return Error(IDLoc, "complex rotation must be 0, 90, 180 or 270"); + case Match_InvalidComplexRotationOdd: + return Error(IDLoc, "complex rotation must be 90 or 270"); } llvm_unreachable("Implement any new match types added!"); @@ -10094,184 +10203,6 @@ #define GET_MATCHER_IMPLEMENTATION #include "ARMGenAsmMatcher.inc" -// Process the list of near-misses, throwing away ones we don't want to report -// to the user, and converting the rest to a source location and string that -// should be reported. -void -ARMAsmParser::FilterNearMisses(SmallVectorImpl &NearMissesIn, - SmallVectorImpl &NearMissesOut, - SMLoc IDLoc, OperandVector &Operands) { - // TODO: If operand didn't match, sub in a dummy one and run target - // predicate, so that we can avoid reporting near-misses that are invalid? - // TODO: Many operand types dont have SuperClasses set, so we report - // redundant ones. - // TODO: Some operands are superclasses of registers (e.g. - // MCK_RegShiftedImm), we don't have any way to represent that currently. - // TODO: This is not all ARM-specific, can some of it be factored out? - - // Record some information about near-misses that we have already seen, so - // that we can avoid reporting redundant ones. For example, if there are - // variants of an instruction that take 8- and 16-bit immediates, we want - // to only report the widest one. - std::multimap OperandMissesSeen; - SmallSet FeatureMissesSeen; - - // Process the near-misses in reverse order, so that we see more general ones - // first, and so can avoid emitting more specific ones. - for (NearMissInfo &I : reverse(NearMissesIn)) { - switch (I.getKind()) { - case NearMissInfo::NearMissOperand: { - SMLoc OperandLoc = - ((ARMOperand &)*Operands[I.getOperandIndex()]).getStartLoc(); - const char *OperandDiag = - getMatchKindDiag((ARMMatchResultTy)I.getOperandError()); - - // If we have already emitted a message for a superclass, don't also report - // the sub-class. We consider all operand classes that we don't have a - // specialised diagnostic for to be equal for the propose of this check, - // so that we don't report the generic error multiple times on the same - // operand. - unsigned DupCheckMatchClass = OperandDiag ? I.getOperandClass() : ~0U; - auto PrevReports = OperandMissesSeen.equal_range(I.getOperandIndex()); - if (std::any_of(PrevReports.first, PrevReports.second, - [DupCheckMatchClass]( - const std::pair Pair) { - if (DupCheckMatchClass == ~0U || Pair.second == ~0U) - return Pair.second == DupCheckMatchClass; - else - return isSubclass((MatchClassKind)DupCheckMatchClass, - (MatchClassKind)Pair.second); - })) - break; - OperandMissesSeen.insert( - std::make_pair(I.getOperandIndex(), DupCheckMatchClass)); - - NearMissMessage Message; - Message.Loc = OperandLoc; - raw_svector_ostream OS(Message.Message); - if (OperandDiag) { - OS << OperandDiag; - } else if (I.getOperandClass() == InvalidMatchClass) { - OS << "too many operands for instruction"; - } else { - OS << "invalid operand for instruction"; - if (DevDiags) { - OS << " class" << I.getOperandClass() << ", error " - << I.getOperandError() << ", opcode " - << MII.getName(I.getOpcode()); - } - } - NearMissesOut.emplace_back(Message); - break; - } - case NearMissInfo::NearMissFeature: { - uint64_t MissingFeatures = I.getFeatures(); - // Don't report the same set of features twice. - if (FeatureMissesSeen.count(MissingFeatures)) - break; - FeatureMissesSeen.insert(MissingFeatures); - - // Special case: don't report a feature set which includes arm-mode for - // targets that don't have ARM mode. - if ((MissingFeatures & Feature_IsARM) && !hasARM()) - break; - // Don't report any near-misses that both require switching instruction - // set, and adding other subtarget features. - if (isThumb() && (MissingFeatures & Feature_IsARM) && - (MissingFeatures & ~Feature_IsARM)) - break; - if (!isThumb() && (MissingFeatures & Feature_IsThumb) && - (MissingFeatures & ~Feature_IsThumb)) - break; - if (!isThumb() && (MissingFeatures & Feature_IsThumb2) && - (MissingFeatures & ~(Feature_IsThumb2 | Feature_IsThumb))) - break; - - NearMissMessage Message; - Message.Loc = IDLoc; - raw_svector_ostream OS(Message.Message); - - OS << "instruction requires:"; - uint64_t Mask = 1; - for (unsigned MaskPos = 0; MaskPos < (sizeof(MissingFeatures) * 8 - 1); - ++MaskPos) { - if (MissingFeatures & Mask) { - OS << " " << getSubtargetFeatureName(MissingFeatures & Mask); - } - Mask <<= 1; - } - NearMissesOut.emplace_back(Message); - - break; - } - case NearMissInfo::NearMissPredicate: { - NearMissMessage Message; - Message.Loc = IDLoc; - switch (I.getPredicateError()) { - case Match_RequiresNotITBlock: - Message.Message = "flag setting instruction only valid outside IT block"; - break; - case Match_RequiresITBlock: - Message.Message = "instruction only valid inside IT block"; - break; - case Match_RequiresV6: - Message.Message = "instruction variant requires ARMv6 or later"; - break; - case Match_RequiresThumb2: - Message.Message = "instruction variant requires Thumb2"; - break; - case Match_RequiresV8: - Message.Message = "instruction variant requires ARMv8 or later"; - break; - case Match_RequiresFlagSetting: - Message.Message = "no flag-preserving variant of this instruction available"; - break; - case Match_InvalidOperand: - Message.Message = "invalid operand for instruction"; - break; - default: - llvm_unreachable("Unhandled target predicate error"); - break; - } - NearMissesOut.emplace_back(Message); - break; - } - case NearMissInfo::NearMissTooFewOperands: { - SMLoc EndLoc = ((ARMOperand &)*Operands.back()).getEndLoc(); - NearMissesOut.emplace_back( - NearMissMessage{ EndLoc, StringRef("too few operands for instruction") }); - break; - } - case NearMissInfo::NoNearMiss: - // This should never leave the matcher. - llvm_unreachable("not a near-miss"); - break; - } - } -} - -void ARMAsmParser::ReportNearMisses(SmallVectorImpl &NearMisses, - SMLoc IDLoc, OperandVector &Operands) { - SmallVector Messages; - FilterNearMisses(NearMisses, Messages, IDLoc, Operands); - - if (Messages.size() == 0) { - // No near-misses were found, so the best we can do is "invalid - // instruction". - Error(IDLoc, "invalid instruction"); - } else if (Messages.size() == 1) { - // One near miss was found, report it as the sole error. - Error(Messages[0].Loc, Messages[0].Message); - } else { - // More than one near miss, so report a generic "invalid instruction" - // error, followed by notes for each of the near-misses. - Error(IDLoc, "invalid instruction, any one of the following would fix this:"); - for (auto &M : Messages) { - Note(M.Loc, M.Message); - } - } -} - // FIXME: This structure should be moved inside ARMTargetParser // when we start to table-generate them, and we can use the ARM // flags below, that were generated by table-gen. Index: lib/Target/Mips/MicroMipsDSPInstrInfo.td =================================================================== --- lib/Target/Mips/MicroMipsDSPInstrInfo.td +++ lib/Target/Mips/MicroMipsDSPInstrInfo.td @@ -415,13 +415,6 @@ class BPOSGE32_MM_DESC : BPOSGE32_DESC_BASE<"bposge32", brtarget_mm, NoItinerary>; -let DecoderNamespace = "MicroMipsDSP", Arch = "mmdsp", - AdditionalPredicates = [HasDSP, InMicroMips] in { - def LWDSP_MM : Load<"lw", DSPROpnd, null_frag, II_LW>, DspMMRel, - LW_FM_MM<0x3f>; - def SWDSP_MM : Store<"sw", DSPROpnd, null_frag, II_SW>, DspMMRel, - LW_FM_MM<0x3e>; -} // Instruction defs. // microMIPS DSP Rev 1 def ADDQ_PH_MM : DspMMRel, ADDQ_PH_MM_ENC, ADDQ_PH_DESC; Index: lib/Target/Mips/MipsDSPInstrInfo.td =================================================================== --- lib/Target/Mips/MipsDSPInstrInfo.td +++ lib/Target/Mips/MipsDSPInstrInfo.td @@ -1284,12 +1284,6 @@ def STORE_CCOND_DSP : Store<"store_ccond_dsp", DSPCC>; } -let DecoderNamespace = "MipsDSP", Arch = "dsp", - AdditionalPredicates = [HasDSP] in { - def LWDSP : Load<"lw", DSPROpnd, null_frag, II_LW>, DspMMRel, LW_FM<0x23>; - def SWDSP : Store<"sw", DSPROpnd, null_frag, II_SW>, DspMMRel, LW_FM<0x2b>; -} - // Pseudo CMP and PICK instructions. class PseudoCMP : PseudoDSP<(outs DSPCC:$cmp), (ins DSPROpnd:$rs, DSPROpnd:$rt), []>, Index: lib/Target/Mips/MipsSEInstrInfo.cpp =================================================================== --- lib/Target/Mips/MipsSEInstrInfo.cpp +++ lib/Target/Mips/MipsSEInstrInfo.cpp @@ -226,8 +226,6 @@ Opc = Mips::SW; else if (Mips::HI64RegClass.hasSubClassEq(RC)) Opc = Mips::SD; - else if (Mips::DSPRRegClass.hasSubClassEq(RC)) - Opc = Mips::SWDSP; // Hi, Lo are normally caller save but they are callee save // for interrupt handling. @@ -304,8 +302,6 @@ Opc = Mips::LW; else if (Mips::LO64RegClass.hasSubClassEq(RC)) Opc = Mips::LD; - else if (Mips::DSPRRegClass.hasSubClassEq(RC)) - Opc = Mips::LWDSP; assert(Opc && "Register class not handled!"); Index: lib/Target/PowerPC/PPCMIPeephole.cpp =================================================================== --- lib/Target/PowerPC/PPCMIPeephole.cpp +++ lib/Target/PowerPC/PPCMIPeephole.cpp @@ -784,7 +784,7 @@ } else continue; } - else if (CMPI1->getOperand(2).isImm() && CMPI2->getOperand(2).isImm()) { + else if (CMPI1->getOperand(2).isImm() && CMPI2->getOperand(2).isImm()){ // In case of comparisons between a register and an immediate, // the operand register must be same for two compare instructions. unsigned Cmp1Operand1 = getSrcVReg(CMPI1->getOperand(1).getReg(), Index: lib/Target/PowerPC/PPCScheduleP9.td =================================================================== --- lib/Target/PowerPC/PPCScheduleP9.td +++ lib/Target/PowerPC/PPCScheduleP9.td @@ -22,7 +22,7 @@ // Try to make sure we have at least 10 dispatch groups in a loop. let LoopMicroOpBufferSize = 60; - let CompleteModel = 0; + let CompleteModel = 1; let UnsupportedFeatures = [HasQPX]; Index: lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp =================================================================== --- lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp +++ lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp @@ -16,7 +16,6 @@ #include "InstPrinter/X86IntelInstPrinter.h" #include "X86MCAsmInfo.h" #include "llvm/ADT/Triple.h" -#include "llvm/DebugInfo/CodeView/CodeView.h" #include "llvm/MC/MCInstrAnalysis.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" @@ -73,128 +72,52 @@ MRI->mapLLVMRegToSEHReg(Reg, SEH); } - // Mapping from CodeView to MC register id. - static const struct { - codeview::RegisterId CVReg; - MCPhysReg Reg; - } RegMap[] = { - { codeview::RegisterId::AL, X86::AL}, - { codeview::RegisterId::CL, X86::CL}, - { codeview::RegisterId::DL, X86::DL}, - { codeview::RegisterId::BL, X86::BL}, - { codeview::RegisterId::AH, X86::AH}, - { codeview::RegisterId::CH, X86::CH}, - { codeview::RegisterId::DH, X86::DH}, - { codeview::RegisterId::BH, X86::BH}, - { codeview::RegisterId::AX, X86::AX}, - { codeview::RegisterId::CX, X86::CX}, - { codeview::RegisterId::DX, X86::DX}, - { codeview::RegisterId::BX, X86::BX}, - { codeview::RegisterId::SP, X86::SP}, - { codeview::RegisterId::BP, X86::BP}, - { codeview::RegisterId::SI, X86::SI}, - { codeview::RegisterId::DI, X86::DI}, - { codeview::RegisterId::EAX, X86::EAX}, - { codeview::RegisterId::ECX, X86::ECX}, - { codeview::RegisterId::EDX, X86::EDX}, - { codeview::RegisterId::EBX, X86::EBX}, - { codeview::RegisterId::ESP, X86::ESP}, - { codeview::RegisterId::EBP, X86::EBP}, - { codeview::RegisterId::ESI, X86::ESI}, - { codeview::RegisterId::EDI, X86::EDI}, - - { codeview::RegisterId::EFLAGS, X86::EFLAGS}, - - { codeview::RegisterId::ST0, X86::FP0}, - { codeview::RegisterId::ST1, X86::FP1}, - { codeview::RegisterId::ST2, X86::FP2}, - { codeview::RegisterId::ST3, X86::FP3}, - { codeview::RegisterId::ST4, X86::FP4}, - { codeview::RegisterId::ST5, X86::FP5}, - { codeview::RegisterId::ST6, X86::FP6}, - { codeview::RegisterId::ST7, X86::FP7}, - - { codeview::RegisterId::XMM0, X86::XMM0}, - { codeview::RegisterId::XMM1, X86::XMM1}, - { codeview::RegisterId::XMM2, X86::XMM2}, - { codeview::RegisterId::XMM3, X86::XMM3}, - { codeview::RegisterId::XMM4, X86::XMM4}, - { codeview::RegisterId::XMM5, X86::XMM5}, - { codeview::RegisterId::XMM6, X86::XMM6}, - { codeview::RegisterId::XMM7, X86::XMM7}, - - { codeview::RegisterId::XMM8, X86::XMM8}, - { codeview::RegisterId::XMM9, X86::XMM9}, - { codeview::RegisterId::XMM10, X86::XMM10}, - { codeview::RegisterId::XMM11, X86::XMM11}, - { codeview::RegisterId::XMM12, X86::XMM12}, - { codeview::RegisterId::XMM13, X86::XMM13}, - { codeview::RegisterId::XMM14, X86::XMM14}, - { codeview::RegisterId::XMM15, X86::XMM15}, - - { codeview::RegisterId::SIL, X86::SIL}, - { codeview::RegisterId::DIL, X86::DIL}, - { codeview::RegisterId::BPL, X86::BPL}, - { codeview::RegisterId::SPL, X86::SPL}, - { codeview::RegisterId::RAX, X86::RAX}, - { codeview::RegisterId::RBX, X86::RBX}, - { codeview::RegisterId::RCX, X86::RCX}, - { codeview::RegisterId::RDX, X86::RDX}, - { codeview::RegisterId::RSI, X86::RSI}, - { codeview::RegisterId::RDI, X86::RDI}, - { codeview::RegisterId::RBP, X86::RBP}, - { codeview::RegisterId::RSP, X86::RSP}, - { codeview::RegisterId::R8, X86::R8}, - { codeview::RegisterId::R9, X86::R9}, - { codeview::RegisterId::R10, X86::R10}, - { codeview::RegisterId::R11, X86::R11}, - { codeview::RegisterId::R12, X86::R12}, - { codeview::RegisterId::R13, X86::R13}, - { codeview::RegisterId::R14, X86::R14}, - { codeview::RegisterId::R15, X86::R15}, - { codeview::RegisterId::R8B, X86::R8B}, - { codeview::RegisterId::R9B, X86::R9B}, - { codeview::RegisterId::R10B, X86::R10B}, - { codeview::RegisterId::R11B, X86::R11B}, - { codeview::RegisterId::R12B, X86::R12B}, - { codeview::RegisterId::R13B, X86::R13B}, - { codeview::RegisterId::R14B, X86::R14B}, - { codeview::RegisterId::R15B, X86::R15B}, - { codeview::RegisterId::R8W, X86::R8W}, - { codeview::RegisterId::R9W, X86::R9W}, - { codeview::RegisterId::R10W, X86::R10W}, - { codeview::RegisterId::R11W, X86::R11W}, - { codeview::RegisterId::R12W, X86::R12W}, - { codeview::RegisterId::R13W, X86::R13W}, - { codeview::RegisterId::R14W, X86::R14W}, - { codeview::RegisterId::R15W, X86::R15W}, - { codeview::RegisterId::R8D, X86::R8D}, - { codeview::RegisterId::R9D, X86::R9D}, - { codeview::RegisterId::R10D, X86::R10D}, - { codeview::RegisterId::R11D, X86::R11D}, - { codeview::RegisterId::R12D, X86::R12D}, - { codeview::RegisterId::R13D, X86::R13D}, - { codeview::RegisterId::R14D, X86::R14D}, - { codeview::RegisterId::R15D, X86::R15D}, - { codeview::RegisterId::AMD64_YMM0, X86::YMM0}, - { codeview::RegisterId::AMD64_YMM1, X86::YMM1}, - { codeview::RegisterId::AMD64_YMM2, X86::YMM2}, - { codeview::RegisterId::AMD64_YMM3, X86::YMM3}, - { codeview::RegisterId::AMD64_YMM4, X86::YMM4}, - { codeview::RegisterId::AMD64_YMM5, X86::YMM5}, - { codeview::RegisterId::AMD64_YMM6, X86::YMM6}, - { codeview::RegisterId::AMD64_YMM7, X86::YMM7}, - { codeview::RegisterId::AMD64_YMM8, X86::YMM8}, - { codeview::RegisterId::AMD64_YMM9, X86::YMM9}, - { codeview::RegisterId::AMD64_YMM10, X86::YMM10}, - { codeview::RegisterId::AMD64_YMM11, X86::YMM11}, - { codeview::RegisterId::AMD64_YMM12, X86::YMM12}, - { codeview::RegisterId::AMD64_YMM13, X86::YMM13}, - { codeview::RegisterId::AMD64_YMM14, X86::YMM14}, - { codeview::RegisterId::AMD64_YMM15, X86::YMM15}, + // These CodeView registers are numbered sequentially starting at value 1. + static const MCPhysReg LowCVRegs[] = { + X86::AL, X86::CL, X86::DL, X86::BL, X86::AH, X86::CH, + X86::DH, X86::BH, X86::AX, X86::CX, X86::DX, X86::BX, + X86::SP, X86::BP, X86::SI, X86::DI, X86::EAX, X86::ECX, + X86::EDX, X86::EBX, X86::ESP, X86::EBP, X86::ESI, X86::EDI, }; - for (unsigned I = 0; I < array_lengthof(RegMap); ++I) - MRI->mapLLVMRegToCVReg(RegMap[I].Reg, static_cast(RegMap[I].CVReg)); + unsigned CVLowRegStart = 1; + for (unsigned I = 0; I < array_lengthof(LowCVRegs); ++I) + MRI->mapLLVMRegToCVReg(LowCVRegs[I], I + CVLowRegStart); + + MRI->mapLLVMRegToCVReg(X86::EFLAGS, 34); + + // The x87 registers start at 128 and are numbered sequentially. + unsigned FP0Start = 128; + for (unsigned I = 0; I < 8; ++I) + MRI->mapLLVMRegToCVReg(X86::FP0 + I, FP0Start + I); + + // The low 8 XMM registers start at 154 and are numbered sequentially. + unsigned CVXMM0Start = 154; + for (unsigned I = 0; I < 8; ++I) + MRI->mapLLVMRegToCVReg(X86::XMM0 + I, CVXMM0Start + I); + + // The high 8 XMM registers start at 252 and are numbered sequentially. + unsigned CVXMM8Start = 252; + for (unsigned I = 0; I < 8; ++I) + MRI->mapLLVMRegToCVReg(X86::XMM8 + I, CVXMM8Start + I); + + // FIXME: XMM16 and above from AVX512 not yet documented. + + // AMD64 registers start at 324 and count up. + unsigned CVX64RegStart = 324; + static const MCPhysReg CVX64Regs[] = { + X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::RAX, X86::RBX, + X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBP, X86::RSP, + X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, + X86::R14, X86::R15, X86::R8B, X86::R9B, X86::R10B, X86::R11B, + X86::R12B, X86::R13B, X86::R14B, X86::R15B, X86::R8W, X86::R9W, + X86::R10W, X86::R11W, X86::R12W, X86::R13W, X86::R14W, X86::R15W, + X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R12D, X86::R13D, + X86::R14D, X86::R15D, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, + X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, + X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, + }; + for (unsigned I = 0; I < array_lengthof(CVX64Regs); ++I) + MRI->mapLLVMRegToCVReg(CVX64Regs[I], CVX64RegStart + I); } MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const Triple &TT, Index: lib/Target/X86/X86FrameLowering.h =================================================================== --- lib/Target/X86/X86FrameLowering.h +++ lib/Target/X86/X86FrameLowering.h @@ -157,6 +157,15 @@ void orderFrameObjects(const MachineFunction &MF, SmallVectorImpl &ObjectsToAllocate) const override; + /// convertArgMovsToPushes - This method tries to convert a call sequence + /// that uses sub and mov instructions to put the argument onto the stack + /// into a series of pushes. + /// Returns true if the transformation succeeded, false if not. + bool convertArgMovsToPushes(MachineFunction &MF, + MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, + uint64_t Amount) const; + /// Wraps up getting a CFI index and building a MachineInstr for it. void BuildCFI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, const DebugLoc &DL, const MCCFIInstruction &CFIInst) const; Index: lib/Target/X86/X86ISelLowering.h =================================================================== --- lib/Target/X86/X86ISelLowering.h +++ lib/Target/X86/X86ISelLowering.h @@ -1189,7 +1189,6 @@ SDValue LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const; SDValue LowerGC_TRANSITION_START(SDValue Op, SelectionDAG &DAG) const; SDValue LowerGC_TRANSITION_END(SDValue Op, SelectionDAG &DAG) const; - SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, Index: lib/Target/X86/X86ISelLowering.cpp =================================================================== --- lib/Target/X86/X86ISelLowering.cpp +++ lib/Target/X86/X86ISelLowering.cpp @@ -5350,13 +5350,6 @@ return false; }; - // Handle UNDEFs. - if (Op.isUndef()) { - APInt UndefSrcElts = APInt::getAllOnesValue(NumElts); - SmallVector SrcEltBits(NumElts, APInt(EltSizeInBits, 0)); - return CastBitData(UndefSrcElts, SrcEltBits); - } - // Extract constant bits from build vector. if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) { unsigned SrcEltSizeInBits = VT.getScalarSizeInBits(); @@ -5967,13 +5960,13 @@ // If we know input saturation won't happen we can treat this // as a truncation shuffle. if (Opcode == X86ISD::PACKSS) { - if ((!N0.isUndef() && DAG.ComputeNumSignBits(N0) <= NumBitsPerElt) || - (!N1.isUndef() && DAG.ComputeNumSignBits(N1) <= NumBitsPerElt)) + if (DAG.ComputeNumSignBits(N0) <= NumBitsPerElt || + DAG.ComputeNumSignBits(N1) <= NumBitsPerElt) return false; } else { APInt ZeroMask = APInt::getHighBitsSet(2 * NumBitsPerElt, NumBitsPerElt); - if ((!N0.isUndef() && !DAG.MaskedValueIsZero(N0, ZeroMask)) || - (!N1.isUndef() && !DAG.MaskedValueIsZero(N1, ZeroMask))) + if (!DAG.MaskedValueIsZero(N0, ZeroMask) || + !DAG.MaskedValueIsZero(N1, ZeroMask)) return false; } @@ -6042,14 +6035,6 @@ for (int i = 0, e = Inputs.size(); i < e; ++i) { int lo = UsedInputs.size() * MaskWidth; int hi = lo + MaskWidth; - - // Strip UNDEF input usage. - if (Inputs[i].isUndef()) - for (int &M : Mask) - if ((lo <= M) && (M < hi)) - M = SM_SentinelUndef; - - // Check for unused inputs. if (any_of(Mask, [lo, hi](int i) { return (lo <= i) && (i < hi); })) { UsedInputs.push_back(Inputs[i]); continue; @@ -8672,39 +8657,6 @@ return SDValue(); } -// X86 has dedicated pack instructions that can handle specific truncation -// operations: PACKSS and PACKUS. -static SDValue lowerVectorShuffleWithPACK(const SDLoc &DL, MVT VT, - ArrayRef Mask, SDValue V1, - SDValue V2, SelectionDAG &DAG, - const X86Subtarget &Subtarget) { - unsigned NumElts = VT.getVectorNumElements(); - unsigned BitSize = VT.getScalarSizeInBits(); - MVT PackSVT = MVT::getIntegerVT(BitSize * 2); - MVT PackVT = MVT::getVectorVT(PackSVT, NumElts / 2); - - // TODO - Add support for unary packs. - SmallVector BinaryMask; - createPackShuffleMask(VT, BinaryMask, false); - - if (isShuffleEquivalent(V1, V2, Mask, BinaryMask)) { - SDValue VV1 = DAG.getBitcast(PackVT, V1); - SDValue VV2 = DAG.getBitcast(PackVT, V2); - if ((V1.isUndef() || DAG.ComputeNumSignBits(VV1) > BitSize) && - (V2.isUndef() || DAG.ComputeNumSignBits(VV2) > BitSize)) - return DAG.getNode(X86ISD::PACKSS, DL, VT, VV1, VV2); - - if (Subtarget.hasSSE41() || PackSVT == MVT::i16) { - APInt ZeroMask = APInt::getHighBitsSet(BitSize * 2, BitSize); - if ((V1.isUndef() || DAG.MaskedValueIsZero(VV1, ZeroMask)) && - (V2.isUndef() || DAG.MaskedValueIsZero(VV2, ZeroMask))) - return DAG.getNode(X86ISD::PACKUS, DL, VT, VV1, VV2); - } - } - - return SDValue(); -} - /// \brief Try to emit a bitmask instruction for a shuffle. /// /// This handles cases where we can model a blend exactly as a bitmask due to @@ -11444,11 +11396,6 @@ lowerVectorShuffleWithUNPCK(DL, MVT::v8i16, Mask, V1, V2, DAG)) return V; - // Use dedicated pack instructions for masks that match their pattern. - if (SDValue V = lowerVectorShuffleWithPACK(DL, MVT::v8i16, Mask, V1, V2, - DAG, Subtarget)) - return V; - // Try to use byte rotation instructions. if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1, Mask, Subtarget, DAG)) @@ -11619,11 +11566,6 @@ DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG)) return Rotate; - // Use dedicated pack instructions for masks that match their pattern. - if (SDValue V = lowerVectorShuffleWithPACK(DL, MVT::v16i8, Mask, V1, V2, DAG, - Subtarget)) - return V; - // Try to use a zext lowering. if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend( DL, MVT::v16i8, V1, V2, Mask, Zeroable, Subtarget, DAG)) @@ -13118,11 +13060,6 @@ lowerVectorShuffleWithUNPCK(DL, MVT::v16i16, Mask, V1, V2, DAG)) return V; - // Use dedicated pack instructions for masks that match their pattern. - if (SDValue V = lowerVectorShuffleWithPACK(DL, MVT::v16i16, Mask, V1, V2, DAG, - Subtarget)) - return V; - // Try to use shift instructions. if (SDValue Shift = lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, Zeroable, Subtarget, DAG)) @@ -13209,11 +13146,6 @@ lowerVectorShuffleWithUNPCK(DL, MVT::v32i8, Mask, V1, V2, DAG)) return V; - // Use dedicated pack instructions for masks that match their pattern. - if (SDValue V = lowerVectorShuffleWithPACK(DL, MVT::v32i8, Mask, V1, V2, DAG, - Subtarget)) - return V; - // Try to use shift instructions. if (SDValue Shift = lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, Zeroable, Subtarget, DAG)) @@ -19372,8 +19304,8 @@ return DAG.getNode(ISD::SUB, dl, PtrVT, RegNodeBase, ParentFrameOffset); } -SDValue X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, - SelectionDAG &DAG) const { +static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget &Subtarget, + SelectionDAG &DAG) { // Helper to detect if the operand is CUR_DIRECTION rounding mode. auto isRoundModeCurDirection = [](SDValue Rnd) { if (!isa(Rnd)) @@ -20194,8 +20126,7 @@ auto &Context = MF.getMMI().getContext(); MCSymbol *S = Context.getOrCreateSymbol(Twine("GCC_except_table") + Twine(MF.getFunctionNumber())); - return DAG.getNode(getGlobalWrapperKind(), dl, VT, - DAG.getMCSymbol(S, PtrVT)); + return DAG.getNode(X86ISD::Wrapper, dl, VT, DAG.getMCSymbol(S, PtrVT)); } case Intrinsic::x86_seh_lsda: { @@ -24111,7 +24042,7 @@ case ISD::VASTART: return LowerVASTART(Op, DAG); case ISD::VAARG: return LowerVAARG(Op, DAG); case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG); - case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); + case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG); case ISD::INTRINSIC_VOID: case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG); case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); @@ -24371,7 +24302,7 @@ } } case ISD::INTRINSIC_WO_CHAIN: { - if (SDValue V = LowerINTRINSIC_WO_CHAIN(SDValue(N, 0), DAG)) + if (SDValue V = LowerINTRINSIC_WO_CHAIN(SDValue(N, 0), Subtarget, DAG)) Results.push_back(V); return; } @@ -31906,85 +31837,6 @@ return SDValue(); } -static SDValue combineVectorPack(SDNode *N, SelectionDAG &DAG, - TargetLowering::DAGCombinerInfo &DCI, - const X86Subtarget &Subtarget) { - unsigned Opcode = N->getOpcode(); - assert((X86ISD::PACKSS == Opcode || X86ISD::PACKUS == Opcode) && - "Unexpected shift opcode"); - - EVT VT = N->getValueType(0); - SDValue N0 = N->getOperand(0); - SDValue N1 = N->getOperand(1); - unsigned DstBitsPerElt = VT.getScalarSizeInBits(); - unsigned SrcBitsPerElt = 2 * DstBitsPerElt; - assert(N0.getScalarValueSizeInBits() == SrcBitsPerElt && - N1.getScalarValueSizeInBits() == SrcBitsPerElt && - "Unexpected PACKSS/PACKUS input type"); - - // Constant Folding. - APInt UndefElts0, UndefElts1; - SmallVector EltBits0, EltBits1; - if ((N0->isUndef() || N->isOnlyUserOf(N0.getNode())) && - (N1->isUndef() || N->isOnlyUserOf(N1.getNode())) && - getTargetConstantBitsFromNode(N0, SrcBitsPerElt, UndefElts0, EltBits0) && - getTargetConstantBitsFromNode(N1, SrcBitsPerElt, UndefElts1, EltBits1)) { - unsigned NumLanes = VT.getSizeInBits() / 128; - unsigned NumDstElts = VT.getVectorNumElements(); - unsigned NumSrcElts = NumDstElts / 2; - unsigned NumDstEltsPerLane = NumDstElts / NumLanes; - unsigned NumSrcEltsPerLane = NumSrcElts / NumLanes; - bool IsSigned = (X86ISD::PACKSS == Opcode); - - APInt Undefs(NumDstElts, 0); - SmallVector Bits(NumDstElts, APInt::getNullValue(DstBitsPerElt)); - for (unsigned Lane = 0; Lane != NumLanes; ++Lane) { - for (unsigned Elt = 0; Elt != NumDstEltsPerLane; ++Elt) { - unsigned SrcIdx = Lane * NumSrcEltsPerLane + Elt % NumSrcEltsPerLane; - auto &UndefElts = (Elt >= NumSrcEltsPerLane ? UndefElts1 : UndefElts0); - auto &EltBits = (Elt >= NumSrcEltsPerLane ? EltBits1 : EltBits0); - - if (UndefElts[SrcIdx]) { - Undefs.setBit(Lane * NumDstEltsPerLane + Elt); - continue; - } - - APInt &Val = EltBits[SrcIdx]; - if (IsSigned) { - // PACKSS: Truncate signed value with signed saturation. - // Source values less than dst minint are saturated to minint. - // Source values greater than dst maxint are saturated to maxint. - if (Val.isSignedIntN(DstBitsPerElt)) - Val = Val.trunc(DstBitsPerElt); - else if (Val.isNegative()) - Val = APInt::getSignedMinValue(DstBitsPerElt); - else - Val = APInt::getSignedMaxValue(DstBitsPerElt); - } else { - // PACKUS: Truncate signed value with unsigned saturation. - // Source values less than zero are saturated to zero. - // Source values greater than dst maxuint are saturated to maxuint. - if (Val.isIntN(DstBitsPerElt)) - Val = Val.trunc(DstBitsPerElt); - else if (Val.isNegative()) - Val = APInt::getNullValue(DstBitsPerElt); - else - Val = APInt::getAllOnesValue(DstBitsPerElt); - } - Bits[Lane * NumDstEltsPerLane + Elt] = Val; - } - } - - return getConstVector(Bits, Undefs, VT.getSimpleVT(), DAG, SDLoc(N)); - } - - // Attempt to combine as shuffle. - SDValue Op(N, 0); - combineX86ShufflesRecursively({Op}, 0, Op, {0}, {}, /*Depth*/ 1, - /*HasVarMask*/ false, DAG, DCI, Subtarget); - return SDValue(); -} - static SDValue combineVectorShiftImm(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget) { @@ -36216,8 +36068,6 @@ case ISD::SETCC: return combineSetCC(N, DAG, Subtarget); case X86ISD::SETCC: return combineX86SetCC(N, DAG, Subtarget); case X86ISD::BRCOND: return combineBrCond(N, DAG, Subtarget); - case X86ISD::PACKSS: - case X86ISD::PACKUS: return combineVectorPack(N, DAG, DCI, Subtarget); case X86ISD::VSHLI: case X86ISD::VSRAI: case X86ISD::VSRLI: Index: lib/Transforms/IPO/FunctionImport.cpp =================================================================== --- lib/Transforms/IPO/FunctionImport.cpp +++ lib/Transforms/IPO/FunctionImport.cpp @@ -463,6 +463,10 @@ // Make value live and add it to the worklist if it was not live before. // FIXME: we should only make the prevailing copy live here auto visit = [&](ValueInfo VI) { + for (auto &S : VI.getSummaryList()) + S->setLive(true); + ++LiveSymbols; + Worklist.push_back(VI); // FIXME: If we knew which edges were created for indirect call profiles, // we could skip them here. Any that are live should be reached via // other edges, e.g. reference edges. Otherwise, using a profile collected Index: lib/Transforms/IPO/PassManagerBuilder.cpp =================================================================== --- lib/Transforms/IPO/PassManagerBuilder.cpp +++ lib/Transforms/IPO/PassManagerBuilder.cpp @@ -94,6 +94,15 @@ "enable-loopinterchange", cl::init(false), cl::Hidden, cl::desc("Enable the new, experimental LoopInterchange Pass")); +static cl::opt EnableNonLTOGlobalsModRef( + "enable-non-lto-gmr", cl::init(true), cl::Hidden, + cl::desc( + "Enable the GlobalsModRef AliasAnalysis outside of the LTO pipeline.")); + +static cl::opt EnableLoopLoadElim( + "enable-loop-load-elim", cl::init(true), cl::Hidden, + cl::desc("Enable the LoopLoadElimination Pass")); + static cl::opt EnablePrepareForThinLTO("prepare-for-thinlto", cl::init(false), cl::Hidden, cl::desc("Enable preparation for ThinLTO.")); @@ -481,10 +490,11 @@ if (!PerformThinLTO && !PrepareForThinLTOUsingPGOSampleProfile) addPGOInstrPasses(MPM); - // We add a module alias analysis pass here. In part due to bugs in the - // analysis infrastructure this "works" in that the analysis stays alive - // for the entire SCC pass run below. - MPM.add(createGlobalsAAWrapperPass()); + if (EnableNonLTOGlobalsModRef) + // We add a module alias analysis pass here. In part due to bugs in the + // analysis infrastructure this "works" in that the analysis stays alive + // for the entire SCC pass run below. + MPM.add(createGlobalsAAWrapperPass()); // Start of CallGraph SCC passes. if (!DisableUnitAtATime) @@ -550,22 +560,23 @@ MPM.add(createLICMPass()); // Hoist loop invariants } - // We add a fresh GlobalsModRef run at this point. This is particularly - // useful as the above will have inlined, DCE'ed, and function-attr - // propagated everything. We should at this point have a reasonably minimal - // and richly annotated call graph. By computing aliasing and mod/ref - // information for all local globals here, the late loop passes and notably - // the vectorizer will be able to use them to help recognize vectorizable - // memory operations. - // - // Note that this relies on a bug in the pass manager which preserves - // a module analysis into a function pass pipeline (and throughout it) so - // long as the first function pass doesn't invalidate the module analysis. - // Thus both Float2Int and LoopRotate have to preserve AliasAnalysis for - // this to work. Fortunately, it is trivial to preserve AliasAnalysis - // (doing nothing preserves it as it is required to be conservatively - // correct in the face of IR changes). - MPM.add(createGlobalsAAWrapperPass()); + if (EnableNonLTOGlobalsModRef) + // We add a fresh GlobalsModRef run at this point. This is particularly + // useful as the above will have inlined, DCE'ed, and function-attr + // propagated everything. We should at this point have a reasonably minimal + // and richly annotated call graph. By computing aliasing and mod/ref + // information for all local globals here, the late loop passes and notably + // the vectorizer will be able to use them to help recognize vectorizable + // memory operations. + // + // Note that this relies on a bug in the pass manager which preserves + // a module analysis into a function pass pipeline (and throughout it) so + // long as the first function pass doesn't invalidate the module analysis. + // Thus both Float2Int and LoopRotate have to preserve AliasAnalysis for + // this to work. Fortunately, it is trivial to preserve AliasAnalysis + // (doing nothing preserves it as it is required to be conservatively + // correct in the face of IR changes). + MPM.add(createGlobalsAAWrapperPass()); MPM.add(createFloat2IntPass()); @@ -586,7 +597,8 @@ // Eliminate loads by forwarding stores from the previous iteration to loads // of the current iteration. - MPM.add(createLoopLoadEliminationPass()); + if (EnableLoopLoadElim) + MPM.add(createLoopLoadEliminationPass()); // FIXME: Because of #pragma vectorize enable, the passes below are always // inserted in the pipeline, even when the vectorizer doesn't run (ex. when Index: lib/Transforms/InstCombine/InstCombineCompares.cpp =================================================================== --- lib/Transforms/InstCombine/InstCombineCompares.cpp +++ lib/Transforms/InstCombine/InstCombineCompares.cpp @@ -1414,10 +1414,10 @@ /// Fold icmp (trunc X, Y), C. Instruction *InstCombiner::foldICmpTruncConstant(ICmpInst &Cmp, TruncInst *Trunc, - const APInt &C) { + const APInt *C) { ICmpInst::Predicate Pred = Cmp.getPredicate(); Value *X = Trunc->getOperand(0); - if (C.isOneValue() && C.getBitWidth() > 1) { + if (C->isOneValue() && C->getBitWidth() > 1) { // icmp slt trunc(signum(V)) 1 --> icmp slt V, 1 Value *V = nullptr; if (Pred == ICmpInst::ICMP_SLT && match(X, m_Signum(m_Value(V)))) @@ -1435,7 +1435,7 @@ // If all the high bits are known, we can do this xform. if ((Known.Zero | Known.One).countLeadingOnes() >= SrcBits - DstBits) { // Pull in the high bits from known-ones set. - APInt NewRHS = C.zext(SrcBits); + APInt NewRHS = C->zext(SrcBits); NewRHS |= Known.One & APInt::getHighBitsSet(SrcBits, SrcBits - DstBits); return new ICmpInst(Pred, X, ConstantInt::get(X->getType(), NewRHS)); } @@ -1447,7 +1447,7 @@ /// Fold icmp (xor X, Y), C. Instruction *InstCombiner::foldICmpXorConstant(ICmpInst &Cmp, BinaryOperator *Xor, - const APInt &C) { + const APInt *C) { Value *X = Xor->getOperand(0); Value *Y = Xor->getOperand(1); const APInt *XorC; @@ -1457,8 +1457,8 @@ // If this is a comparison that tests the signbit (X < 0) or (x > -1), // fold the xor. ICmpInst::Predicate Pred = Cmp.getPredicate(); - bool TrueIfSigned = false; - if (isSignBitCheck(Cmp.getPredicate(), C, TrueIfSigned)) { + if ((Pred == ICmpInst::ICMP_SLT && C->isNullValue()) || + (Pred == ICmpInst::ICMP_SGT && C->isAllOnesValue())) { // If the sign bit of the XorCst is not set, there is no change to // the operation, just stop using the Xor. @@ -1468,13 +1468,17 @@ return &Cmp; } - // Emit the opposite comparison. - if (TrueIfSigned) - return new ICmpInst(ICmpInst::ICMP_SGT, X, - ConstantInt::getAllOnesValue(X->getType())); + // Was the old condition true if the operand is positive? + bool isTrueIfPositive = Pred == ICmpInst::ICMP_SGT; + + // If so, the new one isn't. + isTrueIfPositive ^= true; + + Constant *CmpConstant = cast(Cmp.getOperand(1)); + if (isTrueIfPositive) + return new ICmpInst(ICmpInst::ICMP_SGT, X, SubOne(CmpConstant)); else - return new ICmpInst(ICmpInst::ICMP_SLT, X, - ConstantInt::getNullValue(X->getType())); + return new ICmpInst(ICmpInst::ICMP_SLT, X, AddOne(CmpConstant)); } if (Xor->hasOneUse()) { @@ -1482,7 +1486,7 @@ if (!Cmp.isEquality() && XorC->isSignMask()) { Pred = Cmp.isSigned() ? Cmp.getUnsignedPredicate() : Cmp.getSignedPredicate(); - return new ICmpInst(Pred, X, ConstantInt::get(X->getType(), C ^ *XorC)); + return new ICmpInst(Pred, X, ConstantInt::get(X->getType(), *C ^ *XorC)); } // (icmp u/s (xor X ~SignMask), C) -> (icmp s/u X, (xor C ~SignMask)) @@ -1490,18 +1494,18 @@ Pred = Cmp.isSigned() ? Cmp.getUnsignedPredicate() : Cmp.getSignedPredicate(); Pred = Cmp.getSwappedPredicate(Pred); - return new ICmpInst(Pred, X, ConstantInt::get(X->getType(), C ^ *XorC)); + return new ICmpInst(Pred, X, ConstantInt::get(X->getType(), *C ^ *XorC)); } } // (icmp ugt (xor X, C), ~C) -> (icmp ult X, C) // iff -C is a power of 2 - if (Pred == ICmpInst::ICMP_UGT && *XorC == ~C && (C + 1).isPowerOf2()) + if (Pred == ICmpInst::ICMP_UGT && *XorC == ~(*C) && (*C + 1).isPowerOf2()) return new ICmpInst(ICmpInst::ICMP_ULT, X, Y); // (icmp ult (xor X, C), -C) -> (icmp uge X, C) // iff -C is a power of 2 - if (Pred == ICmpInst::ICMP_ULT && *XorC == -C && C.isPowerOf2()) + if (Pred == ICmpInst::ICMP_ULT && *XorC == -(*C) && C->isPowerOf2()) return new ICmpInst(ICmpInst::ICMP_UGE, X, Y); return nullptr; @@ -1509,7 +1513,7 @@ /// Fold icmp (and (sh X, Y), C2), C1. Instruction *InstCombiner::foldICmpAndShift(ICmpInst &Cmp, BinaryOperator *And, - const APInt &C1, const APInt &C2) { + const APInt *C1, const APInt *C2) { BinaryOperator *Shift = dyn_cast(And->getOperand(0)); if (!Shift || !Shift->isShift()) return nullptr; @@ -1533,7 +1537,7 @@ // also fold a signed comparison if the mask value and comparison value // are not negative. These constraints may not be obvious, but we can // prove that they are correct using an SMT solver. - if (!Cmp.isSigned() || (!C2.isNegative() && !C1.isNegative())) + if (!Cmp.isSigned() || (!C2->isNegative() && !C1->isNegative())) CanFold = true; } else if (ShiftOpcode == Instruction::LShr) { // For a logical right shift, we can fold if the comparison is not signed. @@ -1541,15 +1545,15 @@ // shifted comparison value are not negative. These constraints may not be // obvious, but we can prove that they are correct using an SMT solver. if (!Cmp.isSigned() || - (!C2.shl(*C3).isNegative() && !C1.shl(*C3).isNegative())) + (!C2->shl(*C3).isNegative() && !C1->shl(*C3).isNegative())) CanFold = true; } if (CanFold) { - APInt NewCst = IsShl ? C1.lshr(*C3) : C1.shl(*C3); + APInt NewCst = IsShl ? C1->lshr(*C3) : C1->shl(*C3); APInt SameAsC1 = IsShl ? NewCst.shl(*C3) : NewCst.lshr(*C3); // Check to see if we are shifting out any of the bits being compared. - if (SameAsC1 != C1) { + if (SameAsC1 != *C1) { // If we shifted bits out, the fold is not going to work out. As a // special case, check to see if this means that the result is always // true or false now. @@ -1559,7 +1563,7 @@ return replaceInstUsesWith(Cmp, ConstantInt::getTrue(Cmp.getType())); } else { Cmp.setOperand(1, ConstantInt::get(And->getType(), NewCst)); - APInt NewAndCst = IsShl ? C2.lshr(*C3) : C2.shl(*C3); + APInt NewAndCst = IsShl ? C2->lshr(*C3) : C2->shl(*C3); And->setOperand(1, ConstantInt::get(And->getType(), NewAndCst)); And->setOperand(0, Shift->getOperand(0)); Worklist.Add(Shift); // Shift is dead. @@ -1571,7 +1575,7 @@ // Turn ((X >> Y) & C2) == 0 into (X & (C2 << Y)) == 0. The latter is // preferable because it allows the C2 << Y expression to be hoisted out of a // loop if Y is invariant and X is not. - if (Shift->hasOneUse() && C1.isNullValue() && Cmp.isEquality() && + if (Shift->hasOneUse() && C1->isNullValue() && Cmp.isEquality() && !Shift->isArithmeticShift() && !isa(Shift->getOperand(0))) { // Compute C2 << Y. Value *NewShift = @@ -1590,7 +1594,7 @@ /// Fold icmp (and X, C2), C1. Instruction *InstCombiner::foldICmpAndConstConst(ICmpInst &Cmp, BinaryOperator *And, - const APInt &C1) { + const APInt *C1) { const APInt *C2; if (!match(And->getOperand(1), m_APInt(C2))) return nullptr; @@ -1608,28 +1612,28 @@ // when we're checking the sign bit would not work. Value *W; if (match(And->getOperand(0), m_OneUse(m_Trunc(m_Value(W)))) && - (Cmp.isEquality() || (!C1.isNegative() && !C2->isNegative()))) { + (Cmp.isEquality() || (!C1->isNegative() && !C2->isNegative()))) { // TODO: Is this a good transform for vectors? Wider types may reduce // throughput. Should this transform be limited (even for scalars) by using // shouldChangeType()? if (!Cmp.getType()->isVectorTy()) { Type *WideType = W->getType(); unsigned WideScalarBits = WideType->getScalarSizeInBits(); - Constant *ZextC1 = ConstantInt::get(WideType, C1.zext(WideScalarBits)); + Constant *ZextC1 = ConstantInt::get(WideType, C1->zext(WideScalarBits)); Constant *ZextC2 = ConstantInt::get(WideType, C2->zext(WideScalarBits)); Value *NewAnd = Builder.CreateAnd(W, ZextC2, And->getName()); return new ICmpInst(Cmp.getPredicate(), NewAnd, ZextC1); } } - if (Instruction *I = foldICmpAndShift(Cmp, And, C1, *C2)) + if (Instruction *I = foldICmpAndShift(Cmp, And, C1, C2)) return I; // (icmp pred (and (or (lshr A, B), A), 1), 0) --> // (icmp pred (and A, (or (shl 1, B), 1), 0)) // // iff pred isn't signed - if (!Cmp.isSigned() && C1.isNullValue() && And->getOperand(0)->hasOneUse() && + if (!Cmp.isSigned() && C1->isNullValue() && And->getOperand(0)->hasOneUse() && match(And->getOperand(1), m_One())) { Constant *One = cast(And->getOperand(1)); Value *Or = And->getOperand(0); @@ -1669,7 +1673,7 @@ /// Fold icmp (and X, Y), C. Instruction *InstCombiner::foldICmpAndConstant(ICmpInst &Cmp, BinaryOperator *And, - const APInt &C) { + const APInt *C) { if (Instruction *I = foldICmpAndConstConst(Cmp, And, C)) return I; @@ -1694,7 +1698,7 @@ // X & -C == -C -> X > u ~C // X & -C != -C -> X <= u ~C // iff C is a power of 2 - if (Cmp.getOperand(1) == Y && (-C).isPowerOf2()) { + if (Cmp.getOperand(1) == Y && (-(*C)).isPowerOf2()) { auto NewPred = Cmp.getPredicate() == CmpInst::ICMP_EQ ? CmpInst::ICMP_UGT : CmpInst::ICMP_ULE; return new ICmpInst(NewPred, X, SubOne(cast(Cmp.getOperand(1)))); @@ -1704,7 +1708,7 @@ // (X & C2) != 0 -> (trunc X) < 0 // iff C2 is a power of 2 and it masks the sign bit of a legal integer type. const APInt *C2; - if (And->hasOneUse() && C.isNullValue() && match(Y, m_APInt(C2))) { + if (And->hasOneUse() && C->isNullValue() && match(Y, m_APInt(C2))) { int32_t ExactLogBase2 = C2->exactLogBase2(); if (ExactLogBase2 != -1 && DL.isLegalInteger(ExactLogBase2 + 1)) { Type *NTy = IntegerType::get(Cmp.getContext(), ExactLogBase2 + 1); @@ -1722,9 +1726,9 @@ /// Fold icmp (or X, Y), C. Instruction *InstCombiner::foldICmpOrConstant(ICmpInst &Cmp, BinaryOperator *Or, - const APInt &C) { + const APInt *C) { ICmpInst::Predicate Pred = Cmp.getPredicate(); - if (C.isOneValue()) { + if (C->isOneValue()) { // icmp slt signum(V) 1 --> icmp slt V, 1 Value *V = nullptr; if (Pred == ICmpInst::ICMP_SLT && match(Or, m_Signum(m_Value(V)))) @@ -1736,12 +1740,12 @@ // X | C != C --> X >u C // iff C+1 is a power of 2 (C is a bitmask of the low bits) if (Cmp.isEquality() && Cmp.getOperand(1) == Or->getOperand(1) && - (C + 1).isPowerOf2()) { + (*C + 1).isPowerOf2()) { Pred = (Pred == CmpInst::ICMP_EQ) ? CmpInst::ICMP_ULE : CmpInst::ICMP_UGT; return new ICmpInst(Pred, Or->getOperand(0), Or->getOperand(1)); } - if (!Cmp.isEquality() || !C.isNullValue() || !Or->hasOneUse()) + if (!Cmp.isEquality() || !C->isNullValue() || !Or->hasOneUse()) return nullptr; Value *P, *Q; @@ -1775,7 +1779,7 @@ /// Fold icmp (mul X, Y), C. Instruction *InstCombiner::foldICmpMulConstant(ICmpInst &Cmp, BinaryOperator *Mul, - const APInt &C) { + const APInt *C) { const APInt *MulC; if (!match(Mul->getOperand(1), m_APInt(MulC))) return nullptr; @@ -1783,7 +1787,7 @@ // If this is a test of the sign bit and the multiply is sign-preserving with // a constant operand, use the multiply LHS operand instead. ICmpInst::Predicate Pred = Cmp.getPredicate(); - if (isSignTest(Pred, C) && Mul->hasNoSignedWrap()) { + if (isSignTest(Pred, *C) && Mul->hasNoSignedWrap()) { if (MulC->isNegative()) Pred = ICmpInst::getSwappedPredicate(Pred); return new ICmpInst(Pred, Mul->getOperand(0), @@ -1795,14 +1799,14 @@ /// Fold icmp (shl 1, Y), C. static Instruction *foldICmpShlOne(ICmpInst &Cmp, Instruction *Shl, - const APInt &C) { + const APInt *C) { Value *Y; if (!match(Shl, m_Shl(m_One(), m_Value(Y)))) return nullptr; Type *ShiftType = Shl->getType(); - unsigned TypeBits = C.getBitWidth(); - bool CIsPowerOf2 = C.isPowerOf2(); + uint32_t TypeBits = C->getBitWidth(); + bool CIsPowerOf2 = C->isPowerOf2(); ICmpInst::Predicate Pred = Cmp.getPredicate(); if (Cmp.isUnsigned()) { // (1 << Y) pred C -> Y pred Log2(C) @@ -1819,7 +1823,7 @@ // (1 << Y) >= 2147483648 -> Y >= 31 -> Y == 31 // (1 << Y) < 2147483648 -> Y < 31 -> Y != 31 - unsigned CLog2 = C.logBase2(); + unsigned CLog2 = C->logBase2(); if (CLog2 == TypeBits - 1) { if (Pred == ICmpInst::ICMP_UGE) Pred = ICmpInst::ICMP_EQ; @@ -1829,7 +1833,7 @@ return new ICmpInst(Pred, Y, ConstantInt::get(ShiftType, CLog2)); } else if (Cmp.isSigned()) { Constant *BitWidthMinusOne = ConstantInt::get(ShiftType, TypeBits - 1); - if (C.isAllOnesValue()) { + if (C->isAllOnesValue()) { // (1 << Y) <= -1 -> Y == 31 if (Pred == ICmpInst::ICMP_SLE) return new ICmpInst(ICmpInst::ICMP_EQ, Y, BitWidthMinusOne); @@ -1837,7 +1841,7 @@ // (1 << Y) > -1 -> Y != 31 if (Pred == ICmpInst::ICMP_SGT) return new ICmpInst(ICmpInst::ICMP_NE, Y, BitWidthMinusOne); - } else if (!C) { + } else if (!(*C)) { // (1 << Y) < 0 -> Y == 31 // (1 << Y) <= 0 -> Y == 31 if (Pred == ICmpInst::ICMP_SLT || Pred == ICmpInst::ICMP_SLE) @@ -1849,7 +1853,7 @@ return new ICmpInst(ICmpInst::ICMP_NE, Y, BitWidthMinusOne); } } else if (Cmp.isEquality() && CIsPowerOf2) { - return new ICmpInst(Pred, Y, ConstantInt::get(ShiftType, C.logBase2())); + return new ICmpInst(Pred, Y, ConstantInt::get(ShiftType, C->logBase2())); } return nullptr; @@ -1858,10 +1862,10 @@ /// Fold icmp (shl X, Y), C. Instruction *InstCombiner::foldICmpShlConstant(ICmpInst &Cmp, BinaryOperator *Shl, - const APInt &C) { + const APInt *C) { const APInt *ShiftVal; if (Cmp.isEquality() && match(Shl->getOperand(0), m_APInt(ShiftVal))) - return foldICmpShlConstConst(Cmp, Shl->getOperand(1), C, *ShiftVal); + return foldICmpShlConstConst(Cmp, Shl->getOperand(1), *C, *ShiftVal); const APInt *ShiftAmt; if (!match(Shl->getOperand(1), m_APInt(ShiftAmt))) @@ -1869,7 +1873,7 @@ // Check that the shift amount is in range. If not, don't perform undefined // shifts. When the shift is visited, it will be simplified. - unsigned TypeBits = C.getBitWidth(); + unsigned TypeBits = C->getBitWidth(); if (ShiftAmt->uge(TypeBits)) return nullptr; @@ -1883,15 +1887,15 @@ if (Shl->hasNoSignedWrap()) { if (Pred == ICmpInst::ICMP_SGT) { // icmp Pred (shl nsw X, ShiftAmt), C --> icmp Pred X, (C >>s ShiftAmt) - APInt ShiftedC = C.ashr(*ShiftAmt); + APInt ShiftedC = C->ashr(*ShiftAmt); return new ICmpInst(Pred, X, ConstantInt::get(ShType, ShiftedC)); } if (Pred == ICmpInst::ICMP_EQ || Pred == ICmpInst::ICMP_NE) { // This is the same code as the SGT case, but assert the pre-condition // that is needed for this to work with equality predicates. - assert(C.ashr(*ShiftAmt).shl(*ShiftAmt) == C && + assert(C->ashr(*ShiftAmt).shl(*ShiftAmt) == *C && "Compare known true or false was not folded"); - APInt ShiftedC = C.ashr(*ShiftAmt); + APInt ShiftedC = C->ashr(*ShiftAmt); return new ICmpInst(Pred, X, ConstantInt::get(ShType, ShiftedC)); } if (Pred == ICmpInst::ICMP_SLT) { @@ -1899,14 +1903,14 @@ // (X << S) <=s C is equiv to X <=s (C >> S) for all C // (X << S) > S) + 1 if C > S) + 1 if C >s SMIN - assert(!C.isMinSignedValue() && "Unexpected icmp slt"); - APInt ShiftedC = (C - 1).ashr(*ShiftAmt) + 1; + assert(!C->isMinSignedValue() && "Unexpected icmp slt"); + APInt ShiftedC = (*C - 1).ashr(*ShiftAmt) + 1; return new ICmpInst(Pred, X, ConstantInt::get(ShType, ShiftedC)); } // If this is a signed comparison to 0 and the shift is sign preserving, // use the shift LHS operand instead; isSignTest may change 'Pred', so only // do that if we're sure to not continue on in this function. - if (isSignTest(Pred, C)) + if (isSignTest(Pred, *C)) return new ICmpInst(Pred, X, Constant::getNullValue(ShType)); } @@ -1916,15 +1920,15 @@ if (Shl->hasNoUnsignedWrap()) { if (Pred == ICmpInst::ICMP_UGT) { // icmp Pred (shl nuw X, ShiftAmt), C --> icmp Pred X, (C >>u ShiftAmt) - APInt ShiftedC = C.lshr(*ShiftAmt); + APInt ShiftedC = C->lshr(*ShiftAmt); return new ICmpInst(Pred, X, ConstantInt::get(ShType, ShiftedC)); } if (Pred == ICmpInst::ICMP_EQ || Pred == ICmpInst::ICMP_NE) { // This is the same code as the UGT case, but assert the pre-condition // that is needed for this to work with equality predicates. - assert(C.lshr(*ShiftAmt).shl(*ShiftAmt) == C && + assert(C->lshr(*ShiftAmt).shl(*ShiftAmt) == *C && "Compare known true or false was not folded"); - APInt ShiftedC = C.lshr(*ShiftAmt); + APInt ShiftedC = C->lshr(*ShiftAmt); return new ICmpInst(Pred, X, ConstantInt::get(ShType, ShiftedC)); } if (Pred == ICmpInst::ICMP_ULT) { @@ -1932,8 +1936,8 @@ // (X << S) <=u C is equiv to X <=u (C >> S) for all C // (X << S) > S) + 1 if C > S) + 1 if C >u 0 - assert(C.ugt(0) && "ult 0 should have been eliminated"); - APInt ShiftedC = (C - 1).lshr(*ShiftAmt) + 1; + assert(C->ugt(0) && "ult 0 should have been eliminated"); + APInt ShiftedC = (*C - 1).lshr(*ShiftAmt) + 1; return new ICmpInst(Pred, X, ConstantInt::get(ShType, ShiftedC)); } } @@ -1944,13 +1948,13 @@ ShType, APInt::getLowBitsSet(TypeBits, TypeBits - ShiftAmt->getZExtValue())); Value *And = Builder.CreateAnd(X, Mask, Shl->getName() + ".mask"); - Constant *LShrC = ConstantInt::get(ShType, C.lshr(*ShiftAmt)); + Constant *LShrC = ConstantInt::get(ShType, C->lshr(*ShiftAmt)); return new ICmpInst(Pred, And, LShrC); } // Otherwise, if this is a comparison of the sign bit, simplify to and/test. bool TrueIfSigned = false; - if (Shl->hasOneUse() && isSignBitCheck(Pred, C, TrueIfSigned)) { + if (Shl->hasOneUse() && isSignBitCheck(Pred, *C, TrueIfSigned)) { // (X << 31) (X & 1) != 0 Constant *Mask = ConstantInt::get( ShType, @@ -1967,13 +1971,13 @@ // free on the target. It has the additional benefit of comparing to a // smaller constant that may be more target-friendly. unsigned Amt = ShiftAmt->getLimitedValue(TypeBits - 1); - if (Shl->hasOneUse() && Amt != 0 && C.countTrailingZeros() >= Amt && + if (Shl->hasOneUse() && Amt != 0 && C->countTrailingZeros() >= Amt && DL.isLegalInteger(TypeBits - Amt)) { Type *TruncTy = IntegerType::get(Cmp.getContext(), TypeBits - Amt); if (ShType->isVectorTy()) TruncTy = VectorType::get(TruncTy, ShType->getVectorNumElements()); Constant *NewC = - ConstantInt::get(TruncTy, C.ashr(*ShiftAmt).trunc(TypeBits - Amt)); + ConstantInt::get(TruncTy, C->ashr(*ShiftAmt).trunc(TypeBits - Amt)); return new ICmpInst(Pred, Builder.CreateTrunc(X, TruncTy), NewC); } @@ -1983,18 +1987,18 @@ /// Fold icmp ({al}shr X, Y), C. Instruction *InstCombiner::foldICmpShrConstant(ICmpInst &Cmp, BinaryOperator *Shr, - const APInt &C) { + const APInt *C) { // An exact shr only shifts out zero bits, so: // icmp eq/ne (shr X, Y), 0 --> icmp eq/ne X, 0 Value *X = Shr->getOperand(0); CmpInst::Predicate Pred = Cmp.getPredicate(); if (Cmp.isEquality() && Shr->isExact() && Shr->hasOneUse() && - C.isNullValue()) + C->isNullValue()) return new ICmpInst(Pred, X, Cmp.getOperand(1)); const APInt *ShiftVal; if (Cmp.isEquality() && match(Shr->getOperand(0), m_APInt(ShiftVal))) - return foldICmpShrConstConst(Cmp, Shr->getOperand(1), C, *ShiftVal); + return foldICmpShrConstConst(Cmp, Shr->getOperand(1), *C, *ShiftVal); const APInt *ShiftAmt; if (!match(Shr->getOperand(1), m_APInt(ShiftAmt))) @@ -2002,7 +2006,7 @@ // Check that the shift amount is in range. If not, don't perform undefined // shifts. When the shift is visited it will be simplified. - unsigned TypeBits = C.getBitWidth(); + unsigned TypeBits = C->getBitWidth(); unsigned ShAmtVal = ShiftAmt->getLimitedValue(TypeBits); if (ShAmtVal >= TypeBits || ShAmtVal == 0) return nullptr; @@ -2050,13 +2054,13 @@ // If the comparison constant changes with the shift, the comparison cannot // succeed (bits of the comparison constant cannot match the shifted value). // This should be known by InstSimplify and already be folded to true/false. - assert(((IsAShr && C.shl(ShAmtVal).ashr(ShAmtVal) == C) || - (!IsAShr && C.shl(ShAmtVal).lshr(ShAmtVal) == C)) && + assert(((IsAShr && C->shl(ShAmtVal).ashr(ShAmtVal) == *C) || + (!IsAShr && C->shl(ShAmtVal).lshr(ShAmtVal) == *C)) && "Expected icmp+shr simplify did not occur."); // If the bits shifted out are known zero, compare the unshifted value: // (X & 4) >> 1 == 2 --> (X & 4) == 4. - Constant *ShiftedCmpRHS = ConstantInt::get(Shr->getType(), C << ShAmtVal); + Constant *ShiftedCmpRHS = ConstantInt::get(Shr->getType(), *C << ShAmtVal); if (Shr->isExact()) return new ICmpInst(Pred, X, ShiftedCmpRHS); @@ -2075,7 +2079,7 @@ /// Fold icmp (udiv X, Y), C. Instruction *InstCombiner::foldICmpUDivConstant(ICmpInst &Cmp, BinaryOperator *UDiv, - const APInt &C) { + const APInt *C) { const APInt *C2; if (!match(UDiv->getOperand(0), m_APInt(C2))) return nullptr; @@ -2085,17 +2089,17 @@ // (icmp ugt (udiv C2, Y), C) -> (icmp ule Y, C2/(C+1)) Value *Y = UDiv->getOperand(1); if (Cmp.getPredicate() == ICmpInst::ICMP_UGT) { - assert(!C.isMaxValue() && + assert(!C->isMaxValue() && "icmp ugt X, UINT_MAX should have been simplified already."); return new ICmpInst(ICmpInst::ICMP_ULE, Y, - ConstantInt::get(Y->getType(), C2->udiv(C + 1))); + ConstantInt::get(Y->getType(), C2->udiv(*C + 1))); } // (icmp ult (udiv C2, Y), C) -> (icmp ugt Y, C2/C) if (Cmp.getPredicate() == ICmpInst::ICMP_ULT) { - assert(C != 0 && "icmp ult X, 0 should have been simplified already."); + assert(*C != 0 && "icmp ult X, 0 should have been simplified already."); return new ICmpInst(ICmpInst::ICMP_UGT, Y, - ConstantInt::get(Y->getType(), C2->udiv(C))); + ConstantInt::get(Y->getType(), C2->udiv(*C))); } return nullptr; @@ -2104,7 +2108,7 @@ /// Fold icmp ({su}div X, Y), C. Instruction *InstCombiner::foldICmpDivConstant(ICmpInst &Cmp, BinaryOperator *Div, - const APInt &C) { + const APInt *C) { // Fold: icmp pred ([us]div X, C2), C -> range test // Fold this div into the comparison, producing a range check. // Determine, based on the divide type, what the range is being @@ -2139,12 +2143,12 @@ // form X / C2 = C. We solve for X by multiplying C2 and C. // By solving for X, we can turn this into a range check instead of computing // a divide. - APInt Prod = C * *C2; + APInt Prod = *C * *C2; // Determine if the product overflows by seeing if the product is not equal to // the divide. Make sure we do the same kind of divide as in the LHS // instruction that we're folding. - bool ProdOV = (DivIsSigned ? Prod.sdiv(*C2) : Prod.udiv(*C2)) != C; + bool ProdOV = (DivIsSigned ? Prod.sdiv(*C2) : Prod.udiv(*C2)) != *C; ICmpInst::Predicate Pred = Cmp.getPredicate(); @@ -2172,11 +2176,11 @@ HiOverflow = addWithOverflow(HiBound, LoBound, RangeSize, false); } } else if (C2->isStrictlyPositive()) { // Divisor is > 0. - if (C.isNullValue()) { // (X / pos) op 0 + if (C->isNullValue()) { // (X / pos) op 0 // Can't overflow. e.g. X/2 op 0 --> [-1, 2) LoBound = -(RangeSize - 1); HiBound = RangeSize; - } else if (C.isStrictlyPositive()) { // (X / pos) op pos + } else if (C->isStrictlyPositive()) { // (X / pos) op pos LoBound = Prod; // e.g. X/5 op 3 --> [15, 20) HiOverflow = LoOverflow = ProdOV; if (!HiOverflow) @@ -2193,7 +2197,7 @@ } else if (C2->isNegative()) { // Divisor is < 0. if (Div->isExact()) RangeSize.negate(); - if (C.isNullValue()) { // (X / neg) op 0 + if (C->isNullValue()) { // (X / neg) op 0 // e.g. X/-5 op 0 --> [-4, 5) LoBound = RangeSize + 1; HiBound = -RangeSize; @@ -2201,7 +2205,7 @@ HiOverflow = 1; // [INTMIN+1, overflow) HiBound = APInt(); // e.g. X/INTMIN = 0 --> X > INTMIN } - } else if (C.isStrictlyPositive()) { // (X / neg) op pos + } else if (C->isStrictlyPositive()) { // (X / neg) op pos // e.g. X/-5 op 3 --> [-19, -14) HiBound = Prod + 1; HiOverflow = LoOverflow = ProdOV ? -1 : 0; @@ -2274,7 +2278,7 @@ /// Fold icmp (sub X, Y), C. Instruction *InstCombiner::foldICmpSubConstant(ICmpInst &Cmp, BinaryOperator *Sub, - const APInt &C) { + const APInt *C) { Value *X = Sub->getOperand(0), *Y = Sub->getOperand(1); ICmpInst::Predicate Pred = Cmp.getPredicate(); @@ -2285,19 +2289,19 @@ if (Sub->hasNoSignedWrap()) { // (icmp sgt (sub nsw X, Y), -1) -> (icmp sge X, Y) - if (Pred == ICmpInst::ICMP_SGT && C.isAllOnesValue()) + if (Pred == ICmpInst::ICMP_SGT && C->isAllOnesValue()) return new ICmpInst(ICmpInst::ICMP_SGE, X, Y); // (icmp sgt (sub nsw X, Y), 0) -> (icmp sgt X, Y) - if (Pred == ICmpInst::ICMP_SGT && C.isNullValue()) + if (Pred == ICmpInst::ICMP_SGT && C->isNullValue()) return new ICmpInst(ICmpInst::ICMP_SGT, X, Y); // (icmp slt (sub nsw X, Y), 0) -> (icmp slt X, Y) - if (Pred == ICmpInst::ICMP_SLT && C.isNullValue()) + if (Pred == ICmpInst::ICMP_SLT && C->isNullValue()) return new ICmpInst(ICmpInst::ICMP_SLT, X, Y); // (icmp slt (sub nsw X, Y), 1) -> (icmp sle X, Y) - if (Pred == ICmpInst::ICMP_SLT && C.isOneValue()) + if (Pred == ICmpInst::ICMP_SLT && C->isOneValue()) return new ICmpInst(ICmpInst::ICMP_SLE, X, Y); } @@ -2307,14 +2311,14 @@ // C2 - Y (Y | (C - 1)) == C2 // iff (C2 & (C - 1)) == C - 1 and C is a power of 2 - if (Pred == ICmpInst::ICMP_ULT && C.isPowerOf2() && - (*C2 & (C - 1)) == (C - 1)) - return new ICmpInst(ICmpInst::ICMP_EQ, Builder.CreateOr(Y, C - 1), X); + if (Pred == ICmpInst::ICMP_ULT && C->isPowerOf2() && + (*C2 & (*C - 1)) == (*C - 1)) + return new ICmpInst(ICmpInst::ICMP_EQ, Builder.CreateOr(Y, *C - 1), X); // C2 - Y >u C -> (Y | C) != C2 // iff C2 & C == C and C + 1 is a power of 2 - if (Pred == ICmpInst::ICMP_UGT && (C + 1).isPowerOf2() && (*C2 & C) == C) - return new ICmpInst(ICmpInst::ICMP_NE, Builder.CreateOr(Y, C), X); + if (Pred == ICmpInst::ICMP_UGT && (*C + 1).isPowerOf2() && (*C2 & *C) == *C) + return new ICmpInst(ICmpInst::ICMP_NE, Builder.CreateOr(Y, *C), X); return nullptr; } @@ -2322,7 +2326,7 @@ /// Fold icmp (add X, Y), C. Instruction *InstCombiner::foldICmpAddConstant(ICmpInst &Cmp, BinaryOperator *Add, - const APInt &C) { + const APInt *C) { Value *Y = Add->getOperand(1); const APInt *C2; if (Cmp.isEquality() || !match(Y, m_APInt(C2))) @@ -2339,7 +2343,7 @@ if (Add->hasNoSignedWrap() && (Pred == ICmpInst::ICMP_SGT || Pred == ICmpInst::ICMP_SLT)) { bool Overflow; - APInt NewC = C.ssub_ov(*C2, Overflow); + APInt NewC = C->ssub_ov(*C2, Overflow); // If there is overflow, the result must be true or false. // TODO: Can we assert there is no overflow because InstSimplify always // handles those cases? @@ -2348,7 +2352,7 @@ return new ICmpInst(Pred, X, ConstantInt::get(Ty, NewC)); } - auto CR = ConstantRange::makeExactICmpRegion(Pred, C).subtract(*C2); + auto CR = ConstantRange::makeExactICmpRegion(Pred, *C).subtract(*C2); const APInt &Upper = CR.getUpper(); const APInt &Lower = CR.getLower(); if (Cmp.isSigned()) { @@ -2369,15 +2373,15 @@ // X+C (X & -C2) == C // iff C & (C2-1) == 0 // C2 is a power of 2 - if (Pred == ICmpInst::ICMP_ULT && C.isPowerOf2() && (*C2 & (C - 1)) == 0) - return new ICmpInst(ICmpInst::ICMP_EQ, Builder.CreateAnd(X, -C), + if (Pred == ICmpInst::ICMP_ULT && C->isPowerOf2() && (*C2 & (*C - 1)) == 0) + return new ICmpInst(ICmpInst::ICMP_EQ, Builder.CreateAnd(X, -(*C)), ConstantExpr::getNeg(cast(Y))); // X+C >u C2 -> (X & ~C2) != C // iff C & C2 == 0 // C2+1 is a power of 2 - if (Pred == ICmpInst::ICMP_UGT && (C + 1).isPowerOf2() && (*C2 & C) == 0) - return new ICmpInst(ICmpInst::ICMP_NE, Builder.CreateAnd(X, ~C), + if (Pred == ICmpInst::ICMP_UGT && (*C + 1).isPowerOf2() && (*C2 & *C) == 0) + return new ICmpInst(ICmpInst::ICMP_NE, Builder.CreateAnd(X, ~(*C)), ConstantExpr::getNeg(cast(Y))); return nullptr; @@ -2464,51 +2468,51 @@ if (auto *BO = dyn_cast(Cmp.getOperand(0))) { switch (BO->getOpcode()) { case Instruction::Xor: - if (Instruction *I = foldICmpXorConstant(Cmp, BO, *C)) + if (Instruction *I = foldICmpXorConstant(Cmp, BO, C)) return I; break; case Instruction::And: - if (Instruction *I = foldICmpAndConstant(Cmp, BO, *C)) + if (Instruction *I = foldICmpAndConstant(Cmp, BO, C)) return I; break; case Instruction::Or: - if (Instruction *I = foldICmpOrConstant(Cmp, BO, *C)) + if (Instruction *I = foldICmpOrConstant(Cmp, BO, C)) return I; break; case Instruction::Mul: - if (Instruction *I = foldICmpMulConstant(Cmp, BO, *C)) + if (Instruction *I = foldICmpMulConstant(Cmp, BO, C)) return I; break; case Instruction::Shl: - if (Instruction *I = foldICmpShlConstant(Cmp, BO, *C)) + if (Instruction *I = foldICmpShlConstant(Cmp, BO, C)) return I; break; case Instruction::LShr: case Instruction::AShr: - if (Instruction *I = foldICmpShrConstant(Cmp, BO, *C)) + if (Instruction *I = foldICmpShrConstant(Cmp, BO, C)) return I; break; case Instruction::UDiv: - if (Instruction *I = foldICmpUDivConstant(Cmp, BO, *C)) + if (Instruction *I = foldICmpUDivConstant(Cmp, BO, C)) return I; LLVM_FALLTHROUGH; case Instruction::SDiv: - if (Instruction *I = foldICmpDivConstant(Cmp, BO, *C)) + if (Instruction *I = foldICmpDivConstant(Cmp, BO, C)) return I; break; case Instruction::Sub: - if (Instruction *I = foldICmpSubConstant(Cmp, BO, *C)) + if (Instruction *I = foldICmpSubConstant(Cmp, BO, C)) return I; break; case Instruction::Add: - if (Instruction *I = foldICmpAddConstant(Cmp, BO, *C)) + if (Instruction *I = foldICmpAddConstant(Cmp, BO, C)) return I; break; default: break; } // TODO: These folds could be refactored to be part of the above calls. - if (Instruction *I = foldICmpBinOpEqualityWithConstant(Cmp, BO, *C)) + if (Instruction *I = foldICmpBinOpEqualityWithConstant(Cmp, BO, C)) return I; } @@ -2524,11 +2528,11 @@ } if (auto *TI = dyn_cast(Cmp.getOperand(0))) { - if (Instruction *I = foldICmpTruncConstant(Cmp, TI, *C)) + if (Instruction *I = foldICmpTruncConstant(Cmp, TI, C)) return I; } - if (Instruction *I = foldICmpIntrinsicWithConstant(Cmp, *C)) + if (Instruction *I = foldICmpIntrinsicWithConstant(Cmp, C)) return I; return nullptr; @@ -2538,7 +2542,7 @@ /// icmp eq/ne BO, C. Instruction *InstCombiner::foldICmpBinOpEqualityWithConstant(ICmpInst &Cmp, BinaryOperator *BO, - const APInt &C) { + const APInt *C) { // TODO: Some of these folds could work with arbitrary constants, but this // function is limited to scalar and vector splat constants. if (!Cmp.isEquality()) @@ -2552,7 +2556,7 @@ switch (BO->getOpcode()) { case Instruction::SRem: // If we have a signed (X % (2^c)) == 0, turn it into an unsigned one. - if (C.isNullValue() && BO->hasOneUse()) { + if (C->isNullValue() && BO->hasOneUse()) { const APInt *BOC; if (match(BOp1, m_APInt(BOC)) && BOC->sgt(1) && BOC->isPowerOf2()) { Value *NewRem = Builder.CreateURem(BOp0, BOp1, BO->getName()); @@ -2569,7 +2573,7 @@ Constant *SubC = ConstantExpr::getSub(RHS, cast(BOp1)); return new ICmpInst(Pred, BOp0, SubC); } - } else if (C.isNullValue()) { + } else if (C->isNullValue()) { // Replace ((add A, B) != 0) with (A != -B) if A or B is // efficiently invertible, or if the add has just this one use. if (Value *NegVal = dyn_castNegVal(BOp1)) @@ -2590,7 +2594,7 @@ // For the xor case, we can xor two constants together, eliminating // the explicit xor. return new ICmpInst(Pred, BOp0, ConstantExpr::getXor(RHS, BOC)); - } else if (C.isNullValue()) { + } else if (C->isNullValue()) { // Replace ((xor A, B) != 0) with (A != B) return new ICmpInst(Pred, BOp0, BOp1); } @@ -2603,7 +2607,7 @@ // Replace ((sub BOC, B) != C) with (B != BOC-C). Constant *SubC = ConstantExpr::getSub(cast(BOp0), RHS); return new ICmpInst(Pred, BOp1, SubC); - } else if (C.isNullValue()) { + } else if (C->isNullValue()) { // Replace ((sub A, B) != 0) with (A != B). return new ICmpInst(Pred, BOp0, BOp1); } @@ -2625,7 +2629,7 @@ const APInt *BOC; if (match(BOp1, m_APInt(BOC))) { // If we have ((X & C) == C), turn it into ((X & C) != 0). - if (C == *BOC && C.isPowerOf2()) + if (C == BOC && C->isPowerOf2()) return new ICmpInst(isICMP_NE ? ICmpInst::ICMP_EQ : ICmpInst::ICMP_NE, BO, Constant::getNullValue(RHS->getType())); @@ -2641,7 +2645,7 @@ } // ((X & ~7) == 0) --> X < 8 - if (C.isNullValue() && (~(*BOC) + 1).isPowerOf2()) { + if (C->isNullValue() && (~(*BOC) + 1).isPowerOf2()) { Constant *NegBOC = ConstantExpr::getNeg(cast(BOp1)); auto NewPred = isICMP_NE ? ICmpInst::ICMP_UGE : ICmpInst::ICMP_ULT; return new ICmpInst(NewPred, BOp0, NegBOC); @@ -2650,7 +2654,7 @@ break; } case Instruction::Mul: - if (C.isNullValue() && BO->hasNoSignedWrap()) { + if (C->isNullValue() && BO->hasNoSignedWrap()) { const APInt *BOC; if (match(BOp1, m_APInt(BOC)) && !BOC->isNullValue()) { // The trivial case (mul X, 0) is handled by InstSimplify. @@ -2661,7 +2665,7 @@ } break; case Instruction::UDiv: - if (C.isNullValue()) { + if (C->isNullValue()) { // (icmp eq/ne (udiv A, B), 0) -> (icmp ugt/ule i32 B, A) auto NewPred = isICMP_NE ? ICmpInst::ICMP_ULE : ICmpInst::ICMP_UGT; return new ICmpInst(NewPred, BOp1, BOp0); @@ -2675,7 +2679,7 @@ /// Fold an icmp with LLVM intrinsic and constant operand: icmp Pred II, C. Instruction *InstCombiner::foldICmpIntrinsicWithConstant(ICmpInst &Cmp, - const APInt &C) { + const APInt *C) { IntrinsicInst *II = dyn_cast(Cmp.getOperand(0)); if (!II || !Cmp.isEquality()) return nullptr; @@ -2686,13 +2690,13 @@ case Intrinsic::bswap: Worklist.Add(II); Cmp.setOperand(0, II->getArgOperand(0)); - Cmp.setOperand(1, ConstantInt::get(Ty, C.byteSwap())); + Cmp.setOperand(1, ConstantInt::get(Ty, C->byteSwap())); return &Cmp; case Intrinsic::ctlz: case Intrinsic::cttz: // ctz(A) == bitwidth(A) -> A == 0 and likewise for != - if (C == C.getBitWidth()) { + if (*C == C->getBitWidth()) { Worklist.Add(II); Cmp.setOperand(0, II->getArgOperand(0)); Cmp.setOperand(1, ConstantInt::getNullValue(Ty)); @@ -2703,8 +2707,8 @@ case Intrinsic::ctpop: { // popcount(A) == 0 -> A == 0 and likewise for != // popcount(A) == bitwidth(A) -> A == -1 and likewise for != - bool IsZero = C.isNullValue(); - if (IsZero || C == C.getBitWidth()) { + bool IsZero = C->isNullValue(); + if (IsZero || *C == C->getBitWidth()) { Worklist.Add(II); Cmp.setOperand(0, II->getArgOperand(0)); auto *NewOp = Index: lib/Transforms/InstCombine/InstCombineInternal.h =================================================================== --- lib/Transforms/InstCombine/InstCombineInternal.h +++ lib/Transforms/InstCombine/InstCombineInternal.h @@ -698,31 +698,31 @@ Instruction *foldICmpSelectConstant(ICmpInst &Cmp, SelectInst *Select, ConstantInt *C); Instruction *foldICmpTruncConstant(ICmpInst &Cmp, TruncInst *Trunc, - const APInt &C); + const APInt *C); Instruction *foldICmpAndConstant(ICmpInst &Cmp, BinaryOperator *And, - const APInt &C); + const APInt *C); Instruction *foldICmpXorConstant(ICmpInst &Cmp, BinaryOperator *Xor, - const APInt &C); + const APInt *C); Instruction *foldICmpOrConstant(ICmpInst &Cmp, BinaryOperator *Or, - const APInt &C); + const APInt *C); Instruction *foldICmpMulConstant(ICmpInst &Cmp, BinaryOperator *Mul, - const APInt &C); + const APInt *C); Instruction *foldICmpShlConstant(ICmpInst &Cmp, BinaryOperator *Shl, - const APInt &C); + const APInt *C); Instruction *foldICmpShrConstant(ICmpInst &Cmp, BinaryOperator *Shr, - const APInt &C); + const APInt *C); Instruction *foldICmpUDivConstant(ICmpInst &Cmp, BinaryOperator *UDiv, - const APInt &C); + const APInt *C); Instruction *foldICmpDivConstant(ICmpInst &Cmp, BinaryOperator *Div, - const APInt &C); + const APInt *C); Instruction *foldICmpSubConstant(ICmpInst &Cmp, BinaryOperator *Sub, - const APInt &C); + const APInt *C); Instruction *foldICmpAddConstant(ICmpInst &Cmp, BinaryOperator *Add, - const APInt &C); + const APInt *C); Instruction *foldICmpAndConstConst(ICmpInst &Cmp, BinaryOperator *And, - const APInt &C1); + const APInt *C1); Instruction *foldICmpAndShift(ICmpInst &Cmp, BinaryOperator *And, - const APInt &C1, const APInt &C2); + const APInt *C1, const APInt *C2); Instruction *foldICmpShrConstConst(ICmpInst &I, Value *ShAmt, const APInt &C1, const APInt &C2); Instruction *foldICmpShlConstConst(ICmpInst &I, Value *ShAmt, const APInt &C1, @@ -730,8 +730,8 @@ Instruction *foldICmpBinOpEqualityWithConstant(ICmpInst &Cmp, BinaryOperator *BO, - const APInt &C); - Instruction *foldICmpIntrinsicWithConstant(ICmpInst &ICI, const APInt &C); + const APInt *C); + Instruction *foldICmpIntrinsicWithConstant(ICmpInst &ICI, const APInt *C); // Helpers of visitSelectInst(). Instruction *foldSelectExtConst(SelectInst &Sel); Index: test/Analysis/CostModel/X86/trunc.ll =================================================================== --- test/Analysis/CostModel/X86/trunc.ll +++ test/Analysis/CostModel/X86/trunc.ll @@ -36,7 +36,6 @@ define i32 @trunc_vXi16() { ; SSE: cost of 0 {{.*}} %V2i64 = trunc ; AVX: cost of 0 {{.*}} %V2i64 = trunc - ; AVX512: cost of 0 {{.*}} %V2i64 = trunc %V2i64 = trunc <2 x i64> undef to <2 x i16> ; SSE: cost of 1 {{.*}} %V4i64 = trunc @@ -47,7 +46,6 @@ ; SSE: cost of 3 {{.*}} %V8i64 = trunc ; AVX: cost of 0 {{.*}} %V8i64 = trunc - ; AVX512: cost of 1 {{.*}} %V8i64 = trunc %V8i64 = trunc <8 x i64> undef to <8 x i16> ; SSE2: cost of 3 {{.*}} %V4i32 = trunc @@ -81,7 +79,6 @@ define i32 @trunc_vXi8() { ; SSE: cost of 0 {{.*}} %V2i64 = trunc ; AVX: cost of 0 {{.*}} %V2i64 = trunc - ; AVX512: cost of 0 {{.*}} %V2i64 = trunc %V2i64 = trunc <2 x i64> undef to <2 x i8> ; SSE: cost of 1 {{.*}} %V4i64 = trunc @@ -92,19 +89,16 @@ ; SSE: cost of 3 {{.*}} %V8i64 = trunc ; AVX: cost of 0 {{.*}} %V8i64 = trunc - ; AVX512: cost of 0 {{.*}} %V8i64 = trunc %V8i64 = trunc <8 x i64> undef to <8 x i8> ; SSE: cost of 0 {{.*}} %V2i32 = trunc ; AVX: cost of 0 {{.*}} %V2i32 = trunc - ; AVX512: cost of 0 {{.*}} %V2i32 = trunc %V2i32 = trunc <2 x i32> undef to <2 x i8> ; SSE2: cost of 3 {{.*}} %V4i32 = trunc ; SSSE3: cost of 3 {{.*}} %V4i32 = trunc ; SSE42: cost of 1 {{.*}} %V4i32 = trunc ; AVX: cost of 1 {{.*}} %V4i32 = trunc - ; AVX512: cost of 1 {{.*}} %V4i32 = trunc %V4i32 = trunc <4 x i32> undef to <4 x i8> ; SSE2: cost of 4 {{.*}} %V8i32 = trunc @@ -117,37 +111,30 @@ ; SSE: cost of 7 {{.*}} %V16i32 = trunc ; AVX: cost of 7 {{.*}} %V16i32 = trunc - ; AVX512: cost of 1 {{.*}} %V16i32 = trunc %V16i32 = trunc <16 x i32> undef to <16 x i8> ; SSE: cost of 0 {{.*}} %V2i16 = trunc ; AVX: cost of 0 {{.*}} %V2i16 = trunc - ; AVX512: cost of 0 {{.*}} %V2i16 = trunc %V2i16 = trunc <2 x i16> undef to <2 x i8> ; SSE2: cost of 4 {{.*}} %V4i16 = trunc ; SSSE3: cost of 4 {{.*}} %V4i16 = trunc ; SSE42: cost of 2 {{.*}} %V4i16 = trunc ; AVX: cost of 2 {{.*}} %V4i16 = trunc - ; AVX512: cost of 2 {{.*}} %V4i16 = trunc %V4i16 = trunc <4 x i16> undef to <4 x i8> ; SSE2: cost of 2 {{.*}} %V8i16 = trunc ; SSSE3: cost of 2 {{.*}} %V8i16 = trunc ; SSE42: cost of 1 {{.*}} %V8i16 = trunc ; AVX: cost of 1 {{.*}} %V8i16 = trunc - ; AVX512: cost of 1 {{.*}} %V8i16 = trunc %V8i16 = trunc <8 x i16> undef to <8 x i8> ; SSE: cost of 3 {{.*}} %V16i16 = trunc ; AVX: cost of 4 {{.*}} %V16i16 = trunc - ; AVX512: cost of 4 {{.*}} %V16i16 = trunc %V16i16 = trunc <16 x i16> undef to <16 x i8> ; SSE: cost of 7 {{.*}} %V32i16 = trunc ; AVX: cost of 9 {{.*}} %V32i16 = trunc - ; AVX512F: cost of 9 {{.*}} %V32i16 = trunc - ; AVX512BW: cost of 0 {{.*}} %V32i16 = trunc %V32i16 = trunc <32 x i16> undef to <32 x i8> ret i32 undef Index: test/Analysis/GlobalsModRef/memset-escape.ll =================================================================== --- test/Analysis/GlobalsModRef/memset-escape.ll +++ test/Analysis/GlobalsModRef/memset-escape.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -O1 -S | FileCheck %s +; RUN: opt < %s -O1 -S -enable-non-lto-gmr=true | FileCheck %s target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.10.0" Index: test/Analysis/GlobalsModRef/no-escape.ll =================================================================== --- test/Analysis/GlobalsModRef/no-escape.ll +++ test/Analysis/GlobalsModRef/no-escape.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -basicaa -globals-aa -S -licm | FileCheck %s +; RUN: opt < %s -basicaa -globals-aa -S -enable-non-lto-gmr=true -licm | FileCheck %s target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.10.0" Index: test/Analysis/GlobalsModRef/weak-interposition.ll =================================================================== --- test/Analysis/GlobalsModRef/weak-interposition.ll +++ test/Analysis/GlobalsModRef/weak-interposition.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -O1 < %s | FileCheck %s +; RUN: opt -S -O1 -enable-non-lto-gmr=true < %s | FileCheck %s @a = common global i32 0, align 4 Index: test/Analysis/Lint/noop-cast-expr-no-pointer.ll =================================================================== --- test/Analysis/Lint/noop-cast-expr-no-pointer.ll +++ /dev/null @@ -1,23 +0,0 @@ -; RUN: opt -lint < %s - -; lint shouldn't crash on any of the below functions - -@g_1 = external global [3 x i32] -@g_2 = external global [2 x i32] - -define void @test1() { -entry: - tail call void @f1(i16 zext (i1 icmp eq (i32* getelementptr inbounds ([2 x i32], [2 x i32]* @g_2, i64 0, i64 0), i32* getelementptr inbounds ([3 x i32], [3 x i32]* @g_1, i64 0, i64 1)) to i16)) - ret void -} - -declare void @f1(i16) - -define void @test2() { - tail call void inttoptr (i64 sext (i32 ptrtoint (void ()* @f2 to i32) to i64) to void ()*)() - - ret void -} - -declare void @f2() - Index: test/CodeGen/AArch64/GlobalISel/legalize-or.mir =================================================================== --- test/CodeGen/AArch64/GlobalISel/legalize-or.mir +++ test/CodeGen/AArch64/GlobalISel/legalize-or.mir @@ -1,4 +1,13 @@ -# RUN: llc -O0 -mtriple=aarch64-apple-ios -run-pass=legalizer -global-isel %s -o - | FileCheck %s +# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s + +--- | + target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" + target triple = "aarch64--" + define void @test_scalar_or_small() { + entry: + ret void + } +... --- name: test_scalar_or_small @@ -10,7 +19,7 @@ - { id: 4, class: _ } - { id: 5, class: _ } body: | - bb.0: + bb.0.entry: liveins: %x0, %x1, %x2, %x3 ; CHECK-LABEL: name: test_scalar_or_small ; CHECK: [[OP0:%.*]](s32) = G_TRUNC %0 @@ -26,49 +35,3 @@ %5(s64) = G_ANYEXT %2 %x0 = COPY %5 ... - ---- -name: test_big_scalar_power_of_2 -registers: - - { id: 0, class: _ } - - { id: 1, class: _ } - - { id: 2, class: _ } - - { id: 3, class: _ } - - { id: 4, class: _ } - - { id: 5, class: _ } - - { id: 6, class: _ } - - { id: 7, class: _ } - - { id: 8, class: _ } -body: | - bb.0: - liveins: %x0, %x1, %x2, %x3 - ; CHECK-LABEL: name: test_big_scalar_power_of_2 - ; CHECK: [[OP0_0:%.*]](s64) = COPY %x0 - ; CHECK-NEXT: [[OP0_1:%.*]](s64) = COPY %x1 - ; CHECK-NEXT: [[OP1_0:%.*]](s64) = COPY %x2 - ; CHECK-NEXT: [[OP1_1:%.*]](s64) = COPY %x3 - ; CHECK-NEXT: [[RES_0:%.*]](s64) = G_OR [[OP0_0]], [[OP1_0]] - ; CHECK-NEXT: [[RES_1:%.*]](s64) = G_OR [[OP0_1]], [[OP1_1]] - ; We have a temporary G_MERGE_VALUES in the legalizer - ; that gets cleaned up with the G_UNMERGE_VALUES. - ; Thus, - ; tmp = G_MERGE_VALUES [[RES_0]], [[RES_1]] - ; %7, %8 = G_UNMERGE_VALUES tmp - ; %x0 = COPY %7 - ; %x1 = COPY %8 - ; translates into - ; CHECK-NEXT: %x0 = COPY [[RES_0]] - ; CHECK-NEXT: %x1 = COPY [[RES_1]] - - %0(s64) = COPY %x0 - %1(s64) = COPY %x1 - %2(s64) = COPY %x2 - %3(s64) = COPY %x3 - %4(s128) = G_MERGE_VALUES %0, %1 - %5(s128) = G_MERGE_VALUES %2, %3 - %6(s128) = G_OR %4, %5 - %7(s64), %8(s64) = G_UNMERGE_VALUES %6 - %x0 = COPY %7 - %x1 = COPY %8 - RET_ReallyLR implicit %x0, implicit %x1 -... Index: test/CodeGen/AArch64/machine-outliner-remarks.ll =================================================================== --- test/CodeGen/AArch64/machine-outliner-remarks.ll +++ test/CodeGen/AArch64/machine-outliner-remarks.ll @@ -1,7 +1,7 @@ ; RUN: llc %s -enable-machine-outliner -mtriple=aarch64-unknown-unknown -pass-remarks-missed=machine-outliner -o /dev/null 2>&1 | FileCheck %s ; CHECK: machine-outliner-remarks.ll:5:9: ; CHECK-SAME: Did not outline 2 instructions from 2 locations. -; CHECK-SAME: Instructions from outlining all occurrences (9) >= +; CHECK-SAME: Instructions from outlining all occurrences (7) >= ; CHECK-SAME: Unoutlined instruction count (4) ; CHECK-SAME: (Also found at: machine-outliner-remarks.ll:13:9) ; RUN: llc %s -enable-machine-outliner -mtriple=aarch64-unknown-unknown -o /dev/null -pass-remarks-missed=machine-outliner -pass-remarks-output=%t.yaml @@ -19,7 +19,7 @@ ; YAML-NEXT: - NumOccurrences: '2' ; YAML-NEXT: - String: ' locations.' ; YAML-NEXT: - String: ' Instructions from outlining all occurrences (' -; YAML-NEXT: - OutliningCost: '9' +; YAML-NEXT: - OutliningCost: '7' ; YAML-NEXT: - String: ')' ; YAML-NEXT: - String: ' >= Unoutlined instruction count (' ; YAML-NEXT: - NotOutliningCost: '4' Index: test/CodeGen/AMDGPU/amdpal-cs.ll =================================================================== --- test/CodeGen/AMDGPU/amdpal-cs.ll +++ test/CodeGen/AMDGPU/amdpal-cs.ll @@ -2,9 +2,10 @@ ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -enable-var-scope %s ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s -; amdpal compute shader: check for 0x2e12 (COMPUTE_PGM_RSRC1) in pal metadata +; amdpal compute shader: check for 47176 (COMPUTE_PGM_RSRC1) in .AMDGPU.config +; GCN-LABEL: .AMDGPU.config +; GCN: .long 47176 ; GCN-LABEL: {{^}}cs_amdpal: -; GCN: .amdgpu_pal_metadata{{.*}}0x2e12, define amdgpu_cs half @cs_amdpal(half %arg0) { %add = fadd half %arg0, 1.0 ret half %add Index: test/CodeGen/AMDGPU/amdpal-es.ll =================================================================== --- test/CodeGen/AMDGPU/amdpal-es.ll +++ test/CodeGen/AMDGPU/amdpal-es.ll @@ -1,9 +1,10 @@ ; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s -; amdpal evaluation shader: check for 0x2cca (SPI_SHADER_PGM_RSRC1_ES) in pal metadata +; amdpal pixel shader: check for 45864 (SPI_SHADER_PGM_RSRC1_ES) in .AMDGPU.config +; GCN-LABEL: .AMDGPU.config +; GCN: .long 45864 ; GCN-LABEL: {{^}}es_amdpal: -; GCN: .amdgpu_pal_metadata{{.*}}0x2cca, define amdgpu_es half @es_amdpal(half %arg0) { %add = fadd half %arg0, 1.0 ret half %add Index: test/CodeGen/AMDGPU/amdpal-gs.ll =================================================================== --- test/CodeGen/AMDGPU/amdpal-gs.ll +++ test/CodeGen/AMDGPU/amdpal-gs.ll @@ -2,9 +2,10 @@ ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s -; amdpal geometry shader: check for 0x2c8a (SPI_SHADER_PGM_RSRC1_GS) in pal metadata +; amdpal pixel shader: check for 45608 (SPI_SHADER_PGM_RSRC1_GS) in .AMDGPU.config +; GCN-LABEL: .AMDGPU.config +; GCN: .long 45608 ; GCN-LABEL: {{^}}gs_amdpal: -; GCN: .amdgpu_pal_metadata{{.*}}0x2c8a, define amdgpu_gs half @gs_amdpal(half %arg0) { %add = fadd half %arg0, 1.0 ret half %add Index: test/CodeGen/AMDGPU/amdpal-hs.ll =================================================================== --- test/CodeGen/AMDGPU/amdpal-hs.ll +++ test/CodeGen/AMDGPU/amdpal-hs.ll @@ -2,9 +2,10 @@ ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s -; amdpal hull shader: check for 0x2d0a (SPI_SHADER_PGM_RSRC1_HS) in pal metadata +; amdpal pixel shader: check for 46120 (SPI_SHADER_PGM_RSRC1_HS) in .AMDGPU.config +; GCN-LABEL: .AMDGPU.config +; GCN: .long 46120 ; GCN-LABEL: {{^}}hs_amdpal: -; GCN: .amdgpu_pal_metadata{{.*}}0x2d0a, define amdgpu_hs half @hs_amdpal(half %arg0) { %add = fadd half %arg0, 1.0 ret half %add Index: test/CodeGen/AMDGPU/amdpal-ls.ll =================================================================== --- test/CodeGen/AMDGPU/amdpal-ls.ll +++ test/CodeGen/AMDGPU/amdpal-ls.ll @@ -1,9 +1,10 @@ ; RUN: llc -mtriple=amdgcn--amdpal -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s -; amdpal load shader: check for 0x2d4a (SPI_SHADER_PGM_RSRC1_LS) in pal metadata +; amdpal pixel shader: check for 46376 (SPI_SHADER_PGM_RSRC1_LS) in .AMDGPU.config +; GCN-LABEL: .AMDGPU.config +; GCN: .long 46376 ; GCN-LABEL: {{^}}ls_amdpal: -; GCN: .amdgpu_pal_metadata{{.*}}0x2d4a, define amdgpu_ls half @ls_amdpal(half %arg0) { %add = fadd half %arg0, 1.0 ret half %add Index: test/CodeGen/AMDGPU/amdpal-ps.ll =================================================================== --- test/CodeGen/AMDGPU/amdpal-ps.ll +++ test/CodeGen/AMDGPU/amdpal-ps.ll @@ -2,16 +2,13 @@ ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s -; amdpal pixel shader: check for 0x2c0a (SPI_SHADER_PGM_RSRC1_PS) in pal -; metadata. Check for 0x2c0b (SPI_SHADER_PGM_RSRC2_PS) in pal metadata, and -; it has a value starting 0x42 as it is set to 0x42000000 in the metadata -; below. Also check that key 0x10000000 value 0x12345678 is propagated. +; amdpal pixel shader: check for 45096 (SPI_SHADER_PGM_RSRC1_PS) in .AMDGPU.config +; GCN-LABEL: .AMDGPU.config +; GCN: .long 45096 ; GCN-LABEL: {{^}}ps_amdpal: -; GCN: .amdgpu_pal_metadata{{.*0x2c0a,[^,]*,0x2c0b,0x42.*,0x10000000,0x12345678}} define amdgpu_ps half @ps_amdpal(half %arg0) { %add = fadd half %arg0, 1.0 ret half %add } -!amdgpu.pal.metadata = !{!0} -!0 = !{i32 11275, i32 1107296256, i32 268435456, i32 305419896} + Index: test/CodeGen/AMDGPU/amdpal-vs.ll =================================================================== --- test/CodeGen/AMDGPU/amdpal-vs.ll +++ test/CodeGen/AMDGPU/amdpal-vs.ll @@ -2,9 +2,10 @@ ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -enable-var-scope %s -; amdpal vertex shader: check for 45352 (SPI_SHADER_PGM_RSRC1_VS) in pal metadata +; amdpal pixel shader: check for 45352 (SPI_SHADER_PGM_RSRC1_VS) in .AMDGPU.config +; GCN-LABEL: .AMDGPU.config +; GCN: .long 45352 ; GCN-LABEL: {{^}}vs_amdpal: -; GCN: .amdgpu_pal_metadata{{.*}}0x2c4a, define amdgpu_vs half @vs_amdpal(half %arg0) { %add = fadd half %arg0, 1.0 ret half %add Index: test/CodeGen/AMDGPU/readlane_exec0.mir =================================================================== --- test/CodeGen/AMDGPU/readlane_exec0.mir +++ /dev/null @@ -1,32 +0,0 @@ -# RUN: llc -o - %s -march=amdgcn -mcpu=fiji -run-pass=si-insert-skips -verify-machineinstrs | FileCheck -check-prefix=GCN %s - -# GCN-LABEL: readlane_exec0 -# GCN: bb.0 -# GCN: S_CBRANCH_EXECZ %bb.2 - ---- -name: readlane_exec0 - -body: | - bb.0: - successors: %bb.1, %bb.2 - liveins: %vgpr1_vgpr2:0x00000001, %vgpr2_vgpr3:0x00000003 - - %vgpr4 = V_AND_B32_e32 1, %vgpr1, implicit %exec - V_CMP_EQ_U32_e32 1, killed %vgpr4, implicit-def %vcc, implicit %exec - %sgpr0_sgpr1 = S_AND_SAVEEXEC_B64 killed %vcc, implicit-def %exec, implicit-def %scc, implicit %exec - SI_MASK_BRANCH %bb.2, implicit %exec - S_BRANCH %bb.1 - - bb.1: - - %sgpr10 = V_READFIRSTLANE_B32 %vgpr2, implicit %exec - %sgpr11 = V_READFIRSTLANE_B32 %vgpr3, implicit %exec - %sgpr10 = S_LOAD_DWORD_IMM killed %sgpr10_sgpr11, 0, 0 - S_WAITCNT 127 - %vgpr0 = V_XOR_B32_e32 killed %sgpr10, killed %vgpr0, implicit %exec - - bb.2: - - %exec = S_OR_B64 %exec, killed %sgpr0_sgpr1, implicit-def %scc -... Index: test/CodeGen/Mips/dsp-spill-reload.ll =================================================================== --- test/CodeGen/Mips/dsp-spill-reload.ll +++ /dev/null @@ -1,52 +0,0 @@ -; RUN: llc -march=mips -mattr=+dsp < %s -asm-show-inst -O0 | FileCheck %s \ -; RUN: --check-prefixes=ASM,ALL -; RUN: llc -march=mips -mattr=+dsp,+micromips < %s -O0 -filetype=obj | \ -; RUN: llvm-objdump -d - | FileCheck %s --check-prefixes=MM-OBJ,ALL - -; Test that spill and reloads use the dsp "variant" instructions. We use -O0 -; to use the simple register allocator. - -; To test the micromips output, we have to take a round trip through the -; object file encoder/decoder as the instruction mapping tables are used to -; support micromips. - -; FIXME: We should be able to get rid of those instructions with the variable -; value registers. - -; ALL-LABEL: spill_reload: - -define <4 x i8> @spill_reload(<4 x i8> %a, <4 x i8> %b, i32 %g) { -entry: - %c = tail call <4 x i8> @llvm.mips.addu.qb(<4 x i8> %a, <4 x i8> %b) - %cond = icmp eq i32 %g, 0 - br i1 %cond, label %true, label %end - -; ASM: SWDSP -; ASM: SWDSP -; ASM: SWDSP - -; MM-OBJ: sw ${{[0-9]+}}, {{[0-9]+}}($sp) -; MM-OBJ: sw ${{[0-9]+}}, {{[0-9]+}}($sp) -; MM-OBJ: sw ${{[0-9]+}}, {{[0-9]+}}($sp) -; MM-OBJ: sw ${{[0-9]+}}, {{[0-9]+}}($sp) - -true: - ret <4 x i8> %c - -; ASM: LWDSP - -; MM-OBJ: lw ${{[0-9]+}}, {{[0-9]+}}($sp) - -end: - %d = tail call <4 x i8> @llvm.mips.addu.qb(<4 x i8> %c, <4 x i8> %a) - ret <4 x i8> %d - -; ASM: LWDSP -; ASM: LWDSP - -; MM-OBJ: lw ${{[0-9]+}}, {{[0-9]+}}($sp) -; MM-OBJ: lw ${{[0-9]+}}, {{[0-9]+}}($sp) - -} - -declare <4 x i8> @llvm.mips.addu.qb(<4 x i8>, <4 x i8>) nounwind Index: test/CodeGen/PowerPC/debuginfo-split-int.ll =================================================================== --- test/CodeGen/PowerPC/debuginfo-split-int.ll +++ test/CodeGen/PowerPC/debuginfo-split-int.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -stop-before=expand-isel-pseudos -o - | FileCheck %s +; RUN: llc < %s -stop-after=isel -o - | FileCheck %s source_filename = "foo.c" target datalayout = "E-m:e-p:32:32-i64:64-n32" Index: test/CodeGen/X86/avx-cvt-2.ll =================================================================== --- test/CodeGen/X86/avx-cvt-2.ll +++ test/CodeGen/X86/avx-cvt-2.ll @@ -50,7 +50,7 @@ ; CHECK-NEXT: vpshufb %xmm2, %xmm1, %xmm1 ; CHECK-NEXT: vpshufb %xmm2, %xmm0, %xmm0 ; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] -; CHECK-NEXT: vpackuswb %xmm0, %xmm0, %xmm0 +; CHECK-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u] ; CHECK-NEXT: vmovq %xmm0, (%rdi) ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retq @@ -68,7 +68,7 @@ ; CHECK-NEXT: vpshufb %xmm2, %xmm1, %xmm1 ; CHECK-NEXT: vpshufb %xmm2, %xmm0, %xmm0 ; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] -; CHECK-NEXT: vpacksswb %xmm0, %xmm0, %xmm0 +; CHECK-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u] ; CHECK-NEXT: vmovq %xmm0, (%rdi) ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: retq Index: test/CodeGen/X86/avx2-intrinsics-x86.ll =================================================================== --- test/CodeGen/X86/avx2-intrinsics-x86.ll +++ test/CodeGen/X86/avx2-intrinsics-x86.ll @@ -21,15 +21,15 @@ define <16 x i16> @test_x86_avx2_packssdw_fold() { ; AVX2-LABEL: test_x86_avx2_packssdw_fold: ; AVX2: ## BB#0: -; AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [0,0,0,0,255,32767,32767,65535,0,0,0,0,32769,32768,0,65280] -; AVX2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A] +; AVX2-NEXT: vpxor %xmm0, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xef,0xc0] +; AVX2-NEXT: vpackssdw LCPI1_0, %ymm0, %ymm0 ## encoding: [0xc5,0xfd,0x6b,0x05,A,A,A,A] ; AVX2-NEXT: ## fixup A - offset: 4, value: LCPI1_0, kind: FK_Data_4 ; AVX2-NEXT: retl ## encoding: [0xc3] ; ; AVX512VL-LABEL: test_x86_avx2_packssdw_fold: ; AVX512VL: ## BB#0: -; AVX512VL-NEXT: vmovaps LCPI1_0, %ymm0 ## EVEX TO VEX Compression ymm0 = [0,0,0,0,255,32767,32767,65535,0,0,0,0,32769,32768,0,65280] -; AVX512VL-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A] +; AVX512VL-NEXT: vpxor %xmm0, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xef,0xc0] +; AVX512VL-NEXT: vpackssdw LCPI1_0, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0x6b,0x05,A,A,A,A] ; AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI1_0, kind: FK_Data_4 ; AVX512VL-NEXT: retl ## encoding: [0xc3] %res = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> zeroinitializer, <8 x i32> ) @@ -56,16 +56,20 @@ define <32 x i8> @test_x86_avx2_packsswb_fold() { ; AVX2-LABEL: test_x86_avx2_packsswb_fold: ; AVX2: ## BB#0: -; AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0,0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0] -; AVX2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A] +; AVX2-NEXT: vpxor %xmm0, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xef,0xc0] +; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [0,255,256,65535,65535,65281,65280,32858,0,255,256,65535,65535,65281,65280,32858] +; AVX2-NEXT: ## encoding: [0xc5,0xfd,0x6f,0x0d,A,A,A,A] ; AVX2-NEXT: ## fixup A - offset: 4, value: LCPI3_0, kind: FK_Data_4 +; AVX2-NEXT: vpacksswb %ymm0, %ymm1, %ymm0 ## encoding: [0xc5,0xf5,0x63,0xc0] ; AVX2-NEXT: retl ## encoding: [0xc3] ; ; AVX512VL-LABEL: test_x86_avx2_packsswb_fold: ; AVX512VL: ## BB#0: -; AVX512VL-NEXT: vmovaps LCPI3_0, %ymm0 ## EVEX TO VEX Compression ymm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0,0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0] -; AVX512VL-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A] +; AVX512VL-NEXT: vpxor %xmm0, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xef,0xc0] +; AVX512VL-NEXT: vmovdqa LCPI3_0, %ymm1 ## EVEX TO VEX Compression ymm1 = [0,255,256,65535,65535,65281,65280,32858,0,255,256,65535,65535,65281,65280,32858] +; AVX512VL-NEXT: ## encoding: [0xc5,0xfd,0x6f,0x0d,A,A,A,A] ; AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI3_0, kind: FK_Data_4 +; AVX512VL-NEXT: vpacksswb %ymm0, %ymm1, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf5,0x63,0xc0] ; AVX512VL-NEXT: retl ## encoding: [0xc3] %res = call <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16> , <16 x i16> zeroinitializer) ret <32 x i8> %res @@ -91,16 +95,20 @@ define <32 x i8> @test_x86_avx2_packuswb_fold() { ; AVX2-LABEL: test_x86_avx2_packuswb_fold: ; AVX2: ## BB#0: -; AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0,0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0] -; AVX2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A] +; AVX2-NEXT: vpxor %xmm0, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xef,0xc0] +; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [0,255,256,65535,65535,65281,65280,32858,0,255,256,65535,65535,65281,65280,32858] +; AVX2-NEXT: ## encoding: [0xc5,0xfd,0x6f,0x0d,A,A,A,A] ; AVX2-NEXT: ## fixup A - offset: 4, value: LCPI5_0, kind: FK_Data_4 +; AVX2-NEXT: vpackuswb %ymm0, %ymm1, %ymm0 ## encoding: [0xc5,0xf5,0x67,0xc0] ; AVX2-NEXT: retl ## encoding: [0xc3] ; ; AVX512VL-LABEL: test_x86_avx2_packuswb_fold: ; AVX512VL: ## BB#0: -; AVX512VL-NEXT: vmovaps LCPI5_0, %ymm0 ## EVEX TO VEX Compression ymm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0,0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0] -; AVX512VL-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A] +; AVX512VL-NEXT: vpxor %xmm0, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xef,0xc0] +; AVX512VL-NEXT: vmovdqa LCPI5_0, %ymm1 ## EVEX TO VEX Compression ymm1 = [0,255,256,65535,65535,65281,65280,32858,0,255,256,65535,65535,65281,65280,32858] +; AVX512VL-NEXT: ## encoding: [0xc5,0xfd,0x6f,0x0d,A,A,A,A] ; AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI5_0, kind: FK_Data_4 +; AVX512VL-NEXT: vpackuswb %ymm0, %ymm1, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf5,0x67,0xc0] ; AVX512VL-NEXT: retl ## encoding: [0xc3] %res = call <32 x i8> @llvm.x86.avx2.packuswb(<16 x i16> , <16 x i16> zeroinitializer) ret <32 x i8> %res @@ -842,16 +850,16 @@ define <16 x i16> @test_x86_avx2_packusdw_fold() { ; AVX2-LABEL: test_x86_avx2_packusdw_fold: ; AVX2: ## BB#0: -; AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [0,0,0,0,255,32767,65535,0,0,0,0,0,0,0,0,0] -; AVX2-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A] -; AVX2-NEXT: ## fixup A - offset: 4, value: LCPI55_0, kind: FK_Data_4 +; AVX2-NEXT: vpxor %xmm0, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xef,0xc0] +; AVX2-NEXT: vpackusdw LCPI55_0, %ymm0, %ymm0 ## encoding: [0xc4,0xe2,0x7d,0x2b,0x05,A,A,A,A] +; AVX2-NEXT: ## fixup A - offset: 5, value: LCPI55_0, kind: FK_Data_4 ; AVX2-NEXT: retl ## encoding: [0xc3] ; ; AVX512VL-LABEL: test_x86_avx2_packusdw_fold: ; AVX512VL: ## BB#0: -; AVX512VL-NEXT: vmovaps LCPI55_0, %ymm0 ## EVEX TO VEX Compression ymm0 = [0,0,0,0,255,32767,65535,0,0,0,0,0,0,0,0,0] -; AVX512VL-NEXT: ## encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A] -; AVX512VL-NEXT: ## fixup A - offset: 4, value: LCPI55_0, kind: FK_Data_4 +; AVX512VL-NEXT: vpxor %xmm0, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xef,0xc0] +; AVX512VL-NEXT: vpackusdw LCPI55_0, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x2b,0x05,A,A,A,A] +; AVX512VL-NEXT: ## fixup A - offset: 5, value: LCPI55_0, kind: FK_Data_4 ; AVX512VL-NEXT: retl ## encoding: [0xc3] %res = call <16 x i16> @llvm.x86.avx2.packusdw(<8 x i32> zeroinitializer, <8 x i32> ) ret <16 x i16> %res Index: test/CodeGen/X86/avx2-shift.ll =================================================================== --- test/CodeGen/X86/avx2-shift.ll +++ test/CodeGen/X86/avx2-shift.ll @@ -556,7 +556,7 @@ ; X32-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero ; X32-NEXT: vpmovsxwd %xmm0, %ymm0 ; X32-NEXT: vpsravd %ymm1, %ymm0, %ymm0 -; X32-NEXT: vpackssdw %ymm0, %ymm0, %ymm0 +; X32-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; X32-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] ; X32-NEXT: # kill: %XMM0 %XMM0 %YMM0 ; X32-NEXT: vzeroupper @@ -567,7 +567,7 @@ ; X64-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero ; X64-NEXT: vpmovsxwd %xmm0, %ymm0 ; X64-NEXT: vpsravd %ymm1, %ymm0, %ymm0 -; X64-NEXT: vpackssdw %ymm0, %ymm0, %ymm0 +; X64-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; X64-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] ; X64-NEXT: # kill: %XMM0 %XMM0 %YMM0 ; X64-NEXT: vzeroupper Index: test/CodeGen/X86/avx2-vbroadcast.ll =================================================================== --- test/CodeGen/X86/avx2-vbroadcast.ll +++ test/CodeGen/X86/avx2-vbroadcast.ll @@ -267,14 +267,16 @@ ; X32-AVX2-LABEL: broadcast_mem_v4i16_v16i16: ; X32-AVX2: ## BB#0: ; X32-AVX2-NEXT: movl {{[0-9]+}}(%esp), %eax -; X32-AVX2-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero -; X32-AVX2-NEXT: vbroadcastsd %xmm0, %ymm0 +; X32-AVX2-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero +; X32-AVX2-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6,7,4,5,6,7,6,7],zero,zero +; X32-AVX2-NEXT: vpbroadcastq %xmm0, %ymm0 ; X32-AVX2-NEXT: retl ; ; X64-AVX2-LABEL: broadcast_mem_v4i16_v16i16: ; X64-AVX2: ## BB#0: -; X64-AVX2-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero -; X64-AVX2-NEXT: vbroadcastsd %xmm0, %ymm0 +; X64-AVX2-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero +; X64-AVX2-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6,7,4,5,6,7,6,7],zero,zero +; X64-AVX2-NEXT: vpbroadcastq %xmm0, %ymm0 ; X64-AVX2-NEXT: retq ; ; X32-AVX512VL-LABEL: broadcast_mem_v4i16_v16i16: Index: test/CodeGen/X86/avx2-vector-shifts.ll =================================================================== --- test/CodeGen/X86/avx2-vector-shifts.ll +++ test/CodeGen/X86/avx2-vector-shifts.ll @@ -499,7 +499,7 @@ ; X32-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero ; X32-NEXT: vpmovsxwd %xmm0, %ymm0 ; X32-NEXT: vpsravd %ymm1, %ymm0, %ymm0 -; X32-NEXT: vpackssdw %ymm0, %ymm0, %ymm0 +; X32-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; X32-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] ; X32-NEXT: # kill: %XMM0 %XMM0 %YMM0 ; X32-NEXT: vzeroupper @@ -510,7 +510,7 @@ ; X64-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero ; X64-NEXT: vpmovsxwd %xmm0, %ymm0 ; X64-NEXT: vpsravd %ymm1, %ymm0, %ymm0 -; X64-NEXT: vpackssdw %ymm0, %ymm0, %ymm0 +; X64-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; X64-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] ; X64-NEXT: # kill: %XMM0 %XMM0 %YMM0 ; X64-NEXT: vzeroupper Index: test/CodeGen/X86/avx512-any_extend_load.ll =================================================================== --- test/CodeGen/X86/avx512-any_extend_load.ll +++ test/CodeGen/X86/avx512-any_extend_load.ll @@ -57,7 +57,7 @@ ; KNL: # BB#0: ; KNL-NEXT: vpmovzxbw {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero ; KNL-NEXT: vpaddb {{.*}}(%rip), %xmm0, %xmm0 -; KNL-NEXT: vpackuswb %xmm0, %xmm0, %xmm0 +; KNL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u] ; KNL-NEXT: vmovq %xmm0, (%rdi) ; KNL-NEXT: retq ; Index: test/CodeGen/X86/avx512-trunc.ll =================================================================== --- test/CodeGen/X86/avx512-trunc.ll +++ test/CodeGen/X86/avx512-trunc.ll @@ -584,7 +584,7 @@ ; KNL-LABEL: usat_trunc_wb_128_mem: ; KNL: ## BB#0: ; KNL-NEXT: vpminuw {{.*}}(%rip), %xmm0, %xmm0 -; KNL-NEXT: vpackuswb %xmm0, %xmm0, %xmm0 +; KNL-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u] ; KNL-NEXT: vmovq %xmm0, (%rdi) ; KNL-NEXT: retq ; Index: test/CodeGen/X86/bitcast-and-setcc-256.ll =================================================================== --- test/CodeGen/X86/bitcast-and-setcc-256.ll +++ test/CodeGen/X86/bitcast-and-setcc-256.ll @@ -149,18 +149,41 @@ } define i16 @v16i16(<16 x i16> %a, <16 x i16> %b, <16 x i16> %c, <16 x i16> %d) { -; SSE2-SSSE3-LABEL: v16i16: -; SSE2-SSSE3: # BB#0: -; SSE2-SSSE3-NEXT: pcmpgtw %xmm3, %xmm1 -; SSE2-SSSE3-NEXT: pcmpgtw %xmm2, %xmm0 -; SSE2-SSSE3-NEXT: packsswb %xmm1, %xmm0 -; SSE2-SSSE3-NEXT: pcmpgtw %xmm7, %xmm5 -; SSE2-SSSE3-NEXT: pcmpgtw %xmm6, %xmm4 -; SSE2-SSSE3-NEXT: packsswb %xmm5, %xmm4 -; SSE2-SSSE3-NEXT: pand %xmm0, %xmm4 -; SSE2-SSSE3-NEXT: pmovmskb %xmm4, %eax -; SSE2-SSSE3-NEXT: # kill: %AX %AX %EAX -; SSE2-SSSE3-NEXT: retq +; SSE2-LABEL: v16i16: +; SSE2: # BB#0: +; SSE2-NEXT: pcmpgtw %xmm3, %xmm1 +; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [255,255,255,255,255,255,255,255] +; SSE2-NEXT: pand %xmm3, %xmm1 +; SSE2-NEXT: pcmpgtw %xmm2, %xmm0 +; SSE2-NEXT: pand %xmm3, %xmm0 +; SSE2-NEXT: packuswb %xmm1, %xmm0 +; SSE2-NEXT: pcmpgtw %xmm7, %xmm5 +; SSE2-NEXT: pand %xmm3, %xmm5 +; SSE2-NEXT: pcmpgtw %xmm6, %xmm4 +; SSE2-NEXT: pand %xmm3, %xmm4 +; SSE2-NEXT: packuswb %xmm5, %xmm4 +; SSE2-NEXT: pand %xmm0, %xmm4 +; SSE2-NEXT: pmovmskb %xmm4, %eax +; SSE2-NEXT: # kill: %AX %AX %EAX +; SSE2-NEXT: retq +; +; SSSE3-LABEL: v16i16: +; SSSE3: # BB#0: +; SSSE3-NEXT: pcmpgtw %xmm3, %xmm1 +; SSSE3-NEXT: movdqa {{.*#+}} xmm3 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u> +; SSSE3-NEXT: pshufb %xmm3, %xmm1 +; SSSE3-NEXT: pcmpgtw %xmm2, %xmm0 +; SSSE3-NEXT: pshufb %xmm3, %xmm0 +; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] +; SSSE3-NEXT: pcmpgtw %xmm7, %xmm5 +; SSSE3-NEXT: pshufb %xmm3, %xmm5 +; SSSE3-NEXT: pcmpgtw %xmm6, %xmm4 +; SSSE3-NEXT: pshufb %xmm3, %xmm4 +; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm5[0] +; SSSE3-NEXT: pand %xmm0, %xmm4 +; SSSE3-NEXT: pmovmskb %xmm4, %eax +; SSSE3-NEXT: # kill: %AX %AX %EAX +; SSSE3-NEXT: retq ; ; AVX1-LABEL: v16i16: ; AVX1: # BB#0: @@ -213,33 +236,42 @@ ; SSE2-LABEL: v8i32: ; SSE2: # BB#0: ; SSE2-NEXT: pcmpgtd %xmm3, %xmm1 -; SSE2-NEXT: packssdw %xmm0, %xmm1 +; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7] +; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,6,6,7] +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; SSE2-NEXT: pcmpgtd %xmm2, %xmm0 -; SSE2-NEXT: packssdw %xmm0, %xmm0 +; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7] +; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,6,7] +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; SSE2-NEXT: pcmpgtd %xmm7, %xmm5 -; SSE2-NEXT: packssdw %xmm0, %xmm5 +; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm5[0,2,2,3,4,5,6,7] +; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,6,6,7] +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; SSE2-NEXT: pcmpgtd %xmm6, %xmm4 -; SSE2-NEXT: packssdw %xmm0, %xmm4 -; SSE2-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm5[0] -; SSE2-NEXT: pand %xmm0, %xmm4 -; SSE2-NEXT: pand {{.*}}(%rip), %xmm4 -; SSE2-NEXT: packuswb %xmm4, %xmm4 -; SSE2-NEXT: pmovmskb %xmm4, %eax +; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm4[0,2,2,3,4,5,6,7] +; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,4,6,6,7] +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3] +; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0] +; SSE2-NEXT: pand %xmm0, %xmm2 +; SSE2-NEXT: pand {{.*}}(%rip), %xmm2 +; SSE2-NEXT: packuswb %xmm2, %xmm2 +; SSE2-NEXT: pmovmskb %xmm2, %eax ; SSE2-NEXT: # kill: %AL %AL %EAX ; SSE2-NEXT: retq ; ; SSSE3-LABEL: v8i32: ; SSSE3: # BB#0: ; SSSE3-NEXT: pcmpgtd %xmm3, %xmm1 -; SSSE3-NEXT: packssdw %xmm0, %xmm1 +; SSSE3-NEXT: movdqa {{.*#+}} xmm3 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] +; SSSE3-NEXT: pshufb %xmm3, %xmm1 ; SSSE3-NEXT: pcmpgtd %xmm2, %xmm0 -; SSSE3-NEXT: packssdw %xmm0, %xmm0 +; SSSE3-NEXT: pshufb %xmm3, %xmm0 ; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; SSSE3-NEXT: pcmpgtd %xmm7, %xmm5 -; SSSE3-NEXT: packssdw %xmm0, %xmm5 +; SSSE3-NEXT: pshufb %xmm3, %xmm5 ; SSSE3-NEXT: pcmpgtd %xmm6, %xmm4 -; SSSE3-NEXT: packssdw %xmm0, %xmm4 +; SSSE3-NEXT: pshufb %xmm3, %xmm4 ; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm5[0] ; SSSE3-NEXT: pand %xmm0, %xmm4 ; SSSE3-NEXT: pshufb {{.*#+}} xmm4 = xmm4[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u] Index: test/CodeGen/X86/bitcast-and-setcc-512.ll =================================================================== --- test/CodeGen/X86/bitcast-and-setcc-512.ll +++ test/CodeGen/X86/bitcast-and-setcc-512.ll @@ -40,7 +40,7 @@ ; SSE-NEXT: pand %xmm0, %xmm2 ; SSE-NEXT: psllw $15, %xmm2 ; SSE-NEXT: psraw $15, %xmm2 -; SSE-NEXT: packsswb %xmm0, %xmm2 +; SSE-NEXT: pshufb {{.*#+}} xmm2 = xmm2[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u] ; SSE-NEXT: pmovmskb %xmm2, %eax ; SSE-NEXT: # kill: %AL %AL %EAX ; SSE-NEXT: retq @@ -77,7 +77,7 @@ ; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: vpsllw $15, %xmm0, %xmm0 ; AVX1-NEXT: vpsraw $15, %xmm0, %xmm0 -; AVX1-NEXT: vpacksswb %xmm0, %xmm0, %xmm0 +; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u] ; AVX1-NEXT: vpmovmskb %xmm0, %eax ; AVX1-NEXT: # kill: %AL %AL %EAX ; AVX1-NEXT: vzeroupper @@ -107,7 +107,7 @@ ; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 ; AVX2-NEXT: vpsllw $15, %xmm0, %xmm0 ; AVX2-NEXT: vpsraw $15, %xmm0, %xmm0 -; AVX2-NEXT: vpacksswb %xmm0, %xmm0, %xmm0 +; AVX2-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u] ; AVX2-NEXT: vpmovmskb %xmm0, %eax ; AVX2-NEXT: # kill: %AL %AL %EAX ; AVX2-NEXT: vzeroupper @@ -172,7 +172,7 @@ ; SSE-NEXT: pand %xmm0, %xmm2 ; SSE-NEXT: psllw $15, %xmm2 ; SSE-NEXT: psraw $15, %xmm2 -; SSE-NEXT: packsswb %xmm0, %xmm2 +; SSE-NEXT: pshufb {{.*#+}} xmm2 = xmm2[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u] ; SSE-NEXT: pmovmskb %xmm2, %eax ; SSE-NEXT: # kill: %AL %AL %EAX ; SSE-NEXT: retq @@ -201,7 +201,7 @@ ; AVX12-NEXT: vpand %xmm1, %xmm0, %xmm0 ; AVX12-NEXT: vpsllw $15, %xmm0, %xmm0 ; AVX12-NEXT: vpsraw $15, %xmm0, %xmm0 -; AVX12-NEXT: vpacksswb %xmm0, %xmm0, %xmm0 +; AVX12-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u] ; AVX12-NEXT: vpmovmskb %xmm0, %eax ; AVX12-NEXT: # kill: %AL %AL %EAX ; AVX12-NEXT: vzeroupper @@ -235,24 +235,33 @@ ; SSE-LABEL: v32i16: ; SSE: # BB#0: ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm8 -; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm10 +; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm11 ; SSE-NEXT: pcmpgtw %xmm5, %xmm1 +; SSE-NEXT: movdqa {{.*#+}} xmm5 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u> +; SSE-NEXT: pshufb %xmm5, %xmm1 ; SSE-NEXT: pcmpgtw %xmm4, %xmm0 -; SSE-NEXT: packsswb %xmm1, %xmm0 +; SSE-NEXT: pshufb %xmm5, %xmm0 +; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; SSE-NEXT: pcmpgtw %xmm7, %xmm3 +; SSE-NEXT: pshufb %xmm5, %xmm3 ; SSE-NEXT: pcmpgtw %xmm6, %xmm2 -; SSE-NEXT: packsswb %xmm3, %xmm2 +; SSE-NEXT: pshufb %xmm5, %xmm2 +; SSE-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0] ; SSE-NEXT: pcmpgtw {{[0-9]+}}(%rsp), %xmm11 -; SSE-NEXT: pcmpgtw {{[0-9]+}}(%rsp), %xmm10 -; SSE-NEXT: packsswb %xmm11, %xmm10 -; SSE-NEXT: pand %xmm0, %xmm10 +; SSE-NEXT: pshufb %xmm5, %xmm11 ; SSE-NEXT: pcmpgtw {{[0-9]+}}(%rsp), %xmm9 +; SSE-NEXT: pshufb %xmm5, %xmm9 +; SSE-NEXT: punpcklqdq {{.*#+}} xmm9 = xmm9[0],xmm11[0] +; SSE-NEXT: pand %xmm0, %xmm9 +; SSE-NEXT: pcmpgtw {{[0-9]+}}(%rsp), %xmm10 +; SSE-NEXT: pshufb %xmm5, %xmm10 ; SSE-NEXT: pcmpgtw {{[0-9]+}}(%rsp), %xmm8 -; SSE-NEXT: packsswb %xmm9, %xmm8 +; SSE-NEXT: pshufb %xmm5, %xmm8 +; SSE-NEXT: punpcklqdq {{.*#+}} xmm8 = xmm8[0],xmm10[0] ; SSE-NEXT: pand %xmm2, %xmm8 -; SSE-NEXT: pmovmskb %xmm10, %ecx +; SSE-NEXT: pmovmskb %xmm9, %ecx ; SSE-NEXT: pmovmskb %xmm8, %eax ; SSE-NEXT: shll $16, %eax ; SSE-NEXT: orl %ecx, %eax @@ -630,27 +639,33 @@ ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm11 ; SSE-NEXT: pcmpgtd %xmm7, %xmm3 -; SSE-NEXT: packssdw %xmm0, %xmm3 +; SSE-NEXT: movdqa {{.*#+}} xmm7 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] +; SSE-NEXT: pshufb %xmm7, %xmm3 ; SSE-NEXT: pcmpgtd %xmm6, %xmm2 -; SSE-NEXT: packssdw %xmm0, %xmm2 +; SSE-NEXT: pshufb %xmm7, %xmm2 ; SSE-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0] +; SSE-NEXT: movdqa {{.*#+}} xmm3 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u> +; SSE-NEXT: pshufb %xmm3, %xmm2 ; SSE-NEXT: pcmpgtd %xmm5, %xmm1 -; SSE-NEXT: packssdw %xmm0, %xmm1 +; SSE-NEXT: pshufb %xmm7, %xmm1 ; SSE-NEXT: pcmpgtd %xmm4, %xmm0 -; SSE-NEXT: packssdw %xmm0, %xmm0 +; SSE-NEXT: pshufb %xmm7, %xmm0 ; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] -; SSE-NEXT: packsswb %xmm2, %xmm0 +; SSE-NEXT: pshufb %xmm3, %xmm0 +; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0] ; SSE-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm11 -; SSE-NEXT: packssdw %xmm0, %xmm11 +; SSE-NEXT: pshufb %xmm7, %xmm11 ; SSE-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm9 -; SSE-NEXT: packssdw %xmm0, %xmm9 +; SSE-NEXT: pshufb %xmm7, %xmm9 ; SSE-NEXT: punpcklqdq {{.*#+}} xmm9 = xmm9[0],xmm11[0] +; SSE-NEXT: pshufb %xmm3, %xmm9 ; SSE-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm10 -; SSE-NEXT: packssdw %xmm0, %xmm10 +; SSE-NEXT: pshufb %xmm7, %xmm10 ; SSE-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm8 -; SSE-NEXT: packssdw %xmm0, %xmm8 +; SSE-NEXT: pshufb %xmm7, %xmm8 ; SSE-NEXT: punpcklqdq {{.*#+}} xmm8 = xmm8[0],xmm10[0] -; SSE-NEXT: packsswb %xmm9, %xmm8 +; SSE-NEXT: pshufb %xmm3, %xmm8 +; SSE-NEXT: punpcklqdq {{.*#+}} xmm8 = xmm8[0],xmm9[0] ; SSE-NEXT: pand %xmm0, %xmm8 ; SSE-NEXT: pmovmskb %xmm8, %eax ; SSE-NEXT: # kill: %AX %AX %EAX Index: test/CodeGen/X86/bitcast-setcc-128.ll =================================================================== --- test/CodeGen/X86/bitcast-setcc-128.ll +++ test/CodeGen/X86/bitcast-setcc-128.ll @@ -6,18 +6,27 @@ ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512vl,+avx512bw | FileCheck %s --check-prefixes=AVX512 define i8 @v8i16(<8 x i16> %a, <8 x i16> %b) { -; SSE2-SSSE3-LABEL: v8i16: -; SSE2-SSSE3: # BB#0: -; SSE2-SSSE3-NEXT: pcmpgtw %xmm1, %xmm0 -; SSE2-SSSE3-NEXT: packsswb %xmm0, %xmm0 -; SSE2-SSSE3-NEXT: pmovmskb %xmm0, %eax -; SSE2-SSSE3-NEXT: # kill: %AL %AL %EAX -; SSE2-SSSE3-NEXT: retq +; SSE2-LABEL: v8i16: +; SSE2: # BB#0: +; SSE2-NEXT: pcmpgtw %xmm1, %xmm0 +; SSE2-NEXT: pand {{.*}}(%rip), %xmm0 +; SSE2-NEXT: packuswb %xmm0, %xmm0 +; SSE2-NEXT: pmovmskb %xmm0, %eax +; SSE2-NEXT: # kill: %AL %AL %EAX +; SSE2-NEXT: retq +; +; SSSE3-LABEL: v8i16: +; SSSE3: # BB#0: +; SSSE3-NEXT: pcmpgtw %xmm1, %xmm0 +; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u] +; SSSE3-NEXT: pmovmskb %xmm0, %eax +; SSSE3-NEXT: # kill: %AL %AL %EAX +; SSSE3-NEXT: retq ; ; AVX12-LABEL: v8i16: ; AVX12: # BB#0: ; AVX12-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm0 -; AVX12-NEXT: vpacksswb %xmm0, %xmm0, %xmm0 +; AVX12-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u] ; AVX12-NEXT: vpmovmskb %xmm0, %eax ; AVX12-NEXT: # kill: %AL %AL %EAX ; AVX12-NEXT: retq @@ -494,17 +503,30 @@ } define i8 @v8i8(<8 x i8> %a, <8 x i8> %b) { -; SSE2-SSSE3-LABEL: v8i8: -; SSE2-SSSE3: # BB#0: -; SSE2-SSSE3-NEXT: psllw $8, %xmm1 -; SSE2-SSSE3-NEXT: psraw $8, %xmm1 -; SSE2-SSSE3-NEXT: psllw $8, %xmm0 -; SSE2-SSSE3-NEXT: psraw $8, %xmm0 -; SSE2-SSSE3-NEXT: pcmpgtw %xmm1, %xmm0 -; SSE2-SSSE3-NEXT: packsswb %xmm0, %xmm0 -; SSE2-SSSE3-NEXT: pmovmskb %xmm0, %eax -; SSE2-SSSE3-NEXT: # kill: %AL %AL %EAX -; SSE2-SSSE3-NEXT: retq +; SSE2-LABEL: v8i8: +; SSE2: # BB#0: +; SSE2-NEXT: psllw $8, %xmm1 +; SSE2-NEXT: psraw $8, %xmm1 +; SSE2-NEXT: psllw $8, %xmm0 +; SSE2-NEXT: psraw $8, %xmm0 +; SSE2-NEXT: pcmpgtw %xmm1, %xmm0 +; SSE2-NEXT: pand {{.*}}(%rip), %xmm0 +; SSE2-NEXT: packuswb %xmm0, %xmm0 +; SSE2-NEXT: pmovmskb %xmm0, %eax +; SSE2-NEXT: # kill: %AL %AL %EAX +; SSE2-NEXT: retq +; +; SSSE3-LABEL: v8i8: +; SSSE3: # BB#0: +; SSSE3-NEXT: psllw $8, %xmm1 +; SSSE3-NEXT: psraw $8, %xmm1 +; SSSE3-NEXT: psllw $8, %xmm0 +; SSSE3-NEXT: psraw $8, %xmm0 +; SSSE3-NEXT: pcmpgtw %xmm1, %xmm0 +; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u] +; SSSE3-NEXT: pmovmskb %xmm0, %eax +; SSSE3-NEXT: # kill: %AL %AL %EAX +; SSSE3-NEXT: retq ; ; AVX12-LABEL: v8i8: ; AVX12: # BB#0: @@ -513,7 +535,7 @@ ; AVX12-NEXT: vpsllw $8, %xmm0, %xmm0 ; AVX12-NEXT: vpsraw $8, %xmm0, %xmm0 ; AVX12-NEXT: vpcmpgtw %xmm1, %xmm0, %xmm0 -; AVX12-NEXT: vpacksswb %xmm0, %xmm0, %xmm0 +; AVX12-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u] ; AVX12-NEXT: vpmovmskb %xmm0, %eax ; AVX12-NEXT: # kill: %AL %AL %EAX ; AVX12-NEXT: retq Index: test/CodeGen/X86/bool-vector.ll =================================================================== --- test/CodeGen/X86/bool-vector.ll +++ /dev/null @@ -1,206 +0,0 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=-sse2 | FileCheck %s --check-prefix=X32 -; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X32-SSE2 -; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=X32-AVX2 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-sse2 | FileCheck %s --check-prefix=X64 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64-SSE2 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=X64-AVX2 - -define i32 @PR15215_bad(<4 x i32> %input) { -; X32-LABEL: PR15215_bad: -; X32: # BB#0: # %entry -; X32-NEXT: movb {{[0-9]+}}(%esp), %al -; X32-NEXT: movb {{[0-9]+}}(%esp), %cl -; X32-NEXT: movb {{[0-9]+}}(%esp), %dl -; X32-NEXT: movb {{[0-9]+}}(%esp), %ah -; X32-NEXT: addb %ah, %ah -; X32-NEXT: andb $1, %dl -; X32-NEXT: orb %ah, %dl -; X32-NEXT: shlb $2, %dl -; X32-NEXT: addb %cl, %cl -; X32-NEXT: andb $1, %al -; X32-NEXT: orb %cl, %al -; X32-NEXT: andb $3, %al -; X32-NEXT: orb %dl, %al -; X32-NEXT: movzbl %al, %eax -; X32-NEXT: andl $15, %eax -; X32-NEXT: retl -; -; X32-SSE2-LABEL: PR15215_bad: -; X32-SSE2: # BB#0: # %entry -; X32-SSE2-NEXT: pslld $31, %xmm0 -; X32-SSE2-NEXT: psrad $31, %xmm0 -; X32-SSE2-NEXT: movmskps %xmm0, %eax -; X32-SSE2-NEXT: retl -; -; X32-AVX2-LABEL: PR15215_bad: -; X32-AVX2: # BB#0: # %entry -; X32-AVX2-NEXT: vpslld $31, %xmm0, %xmm0 -; X32-AVX2-NEXT: vpsrad $31, %xmm0, %xmm0 -; X32-AVX2-NEXT: vmovmskps %xmm0, %eax -; X32-AVX2-NEXT: retl -; -; X64-LABEL: PR15215_bad: -; X64: # BB#0: # %entry -; X64-NEXT: addb %cl, %cl -; X64-NEXT: andb $1, %dl -; X64-NEXT: orb %cl, %dl -; X64-NEXT: shlb $2, %dl -; X64-NEXT: addb %sil, %sil -; X64-NEXT: andb $1, %dil -; X64-NEXT: orb %sil, %dil -; X64-NEXT: andb $3, %dil -; X64-NEXT: orb %dl, %dil -; X64-NEXT: movzbl %dil, %eax -; X64-NEXT: andl $15, %eax -; X64-NEXT: retq -; -; X64-SSE2-LABEL: PR15215_bad: -; X64-SSE2: # BB#0: # %entry -; X64-SSE2-NEXT: pslld $31, %xmm0 -; X64-SSE2-NEXT: psrad $31, %xmm0 -; X64-SSE2-NEXT: movmskps %xmm0, %eax -; X64-SSE2-NEXT: retq -; -; X64-AVX2-LABEL: PR15215_bad: -; X64-AVX2: # BB#0: # %entry -; X64-AVX2-NEXT: vpslld $31, %xmm0, %xmm0 -; X64-AVX2-NEXT: vpsrad $31, %xmm0, %xmm0 -; X64-AVX2-NEXT: vmovmskps %xmm0, %eax -; X64-AVX2-NEXT: retq -entry: - %0 = trunc <4 x i32> %input to <4 x i1> - %1 = bitcast <4 x i1> %0 to i4 - %2 = zext i4 %1 to i32 - ret i32 %2 -} - -define i32 @PR15215_good(<4 x i32> %input) { -; X32-LABEL: PR15215_good: -; X32: # BB#0: # %entry -; X32-NEXT: pushl %esi -; X32-NEXT: .Lcfi0: -; X32-NEXT: .cfi_def_cfa_offset 8 -; X32-NEXT: .Lcfi1: -; X32-NEXT: .cfi_offset %esi, -8 -; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax -; X32-NEXT: andl $1, %eax -; X32-NEXT: movzbl {{[0-9]+}}(%esp), %ecx -; X32-NEXT: andl $1, %ecx -; X32-NEXT: movzbl {{[0-9]+}}(%esp), %edx -; X32-NEXT: andl $1, %edx -; X32-NEXT: movzbl {{[0-9]+}}(%esp), %esi -; X32-NEXT: andl $1, %esi -; X32-NEXT: leal (%eax,%ecx,2), %eax -; X32-NEXT: leal (%eax,%edx,4), %eax -; X32-NEXT: leal (%eax,%esi,8), %eax -; X32-NEXT: popl %esi -; X32-NEXT: retl -; -; X32-SSE2-LABEL: PR15215_good: -; X32-SSE2: # BB#0: # %entry -; X32-SSE2-NEXT: pushl %esi -; X32-SSE2-NEXT: .Lcfi0: -; X32-SSE2-NEXT: .cfi_def_cfa_offset 8 -; X32-SSE2-NEXT: .Lcfi1: -; X32-SSE2-NEXT: .cfi_offset %esi, -8 -; X32-SSE2-NEXT: movd %xmm0, %eax -; X32-SSE2-NEXT: andl $1, %eax -; X32-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,2,3] -; X32-SSE2-NEXT: movd %xmm1, %ecx -; X32-SSE2-NEXT: andl $1, %ecx -; X32-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] -; X32-SSE2-NEXT: movd %xmm1, %edx -; X32-SSE2-NEXT: andl $1, %edx -; X32-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,2,3] -; X32-SSE2-NEXT: movd %xmm0, %esi -; X32-SSE2-NEXT: andl $1, %esi -; X32-SSE2-NEXT: leal (%eax,%ecx,2), %eax -; X32-SSE2-NEXT: leal (%eax,%edx,4), %eax -; X32-SSE2-NEXT: leal (%eax,%esi,8), %eax -; X32-SSE2-NEXT: popl %esi -; X32-SSE2-NEXT: retl -; -; X32-AVX2-LABEL: PR15215_good: -; X32-AVX2: # BB#0: # %entry -; X32-AVX2-NEXT: pushl %esi -; X32-AVX2-NEXT: .Lcfi0: -; X32-AVX2-NEXT: .cfi_def_cfa_offset 8 -; X32-AVX2-NEXT: .Lcfi1: -; X32-AVX2-NEXT: .cfi_offset %esi, -8 -; X32-AVX2-NEXT: vmovd %xmm0, %eax -; X32-AVX2-NEXT: andl $1, %eax -; X32-AVX2-NEXT: vpextrd $1, %xmm0, %ecx -; X32-AVX2-NEXT: andl $1, %ecx -; X32-AVX2-NEXT: vpextrd $2, %xmm0, %edx -; X32-AVX2-NEXT: andl $1, %edx -; X32-AVX2-NEXT: vpextrd $3, %xmm0, %esi -; X32-AVX2-NEXT: andl $1, %esi -; X32-AVX2-NEXT: leal (%eax,%ecx,2), %eax -; X32-AVX2-NEXT: leal (%eax,%edx,4), %eax -; X32-AVX2-NEXT: leal (%eax,%esi,8), %eax -; X32-AVX2-NEXT: popl %esi -; X32-AVX2-NEXT: retl -; -; X64-LABEL: PR15215_good: -; X64: # BB#0: # %entry -; X64-NEXT: # kill: %ECX %ECX %RCX -; X64-NEXT: # kill: %EDX %EDX %RDX -; X64-NEXT: # kill: %ESI %ESI %RSI -; X64-NEXT: # kill: %EDI %EDI %RDI -; X64-NEXT: andl $1, %edi -; X64-NEXT: andl $1, %esi -; X64-NEXT: andl $1, %edx -; X64-NEXT: andl $1, %ecx -; X64-NEXT: leal (%rdi,%rsi,2), %eax -; X64-NEXT: leal (%rax,%rdx,4), %eax -; X64-NEXT: leal (%rax,%rcx,8), %eax -; X64-NEXT: retq -; -; X64-SSE2-LABEL: PR15215_good: -; X64-SSE2: # BB#0: # %entry -; X64-SSE2-NEXT: movd %xmm0, %eax -; X64-SSE2-NEXT: andl $1, %eax -; X64-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,2,3] -; X64-SSE2-NEXT: movd %xmm1, %ecx -; X64-SSE2-NEXT: andl $1, %ecx -; X64-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,0,1] -; X64-SSE2-NEXT: movd %xmm1, %edx -; X64-SSE2-NEXT: andl $1, %edx -; X64-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,2,3] -; X64-SSE2-NEXT: movd %xmm0, %esi -; X64-SSE2-NEXT: andl $1, %esi -; X64-SSE2-NEXT: leal (%rax,%rcx,2), %eax -; X64-SSE2-NEXT: leal (%rax,%rdx,4), %eax -; X64-SSE2-NEXT: leal (%rax,%rsi,8), %eax -; X64-SSE2-NEXT: retq -; -; X64-AVX2-LABEL: PR15215_good: -; X64-AVX2: # BB#0: # %entry -; X64-AVX2-NEXT: vmovd %xmm0, %eax -; X64-AVX2-NEXT: andl $1, %eax -; X64-AVX2-NEXT: vpextrd $1, %xmm0, %ecx -; X64-AVX2-NEXT: andl $1, %ecx -; X64-AVX2-NEXT: vpextrd $2, %xmm0, %edx -; X64-AVX2-NEXT: andl $1, %edx -; X64-AVX2-NEXT: vpextrd $3, %xmm0, %esi -; X64-AVX2-NEXT: andl $1, %esi -; X64-AVX2-NEXT: leal (%rax,%rcx,2), %eax -; X64-AVX2-NEXT: leal (%rax,%rdx,4), %eax -; X64-AVX2-NEXT: leal (%rax,%rsi,8), %eax -; X64-AVX2-NEXT: retq -entry: - %0 = trunc <4 x i32> %input to <4 x i1> - %1 = extractelement <4 x i1> %0, i32 0 - %e1 = select i1 %1, i32 1, i32 0 - %2 = extractelement <4 x i1> %0, i32 1 - %e2 = select i1 %2, i32 2, i32 0 - %3 = extractelement <4 x i1> %0, i32 2 - %e3 = select i1 %3, i32 4, i32 0 - %4 = extractelement <4 x i1> %0, i32 3 - %e4 = select i1 %4, i32 8, i32 0 - %5 = or i32 %e1, %e2 - %6 = or i32 %5, %e3 - %7 = or i32 %6, %e4 - ret i32 %7 -} Index: test/CodeGen/X86/psubus.ll =================================================================== --- test/CodeGen/X86/psubus.ll +++ test/CodeGen/X86/psubus.ll @@ -464,17 +464,20 @@ ; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [2147483648,2147483648,2147483648,2147483648] ; SSE2-NEXT: movdqa %xmm0, %xmm5 ; SSE2-NEXT: psubd %xmm2, %xmm0 -; SSE2-NEXT: movdqa %xmm2, %xmm6 -; SSE2-NEXT: pxor %xmm4, %xmm6 +; SSE2-NEXT: pxor %xmm4, %xmm2 ; SSE2-NEXT: pxor %xmm4, %xmm5 -; SSE2-NEXT: pcmpgtd %xmm5, %xmm6 -; SSE2-NEXT: packssdw %xmm0, %xmm6 +; SSE2-NEXT: pcmpgtd %xmm5, %xmm2 +; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,2,2,3,4,5,6,7] +; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,4,6,6,7] +; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm2[0,2,2,3] ; SSE2-NEXT: movdqa %xmm1, %xmm2 ; SSE2-NEXT: pxor %xmm4, %xmm2 ; SSE2-NEXT: pxor %xmm3, %xmm4 ; SSE2-NEXT: pcmpgtd %xmm4, %xmm2 -; SSE2-NEXT: packssdw %xmm0, %xmm2 -; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm6[0] +; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,2,2,3,4,5,6,7] +; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,4,6,6,7] +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3] +; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm5[0] ; SSE2-NEXT: psubd %xmm1, %xmm3 ; SSE2-NEXT: pslld $16, %xmm0 ; SSE2-NEXT: psrad $16, %xmm0 @@ -498,17 +501,17 @@ ; SSSE3-NEXT: pxor %xmm4, %xmm6 ; SSSE3-NEXT: pxor %xmm4, %xmm5 ; SSSE3-NEXT: pcmpgtd %xmm5, %xmm6 -; SSSE3-NEXT: packssdw %xmm0, %xmm6 +; SSSE3-NEXT: movdqa {{.*#+}} xmm5 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] +; SSSE3-NEXT: pshufb %xmm5, %xmm6 ; SSSE3-NEXT: movdqa %xmm1, %xmm2 ; SSSE3-NEXT: pxor %xmm4, %xmm2 ; SSSE3-NEXT: pxor %xmm3, %xmm4 ; SSSE3-NEXT: pcmpgtd %xmm4, %xmm2 -; SSSE3-NEXT: packssdw %xmm0, %xmm2 +; SSSE3-NEXT: pshufb %xmm5, %xmm2 ; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm6[0] ; SSSE3-NEXT: psubd %xmm1, %xmm3 -; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] -; SSSE3-NEXT: pshufb %xmm1, %xmm0 -; SSSE3-NEXT: pshufb %xmm1, %xmm3 +; SSSE3-NEXT: pshufb %xmm5, %xmm0 +; SSSE3-NEXT: pshufb %xmm5, %xmm3 ; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm0[0] ; SSSE3-NEXT: pandn %xmm3, %xmm2 ; SSSE3-NEXT: movdqa %xmm2, %xmm0 @@ -526,15 +529,15 @@ ; SSE41-NEXT: pxor %xmm5, %xmm0 ; SSE41-NEXT: pxor %xmm5, %xmm6 ; SSE41-NEXT: pcmpgtd %xmm6, %xmm0 -; SSE41-NEXT: packssdw %xmm0, %xmm0 -; SSE41-NEXT: movdqa %xmm2, %xmm1 -; SSE41-NEXT: pxor %xmm5, %xmm1 +; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] +; SSE41-NEXT: pshufb %xmm1, %xmm0 +; SSE41-NEXT: movdqa %xmm2, %xmm6 +; SSE41-NEXT: pxor %xmm5, %xmm6 ; SSE41-NEXT: pxor %xmm4, %xmm5 -; SSE41-NEXT: pcmpgtd %xmm5, %xmm1 -; SSE41-NEXT: packssdw %xmm0, %xmm1 -; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] +; SSE41-NEXT: pcmpgtd %xmm5, %xmm6 +; SSE41-NEXT: pshufb %xmm1, %xmm6 +; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm6[0] ; SSE41-NEXT: psubd %xmm2, %xmm4 -; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] ; SSE41-NEXT: pshufb %xmm1, %xmm3 ; SSE41-NEXT: pshufb %xmm1, %xmm4 ; SSE41-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm4[0] @@ -852,30 +855,35 @@ define <8 x i16> @test15(<8 x i16> %x, <8 x i32> %y) nounwind { ; SSE2-LABEL: test15: ; SSE2: # BB#0: # %vector.ph -; SSE2-NEXT: movdqa %xmm0, %xmm3 ; SSE2-NEXT: pxor %xmm4, %xmm4 -; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1],xmm0[2],xmm4[2],xmm0[3],xmm4[3] -; SSE2-NEXT: punpckhwd {{.*#+}} xmm3 = xmm3[4],xmm4[4],xmm3[5],xmm4[5],xmm3[6],xmm4[6],xmm3[7],xmm4[7] +; SSE2-NEXT: movdqa %xmm0, %xmm3 +; SSE2-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1],xmm3[2],xmm4[2],xmm3[3],xmm4[3] +; SSE2-NEXT: punpckhwd {{.*#+}} xmm0 = xmm0[4],xmm4[4],xmm0[5],xmm4[5],xmm0[6],xmm4[6],xmm0[7],xmm4[7] ; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [2147483648,2147483648,2147483648,2147483648] -; SSE2-NEXT: movdqa %xmm3, %xmm5 -; SSE2-NEXT: psubd %xmm2, %xmm3 +; SSE2-NEXT: movdqa %xmm0, %xmm5 +; SSE2-NEXT: psubd %xmm2, %xmm0 ; SSE2-NEXT: pxor %xmm4, %xmm2 ; SSE2-NEXT: pxor %xmm4, %xmm5 ; SSE2-NEXT: pcmpgtd %xmm2, %xmm5 -; SSE2-NEXT: packssdw %xmm0, %xmm5 -; SSE2-NEXT: movdqa %xmm1, %xmm2 -; SSE2-NEXT: pxor %xmm4, %xmm2 -; SSE2-NEXT: pxor %xmm0, %xmm4 -; SSE2-NEXT: pcmpgtd %xmm2, %xmm4 -; SSE2-NEXT: packssdw %xmm0, %xmm4 -; SSE2-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm5[0] -; SSE2-NEXT: psubd %xmm1, %xmm0 -; SSE2-NEXT: pslld $16, %xmm3 -; SSE2-NEXT: psrad $16, %xmm3 +; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm5[0,2,2,3,4,5,6,7] +; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,4,6,6,7] +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3] +; SSE2-NEXT: movdqa %xmm1, %xmm5 +; SSE2-NEXT: pxor %xmm4, %xmm5 +; SSE2-NEXT: pxor %xmm3, %xmm4 +; SSE2-NEXT: pcmpgtd %xmm5, %xmm4 +; SSE2-NEXT: pshuflw {{.*#+}} xmm4 = xmm4[0,2,2,3,4,5,6,7] +; SSE2-NEXT: pshufhw {{.*#+}} xmm4 = xmm4[0,1,2,3,4,6,6,7] +; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[0,2,2,3] +; SSE2-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm2[0] +; SSE2-NEXT: psubd %xmm1, %xmm3 ; SSE2-NEXT: pslld $16, %xmm0 ; SSE2-NEXT: psrad $16, %xmm0 -; SSE2-NEXT: packssdw %xmm3, %xmm0 -; SSE2-NEXT: pand %xmm4, %xmm0 +; SSE2-NEXT: pslld $16, %xmm3 +; SSE2-NEXT: psrad $16, %xmm3 +; SSE2-NEXT: packssdw %xmm0, %xmm3 +; SSE2-NEXT: pand %xmm4, %xmm3 +; SSE2-NEXT: movdqa %xmm3, %xmm0 ; SSE2-NEXT: retq ; ; SSSE3-LABEL: test15: @@ -890,17 +898,17 @@ ; SSSE3-NEXT: pxor %xmm4, %xmm2 ; SSSE3-NEXT: pxor %xmm4, %xmm5 ; SSSE3-NEXT: pcmpgtd %xmm2, %xmm5 -; SSSE3-NEXT: packssdw %xmm0, %xmm5 -; SSSE3-NEXT: movdqa %xmm1, %xmm2 -; SSSE3-NEXT: pxor %xmm4, %xmm2 +; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] +; SSSE3-NEXT: pshufb %xmm2, %xmm5 +; SSSE3-NEXT: movdqa %xmm1, %xmm6 +; SSSE3-NEXT: pxor %xmm4, %xmm6 ; SSSE3-NEXT: pxor %xmm3, %xmm4 -; SSSE3-NEXT: pcmpgtd %xmm2, %xmm4 -; SSSE3-NEXT: packssdw %xmm0, %xmm4 +; SSSE3-NEXT: pcmpgtd %xmm6, %xmm4 +; SSSE3-NEXT: pshufb %xmm2, %xmm4 ; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm5[0] ; SSSE3-NEXT: psubd %xmm1, %xmm3 -; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] -; SSSE3-NEXT: pshufb %xmm1, %xmm0 -; SSSE3-NEXT: pshufb %xmm1, %xmm3 +; SSSE3-NEXT: pshufb %xmm2, %xmm0 +; SSSE3-NEXT: pshufb %xmm2, %xmm3 ; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm0[0] ; SSSE3-NEXT: pand %xmm4, %xmm3 ; SSSE3-NEXT: movdqa %xmm3, %xmm0 @@ -917,15 +925,15 @@ ; SSE41-NEXT: pxor %xmm4, %xmm1 ; SSE41-NEXT: pxor %xmm4, %xmm5 ; SSE41-NEXT: pcmpgtd %xmm1, %xmm5 -; SSE41-NEXT: packssdw %xmm0, %xmm5 -; SSE41-NEXT: movdqa %xmm2, %xmm1 -; SSE41-NEXT: pxor %xmm4, %xmm1 +; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] +; SSE41-NEXT: pshufb %xmm1, %xmm5 +; SSE41-NEXT: movdqa %xmm2, %xmm6 +; SSE41-NEXT: pxor %xmm4, %xmm6 ; SSE41-NEXT: pxor %xmm3, %xmm4 -; SSE41-NEXT: pcmpgtd %xmm1, %xmm4 -; SSE41-NEXT: packssdw %xmm0, %xmm4 +; SSE41-NEXT: pcmpgtd %xmm6, %xmm4 +; SSE41-NEXT: pshufb %xmm1, %xmm4 ; SSE41-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm4[0] ; SSE41-NEXT: psubd %xmm2, %xmm3 -; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] ; SSE41-NEXT: pshufb %xmm1, %xmm0 ; SSE41-NEXT: pshufb %xmm1, %xmm3 ; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm3[0] @@ -992,30 +1000,35 @@ define <8 x i16> @test16(<8 x i16> %x, <8 x i32> %y) nounwind { ; SSE2-LABEL: test16: ; SSE2: # BB#0: # %vector.ph -; SSE2-NEXT: movdqa %xmm0, %xmm3 ; SSE2-NEXT: pxor %xmm4, %xmm4 -; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1],xmm0[2],xmm4[2],xmm0[3],xmm4[3] -; SSE2-NEXT: punpckhwd {{.*#+}} xmm3 = xmm3[4],xmm4[4],xmm3[5],xmm4[5],xmm3[6],xmm4[6],xmm3[7],xmm4[7] +; SSE2-NEXT: movdqa %xmm0, %xmm3 +; SSE2-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1],xmm3[2],xmm4[2],xmm3[3],xmm4[3] +; SSE2-NEXT: punpckhwd {{.*#+}} xmm0 = xmm0[4],xmm4[4],xmm0[5],xmm4[5],xmm0[6],xmm4[6],xmm0[7],xmm4[7] ; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [2147483648,2147483648,2147483648,2147483648] -; SSE2-NEXT: movdqa %xmm3, %xmm5 -; SSE2-NEXT: psubd %xmm2, %xmm3 +; SSE2-NEXT: movdqa %xmm0, %xmm5 +; SSE2-NEXT: psubd %xmm2, %xmm0 ; SSE2-NEXT: pxor %xmm4, %xmm2 ; SSE2-NEXT: pxor %xmm4, %xmm5 ; SSE2-NEXT: pcmpgtd %xmm2, %xmm5 -; SSE2-NEXT: packssdw %xmm0, %xmm5 -; SSE2-NEXT: movdqa %xmm1, %xmm2 -; SSE2-NEXT: pxor %xmm4, %xmm2 -; SSE2-NEXT: pxor %xmm0, %xmm4 -; SSE2-NEXT: pcmpgtd %xmm2, %xmm4 -; SSE2-NEXT: packssdw %xmm0, %xmm4 -; SSE2-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm5[0] -; SSE2-NEXT: psubd %xmm1, %xmm0 -; SSE2-NEXT: pslld $16, %xmm3 -; SSE2-NEXT: psrad $16, %xmm3 +; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm5[0,2,2,3,4,5,6,7] +; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,4,6,6,7] +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3] +; SSE2-NEXT: movdqa %xmm1, %xmm5 +; SSE2-NEXT: pxor %xmm4, %xmm5 +; SSE2-NEXT: pxor %xmm3, %xmm4 +; SSE2-NEXT: pcmpgtd %xmm5, %xmm4 +; SSE2-NEXT: pshuflw {{.*#+}} xmm4 = xmm4[0,2,2,3,4,5,6,7] +; SSE2-NEXT: pshufhw {{.*#+}} xmm4 = xmm4[0,1,2,3,4,6,6,7] +; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[0,2,2,3] +; SSE2-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm2[0] +; SSE2-NEXT: psubd %xmm1, %xmm3 ; SSE2-NEXT: pslld $16, %xmm0 ; SSE2-NEXT: psrad $16, %xmm0 -; SSE2-NEXT: packssdw %xmm3, %xmm0 -; SSE2-NEXT: pand %xmm4, %xmm0 +; SSE2-NEXT: pslld $16, %xmm3 +; SSE2-NEXT: psrad $16, %xmm3 +; SSE2-NEXT: packssdw %xmm0, %xmm3 +; SSE2-NEXT: pand %xmm4, %xmm3 +; SSE2-NEXT: movdqa %xmm3, %xmm0 ; SSE2-NEXT: retq ; ; SSSE3-LABEL: test16: @@ -1030,17 +1043,17 @@ ; SSSE3-NEXT: pxor %xmm4, %xmm2 ; SSSE3-NEXT: pxor %xmm4, %xmm5 ; SSSE3-NEXT: pcmpgtd %xmm2, %xmm5 -; SSSE3-NEXT: packssdw %xmm0, %xmm5 -; SSSE3-NEXT: movdqa %xmm1, %xmm2 -; SSSE3-NEXT: pxor %xmm4, %xmm2 +; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] +; SSSE3-NEXT: pshufb %xmm2, %xmm5 +; SSSE3-NEXT: movdqa %xmm1, %xmm6 +; SSSE3-NEXT: pxor %xmm4, %xmm6 ; SSSE3-NEXT: pxor %xmm3, %xmm4 -; SSSE3-NEXT: pcmpgtd %xmm2, %xmm4 -; SSSE3-NEXT: packssdw %xmm0, %xmm4 +; SSSE3-NEXT: pcmpgtd %xmm6, %xmm4 +; SSSE3-NEXT: pshufb %xmm2, %xmm4 ; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm5[0] ; SSSE3-NEXT: psubd %xmm1, %xmm3 -; SSSE3-NEXT: movdqa {{.*#+}} xmm1 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] -; SSSE3-NEXT: pshufb %xmm1, %xmm0 -; SSSE3-NEXT: pshufb %xmm1, %xmm3 +; SSSE3-NEXT: pshufb %xmm2, %xmm0 +; SSSE3-NEXT: pshufb %xmm2, %xmm3 ; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm0[0] ; SSSE3-NEXT: pand %xmm4, %xmm3 ; SSSE3-NEXT: movdqa %xmm3, %xmm0 @@ -1057,15 +1070,15 @@ ; SSE41-NEXT: pxor %xmm4, %xmm1 ; SSE41-NEXT: pxor %xmm4, %xmm5 ; SSE41-NEXT: pcmpgtd %xmm1, %xmm5 -; SSE41-NEXT: packssdw %xmm0, %xmm5 -; SSE41-NEXT: movdqa %xmm2, %xmm1 -; SSE41-NEXT: pxor %xmm4, %xmm1 +; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] +; SSE41-NEXT: pshufb %xmm1, %xmm5 +; SSE41-NEXT: movdqa %xmm2, %xmm6 +; SSE41-NEXT: pxor %xmm4, %xmm6 ; SSE41-NEXT: pxor %xmm3, %xmm4 -; SSE41-NEXT: pcmpgtd %xmm1, %xmm4 -; SSE41-NEXT: packssdw %xmm0, %xmm4 +; SSE41-NEXT: pcmpgtd %xmm6, %xmm4 +; SSE41-NEXT: pshufb %xmm1, %xmm4 ; SSE41-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm4[0] ; SSE41-NEXT: psubd %xmm2, %xmm3 -; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] ; SSE41-NEXT: pshufb %xmm1, %xmm0 ; SSE41-NEXT: pshufb %xmm1, %xmm3 ; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm3[0] Index: test/CodeGen/X86/shuffle-strided-with-offset-256.ll =================================================================== --- test/CodeGen/X86/shuffle-strided-with-offset-256.ll +++ test/CodeGen/X86/shuffle-strided-with-offset-256.ll @@ -88,8 +88,7 @@ ; AVX2-LABEL: shuffle_v16i16_to_v8i16_1: ; AVX2: # BB#0: ; AVX2-NEXT: vmovdqa (%rdi), %ymm0 -; AVX2-NEXT: vpsrld $16, %ymm0, %ymm0 -; AVX2-NEXT: vpackusdw %ymm0, %ymm0, %ymm0 +; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[2,3,6,7,10,11,14,15,10,11,14,15,14,15],zero,zero,ymm0[18,19,22,23,26,27,30,31,26,27,30,31,30,31],zero,zero ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] ; AVX2-NEXT: vmovdqa %xmm0, (%rsi) ; AVX2-NEXT: vzeroupper Index: test/CodeGen/X86/sjlj-eh.ll =================================================================== --- test/CodeGen/X86/sjlj-eh.ll +++ test/CodeGen/X86/sjlj-eh.ll @@ -88,7 +88,7 @@ ; CHECK-X64: leaq __gxx_personality_sj0(%rip), %rax ; CHECK-X64: movq %rax, -280(%rbp) ; UFC.__lsda = $LSDA -; CHECK-X64: leaq [[LSDA:GCC_except_table[0-9]+]](%rip), %rax +; CHECK-X64: movl $[[LSDA:GCC_except_table[0-9]+]], %eax ; CHECK-X64: movq %rax, -272(%rbp) ; UFC.__jbuf[0] = $RBP ; CHECK-X64: movq %rbp, -264(%rbp) Index: test/CodeGen/X86/sse2-intrinsics-x86.ll =================================================================== --- test/CodeGen/X86/sse2-intrinsics-x86.ll +++ test/CodeGen/X86/sse2-intrinsics-x86.ll @@ -684,22 +684,22 @@ define <8 x i16> @test_x86_sse2_packssdw_128_fold() { ; SSE-LABEL: test_x86_sse2_packssdw_128_fold: ; SSE: ## BB#0: -; SSE-NEXT: movaps {{.*#+}} xmm0 = [0,0,0,0,32767,32767,65535,32768] -; SSE-NEXT: ## encoding: [0x0f,0x28,0x05,A,A,A,A] -; SSE-NEXT: ## fixup A - offset: 3, value: LCPI32_0, kind: FK_Data_4 +; SSE-NEXT: pxor %xmm0, %xmm0 ## encoding: [0x66,0x0f,0xef,0xc0] +; SSE-NEXT: packssdw LCPI32_0, %xmm0 ## encoding: [0x66,0x0f,0x6b,0x05,A,A,A,A] +; SSE-NEXT: ## fixup A - offset: 4, value: LCPI32_0, kind: FK_Data_4 ; SSE-NEXT: retl ## encoding: [0xc3] ; ; AVX2-LABEL: test_x86_sse2_packssdw_128_fold: ; AVX2: ## BB#0: -; AVX2-NEXT: vmovaps {{.*#+}} xmm0 = [0,0,0,0,32767,32767,65535,32768] -; AVX2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A] +; AVX2-NEXT: vpxor %xmm0, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xef,0xc0] +; AVX2-NEXT: vpackssdw LCPI32_0, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0x6b,0x05,A,A,A,A] ; AVX2-NEXT: ## fixup A - offset: 4, value: LCPI32_0, kind: FK_Data_4 ; AVX2-NEXT: retl ## encoding: [0xc3] ; ; SKX-LABEL: test_x86_sse2_packssdw_128_fold: ; SKX: ## BB#0: -; SKX-NEXT: vmovaps LCPI32_0, %xmm0 ## EVEX TO VEX Compression xmm0 = [0,0,0,0,32767,32767,65535,32768] -; SKX-NEXT: ## encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A] +; SKX-NEXT: vpxor %xmm0, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xef,0xc0] +; SKX-NEXT: vpackssdw LCPI32_0, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6b,0x05,A,A,A,A] ; SKX-NEXT: ## fixup A - offset: 4, value: LCPI32_0, kind: FK_Data_4 ; SKX-NEXT: retl ## encoding: [0xc3] %res = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> zeroinitializer, <4 x i32> ) @@ -731,23 +731,29 @@ define <16 x i8> @test_x86_sse2_packsswb_128_fold() { ; SSE-LABEL: test_x86_sse2_packsswb_128_fold: ; SSE: ## BB#0: -; SSE-NEXT: movaps {{.*#+}} xmm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0] -; SSE-NEXT: ## encoding: [0x0f,0x28,0x05,A,A,A,A] -; SSE-NEXT: ## fixup A - offset: 3, value: LCPI34_0, kind: FK_Data_4 +; SSE-NEXT: pxor %xmm1, %xmm1 ## encoding: [0x66,0x0f,0xef,0xc9] +; SSE-NEXT: movdqa {{.*#+}} xmm0 = [0,255,256,65535,65535,65281,65280,32858] +; SSE-NEXT: ## encoding: [0x66,0x0f,0x6f,0x05,A,A,A,A] +; SSE-NEXT: ## fixup A - offset: 4, value: LCPI34_0, kind: FK_Data_4 +; SSE-NEXT: packsswb %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x63,0xc1] ; SSE-NEXT: retl ## encoding: [0xc3] ; ; AVX2-LABEL: test_x86_sse2_packsswb_128_fold: ; AVX2: ## BB#0: -; AVX2-NEXT: vmovaps {{.*#+}} xmm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0] -; AVX2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A] +; AVX2-NEXT: vpxor %xmm0, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xef,0xc0] +; AVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [0,255,256,65535,65535,65281,65280,32858] +; AVX2-NEXT: ## encoding: [0xc5,0xf9,0x6f,0x0d,A,A,A,A] ; AVX2-NEXT: ## fixup A - offset: 4, value: LCPI34_0, kind: FK_Data_4 +; AVX2-NEXT: vpacksswb %xmm0, %xmm1, %xmm0 ## encoding: [0xc5,0xf1,0x63,0xc0] ; AVX2-NEXT: retl ## encoding: [0xc3] ; ; SKX-LABEL: test_x86_sse2_packsswb_128_fold: ; SKX: ## BB#0: -; SKX-NEXT: vmovaps LCPI34_0, %xmm0 ## EVEX TO VEX Compression xmm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0] -; SKX-NEXT: ## encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A] +; SKX-NEXT: vpxor %xmm0, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xef,0xc0] +; SKX-NEXT: vmovdqa LCPI34_0, %xmm1 ## EVEX TO VEX Compression xmm1 = [0,255,256,65535,65535,65281,65280,32858] +; SKX-NEXT: ## encoding: [0xc5,0xf9,0x6f,0x0d,A,A,A,A] ; SKX-NEXT: ## fixup A - offset: 4, value: LCPI34_0, kind: FK_Data_4 +; SKX-NEXT: vpacksswb %xmm0, %xmm1, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf1,0x63,0xc0] ; SKX-NEXT: retl ## encoding: [0xc3] %res = call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> , <8 x i16> zeroinitializer) ret <16 x i8> %res @@ -778,23 +784,29 @@ define <16 x i8> @test_x86_sse2_packuswb_128_fold() { ; SSE-LABEL: test_x86_sse2_packuswb_128_fold: ; SSE: ## BB#0: -; SSE-NEXT: movaps {{.*#+}} xmm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0] -; SSE-NEXT: ## encoding: [0x0f,0x28,0x05,A,A,A,A] -; SSE-NEXT: ## fixup A - offset: 3, value: LCPI36_0, kind: FK_Data_4 +; SSE-NEXT: pxor %xmm1, %xmm1 ## encoding: [0x66,0x0f,0xef,0xc9] +; SSE-NEXT: movdqa {{.*#+}} xmm0 = [0,255,256,65535,65535,65281,65280,32858] +; SSE-NEXT: ## encoding: [0x66,0x0f,0x6f,0x05,A,A,A,A] +; SSE-NEXT: ## fixup A - offset: 4, value: LCPI36_0, kind: FK_Data_4 +; SSE-NEXT: packuswb %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x67,0xc1] ; SSE-NEXT: retl ## encoding: [0xc3] ; ; AVX2-LABEL: test_x86_sse2_packuswb_128_fold: ; AVX2: ## BB#0: -; AVX2-NEXT: vmovaps {{.*#+}} xmm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0] -; AVX2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A] +; AVX2-NEXT: vpxor %xmm0, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xef,0xc0] +; AVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [0,255,256,65535,65535,65281,65280,32858] +; AVX2-NEXT: ## encoding: [0xc5,0xf9,0x6f,0x0d,A,A,A,A] ; AVX2-NEXT: ## fixup A - offset: 4, value: LCPI36_0, kind: FK_Data_4 +; AVX2-NEXT: vpackuswb %xmm0, %xmm1, %xmm0 ## encoding: [0xc5,0xf1,0x67,0xc0] ; AVX2-NEXT: retl ## encoding: [0xc3] ; ; SKX-LABEL: test_x86_sse2_packuswb_128_fold: ; SKX: ## BB#0: -; SKX-NEXT: vmovaps LCPI36_0, %xmm0 ## EVEX TO VEX Compression xmm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0] -; SKX-NEXT: ## encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A] +; SKX-NEXT: vpxor %xmm0, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xef,0xc0] +; SKX-NEXT: vmovdqa LCPI36_0, %xmm1 ## EVEX TO VEX Compression xmm1 = [0,255,256,65535,65535,65281,65280,32858] +; SKX-NEXT: ## encoding: [0xc5,0xf9,0x6f,0x0d,A,A,A,A] ; SKX-NEXT: ## fixup A - offset: 4, value: LCPI36_0, kind: FK_Data_4 +; SKX-NEXT: vpackuswb %xmm0, %xmm1, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf1,0x67,0xc0] ; SKX-NEXT: retl ## encoding: [0xc3] %res = call <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16> , <8 x i16> zeroinitializer) ret <16 x i8> %res Index: test/CodeGen/X86/sse41-intrinsics-x86.ll =================================================================== --- test/CodeGen/X86/sse41-intrinsics-x86.ll +++ test/CodeGen/X86/sse41-intrinsics-x86.ll @@ -138,23 +138,23 @@ define <8 x i16> @test_x86_sse41_packusdw_fold() { ; SSE41-LABEL: test_x86_sse41_packusdw_fold: ; SSE41: ## BB#0: -; SSE41-NEXT: movaps {{.*#+}} xmm0 = [0,0,0,0,65535,65535,0,0] -; SSE41-NEXT: ## encoding: [0x0f,0x28,0x05,A,A,A,A] -; SSE41-NEXT: ## fixup A - offset: 3, value: LCPI7_0, kind: FK_Data_4 +; SSE41-NEXT: pxor %xmm0, %xmm0 ## encoding: [0x66,0x0f,0xef,0xc0] +; SSE41-NEXT: packusdw LCPI7_0, %xmm0 ## encoding: [0x66,0x0f,0x38,0x2b,0x05,A,A,A,A] +; SSE41-NEXT: ## fixup A - offset: 5, value: LCPI7_0, kind: FK_Data_4 ; SSE41-NEXT: retl ## encoding: [0xc3] ; ; AVX2-LABEL: test_x86_sse41_packusdw_fold: ; AVX2: ## BB#0: -; AVX2-NEXT: vmovaps {{.*#+}} xmm0 = [0,0,0,0,65535,65535,0,0] -; AVX2-NEXT: ## encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A] -; AVX2-NEXT: ## fixup A - offset: 4, value: LCPI7_0, kind: FK_Data_4 +; AVX2-NEXT: vpxor %xmm0, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xef,0xc0] +; AVX2-NEXT: vpackusdw LCPI7_0, %xmm0, %xmm0 ## encoding: [0xc4,0xe2,0x79,0x2b,0x05,A,A,A,A] +; AVX2-NEXT: ## fixup A - offset: 5, value: LCPI7_0, kind: FK_Data_4 ; AVX2-NEXT: retl ## encoding: [0xc3] ; ; SKX-LABEL: test_x86_sse41_packusdw_fold: ; SKX: ## BB#0: -; SKX-NEXT: vmovaps LCPI7_0, %xmm0 ## EVEX TO VEX Compression xmm0 = [0,0,0,0,65535,65535,0,0] -; SKX-NEXT: ## encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A] -; SKX-NEXT: ## fixup A - offset: 4, value: LCPI7_0, kind: FK_Data_4 +; SKX-NEXT: vpxor %xmm0, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xef,0xc0] +; SKX-NEXT: vpackusdw LCPI7_0, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x2b,0x05,A,A,A,A] +; SKX-NEXT: ## fixup A - offset: 5, value: LCPI7_0, kind: FK_Data_4 ; SKX-NEXT: retl ## encoding: [0xc3] %res = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> zeroinitializer, <4 x i32> ) ret <8 x i16> %res Index: test/CodeGen/X86/vector-compare-results.ll =================================================================== --- test/CodeGen/X86/vector-compare-results.ll +++ test/CodeGen/X86/vector-compare-results.ll @@ -886,11 +886,16 @@ ; SSE2-LABEL: test_cmp_v32i16: ; SSE2: # BB#0: ; SSE2-NEXT: pcmpgtw %xmm5, %xmm1 +; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [255,255,255,255,255,255,255,255] +; SSE2-NEXT: pand %xmm5, %xmm1 ; SSE2-NEXT: pcmpgtw %xmm4, %xmm0 -; SSE2-NEXT: packsswb %xmm1, %xmm0 +; SSE2-NEXT: pand %xmm5, %xmm0 +; SSE2-NEXT: packuswb %xmm1, %xmm0 ; SSE2-NEXT: pcmpgtw %xmm7, %xmm3 +; SSE2-NEXT: pand %xmm5, %xmm3 ; SSE2-NEXT: pcmpgtw %xmm6, %xmm2 -; SSE2-NEXT: packsswb %xmm3, %xmm2 +; SSE2-NEXT: pand %xmm5, %xmm2 +; SSE2-NEXT: packuswb %xmm3, %xmm2 ; SSE2-NEXT: movdqa %xmm2, -{{[0-9]+}}(%rsp) ; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al ; SSE2-NEXT: andb $1, %al @@ -3405,27 +3410,48 @@ ; SSE2-LABEL: test_cmp_v32i32: ; SSE2: # BB#0: ; SSE2-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm3 -; SSE2-NEXT: packssdw %xmm0, %xmm3 +; SSE2-NEXT: pshuflw {{.*#+}} xmm3 = xmm3[0,2,2,3,4,5,6,7] +; SSE2-NEXT: pshufhw {{.*#+}} xmm3 = xmm3[0,1,2,3,4,6,6,7] +; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3] ; SSE2-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm2 -; SSE2-NEXT: packssdw %xmm0, %xmm2 +; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,2,2,3,4,5,6,7] +; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,4,6,6,7] +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3] ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0] +; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [255,255,255,255,255,255,255,255] +; SSE2-NEXT: pand %xmm3, %xmm2 ; SSE2-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm1 -; SSE2-NEXT: packssdw %xmm0, %xmm1 +; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7] +; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,6,6,7] +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; SSE2-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm0 -; SSE2-NEXT: packssdw %xmm0, %xmm0 +; SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7] +; SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,6,7] +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] -; SSE2-NEXT: packsswb %xmm2, %xmm0 +; SSE2-NEXT: pand %xmm3, %xmm0 +; SSE2-NEXT: packuswb %xmm2, %xmm0 ; SSE2-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm7 -; SSE2-NEXT: packssdw %xmm0, %xmm7 +; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm7[0,2,2,3,4,5,6,7] +; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,6,6,7] +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; SSE2-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm6 -; SSE2-NEXT: packssdw %xmm0, %xmm6 -; SSE2-NEXT: punpcklqdq {{.*#+}} xmm6 = xmm6[0],xmm7[0] +; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm6[0,2,2,3,4,5,6,7] +; SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,4,6,6,7] +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3] +; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0] +; SSE2-NEXT: pand %xmm3, %xmm2 ; SSE2-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm5 -; SSE2-NEXT: packssdw %xmm0, %xmm5 +; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm5[0,2,2,3,4,5,6,7] +; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,6,6,7] +; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; SSE2-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm4 -; SSE2-NEXT: packssdw %xmm0, %xmm4 -; SSE2-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm5[0] -; SSE2-NEXT: packsswb %xmm6, %xmm4 +; SSE2-NEXT: pshuflw {{.*#+}} xmm4 = xmm4[0,2,2,3,4,5,6,7] +; SSE2-NEXT: pshufhw {{.*#+}} xmm4 = xmm4[0,1,2,3,4,6,6,7] +; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[0,2,2,3] +; SSE2-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm1[0] +; SSE2-NEXT: pand %xmm3, %xmm4 +; SSE2-NEXT: packuswb %xmm2, %xmm4 ; SSE2-NEXT: movdqa %xmm4, -{{[0-9]+}}(%rsp) ; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al ; SSE2-NEXT: andb $1, %al @@ -3529,119 +3555,105 @@ ; ; SSE42-LABEL: test_cmp_v32i32: ; SSE42: # BB#0: -; SSE42-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm3 -; SSE42-NEXT: packssdw %xmm0, %xmm3 -; SSE42-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm2 -; SSE42-NEXT: packssdw %xmm0, %xmm2 -; SSE42-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0] -; SSE42-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm1 -; SSE42-NEXT: packssdw %xmm0, %xmm1 ; SSE42-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm0 -; SSE42-NEXT: packssdw %xmm0, %xmm0 -; SSE42-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] -; SSE42-NEXT: packsswb %xmm2, %xmm0 -; SSE42-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm7 -; SSE42-NEXT: packssdw %xmm0, %xmm7 -; SSE42-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm6 -; SSE42-NEXT: packssdw %xmm0, %xmm6 -; SSE42-NEXT: punpcklqdq {{.*#+}} xmm6 = xmm6[0],xmm7[0] -; SSE42-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm5 -; SSE42-NEXT: packssdw %xmm0, %xmm5 +; SSE42-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm1 +; SSE42-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm2 +; SSE42-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm3 ; SSE42-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm4 -; SSE42-NEXT: packssdw %xmm0, %xmm4 -; SSE42-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm5[0] -; SSE42-NEXT: packsswb %xmm6, %xmm4 -; SSE42-NEXT: pextrb $15, %xmm4, %eax +; SSE42-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm5 +; SSE42-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm6 +; SSE42-NEXT: pcmpgtd {{[0-9]+}}(%rsp), %xmm7 +; SSE42-NEXT: pextrb $12, %xmm7, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, 2(%rdi) -; SSE42-NEXT: pextrb $14, %xmm4, %eax +; SSE42-NEXT: pextrb $8, %xmm7, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, 2(%rdi) -; SSE42-NEXT: pextrb $13, %xmm4, %eax +; SSE42-NEXT: pextrb $4, %xmm7, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, 2(%rdi) -; SSE42-NEXT: pextrb $12, %xmm4, %eax +; SSE42-NEXT: pextrb $0, %xmm7, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, 2(%rdi) -; SSE42-NEXT: pextrb $11, %xmm4, %eax +; SSE42-NEXT: pextrb $12, %xmm6, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, 2(%rdi) -; SSE42-NEXT: pextrb $10, %xmm4, %eax +; SSE42-NEXT: pextrb $8, %xmm6, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, 2(%rdi) -; SSE42-NEXT: pextrb $9, %xmm4, %eax +; SSE42-NEXT: pextrb $4, %xmm6, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, 2(%rdi) -; SSE42-NEXT: pextrb $8, %xmm4, %eax +; SSE42-NEXT: pextrb $0, %xmm6, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, 2(%rdi) -; SSE42-NEXT: pextrb $7, %xmm4, %eax +; SSE42-NEXT: pextrb $12, %xmm5, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, 2(%rdi) -; SSE42-NEXT: pextrb $6, %xmm4, %eax +; SSE42-NEXT: pextrb $8, %xmm5, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, 2(%rdi) -; SSE42-NEXT: pextrb $5, %xmm4, %eax +; SSE42-NEXT: pextrb $4, %xmm5, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, 2(%rdi) -; SSE42-NEXT: pextrb $4, %xmm4, %eax +; SSE42-NEXT: pextrb $0, %xmm5, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, 2(%rdi) -; SSE42-NEXT: pextrb $3, %xmm4, %eax +; SSE42-NEXT: pextrb $12, %xmm4, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, 2(%rdi) -; SSE42-NEXT: pextrb $2, %xmm4, %eax +; SSE42-NEXT: pextrb $8, %xmm4, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, 2(%rdi) -; SSE42-NEXT: pextrb $1, %xmm4, %eax +; SSE42-NEXT: pextrb $4, %xmm4, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, 2(%rdi) ; SSE42-NEXT: pextrb $0, %xmm4, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, 2(%rdi) -; SSE42-NEXT: pextrb $15, %xmm0, %eax +; SSE42-NEXT: pextrb $12, %xmm3, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, (%rdi) -; SSE42-NEXT: pextrb $14, %xmm0, %eax +; SSE42-NEXT: pextrb $8, %xmm3, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, (%rdi) -; SSE42-NEXT: pextrb $13, %xmm0, %eax +; SSE42-NEXT: pextrb $4, %xmm3, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, (%rdi) -; SSE42-NEXT: pextrb $12, %xmm0, %eax +; SSE42-NEXT: pextrb $0, %xmm3, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, (%rdi) -; SSE42-NEXT: pextrb $11, %xmm0, %eax +; SSE42-NEXT: pextrb $12, %xmm2, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, (%rdi) -; SSE42-NEXT: pextrb $10, %xmm0, %eax +; SSE42-NEXT: pextrb $8, %xmm2, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, (%rdi) -; SSE42-NEXT: pextrb $9, %xmm0, %eax +; SSE42-NEXT: pextrb $4, %xmm2, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, (%rdi) -; SSE42-NEXT: pextrb $8, %xmm0, %eax +; SSE42-NEXT: pextrb $0, %xmm2, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, (%rdi) -; SSE42-NEXT: pextrb $7, %xmm0, %eax +; SSE42-NEXT: pextrb $12, %xmm1, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, (%rdi) -; SSE42-NEXT: pextrb $6, %xmm0, %eax +; SSE42-NEXT: pextrb $8, %xmm1, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, (%rdi) -; SSE42-NEXT: pextrb $5, %xmm0, %eax +; SSE42-NEXT: pextrb $4, %xmm1, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, (%rdi) -; SSE42-NEXT: pextrb $4, %xmm0, %eax +; SSE42-NEXT: pextrb $0, %xmm1, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, (%rdi) -; SSE42-NEXT: pextrb $3, %xmm0, %eax +; SSE42-NEXT: pextrb $12, %xmm0, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, (%rdi) -; SSE42-NEXT: pextrb $2, %xmm0, %eax +; SSE42-NEXT: pextrb $8, %xmm0, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, (%rdi) -; SSE42-NEXT: pextrb $1, %xmm0, %eax +; SSE42-NEXT: pextrb $4, %xmm0, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, (%rdi) ; SSE42-NEXT: pextrb $0, %xmm0, %eax @@ -4353,17 +4365,26 @@ ; SSE2-LABEL: test_cmp_v64i16: ; SSE2: # BB#0: ; SSE2-NEXT: pcmpgtw {{[0-9]+}}(%rsp), %xmm1 +; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [255,255,255,255,255,255,255,255] +; SSE2-NEXT: pand %xmm8, %xmm1 ; SSE2-NEXT: pcmpgtw {{[0-9]+}}(%rsp), %xmm0 -; SSE2-NEXT: packsswb %xmm1, %xmm0 +; SSE2-NEXT: pand %xmm8, %xmm0 +; SSE2-NEXT: packuswb %xmm1, %xmm0 ; SSE2-NEXT: pcmpgtw {{[0-9]+}}(%rsp), %xmm3 +; SSE2-NEXT: pand %xmm8, %xmm3 ; SSE2-NEXT: pcmpgtw {{[0-9]+}}(%rsp), %xmm2 -; SSE2-NEXT: packsswb %xmm3, %xmm2 +; SSE2-NEXT: pand %xmm8, %xmm2 +; SSE2-NEXT: packuswb %xmm3, %xmm2 ; SSE2-NEXT: pcmpgtw {{[0-9]+}}(%rsp), %xmm5 +; SSE2-NEXT: pand %xmm8, %xmm5 ; SSE2-NEXT: pcmpgtw {{[0-9]+}}(%rsp), %xmm4 -; SSE2-NEXT: packsswb %xmm5, %xmm4 +; SSE2-NEXT: pand %xmm8, %xmm4 +; SSE2-NEXT: packuswb %xmm5, %xmm4 ; SSE2-NEXT: pcmpgtw {{[0-9]+}}(%rsp), %xmm7 +; SSE2-NEXT: pand %xmm8, %xmm7 ; SSE2-NEXT: pcmpgtw {{[0-9]+}}(%rsp), %xmm6 -; SSE2-NEXT: packsswb %xmm7, %xmm6 +; SSE2-NEXT: pand %xmm8, %xmm6 +; SSE2-NEXT: packuswb %xmm7, %xmm6 ; SSE2-NEXT: movdqa %xmm6, -{{[0-9]+}}(%rsp) ; SSE2-NEXT: movb -{{[0-9]+}}(%rsp), %al ; SSE2-NEXT: andb $1, %al @@ -9337,155 +9358,121 @@ ; ; SSE42-LABEL: test_cmp_v32i64: ; SSE42: # BB#0: -; SSE42-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm10 -; SSE42-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9 -; SSE42-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm11 -; SSE42-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm8 +; SSE42-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm15 ; SSE42-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm14 ; SSE42-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm13 -; SSE42-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm15 ; SSE42-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm12 -; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm7 -; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm6 -; SSE42-NEXT: shufps {{.*#+}} xmm6 = xmm6[0,2],xmm7[0,2] -; SSE42-NEXT: movdqa {{.*#+}} xmm7 = [0,1,4,5,4,5,6,7,0,1,4,5,8,9,12,13] -; SSE42-NEXT: pshufb %xmm7, %xmm6 -; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm5 -; SSE42-NEXT: pshufd {{.*#+}} xmm5 = xmm5[0,2,2,3] -; SSE42-NEXT: pshuflw {{.*#+}} xmm5 = xmm5[0,2,2,3,4,5,6,7] -; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm4 -; SSE42-NEXT: pshufd {{.*#+}} xmm4 = xmm4[0,2,2,3] -; SSE42-NEXT: pshuflw {{.*#+}} xmm4 = xmm4[0,2,2,3,4,5,6,7] -; SSE42-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1] -; SSE42-NEXT: pblendw {{.*#+}} xmm4 = xmm4[0,1,2,3],xmm6[4,5,6,7] -; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm3 -; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm2 -; SSE42-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm3[0,2] -; SSE42-NEXT: pshufb %xmm7, %xmm2 -; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm1 -; SSE42-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] -; SSE42-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7] +; SSE42-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm11 +; SSE42-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm10 +; SSE42-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9 +; SSE42-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm8 ; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm0 -; SSE42-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] -; SSE42-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7] -; SSE42-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] -; SSE42-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7] -; SSE42-NEXT: packsswb %xmm4, %xmm0 -; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm12 -; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [0,1,8,9,2,3,10,11,8,9,12,13,10,11,14,15] -; SSE42-NEXT: pshufb %xmm1, %xmm12 -; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm15 -; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm13 -; SSE42-NEXT: shufps {{.*#+}} xmm13 = xmm13[0,2],xmm15[0,2] -; SSE42-NEXT: pshufb %xmm7, %xmm13 -; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm14 -; SSE42-NEXT: pshufd {{.*#+}} xmm2 = xmm14[0,2,2,3] -; SSE42-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,1,0,2,4,5,6,7] -; SSE42-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm13[4,5,6,7] -; SSE42-NEXT: pblendw {{.*#+}} xmm2 = xmm12[0,1],xmm2[2,3,4,5,6,7] +; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm1 +; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm2 +; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm3 +; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm4 +; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm5 +; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm6 +; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm7 ; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm8 -; SSE42-NEXT: pshufb %xmm1, %xmm8 -; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm11 ; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm9 -; SSE42-NEXT: shufps {{.*#+}} xmm9 = xmm9[0,2],xmm11[0,2] -; SSE42-NEXT: pshufb %xmm7, %xmm9 ; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm10 -; SSE42-NEXT: pshufd {{.*#+}} xmm1 = xmm10[0,2,2,3] -; SSE42-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,1,0,2,4,5,6,7] -; SSE42-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm9[4,5,6,7] -; SSE42-NEXT: pblendw {{.*#+}} xmm1 = xmm8[0,1],xmm1[2,3,4,5,6,7] -; SSE42-NEXT: packsswb %xmm2, %xmm1 -; SSE42-NEXT: pextrb $15, %xmm1, %eax +; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm11 +; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm12 +; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm13 +; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm14 +; SSE42-NEXT: pcmpgtq {{[0-9]+}}(%rsp), %xmm15 +; SSE42-NEXT: pextrb $8, %xmm15, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, 2(%rdi) -; SSE42-NEXT: pextrb $14, %xmm1, %eax +; SSE42-NEXT: pextrb $0, %xmm15, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, 2(%rdi) -; SSE42-NEXT: pextrb $13, %xmm1, %eax +; SSE42-NEXT: pextrb $8, %xmm14, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, 2(%rdi) -; SSE42-NEXT: pextrb $12, %xmm1, %eax +; SSE42-NEXT: pextrb $0, %xmm14, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, 2(%rdi) -; SSE42-NEXT: pextrb $11, %xmm1, %eax +; SSE42-NEXT: pextrb $8, %xmm13, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, 2(%rdi) -; SSE42-NEXT: pextrb $10, %xmm1, %eax +; SSE42-NEXT: pextrb $0, %xmm13, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, 2(%rdi) -; SSE42-NEXT: pextrb $9, %xmm1, %eax +; SSE42-NEXT: pextrb $8, %xmm12, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, 2(%rdi) -; SSE42-NEXT: pextrb $8, %xmm1, %eax +; SSE42-NEXT: pextrb $0, %xmm12, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, 2(%rdi) -; SSE42-NEXT: pextrb $7, %xmm1, %eax +; SSE42-NEXT: pextrb $8, %xmm11, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, 2(%rdi) -; SSE42-NEXT: pextrb $6, %xmm1, %eax +; SSE42-NEXT: pextrb $0, %xmm11, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, 2(%rdi) -; SSE42-NEXT: pextrb $5, %xmm1, %eax +; SSE42-NEXT: pextrb $8, %xmm10, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, 2(%rdi) -; SSE42-NEXT: pextrb $4, %xmm1, %eax +; SSE42-NEXT: pextrb $0, %xmm10, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, 2(%rdi) -; SSE42-NEXT: pextrb $3, %xmm1, %eax +; SSE42-NEXT: pextrb $8, %xmm9, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, 2(%rdi) -; SSE42-NEXT: pextrb $2, %xmm1, %eax +; SSE42-NEXT: pextrb $0, %xmm9, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, 2(%rdi) -; SSE42-NEXT: pextrb $1, %xmm1, %eax +; SSE42-NEXT: pextrb $8, %xmm8, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, 2(%rdi) -; SSE42-NEXT: pextrb $0, %xmm1, %eax +; SSE42-NEXT: pextrb $0, %xmm8, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, 2(%rdi) -; SSE42-NEXT: pextrb $15, %xmm0, %eax +; SSE42-NEXT: pextrb $8, %xmm7, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, (%rdi) -; SSE42-NEXT: pextrb $14, %xmm0, %eax +; SSE42-NEXT: pextrb $0, %xmm7, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, (%rdi) -; SSE42-NEXT: pextrb $13, %xmm0, %eax +; SSE42-NEXT: pextrb $8, %xmm6, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, (%rdi) -; SSE42-NEXT: pextrb $12, %xmm0, %eax +; SSE42-NEXT: pextrb $0, %xmm6, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, (%rdi) -; SSE42-NEXT: pextrb $11, %xmm0, %eax +; SSE42-NEXT: pextrb $8, %xmm5, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, (%rdi) -; SSE42-NEXT: pextrb $10, %xmm0, %eax +; SSE42-NEXT: pextrb $0, %xmm5, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, (%rdi) -; SSE42-NEXT: pextrb $9, %xmm0, %eax +; SSE42-NEXT: pextrb $8, %xmm4, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, (%rdi) -; SSE42-NEXT: pextrb $8, %xmm0, %eax +; SSE42-NEXT: pextrb $0, %xmm4, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, (%rdi) -; SSE42-NEXT: pextrb $7, %xmm0, %eax +; SSE42-NEXT: pextrb $8, %xmm3, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, (%rdi) -; SSE42-NEXT: pextrb $6, %xmm0, %eax +; SSE42-NEXT: pextrb $0, %xmm3, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, (%rdi) -; SSE42-NEXT: pextrb $5, %xmm0, %eax +; SSE42-NEXT: pextrb $8, %xmm2, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, (%rdi) -; SSE42-NEXT: pextrb $4, %xmm0, %eax +; SSE42-NEXT: pextrb $0, %xmm2, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, (%rdi) -; SSE42-NEXT: pextrb $3, %xmm0, %eax +; SSE42-NEXT: pextrb $8, %xmm1, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, (%rdi) -; SSE42-NEXT: pextrb $2, %xmm0, %eax +; SSE42-NEXT: pextrb $0, %xmm1, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, (%rdi) -; SSE42-NEXT: pextrb $1, %xmm0, %eax +; SSE42-NEXT: pextrb $8, %xmm0, %eax ; SSE42-NEXT: andb $1, %al ; SSE42-NEXT: movb %al, (%rdi) ; SSE42-NEXT: pextrb $0, %xmm0, %eax Index: test/CodeGen/X86/vector-mul.ll =================================================================== --- test/CodeGen/X86/vector-mul.ll +++ test/CodeGen/X86/vector-mul.ll @@ -358,10 +358,13 @@ ; X64-XOP-NEXT: vpmovsxbw %xmm0, %xmm1 ; X64-XOP-NEXT: vmovdqa {{.*#+}} xmm2 = [17,17,17,17,17,17,17,17] ; X64-XOP-NEXT: vpmullw %xmm2, %xmm1, %xmm1 +; X64-XOP-NEXT: vmovdqa {{.*#+}} xmm3 = [255,255,255,255,255,255,255,255] +; X64-XOP-NEXT: vpand %xmm3, %xmm1, %xmm1 ; X64-XOP-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] ; X64-XOP-NEXT: vpmovsxbw %xmm0, %xmm0 ; X64-XOP-NEXT: vpmullw %xmm2, %xmm0, %xmm0 -; X64-XOP-NEXT: vpperm {{.*#+}} xmm0 = xmm1[0,2,4,6,8,10,12,14],xmm0[0,2,4,6,8,10,12,14] +; X64-XOP-NEXT: vpand %xmm3, %xmm0, %xmm0 +; X64-XOP-NEXT: vpackuswb %xmm0, %xmm1, %xmm0 ; X64-XOP-NEXT: retq ; ; X64-AVX2-LABEL: mul_v16i8_17: @@ -490,10 +493,13 @@ ; X64-XOP: # BB#0: ; X64-XOP-NEXT: vpmovsxbw %xmm0, %xmm1 ; X64-XOP-NEXT: vpmullw {{.*}}(%rip), %xmm1, %xmm1 +; X64-XOP-NEXT: vmovdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255] +; X64-XOP-NEXT: vpand %xmm2, %xmm1, %xmm1 ; X64-XOP-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] ; X64-XOP-NEXT: vpmovsxbw %xmm0, %xmm0 ; X64-XOP-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0 -; X64-XOP-NEXT: vpperm {{.*#+}} xmm0 = xmm1[0,2,4,6,8,10,12,14],xmm0[0,2,4,6,8,10,12,14] +; X64-XOP-NEXT: vpand %xmm2, %xmm0, %xmm0 +; X64-XOP-NEXT: vpackuswb %xmm0, %xmm1, %xmm0 ; X64-XOP-NEXT: retq ; ; X64-AVX2-LABEL: mul_v16i8_2_3_9_17_33_65_129_2_3_9_17_33_65_129_2_3: @@ -631,10 +637,13 @@ ; X64-XOP-NEXT: vpmovsxbw %xmm0, %xmm1 ; X64-XOP-NEXT: vmovdqa {{.*#+}} xmm2 = [31,31,31,31,31,31,31,31] ; X64-XOP-NEXT: vpmullw %xmm2, %xmm1, %xmm1 +; X64-XOP-NEXT: vmovdqa {{.*#+}} xmm3 = [255,255,255,255,255,255,255,255] +; X64-XOP-NEXT: vpand %xmm3, %xmm1, %xmm1 ; X64-XOP-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] ; X64-XOP-NEXT: vpmovsxbw %xmm0, %xmm0 ; X64-XOP-NEXT: vpmullw %xmm2, %xmm0, %xmm0 -; X64-XOP-NEXT: vpperm {{.*#+}} xmm0 = xmm1[0,2,4,6,8,10,12,14],xmm0[0,2,4,6,8,10,12,14] +; X64-XOP-NEXT: vpand %xmm3, %xmm0, %xmm0 +; X64-XOP-NEXT: vpackuswb %xmm0, %xmm1, %xmm0 ; X64-XOP-NEXT: retq ; ; X64-AVX2-LABEL: mul_v16i8_31: @@ -996,10 +1005,13 @@ ; X64-XOP-NEXT: vpmovsxbw %xmm0, %xmm1 ; X64-XOP-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,3,7,15,31,63,127] ; X64-XOP-NEXT: vpmullw %xmm2, %xmm1, %xmm1 +; X64-XOP-NEXT: vmovdqa {{.*#+}} xmm3 = [255,255,255,255,255,255,255,255] +; X64-XOP-NEXT: vpand %xmm3, %xmm1, %xmm1 ; X64-XOP-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] ; X64-XOP-NEXT: vpmovsxbw %xmm0, %xmm0 ; X64-XOP-NEXT: vpmullw %xmm2, %xmm0, %xmm0 -; X64-XOP-NEXT: vpperm {{.*#+}} xmm0 = xmm1[0,2,4,6,8,10,12,14],xmm0[0,2,4,6,8,10,12,14] +; X64-XOP-NEXT: vpand %xmm3, %xmm0, %xmm0 +; X64-XOP-NEXT: vpackuswb %xmm0, %xmm1, %xmm0 ; X64-XOP-NEXT: retq ; ; X64-AVX2-LABEL: mul_v16i8_0_1_3_7_15_31_63_127_0_1_3_7_15_31_63_127: Index: test/CodeGen/X86/vector-shift-ashr-128.ll =================================================================== --- test/CodeGen/X86/vector-shift-ashr-128.ll +++ test/CodeGen/X86/vector-shift-ashr-128.ll @@ -320,7 +320,7 @@ ; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero ; AVX2-NEXT: vpmovsxwd %xmm0, %ymm0 ; AVX2-NEXT: vpsravd %ymm1, %ymm0, %ymm0 -; AVX2-NEXT: vpackssdw %ymm0, %ymm0, %ymm0 +; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] ; AVX2-NEXT: # kill: %XMM0 %XMM0 %YMM0 ; AVX2-NEXT: vzeroupper @@ -1253,7 +1253,7 @@ ; AVX2: # BB#0: ; AVX2-NEXT: vpmovsxwd %xmm0, %ymm0 ; AVX2-NEXT: vpsravd {{.*}}(%rip), %ymm0, %ymm0 -; AVX2-NEXT: vpackssdw %ymm0, %ymm0, %ymm0 +; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] ; AVX2-NEXT: # kill: %XMM0 %XMM0 %YMM0 ; AVX2-NEXT: vzeroupper Index: test/CodeGen/X86/vector-trunc.ll =================================================================== --- test/CodeGen/X86/vector-trunc.ll +++ test/CodeGen/X86/vector-trunc.ll @@ -398,8 +398,9 @@ ; SSSE3: # BB#0: # %entry ; SSSE3-NEXT: psrad $16, %xmm0 ; SSSE3-NEXT: psrad $16, %xmm1 -; SSSE3-NEXT: packssdw %xmm0, %xmm1 -; SSSE3-NEXT: packssdw %xmm0, %xmm0 +; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] +; SSSE3-NEXT: pshufb %xmm2, %xmm1 +; SSSE3-NEXT: pshufb %xmm2, %xmm0 ; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; SSSE3-NEXT: retq ; @@ -407,8 +408,9 @@ ; SSE41: # BB#0: # %entry ; SSE41-NEXT: psrad $16, %xmm0 ; SSE41-NEXT: psrad $16, %xmm1 -; SSE41-NEXT: packssdw %xmm0, %xmm1 -; SSE41-NEXT: packssdw %xmm0, %xmm0 +; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] +; SSE41-NEXT: pshufb %xmm2, %xmm1 +; SSE41-NEXT: pshufb %xmm2, %xmm0 ; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; SSE41-NEXT: retq ; @@ -417,8 +419,9 @@ ; AVX1-NEXT: vpsrad $16, %xmm0, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; AVX1-NEXT: vpsrad $16, %xmm0, %xmm0 -; AVX1-NEXT: vpackssdw %xmm0, %xmm0, %xmm0 -; AVX1-NEXT: vpackssdw %xmm0, %xmm1, %xmm1 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] +; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1 ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0] ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq @@ -426,7 +429,7 @@ ; AVX2-LABEL: trunc8i32_8i16_ashr: ; AVX2: # BB#0: # %entry ; AVX2-NEXT: vpsrad $16, %ymm0, %ymm0 -; AVX2-NEXT: vpackssdw %ymm0, %ymm0, %ymm0 +; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] ; AVX2-NEXT: # kill: %XMM0 %XMM0 %YMM0 ; AVX2-NEXT: vzeroupper @@ -489,26 +492,25 @@ ; ; SSE41-LABEL: trunc8i32_8i16_lshr: ; SSE41: # BB#0: # %entry -; SSE41-NEXT: psrld $16, %xmm0 -; SSE41-NEXT: psrld $16, %xmm1 -; SSE41-NEXT: packusdw %xmm0, %xmm1 -; SSE41-NEXT: packusdw %xmm0, %xmm0 +; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [2,3,6,7,10,11,14,15,10,11,14,15,14,15,255,255] +; SSE41-NEXT: pshufb %xmm2, %xmm1 +; SSE41-NEXT: pshufb %xmm2, %xmm0 ; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; SSE41-NEXT: retq ; ; AVX1-LABEL: trunc8i32_8i16_lshr: ; AVX1: # BB#0: # %entry ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 -; AVX1-NEXT: vpsrld $16, %xmm1, %xmm1 -; AVX1-NEXT: vpsrld $16, %xmm0, %xmm0 -; AVX1-NEXT: vpackusdw %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [2,3,6,7,10,11,14,15,10,11,14,15,14,15,255,255] +; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1 +; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; AVX1-NEXT: vzeroupper ; AVX1-NEXT: retq ; ; AVX2-LABEL: trunc8i32_8i16_lshr: ; AVX2: # BB#0: # %entry -; AVX2-NEXT: vpsrld $16, %ymm0, %ymm0 -; AVX2-NEXT: vpackusdw %ymm0, %ymm0, %ymm0 +; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[2,3,6,7,10,11,14,15,10,11,14,15,14,15],zero,zero,ymm0[18,19,22,23,26,27,30,31,26,27,30,31,30,31],zero,zero ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] ; AVX2-NEXT: # kill: %XMM0 %XMM0 %YMM0 ; AVX2-NEXT: vzeroupper @@ -784,9 +786,10 @@ ; AVX2: # BB#0: # %entry ; AVX2-NEXT: vpsrad $16, %ymm1, %ymm1 ; AVX2-NEXT: vpsrad $16, %ymm0, %ymm0 -; AVX2-NEXT: vpackssdw %ymm0, %ymm0, %ymm0 +; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] +; AVX2-NEXT: vpshufb %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] -; AVX2-NEXT: vpackssdw %ymm0, %ymm1, %ymm1 +; AVX2-NEXT: vpshufb %ymm2, %ymm1, %ymm1 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3] ; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0 ; AVX2-NEXT: vmovdqu %ymm0, (%rax) @@ -876,11 +879,10 @@ ; ; AVX2-LABEL: trunc16i32_16i16_lshr: ; AVX2: # BB#0: # %entry -; AVX2-NEXT: vpsrld $16, %ymm1, %ymm1 -; AVX2-NEXT: vpsrld $16, %ymm0, %ymm0 -; AVX2-NEXT: vpackusdw %ymm0, %ymm0, %ymm0 +; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [2,3,6,7,10,11,14,15,10,11,14,15,14,15,255,255,18,19,22,23,26,27,30,31,26,27,30,31,30,31,255,255] +; AVX2-NEXT: vpshufb %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] -; AVX2-NEXT: vpackusdw %ymm0, %ymm1, %ymm1 +; AVX2-NEXT: vpshufb %ymm2, %ymm1, %ymm1 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3] ; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0 ; AVX2-NEXT: vmovdqu %ymm0, (%rax) @@ -998,13 +1000,14 @@ ; AVX2: # BB#0: # %entry ; AVX2-NEXT: vpsrad $24, %ymm0, %ymm0 ; AVX2-NEXT: vpsrad $24, %ymm1, %ymm1 -; AVX2-NEXT: vpackssdw %ymm0, %ymm1, %ymm1 +; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31] +; AVX2-NEXT: vpshufb %ymm2, %ymm1, %ymm1 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3] -; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u> -; AVX2-NEXT: vpshufb %xmm2, %xmm1, %xmm1 -; AVX2-NEXT: vpackssdw %ymm0, %ymm0, %ymm0 +; AVX2-NEXT: vmovdqa {{.*#+}} xmm3 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u> +; AVX2-NEXT: vpshufb %xmm3, %xmm1, %xmm1 +; AVX2-NEXT: vpshufb %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] -; AVX2-NEXT: vpshufb %xmm2, %xmm0, %xmm0 +; AVX2-NEXT: vpshufb %xmm3, %xmm0, %xmm0 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; AVX2-NEXT: vmovdqu %xmm0, (%rax) ; AVX2-NEXT: vzeroupper @@ -1053,15 +1056,14 @@ ; ; AVX2-LABEL: trunc16i32_16i8_lshr: ; AVX2: # BB#0: # %entry -; AVX2-NEXT: vpsrld $24, %ymm0, %ymm0 -; AVX2-NEXT: vpsrld $24, %ymm1, %ymm1 -; AVX2-NEXT: vpackssdw %ymm0, %ymm1, %ymm1 +; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [3,255,7,255,11,255,15,255,11,255,15,255,15,255,255,255,19,255,23,255,27,255,31,255,27,255,31,255,31,255,255,255] +; AVX2-NEXT: vpshufb %ymm2, %ymm1, %ymm1 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3] -; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u> -; AVX2-NEXT: vpshufb %xmm2, %xmm1, %xmm1 -; AVX2-NEXT: vpackssdw %ymm0, %ymm0, %ymm0 +; AVX2-NEXT: vmovdqa {{.*#+}} xmm3 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u> +; AVX2-NEXT: vpshufb %xmm3, %xmm1, %xmm1 +; AVX2-NEXT: vpshufb %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3] -; AVX2-NEXT: vpshufb %xmm2, %xmm0, %xmm0 +; AVX2-NEXT: vpshufb %xmm3, %xmm0, %xmm0 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; AVX2-NEXT: vmovdqu %xmm0, (%rax) ; AVX2-NEXT: vzeroupper @@ -1167,13 +1169,38 @@ } define void @trunc16i16_16i8_ashr(<16 x i16> %a) { -; SSE-LABEL: trunc16i16_16i8_ashr: -; SSE: # BB#0: # %entry -; SSE-NEXT: psraw $8, %xmm1 -; SSE-NEXT: psraw $8, %xmm0 -; SSE-NEXT: packsswb %xmm1, %xmm0 -; SSE-NEXT: movdqu %xmm0, (%rax) -; SSE-NEXT: retq +; SSE2-LABEL: trunc16i16_16i8_ashr: +; SSE2: # BB#0: # %entry +; SSE2-NEXT: psraw $8, %xmm0 +; SSE2-NEXT: psraw $8, %xmm1 +; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255] +; SSE2-NEXT: pand %xmm2, %xmm1 +; SSE2-NEXT: pand %xmm2, %xmm0 +; SSE2-NEXT: packuswb %xmm1, %xmm0 +; SSE2-NEXT: movdqu %xmm0, (%rax) +; SSE2-NEXT: retq +; +; SSSE3-LABEL: trunc16i16_16i8_ashr: +; SSSE3: # BB#0: # %entry +; SSSE3-NEXT: psraw $8, %xmm0 +; SSSE3-NEXT: psraw $8, %xmm1 +; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u> +; SSSE3-NEXT: pshufb %xmm2, %xmm1 +; SSSE3-NEXT: pshufb %xmm2, %xmm0 +; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] +; SSSE3-NEXT: movdqu %xmm0, (%rax) +; SSSE3-NEXT: retq +; +; SSE41-LABEL: trunc16i16_16i8_ashr: +; SSE41: # BB#0: # %entry +; SSE41-NEXT: psraw $8, %xmm0 +; SSE41-NEXT: psraw $8, %xmm1 +; SSE41-NEXT: movdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u> +; SSE41-NEXT: pshufb %xmm2, %xmm1 +; SSE41-NEXT: pshufb %xmm2, %xmm0 +; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] +; SSE41-NEXT: movdqu %xmm0, (%rax) +; SSE41-NEXT: retq ; ; AVX1-LABEL: trunc16i16_16i8_ashr: ; AVX1: # BB#0: # %entry @@ -1240,13 +1267,31 @@ } define void @trunc16i16_16i8_lshr(<16 x i16> %a) { -; SSE-LABEL: trunc16i16_16i8_lshr: -; SSE: # BB#0: # %entry -; SSE-NEXT: psrlw $8, %xmm1 -; SSE-NEXT: psrlw $8, %xmm0 -; SSE-NEXT: packuswb %xmm1, %xmm0 -; SSE-NEXT: movdqu %xmm0, (%rax) -; SSE-NEXT: retq +; SSE2-LABEL: trunc16i16_16i8_lshr: +; SSE2: # BB#0: # %entry +; SSE2-NEXT: psrlw $8, %xmm1 +; SSE2-NEXT: psrlw $8, %xmm0 +; SSE2-NEXT: packuswb %xmm1, %xmm0 +; SSE2-NEXT: movdqu %xmm0, (%rax) +; SSE2-NEXT: retq +; +; SSSE3-LABEL: trunc16i16_16i8_lshr: +; SSSE3: # BB#0: # %entry +; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = <1,3,5,7,9,11,13,15,u,u,u,u,u,u,u,u> +; SSSE3-NEXT: pshufb %xmm2, %xmm1 +; SSSE3-NEXT: pshufb %xmm2, %xmm0 +; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] +; SSSE3-NEXT: movdqu %xmm0, (%rax) +; SSSE3-NEXT: retq +; +; SSE41-LABEL: trunc16i16_16i8_lshr: +; SSE41: # BB#0: # %entry +; SSE41-NEXT: movdqa {{.*#+}} xmm2 = <1,3,5,7,9,11,13,15,u,u,u,u,u,u,u,u> +; SSE41-NEXT: pshufb %xmm2, %xmm1 +; SSE41-NEXT: pshufb %xmm2, %xmm0 +; SSE41-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] +; SSE41-NEXT: movdqu %xmm0, (%rax) +; SSE41-NEXT: retq ; ; AVX1-LABEL: trunc16i16_16i8_lshr: ; AVX1: # BB#0: # %entry @@ -1263,7 +1308,10 @@ ; AVX2: # BB#0: # %entry ; AVX2-NEXT: vpsrlw $8, %ymm0, %ymm0 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1 -; AVX2-NEXT: vpackuswb %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u> +; AVX2-NEXT: vpshufb %xmm2, %xmm1, %xmm1 +; AVX2-NEXT: vpshufb %xmm2, %xmm0, %xmm0 +; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; AVX2-NEXT: vmovdqu %xmm0, (%rax) ; AVX2-NEXT: vzeroupper ; AVX2-NEXT: retq Index: test/CodeGen/X86/vselect-avx.ll =================================================================== --- test/CodeGen/X86/vselect-avx.ll +++ test/CodeGen/X86/vselect-avx.ll @@ -99,9 +99,10 @@ ; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3 ; AVX1-NEXT: vpcmpeqd %xmm3, %xmm0, %xmm0 ; AVX1-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm1 -; AVX1-NEXT: vpackssdw %xmm0, %xmm0, %xmm0 +; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] +; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0 ; AVX1-NEXT: vmovq %xmm0, (%rdi) -; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm1[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] +; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm0 ; AVX1-NEXT: vmovq %xmm0, (%rsi) ; AVX1-NEXT: retq ; @@ -122,9 +123,10 @@ ; AVX2-NEXT: vpxor %xmm3, %xmm3, %xmm3 ; AVX2-NEXT: vpcmpeqd %xmm3, %xmm0, %xmm0 ; AVX2-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm1 -; AVX2-NEXT: vpackssdw %xmm0, %xmm0, %xmm0 +; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] +; AVX2-NEXT: vpshufb %xmm2, %xmm0, %xmm0 ; AVX2-NEXT: vmovq %xmm0, (%rdi) -; AVX2-NEXT: vpshufb {{.*#+}} xmm0 = xmm1[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] +; AVX2-NEXT: vpshufb %xmm2, %xmm1, %xmm0 ; AVX2-NEXT: vmovq %xmm0, (%rsi) ; AVX2-NEXT: retq %tmp6 = srem <4 x i32> %induction30, Index: test/CodeGen/X86/widen_arith-2.ll =================================================================== --- test/CodeGen/X86/widen_arith-2.ll +++ test/CodeGen/X86/widen_arith-2.ll @@ -10,6 +10,7 @@ ; CHECK-NEXT: movl $0, (%esp) ; CHECK-NEXT: pcmpeqd %xmm0, %xmm0 ; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [4,4,4,4,4,4,4,4] +; CHECK-NEXT: movdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u> ; CHECK-NEXT: jmp .LBB0_1 ; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .LBB0_2: # %forbody @@ -21,11 +22,11 @@ ; CHECK-NEXT: movl %edx, {{[0-9]+}}(%esp) ; CHECK-NEXT: addl {{[0-9]+}}(%esp), %ecx ; CHECK-NEXT: movl %ecx, {{[0-9]+}}(%esp) -; CHECK-NEXT: pmovzxbw {{.*#+}} xmm2 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero -; CHECK-NEXT: psubw %xmm0, %xmm2 -; CHECK-NEXT: pand %xmm1, %xmm2 -; CHECK-NEXT: packsswb %xmm0, %xmm2 -; CHECK-NEXT: movq %xmm2, (%edx,%eax,8) +; CHECK-NEXT: pmovzxbw {{.*#+}} xmm3 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero +; CHECK-NEXT: psubw %xmm0, %xmm3 +; CHECK-NEXT: pand %xmm1, %xmm3 +; CHECK-NEXT: pshufb %xmm2, %xmm3 +; CHECK-NEXT: movq %xmm3, (%edx,%eax,8) ; CHECK-NEXT: incl (%esp) ; CHECK-NEXT: .LBB0_1: # %forcond ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 Index: test/DebugInfo/COFF/fp-stack.ll =================================================================== --- test/DebugInfo/COFF/fp-stack.ll +++ test/DebugInfo/COFF/fp-stack.ll @@ -12,7 +12,7 @@ ; ASM: .cv_def_range Lfunc_begin0 Lfunc_end0, "A\021\200\000\000\000" ; OBJ: DefRangeRegisterSym { -; OBJ: Register: ST0 (0x80) +; OBJ: Register: 0x80 ; OBJ: MayHaveNoName: 0 ; OBJ: LocalVariableAddrRange { ; OBJ: OffsetStart: .text+0x0 Index: test/DebugInfo/X86/dbg-addr-dse.ll =================================================================== --- test/DebugInfo/X86/dbg-addr-dse.ll +++ test/DebugInfo/X86/dbg-addr-dse.ll @@ -61,7 +61,8 @@ ; DWARF-NEXT: DW_AT_location (0x00000000 ; DWARF-NEXT: {{[^:]*}}: DW_OP_breg7 RSP+{{[0-9]+}} ; DWARF-NEXT: {{[^:]*}}: DW_OP_consts +1, DW_OP_stack_value -; DWARF-NEXT: {{[^:]*}}: DW_OP_breg7 RSP+{{[0-9]+}}) +; FIXME: Needs a fix to LiveDebugVariables +; DWARFX-NEXT: {{[^:]*}}: DW_OP_breg7 RSP+{{[0-9]+}}) ; DWARF-NEXT: DW_AT_name ("x") attributes #0 = { nounwind uwtable } Index: test/DebugInfo/X86/live-debug-vars-dse.mir =================================================================== --- test/DebugInfo/X86/live-debug-vars-dse.mir +++ /dev/null @@ -1,147 +0,0 @@ -# RUN: llc -start-after=machine-scheduler %s -o - | FileCheck %s - -# C source: -# void escape(int *); -# extern int global; -# void f(int x) { -# escape(&x); -# x = 1; -# global = x; -# x = 2; -# escape(&x); -# } - -# CHECK-LABEL: f: # @f -# CHECK: movl %ecx, [[OFF_X:[0-9]+]](%rsp) -# CHECK: #DEBUG_VALUE: f:x <- [DW_OP_plus_uconst [[OFF_X]]] [%RSP+0] -# CHECK: leaq [[OFF_X]](%rsp), %rsi -# CHECK: callq escape -# CHECK: #DEBUG_VALUE: f:x <- 1 -# CHECK: movl $1, global(%rip) -# CHECK: #DEBUG_VALUE: f:x <- [DW_OP_plus_uconst [[OFF_X]]] [%RSP+0] -# CHECK: movl $2, [[OFF_X]](%rsp) -# CHECK: callq escape -# CHECK: retq - - ---- | - ; ModuleID = '' - source_filename = "dse.c" - target datalayout = "e-m:w-i64:64-f80:128-n8:16:32:64-S128" - target triple = "x86_64-pc-windows-msvc19.0.24215" - - @global = external global i32, align 4 - - ; Function Attrs: nounwind readnone speculatable - declare void @llvm.dbg.value(metadata, metadata, metadata) #0 - - declare void @escape(i32*) - - ; Function Attrs: nounwind uwtable - define void @f(i32 %x) #1 !dbg !8 { - entry: - %x.addr = alloca i32, align 4 - store i32 %x, i32* %x.addr, align 4 - call void @llvm.dbg.value(metadata i32* %x.addr, metadata !13, metadata !DIExpression()), !dbg !14 - call void @escape(i32* %x.addr), !dbg !15 - call void @llvm.dbg.value(metadata i32 1, metadata !13, metadata !DIExpression()), !dbg !16 - store i32 1, i32* @global, align 4, !dbg !17 - call void @llvm.dbg.value(metadata i32* %x.addr, metadata !13, metadata !DIExpression()), !dbg !18 - store i32 2, i32* %x.addr, align 4, !dbg !18 - call void @escape(i32* %x.addr), !dbg !19 - ret void, !dbg !20 - } - - ; Function Attrs: nounwind - declare void @llvm.stackprotector(i8*, i8**) #2 - - attributes #0 = { nounwind readnone speculatable } - attributes #1 = { nounwind uwtable } - attributes #2 = { nounwind } - - !llvm.dbg.cu = !{!0} - !llvm.module.flags = !{!3, !4, !5, !6} - !llvm.ident = !{!7} - - !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 6.0.0 ", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2) - !1 = !DIFile(filename: "dse.c", directory: "C:\5Csrc\5Cllvm-project\5Cbuild") - !2 = !{} - !3 = !{i32 2, !"Dwarf Version", i32 4} - !4 = !{i32 2, !"Debug Info Version", i32 3} - !5 = !{i32 1, !"wchar_size", i32 2} - !6 = !{i32 7, !"PIC Level", i32 2} - !7 = !{!"clang version 6.0.0 "} - !8 = distinct !DISubprogram(name: "f", scope: !1, file: !1, line: 3, type: !9, isLocal: false, isDefinition: true, scopeLine: 3, flags: DIFlagPrototyped, isOptimized: true, unit: !0, variables: !12) - !9 = !DISubroutineType(types: !10) - !10 = !{null, !11} - !11 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) - !12 = !{!13} - !13 = !DILocalVariable(name: "x", arg: 1, scope: !8, file: !1, line: 3, type: !11) - !14 = !DILocation(line: 3, column: 12, scope: !8) - !15 = !DILocation(line: 4, column: 3, scope: !8) - !16 = !DILocation(line: 5, column: 5, scope: !8) - !17 = !DILocation(line: 6, column: 10, scope: !8) - !18 = !DILocation(line: 7, column: 5, scope: !8) - !19 = !DILocation(line: 8, column: 3, scope: !8) - !20 = !DILocation(line: 9, column: 1, scope: !8) - -... ---- -name: f -alignment: 4 -exposesReturnsTwice: false -legalized: false -regBankSelected: false -selected: false -tracksRegLiveness: true -registers: - - { id: 0, class: gr32, preferred-register: '' } - - { id: 1, class: gr64, preferred-register: '' } -liveins: - - { reg: '%ecx', virtual-reg: '%0' } -frameInfo: - isFrameAddressTaken: false - isReturnAddressTaken: false - hasStackMap: false - hasPatchPoint: false - stackSize: 0 - offsetAdjustment: 0 - maxAlignment: 8 - adjustsStack: false - hasCalls: true - stackProtector: '' - maxCallFrameSize: 4294967295 - hasOpaqueSPAdjustment: false - hasVAStart: false - hasMustTailInVarArgFunc: false - savePoint: '' - restorePoint: '' -fixedStack: -stack: - - { id: 0, name: x.addr, type: default, offset: 0, size: 4, alignment: 4, - stack-id: 0, callee-saved-register: '', di-variable: '', di-expression: '', - di-location: '' } -constants: -body: | - bb.0.entry: - liveins: %ecx - - %0 = COPY %ecx - MOV32mr %stack.0.x.addr, 1, _, 0, _, %0 :: (store 4 into %ir.x.addr) - DBG_VALUE %stack.0.x.addr, 0, !13, !DIExpression(), debug-location !14 - ADJCALLSTACKDOWN64 32, 0, 0, implicit-def dead %rsp, implicit-def dead %eflags, implicit %rsp, debug-location !15 - %1 = LEA64r %stack.0.x.addr, 1, _, 0, _ - %rcx = COPY %1, debug-location !15 - CALL64pcrel32 @escape, csr_win64, implicit %rsp, implicit %rcx, implicit-def %rsp, debug-location !15 - ADJCALLSTACKUP64 32, 0, implicit-def dead %rsp, implicit-def dead %eflags, implicit %rsp, debug-location !15 - DBG_VALUE 1, debug-use _, !13, !DIExpression(), debug-location !16 - MOV32mi %rip, 1, _, @global, _, 1, debug-location !17 :: (store 4 into @global) - DBG_VALUE %stack.0.x.addr, 0, !13, !DIExpression(), debug-location !18 - MOV32mi %stack.0.x.addr, 1, _, 0, _, 2, debug-location !18 :: (store 4 into %ir.x.addr) - ADJCALLSTACKDOWN64 32, 0, 0, implicit-def dead %rsp, implicit-def dead %eflags, implicit %rsp, debug-location !19 - %rcx = COPY %1, debug-location !19 - CALL64pcrel32 @escape, csr_win64, implicit %rsp, implicit %rcx, implicit-def %rsp, debug-location !19 - ADJCALLSTACKUP64 32, 0, implicit-def dead %rsp, implicit-def dead %eflags, implicit %rsp, debug-location !19 - RET 0, debug-location !20 - -... Index: test/MC/AMDGPU/pal.s =================================================================== --- test/MC/AMDGPU/pal.s +++ /dev/null @@ -1,9 +0,0 @@ -// RUN: llvm-mc -triple amdgcn--amdpal -mcpu=kaveri -show-encoding %s | FileCheck %s --check-prefix=ASM -// RUN: llvm-mc -filetype=obj -triple amdgcn--amdpal -mcpu=kaveri -show-encoding %s | llvm-readobj -symbols -s -sd | FileCheck %s --check-prefix=ELF - -.amdgpu_pal_metadata 0x12345678, 0xfedcba98, 0x2468ace0, 0xfdb97531 -// ASM: .amdgpu_pal_metadata 0x12345678,0xfedcba98,0x2468ace0,0xfdb97531 -// ELF: SHT_NOTE -// ELF: 0000: 04000000 10000000 0C000000 414D4400 -// ELF: 0010: 78563412 98BADCFE E0AC6824 3175B9FD - Index: test/MC/ARM/arm-branch-errors.s =================================================================== --- test/MC/ARM/arm-branch-errors.s +++ test/MC/ARM/arm-branch-errors.s @@ -8,15 +8,9 @@ bl #2 beq #2 -@ CHECK: error: invalid instruction, any one of the following would fix this: +@ CHECK: error: instruction requires: thumb @ CHECK: b #2 -@ CHECK: note: instruction requires: thumb -@ CHECK: note: invalid operand for instruction -@ CHECK: error: invalid instruction, any one of the following would fix this: +@ CHECK: error: instruction requires: thumb @ CHECK: bl #2 -@ CHECK: note: instruction requires: thumb -@ CHECK: note: invalid operand for instruction -@ CHECK: error: invalid instruction, any one of the following would fix this: +@ CHECK: error: instruction requires: thumb @ CHECK: beq #2 -@ CHECK: note: instruction requires: thumb -@ CHECK: note: invalid operand for instruction Index: test/MC/ARM/basic-arm-instructions-v8.1a.s =================================================================== --- test/MC/ARM/basic-arm-instructions-v8.1a.s +++ test/MC/ARM/basic-arm-instructions-v8.1a.s @@ -27,18 +27,18 @@ //CHECK-ERROR: error: invalid operand for instruction //CHECK-ERROR: vqrdmlsh.f64 d3, d5, d5 //CHECK-ERROR: ^ -//CHECK-V8: error: invalid instruction +//CHECK-V8: error: invalid operand for instruction //CHECK-V8: vqrdmlah.i8 q0, q1, q2 -//CHECK-V8: ^ -//CHECK-V8: error: invalid instruction +//CHECK-V8: ^ +//CHECK-V8: error: invalid operand for instruction //CHECK-V8: vqrdmlah.u16 d0, d1, d2 -//CHECK-V8: ^ -//CHECK-V8: error: invalid instruction +//CHECK-V8: ^ +//CHECK-V8: error: invalid operand for instruction //CHECK-V8: vqrdmlsh.f32 q3, q4, q5 -//CHECK-V8: ^ -//CHECK-V8: error: invalid instruction +//CHECK-V8: ^ +//CHECK-V8: error: invalid operand for instruction //CHECK-V8: vqrdmlsh.f64 d3, d5, d5 -//CHECK-V8: ^ +//CHECK-V8: ^ vqrdmlah.s16 d0, d1, d2 //CHECK-V81aARM: vqrdmlah.s16 d0, d1, d2 @ encoding: [0x12,0x0b,0x11,0xf3] @@ -98,19 +98,15 @@ //CHECK-V8: ^ - vqrdmlah.i8 q0, q1, d9[0] - vqrdmlah.s32 q0, q1, d9[7] + vqrdmlah.i8 q0, q1, d9[7] vqrdmlah.u16 d0, d1, d2[3] vqrdmlsh.f32 q3, q4, d5[1] vqrdmlsh.f64 d3, d5, d5[0] //CHECK-ERROR: error: invalid operand for instruction -//CHECK-ERROR: vqrdmlah.i8 q0, q1, d9[0] +//CHECK-ERROR: vqrdmlah.i8 q0, q1, d9[7] //CHECK-ERROR: ^ //CHECK-ERROR: error: invalid operand for instruction -//CHECK-ERROR: vqrdmlah.s32 q0, q1, d9[7] -//CHECK-ERROR: ^ -//CHECK-ERROR: error: invalid operand for instruction //CHECK-ERROR: vqrdmlah.u16 d0, d1, d2[3] //CHECK-ERROR: ^ //CHECK-ERROR: error: invalid operand for instruction @@ -180,14 +176,14 @@ setpan #0 //CHECK-V81aTHUMB: setpan #0 @ encoding: [0x10,0xb6] //CHECK-V81aARM: setpan #0 @ encoding: [0x00,0x00,0x10,0xf1] -//CHECK-V8: instruction requires: armv8.1a +//CHECK-V8: error: instruction requires: armv8.1a //CHECK-V8: setpan #0 //CHECK-V8: ^ setpan #1 //CHECK-V81aTHUMB: setpan #1 @ encoding: [0x18,0xb6] //CHECK-V81aARM: setpan #1 @ encoding: [0x00,0x02,0x10,0xf1] -//CHECK-V8: instruction requires: armv8.1a +//CHECK-V8: error: instruction requires: armv8.1a //CHECK-V8: setpan #1 //CHECK-V8: ^ setpan Index: test/MC/ARM/basic-arm-instructions-v8.s =================================================================== --- test/MC/ARM/basic-arm-instructions-v8.s +++ test/MC/ARM/basic-arm-instructions-v8.s @@ -56,4 +56,4 @@ sevl @ CHECK-V8: sevl @ encoding: [0x05,0xf0,0x20,0xe3] -@ CHECK-V7: instruction requires: armv8 +@ CHECK-V7: error: instruction requires: armv8 Index: test/MC/ARM/basic-thumb2-instructions-v8.s =================================================================== --- test/MC/ARM/basic-thumb2-instructions-v8.s +++ test/MC/ARM/basic-thumb2-instructions-v8.s @@ -31,12 +31,8 @@ @ CHECK-V8: sbc.w r6, r3, sp, asr #16 @ encoding: [0x63,0xeb,0x2d,0x46] @ CHECK-V8: and.w r6, r3, sp, asr #16 @ encoding: [0x03,0xea,0x2d,0x46] @ CHECK-V8: and sp, r0, #0 @ encoding: [0x00,0xf0,0x00,0x0d] -@ CHECK-V7: error: invalid instruction, any one of the following would fix this: -@ CHECk-V7: note: instruction variant requires ARMv8 or later -@ CHECk-V7: note: invalid operand for instruction -@ CHECK-V7: error: invalid instruction, any one of the following would fix this: -@ CHECk-V7: note: instruction variant requires ARMv8 or later -@ CHECk-V7: note: invalid operand for instruction +@ CHECK-V7: error: instruction variant requires ARMv8 or later +@ CHECK-V7: error: instruction variant requires ARMv8 or later @ CHECK-V7: error: invalid operand for instruction @ DCPS{1,2,3} (in ARMv8 only) Index: test/MC/ARM/cps.s =================================================================== --- test/MC/ARM/cps.s +++ test/MC/ARM/cps.s @@ -13,5 +13,5 @@ @ CHECK: cps #0 @ encoding: [0xaf,0xf3,0x00,0x81] @ UNDEF-DAG: cpsie f @ encoding: [0x61,0xb6] -@ UNDEF-DAG: instruction requires: +@ UNDEF-DAG: error: instruction requires: @ UNDEF-DAG: error: instruction 'cps' requires effect for M-class Index: test/MC/ARM/diagnostics.s =================================================================== --- test/MC/ARM/diagnostics.s +++ test/MC/ARM/diagnostics.s @@ -93,21 +93,17 @@ @ Out of range 16-bit immediate on BKPT bkpt #65536 -@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this: -@ CHECK-ERRORS: note: immediate operand must be in the range [0,65535] -@ CHECK-ERRORS: note: too many operands for instruction +@ CHECK-ERRORS: error: immediate operand must be in the range [0,65535] @ CHECK-ERRORS: bkpt #65536 @ CHECK-ERRORS: ^ @ Out of range immediates for v8 HLT instruction. hlt #65536 hlt #-1 -@CHECK-ERRORS-V7: error: invalid instruction -@CHECK-ERRORS-V8: error: immediate operand must be in the range [0,65535] +@CHECK-ERRORS: error: immediate operand must be in the range [0,65535] @CHECK-ERRORS: hlt #65536 -@CHECK-ERRORS: ^ -@CHECK-ERRORS-V7: error: invalid instruction -@CHECK-ERRORS-V8: error: immediate operand must be in the range [0,65535] +@CHECK-ERRORS: ^ +@CHECK-ERRORS: error: immediate operand must be in the range [0,65535] @CHECK-ERRORS: hlt #-1 @CHECK-ERRORS: ^ @@ -133,19 +129,17 @@ @ CHECK-ERRORS-V7: error: immediate operand must be in the range [0,7] @ CHECK-ERRORS-V7: error: immediate operand must be in the range [0,7] @ CHECK-ERRORS-V7: error: immediate operand must be in the range [0,7] -@ CHECK-ERRORS-V8: error: invalid instruction -@ CHECK-ERRORS-V8: error: invalid instruction -@ CHECK-ERRORS-V8: error: invalid instruction -@ CHECK-ERRORS-V8: error: invalid instruction +@ CHECK-ERRORS-V8: error: invalid operand for instruction +@ CHECK-ERRORS-V8: error: invalid operand for instruction +@ CHECK-ERRORS-V8: error: invalid operand for instruction +@ CHECK-ERRORS-V8: error: invalid operand for instruction @ Out of range immediates for DBG dbg #-1 dbg #16 -@ CHECK-ERRORS-V7: error: immediate operand must be in the range [0,15] -@ CHECK-ERRORS-V7: error: immediate operand must be in the range [0,15] -@ CHECK-ERRORS-V8: error: immediate operand must be in the range [0,15] -@ CHECK-ERRORS-V8: error: immediate operand must be in the range [0,15] +@ CHECK-ERRORS: error: immediate operand must be in the range [0,15] +@ CHECK-ERRORS: error: immediate operand must be in the range [0,15] @ Double-check that we're synced up with the right diagnostics. @ CHECK-ERRORS: dbg #16 @ CHECK-ERRORS: ^ @@ -157,15 +151,13 @@ mcr2 p7, #1, r5, c1, c1, #8 mcrr p7, #16, r5, r4, c1 mcrr2 p7, #16, r5, r4, c1 -@ CHECK-ERRORS: immediate operand must be in the range [0,7] -@ CHECK-ERRORS: immediate operand must be in the range [0,7] -@ CHECK-ERRORS-V7: immediate operand must be in the range [0,7] -@ CHECK-ERRORS-V7: immediate operand must be in the range [0,7] -@ CHECK-ERRORS-V8: invalid instruction -@ CHECK-ERRORS-V8: too many operands for instruction -@ CHECK-ERRORS: immediate operand must be in the range [0,15] -@ CHECK-ERRORS-V7: immediate operand must be in the range [0,15] -@ CHECK-ERRORS-V8: invalid instruction +@ CHECK-ERRORS: error: immediate operand must be in the range [0,7] +@ CHECK-ERRORS: error: immediate operand must be in the range [0,7] +@ CHECK-ERRORS: error: immediate operand must be in the range [0,7] +@ CHECK-ERRORS: error: immediate operand must be in the range [0,7] +@ CHECK-ERRORS: error: immediate operand must be in the range [0,15] +@ CHECK-ERRORS-V7: error: immediate operand must be in the range [0,15] +@ CHECK-ERRORS-V8: error: invalid operand for instruction @ p10 and p11 are reserved for NEON mcr p10, #2, r5, c1, c1, #4 @@ -182,7 +174,7 @@ @ Invalid 's' bit usage for MOVW movs r6, #0xffff movwseq r9, #0xffff -@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: immediate operand must be in the range [0,255] @ CHECK-ERRORS: error: instruction 'movw' can not set flags, but 's' suffix specified @ Out of range immediate for MOVT @@ -198,15 +190,13 @@ mrc2 p14, #0, r1, c1, c2, #9 mrrc p7, #16, r5, r4, c1 mrrc2 p7, #17, r5, r4, c1 -@ CHECK-ERRORS: immediate operand must be in the range [0,7] -@ CHECK-ERRORS: immediate operand must be in the range [0,7] -@ CHECK-ERRORS-V7: immediate operand must be in the range [0,7] -@ CHECK-ERRORS-V8: invalid instruction -@ CHECK-ERRORS-V7: immediate operand must be in the range [0,7] -@ CHECK-ERRORS-V8: too many operands for instruction -@ CHECK-ERRORS: immediate operand must be in the range [0,15] -@ CHECK-ERRORS-V7: immediate operand must be in the range [0,15] -@ CHECK-ERRORS-V8: invalid instruction +@ CHECK-ERRORS: error: immediate operand must be in the range [0,7] +@ CHECK-ERRORS: error: immediate operand must be in the range [0,7] +@ CHECK-ERRORS: error: immediate operand must be in the range [0,7] +@ CHECK-ERRORS: error: immediate operand must be in the range [0,7] +@ CHECK-ERRORS: error: immediate operand must be in the range [0,15] +@ CHECK-ERRORS-V7: error: immediate operand must be in the range [0,15] +@ CHECK-ERRORS-V8: error: invalid operand for instruction @ Shifter operand validation for PKH instructions. pkhbt r2, r2, r3, lsl #-1 @@ -428,7 +418,7 @@ @ Bad CPS instruction format. cps f,#1 -@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: immediate operand must be in the range [0,31] @ CHECK-ERRORS: cps f,#1 @ CHECK-ERRORS: ^ Index: test/MC/ARM/directive-arch_extension-fp.s =================================================================== --- test/MC/ARM/directive-arch_extension-fp.s +++ test/MC/ARM/directive-arch_extension-fp.s @@ -17,133 +17,133 @@ .type fp,%function fp: vmrs r0, mvfr2 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vselgt.f32 s0, s0, s0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vselge.f32 s0, s0, s0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vseleq.f32 s0, s0, s0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vselvs.f32 s0, s0, s0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vmaxnm.f32 s0, s0, s0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vminnm.f32 s0, s0, s0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vselgt.f64 d0, d0, d0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vselge.f64 d0, d0, d0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vseleq.f64 d0, d0, d0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vselvs.f64 d0, d0, d0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vmaxnm.f64 d0, d0, d0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vminnm.f64 d0, d0, d0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vcvtb.f64.f16 d0, s0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vcvtb.f16.f64 s0, d0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vcvtt.f64.f16 d0, s0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vcvtt.f16.f64 s0, d0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vcvta.s32.f32 s0, s0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vcvta.u32.f32 s0, s0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vcvta.s32.f64 s0, d0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vcvta.u32.f64 s0, d0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vcvtn.s32.f32 s0, s0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vcvtn.u32.f32 s0, s0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vcvtn.s32.f64 s0, d0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vcvtn.u32.f64 s0, d0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vcvtp.s32.f32 s0, s0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vcvtp.u32.f32 s0, s0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vcvtp.s32.f64 s0, d0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vcvtp.u32.f64 s0, d0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vcvtm.s32.f32 s0, s0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vcvtm.u32.f32 s0, s0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vcvtm.s32.f64 s0, d0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vcvtm.u32.f64 s0, d0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vrintz.f32 s0, s1 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vrintz.f64 d0, d1 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vrintz.f32.f32 s0, s0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vrintz.f64.f64 d0, d0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vrintr.f32 s0, s1 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vrintr.f64 d0, d1 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vrintr.f32.f32 s0, s0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vrintr.f64.f64 d0, d0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vrintx.f32 s0, s1 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vrintx.f64 d0, d1 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vrintx.f32.f32 s0, s0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vrintx.f64.f64 d0, d0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vrinta.f32 s0, s0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vrinta.f64 d0, d0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vrinta.f32.f32 s0, s0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vrinta.f64.f64 d0, d0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vrintn.f32 s0, s0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vrintn.f64 d0, d0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vrintn.f32.f32 s0, s0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vrintn.f64.f64 d0, d0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vrintp.f32 s0, s0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vrintp.f64 d0, d0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vrintp.f32.f32 s0, s0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vrintp.f64.f64 d0, d0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vrintm.f32 s0, s0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vrintm.f64 d0, d0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vrintm.f32.f32 s0, s0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 vrintm.f64.f64 d0, d0 -@ CHECK-V7: instruction requires: FPARMv8 +@ CHECK-V7: error: instruction requires: FPARMv8 .arch_extension nofp @ CHECK-V7: error: architectural extension 'fp' is not allowed for the current base architecture @@ -153,131 +153,131 @@ .type nofp,%function nofp: vmrs r0, mvfr2 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vselgt.f32 s0, s0, s0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vselge.f32 s0, s0, s0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vseleq.f32 s0, s0, s0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vselvs.f32 s0, s0, s0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vmaxnm.f32 s0, s0, s0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vminnm.f32 s0, s0, s0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vselgt.f64 d0, d0, d0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vselge.f64 d0, d0, d0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vseleq.f64 d0, d0, d0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vselvs.f64 d0, d0, d0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vmaxnm.f64 d0, d0, d0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vminnm.f64 d0, d0, d0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtb.f64.f16 d0, s0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtb.f16.f64 s0, d0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtt.f64.f16 d0, s0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtt.f16.f64 s0, d0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvta.s32.f32 s0, s0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvta.u32.f32 s0, s0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvta.s32.f64 s0, d0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvta.u32.f64 s0, d0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtn.s32.f32 s0, s0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtn.u32.f32 s0, s0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtn.s32.f64 s0, d0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtn.u32.f64 s0, d0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtp.s32.f32 s0, s0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtp.u32.f32 s0, s0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtp.s32.f64 s0, d0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtp.u32.f64 s0, d0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtm.s32.f32 s0, s0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtm.u32.f32 s0, s0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtm.s32.f64 s0, d0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vcvtm.u32.f64 s0, d0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintz.f32 s0, s1 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintz.f64 d0, d1 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintz.f32.f32 s0, s0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintz.f64.f64 d0, d0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintr.f32 s0, s1 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintr.f64 d0, d1 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintr.f32.f32 s0, s0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintr.f64.f64 d0, d0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintx.f32 s0, s1 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintx.f64 d0, d1 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintx.f32.f32 s0, s0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintx.f64.f64 d0, d0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrinta.f32 s0, s0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrinta.f64 d0, d0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrinta.f32.f32 s0, s0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrinta.f64.f64 d0, d0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintn.f32 s0, s0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintn.f64 d0, d0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintn.f32.f32 s0, s0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintn.f64.f64 d0, d0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintp.f32 s0, s0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintp.f64 d0, d0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintp.f32.f32 s0, s0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintp.f64.f64 d0, d0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintm.f32 s0, s0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintm.f64 d0, d0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintm.f32.f32 s0, s0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 vrintm.f64.f64 d0, d0 -@ CHECK: instruction requires: FPARMv8 +@ CHECK: error: instruction requires: FPARMv8 Index: test/MC/ARM/directive-arch_extension-idiv.s =================================================================== --- test/MC/ARM/directive-arch_extension-idiv.s +++ test/MC/ARM/directive-arch_extension-idiv.s @@ -25,10 +25,10 @@ idiv: udiv r0, r1, r2 @ CHECK-ARMv6: error: instruction requires: divide in ARM -@ CHECK-THUMBv6: error: instruction requires: divide in THUMB armv8m.base +@ CHECK-THUMBv6: error: instruction requires: divide in ARM arm-mode sdiv r0, r1, r2 @ CHECK-ARMv6: error: instruction requires: divide in ARM -@ CHECK-THUMBv6: error: instruction requires: divide in THUMB armv8m.base +@ CHECK-THUMBv6: error: instruction requires: divide in ARM arm-mode .arch_extension noidiv @ CHECK-V6: error: architectural extension 'idiv' is not allowed for the current base architecture @@ -42,12 +42,12 @@ noidiv: udiv r0, r1, r2 @ CHECK-ARMv6: error: instruction requires: divide in ARM -@ CHECK-THUMBv6: error: instruction requires: divide in THUMB armv8m.base +@ CHECK-THUMBv6: error: instruction requires: divide in ARM arm-mode @ CHECK-ARMv7: error: instruction requires: divide in ARM @ CHECK-THUMBv7: error: instruction requires: divide in THUMB sdiv r0, r1, r2 @ CHECK-ARMv6: error: instruction requires: divide in ARM -@ CHECK-THUMBv6: error: instruction requires: divide in THUMB armv8m.base +@ CHECK-THUMBv6: error: instruction requires: divide in ARM arm-mode @ CHECK-ARMv7: error: instruction requires: divide in ARM @ CHECK-THUMBv7: error: instruction requires: divide in THUMB Index: test/MC/ARM/fp-const-errors.s =================================================================== --- test/MC/ARM/fp-const-errors.s +++ test/MC/ARM/fp-const-errors.s @@ -2,10 +2,10 @@ @ Test for floating point constants that are out of the 8-bit encoded value range vmov.f32 s2, #32.0 -@ CHECK: invalid operand for instruction +@ CHECK: error: invalid operand for instruction vmov.f64 d2, #32.0 -@ CHECK: invalid operand for instruction +@ CHECK: error: invalid operand for instruction @ Test that vmov.f instructions do not accept an 8-bit encoded float as an operand vmov.f32 s1, #0x70 @@ -22,4 +22,4 @@ @ CHECK: error: invalid floating point immediate vmov.i64 d0, 0x8000000000000000 -@ CHECK: invalid operand for instruction +@ CHECK: error: invalid operand for instruction Index: test/MC/ARM/fullfp16-neg.s =================================================================== --- test/MC/ARM/fullfp16-neg.s +++ test/MC/ARM/fullfp16-neg.s @@ -2,66 +2,66 @@ @ RUN: not llvm-mc -triple armv8a-none-eabi -mattr=-fullfp16,+thumb-mode -show-encoding < %s 2>&1 | FileCheck %s vadd.f16 s0, s1, s0 -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: vsub.f16 s0, s1, s0 -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: vdiv.f16 s0, s1, s0 -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: vmul.f16 s0, s1, s0 -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: vnmul.f16 s0, s1, s0 -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: vmla.f16 s1, s2, s0 -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: vmls.f16 s1, s2, s0 -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: vnmla.f16 s1, s2, s0 -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: vnmls.f16 s1, s2, s0 -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: vcmp.f16 s0, s1 -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: vcmp.f16 s2, #0 -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: vcmpe.f16 s1, s0 -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: vcmpe.f16 s0, #0 -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: vabs.f16 s0, s0 -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: vneg.f16 s0, s0 -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: vsqrt.f16 s0, s0 -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: vcvt.f16.s32 s0, s0 vcvt.f16.u32 s0, s0 vcvt.s32.f16 s0, s0 vcvt.u32.f16 s0, s0 -@ CHECK: instruction requires: full half-float -@ CHECK: instruction requires: full half-float -@ CHECK: instruction requires: full half-float -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vcvtr.s32.f16 s0, s1 vcvtr.u32.f16 s0, s1 -@ CHECK: instruction requires: full half-float -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vcvt.f16.u32 s0, s0, #20 vcvt.f16.u16 s0, s0, #1 @@ -71,119 +71,119 @@ vcvt.u16.f16 s28, s28, #1 vcvt.s32.f16 s1, s1, #20 vcvt.s16.f16 s17, s17, #1 -@ CHECK: instruction requires: full half-float -@ CHECK: instruction requires: full half-float -@ CHECK: instruction requires: full half-float -@ CHECK: instruction requires: full half-float -@ CHECK: instruction requires: full half-float -@ CHECK: instruction requires: full half-float -@ CHECK: instruction requires: full half-float -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vcvta.s32.f16 s2, s3 -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: vcvtn.s32.f16 s6, s23 -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: vcvtp.s32.f16 s0, s4 -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: vcvtm.s32.f16 s17, s8 -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: vcvta.u32.f16 s2, s3 -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: vcvtn.u32.f16 s6, s23 -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: vcvtp.u32.f16 s0, s4 -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: vcvtm.u32.f16 s17, s8 -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: vselge.f16 s4, s1, s23 -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: vselgt.f16 s0, s1, s0 -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: vseleq.f16 s30, s28, s23 -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: vselvs.f16 s21, s16, s14 -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: vmaxnm.f16 s5, s12, s0 -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: vminnm.f16 s0, s0, s12 -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: vrintz.f16 s3, s24 -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: vrintr.f16 s0, s9 -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: vrintx.f16 s10, s14 -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: vrinta.f16 s12, s1 -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: vrintn.f16 s12, s1 -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: vrintp.f16 s12, s1 -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: vrintm.f16 s12, s1 -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: vfma.f16 s2, s7, s4 -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: vfms.f16 s2, s7, s4 -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: vfnma.f16 s2, s7, s4 -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: vfnms.f16 s2, s7, s4 -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: vmovx.f16 s2, s5 vins.f16 s2, s5 -@ CHECK: instruction requires: full half-float -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vldr.16 s1, [pc, #6] vldr.16 s2, [pc, #510] vldr.16 s3, [pc, #-510] vldr.16 s4, [r4, #-18] -@ CHECK: instruction requires: full half-float -@ CHECK: instruction requires: full half-float -@ CHECK: instruction requires: full half-float -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vstr.16 s1, [pc, #6] vstr.16 s2, [pc, #510] vstr.16 s3, [pc, #-510] vstr.16 s4, [r4, #-18] -@ CHECK: instruction requires: full half-float -@ CHECK: instruction requires: full half-float -@ CHECK: instruction requires: full half-float -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vmov.f16 s0, #1.0 -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: vmov.f16 s1, r2 vmov.f16 r3, s4 -@ CHECK: instruction requires: full half-float -@ CHECK: instruction requires: full half-float +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: Index: test/MC/ARM/fullfp16-neon-neg.s =================================================================== --- test/MC/ARM/fullfp16-neon-neg.s +++ test/MC/ARM/fullfp16-neon-neg.s @@ -5,187 +5,187 @@ vadd.f16 d0, d1, d2 vadd.f16 q0, q1, q2 -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vsub.f16 d0, d1, d2 vsub.f16 q0, q1, q2 -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vmul.f16 d0, d1, d2 vmul.f16 q0, q1, q2 -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vmul.f16 d1, d2, d3[2] vmul.f16 q4, q5, d6[3] -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vmla.f16 d0, d1, d2 vmla.f16 q0, q1, q2 -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vmla.f16 d5, d6, d7[2] vmla.f16 q5, q6, d7[3] -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vmls.f16 d0, d1, d2 vmls.f16 q0, q1, q2 -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vmls.f16 d5, d6, d7[2] vmls.f16 q5, q6, d7[3] -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vfma.f16 d0, d1, d2 vfma.f16 q0, q1, q2 -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vfms.f16 d0, d1, d2 vfms.f16 q0, q1, q2 -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vceq.f16 d2, d3, d4 vceq.f16 q2, q3, q4 -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vceq.f16 d2, d3, #0 vceq.f16 q2, q3, #0 -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vcge.f16 d2, d3, d4 vcge.f16 q2, q3, q4 -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vcge.f16 d2, d3, #0 vcge.f16 q2, q3, #0 -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vcgt.f16 d2, d3, d4 vcgt.f16 q2, q3, q4 -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vcgt.f16 d2, d3, #0 vcgt.f16 q2, q3, #0 -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vcle.f16 d2, d3, d4 vcle.f16 q2, q3, q4 -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vcle.f16 d2, d3, #0 vcle.f16 q2, q3, #0 -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vclt.f16 d2, d3, d4 vclt.f16 q2, q3, q4 -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vclt.f16 d2, d3, #0 vclt.f16 q2, q3, #0 -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vacge.f16 d0, d1, d2 vacge.f16 q0, q1, q2 -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vacgt.f16 d0, d1, d2 vacgt.f16 q0, q1, q2 -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vacle.f16 d0, d1, d2 vacle.f16 q0, q1, q2 -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vaclt.f16 d0, d1, d2 vaclt.f16 q0, q1, q2 -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vabd.f16 d0, d1, d2 vabd.f16 q0, q1, q2 -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vabs.f16 d0, d1 vabs.f16 q0, q1 -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vmax.f16 d0, d1, d2 vmax.f16 q0, q1, q2 -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vmin.f16 d0, d1, d2 vmin.f16 q0, q1, q2 -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vmaxnm.f16 d0, d1, d2 vmaxnm.f16 q0, q1, q2 -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vminnm.f16 d0, d1, d2 vminnm.f16 q0, q1, q2 -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vpadd.f16 d0, d1, d2 -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: vpmax.f16 d0, d1, d2 -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: vpmin.f16 d0, d1, d2 -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: vrecpe.f16 d0, d1 vrecpe.f16 q0, q1 -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vrecps.f16 d0, d1, d2 vrecps.f16 q0, q1, q2 -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vrsqrte.f16 d0, d1 vrsqrte.f16 q0, q1 -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vrsqrts.f16 d0, d1, d2 vrsqrts.f16 q0, q1, q2 -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vneg.f16 d0, d1 vneg.f16 q0, q1 -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vcvt.s16.f16 d0, d1 vcvt.u16.f16 d0, d1 @@ -195,50 +195,50 @@ vcvt.u16.f16 q0, q1 vcvt.f16.s16 q0, q1 vcvt.f16.u16 q0, q1 -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vcvta.s16.f16 d0, d1 vcvta.s16.f16 q0, q1 vcvta.u16.f16 d0, d1 vcvta.u16.f16 q0, q1 -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vcvtm.s16.f16 d0, d1 vcvtm.s16.f16 q0, q1 vcvtm.u16.f16 d0, d1 vcvtm.u16.f16 q0, q1 -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vcvtn.s16.f16 d0, d1 vcvtn.s16.f16 q0, q1 vcvtn.u16.f16 d0, d1 vcvtn.u16.f16 q0, q1 -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vcvtp.s16.f16 d0, d1 vcvtp.s16.f16 q0, q1 vcvtp.u16.f16 d0, d1 vcvtp.u16.f16 q0, q1 -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vcvt.s16.f16 d0, d1, #1 @@ -249,41 +249,41 @@ vcvt.u16.f16 q0, q1, #6 vcvt.f16.s16 q0, q1, #7 vcvt.f16.u16 q0, q1, #8 -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vrinta.f16.f16 d0, d1 vrinta.f16.f16 q0, q1 -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vrintm.f16.f16 d0, d1 vrintm.f16.f16 q0, q1 -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vrintn.f16.f16 d0, d1 vrintn.f16.f16 q0, q1 -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vrintp.f16.f16 d0, d1 vrintp.f16.f16 q0, q1 -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vrintx.f16.f16 d0, d1 vrintx.f16.f16 q0, q1 -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: vrintz.f16.f16 d0, d1 vrintz.f16.f16 q0, q1 -@ CHECK: instruction requires: {{full half-float|NEON}} -@ CHECK: instruction requires: {{full half-float|NEON}} +@ CHECK: error: instruction requires: +@ CHECK: error: instruction requires: Index: test/MC/ARM/invalid-fp-armv8.s =================================================================== --- test/MC/ARM/invalid-fp-armv8.s +++ test/MC/ARM/invalid-fp-armv8.s @@ -35,52 +35,52 @@ @ V8: error: invalid instruction vseleq.f32 s0, d2, d1 -@ V8: error: invalid instruction +@ V8: error: invalid operand for instruction vselgt.f64 s3, s2, s1 @ V8: error: invalid operand for instruction vselgt.f32 s0, q3, q1 -@ V8: error: invalid instruction +@ V8: error: invalid operand for instruction vselgt.f64 q0, s3, q1 -@ V8: error: invalid instruction +@ V8: error: invalid operand for instruction vmaxnm.f32 s0, d2, d1 -@ V8: error: invalid instruction +@ V8: error: invalid operand for instruction vminnm.f64 s3, s2, s1 @ V8: error: invalid operand for instruction vmaxnm.f32 s0, q3, q1 -@ V8: error: invalid instruction +@ V8: error: invalid operand for instruction vmaxnm.f64 q0, s3, q1 -@ V8: error: invalid instruction +@ V8: error: invalid operand for instruction vmaxnmgt.f64 q0, s3, q1 @ CHECK: error: instruction 'vmaxnm' is not predicable, but condition code specified vcvta.s32.f64 d3, s2 -@ V8: error: invalid instruction +@ V8: error: invalid operand for instruction vcvtp.s32.f32 d3, s2 @ V8: error: invalid operand for instruction vcvtn.u32.f64 d3, s2 -@ V8: error: invalid instruction +@ V8: error: invalid operand for instruction vcvtm.u32.f32 d3, s2 @ V8: error: invalid operand for instruction vcvtnge.u32.f64 d3, s2 @ V8: error: instruction 'vcvtn' is not predicable, but condition code specified vcvtbgt.f64.f16 q0, d3 -@ V8: error: invalid instruction +@ V8: error: invalid operand for instruction vcvttlt.f64.f16 s0, s3 -@ V8: note: invalid operand for instruction +@ V8: error: invalid operand for instruction vcvttvs.f16.f64 s0, s3 -@ V8: note: invalid operand for instruction +@ V8: error: invalid operand for instruction vcvtthi.f16.f64 q0, d3 @ V8: error: invalid operand for instruction vrintrlo.f32.f32 d3, q0 -@ V8: error: invalid instruction +@ V8: error: invalid operand for instruction vrintxcs.f32.f32 d3, d0 @ V8: error: instruction requires: NEON vrinta.f64.f64 s3, q0 -@ V8: error: invalid instruction +@ V8: error: invalid operand for instruction vrintn.f32.f32 d3, d0 @ V8: error: instruction requires: NEON vrintp.f32 q3, q0 Index: test/MC/ARM/invalid-hint-thumb.s =================================================================== --- test/MC/ARM/invalid-hint-thumb.s +++ test/MC/ARM/invalid-hint-thumb.s @@ -3,13 +3,6 @@ hint #240 hint #1000 -@ FIXME: set the subclasses of the operand classes so that we only get one error for each. - -@ CHECK: error: invalid instruction, any one of the following would fix this: -@ CHECK: note: immediate operand must be in the range [0,239] -@ CHECK: note: immediate operand must be in the range [0,15] - -@ CHECK: error: invalid instruction, any one of the following would fix this: -@ CHECK: note: immediate operand must be in the range [0,239] -@ CHECK: note: immediate operand must be in the range [0,15] +@ CHECK: error: immediate operand must be in the range [0,239] +@ CHECK: error: immediate operand must be in the range [0,239] Index: test/MC/ARM/invalid-idiv.s =================================================================== --- test/MC/ARM/invalid-idiv.s +++ test/MC/ARM/invalid-idiv.s @@ -9,17 +9,13 @@ sdiv r1, r2, r3 udiv r3, r4, r5 -@ ARM-A15: note: instruction requires: divide in ARM -@ ARM-A15: note: instruction requires: thumb +@ ARM-A15: error: instruction requires: divide in ARM @ ARM-A15: sdiv r1, r2, r3 -@ ARM-A15: note: instruction requires: divide in ARM -@ ARM-A15: note: instruction requires: thumb +@ ARM-A15: error: instruction requires: divide in ARM @ ARM-A15: udiv r3, r4, r5 -@ THUMB-A15: note: instruction requires: arm-mode -@ THUMB-A15: note: instruction requires: divide in THUMB +@ THUMB-A15: error: instruction requires: arm-mode @ THUMB-A15: sdiv r1, r2, r3 -@ THUMB-A15: note: instruction requires: arm-mode -@ THUMB-A15: note: instruction requires: divide in THUMB +@ THUMB-A15: error: instruction requires: arm-mode @ THUMB-A15: udiv r3, r4, r5 @ ARM: error: instruction requires: divide in ARM Index: test/MC/ARM/invalid-neon-v8.s =================================================================== --- test/MC/ARM/invalid-neon-v8.s +++ test/MC/ARM/invalid-neon-v8.s @@ -1,9 +1,9 @@ @ RUN: not llvm-mc -triple armv8 -mattr=-fp-armv8 -show-encoding < %s 2>&1 | FileCheck %s vmaxnm.f32 s4, d5, q1 -@ CHECK: error: invalid instruction +@ CHECK: error: invalid operand for instruction vmaxnm.f64.f64 s4, d5, q1 -@ CHECK: error: invalid instruction +@ CHECK: error: invalid operand for instruction vmaxnmge.f64.f64 s4, d5, q1 @ CHECK: error: instruction 'vmaxnm' is not predicable, but condition code specified @@ -12,20 +12,16 @@ vcvtp.u32.f32 s1, d2 @ CHECK: error: invalid operand for instruction vcvtp.f32.u32 d1, q2 -@ CHECK: error: invalid instruction +@ CHECK: error: invalid operand for instruction vcvtplo.f32.u32 s1, s2 @ CHECK: error: instruction 'vcvtp' is not predicable, but condition code specified vrinta.f64.f64 s3, d12 -@ CHECK: error: invalid instruction +@ CHECK: error: invalid operand for instruction vrintn.f32 d3, q12 -@ CHECK: error: invalid instruction, any one of the following would fix this: -@ CHECK: note: invalid operand for instruction -@ CHECK: note: invalid operand for instruction +@ CHECK: error: invalid operand for instruction vrintz.f32 d3, q12 -@ CHECK: error: invalid instruction, any one of the following would fix this: -@ CHECK: note: invalid operand for instruction -@ CHECK: note: invalid operand for instruction +@ CHECK: error: invalid operand for instruction vrintmge.f32.f32 d3, d4 @ CHECK: error: instruction 'vrintm' is not predicable, but condition code specified @@ -50,7 +46,7 @@ @ CHECK: error: instruction 'sha1h' is not predicable, but condition code specified sha1c.32 s0, d1, q2 -@ CHECK: error: invalid instruction +@ CHECK: error: invalid operand for instruction sha1m.32 q0, s1, q2 @ CHECK: error: invalid operand for instruction sha1p.32 s0, q1, q2 @@ -62,12 +58,12 @@ sha256h2.32 q0, q1, s2 @ CHECK: error: invalid operand for instruction sha256su1.32 s0, d1, q2 -@ CHECK: error: invalid instruction +@ CHECK: error: invalid operand for instruction sha256su1lt.32 q0, d1, q2 @ CHECK: error: instruction 'sha256su1' is not predicable, but condition code specified vmull.p64 q0, s1, s3 -@ CHECK: error: invalid instruction +@ CHECK: error: invalid operand for instruction vmull.p64 s1, d2, d3 @ CHECK: error: invalid operand for instruction vmullge.p64 q0, d16, d17 Index: test/MC/ARM/invalid-special-reg.s =================================================================== --- test/MC/ARM/invalid-special-reg.s +++ test/MC/ARM/invalid-special-reg.s @@ -3,9 +3,9 @@ msr apsr_c, r0 @ CHECK: invalid operand for instruction - msr cpsr_w, r0 + msr cpsr_w @ CHECK: invalid operand for instruction - msr cpsr_cc, r0 + msr cpsr_cc @ CHECK: invalid operand for instruction - msr xpsr_c, r0 + msr xpsr_c @ CHECK: invalid operand for instruction Index: test/MC/ARM/ldr-pseudo-unpredictable.s =================================================================== --- test/MC/ARM/ldr-pseudo-unpredictable.s +++ test/MC/ARM/ldr-pseudo-unpredictable.s @@ -12,10 +12,10 @@ @ CHECK-DARWIN-ARM: ldr pc, Ltmp0 @ CHECK-T2: ldr.w pc, .Ltmp[[TMP0:[0-9]+]] @ CHECK-DARWIN-T2: ldr.w pc, Ltmp0 -@ CHECK-NONE: instruction requires: thumb2 +@ CHECK-NONE: error: instruction requires: thumb2 ldr sp, = 0x8 @ CHECK-ARM: ldr sp, .Ltmp[[TMP1:[0-9]+]] @ CHECK-DARWIN-ARM: ldr sp, Ltmp1 @ CHECK-T2: ldr.w sp, .Ltmp[[TMP1:[0-9]+]] @ CHECK-DARWIN-T2: ldr.w sp, Ltmp1 -@ CHECK-NONE: instruction requires: thumb2 +@ CHECK-NONE: error: instruction requires: thumb2 Index: test/MC/ARM/ldrd-strd-gnu-arm-bad-imm.s =================================================================== --- test/MC/ARM/ldrd-strd-gnu-arm-bad-imm.s +++ test/MC/ARM/ldrd-strd-gnu-arm-bad-imm.s @@ -1,13 +1,9 @@ @ RUN: not llvm-mc -triple=armv7-linux-gnueabi %s 2>&1 | FileCheck %s .text -@ CHECK: error: invalid instruction, any one of the following would fix this: +@ CHECK: error: instruction requires: thumb2 @ CHECK: ldrd r0, [r0, #512] -@ CHECK: note: invalid operand for instruction -@ CHECK: note: instruction requires: thumb2 ldrd r0, [r0, #512] -@ CHECK: error: invalid instruction, any one of the following would fix this: +@ CHECK: error: instruction requires: thumb2 @ CHECK: strd r0, [r0, #512] -@ CHECK: note: invalid operand for instruction -@ CHECK: note: instruction requires: thumb2 strd r0, [r0, #512] Index: test/MC/ARM/lsl-zero-errors.s =================================================================== --- test/MC/ARM/lsl-zero-errors.s +++ test/MC/ARM/lsl-zero-errors.s @@ -13,29 +13,16 @@ lsls r0, pc, #0 lsls pc, pc, #0 -// CHECK-NONARM: error: invalid instruction, any one of the following would fix this: +// CHECK-NONARM: error: instruction requires: arm-mode // CHECK-NONARM-NEXT: lsl pc, r0, #0 -// CHECK-NONARM: instruction requires: arm-mode -// CHECK-NONARM: invalid operand for instruction - -// CHECK-NONARM: error: invalid instruction, any one of the following would fix this: +// CHECK-NONARM: error: instruction requires: arm-mode // CHECK-NONARM-NEXT: lsl r0, pc, #0 -// CHECK-NONARM: instruction requires: arm-mode -// CHECK-NONARM: invalid operand for instruction - // CHECK-NONARM: error: instruction requires: arm-mode // CHECK-NONARM-NEXT: lsl pc, pc, #0 - -// CHECK-NONARM: error: invalid instruction, any one of the following would fix this: +// CHECK-NONARM: error: instruction requires: arm-mode // CHECK-NONARM-NEXT: lsls pc, r0, #0 -// CHECK-NONARM: instruction requires: arm-mode -// CHECK-NONARM: invalid operand for instruction - -// CHECK-NONARM: error: invalid instruction, any one of the following would fix this: +// CHECK-NONARM: error: instruction requires: arm-mode // CHECK-NONARM-NEXT: lsls r0, pc, #0 -// CHECK-NONARM: instruction requires: arm-mode -// CHECK-NONARM: invalid operand for instruction - // CHECK-NONARM: error: instruction requires: arm-mode // CHECK-NONARM-NEXT: lsls pc, pc, #0 @@ -53,25 +40,17 @@ movs r0, pc, lsl #0 movs pc, pc, lsl #0 -// CHECK-NONARM: error: invalid instruction, any one of the following would fix this: +// FIXME: Really the error we should be giving is "requires: arm-mode" +// CHECK-NONARM: error: invalid operand for instruction // CHECK-NONARM-NEXT: mov pc, r0, lsl #0 -// CHECK-NONARM: invalid operand for instruction -// CHECK-NONARM: invalid operand for instruction -// CHECK-NONARM: error: invalid instruction, any one of the following would fix this: +// CHECK-NONARM: error: invalid operand for instruction // CHECK-NONARM-NEXT: mov r0, pc, lsl #0 -// CHECK-NONARM: invalid operand for instruction -// CHECK-NONARM: invalid operand for instruction -// CHECK-NONARM: immediate operand must be in the range [256,65535] -// CHECK-NONARM: error: invalid instruction, any one of the following would fix this: +// CHECK-NONARM: error: invalid operand for instruction // CHECK-NONARM-NEXT: mov pc, pc, lsl #0 -// CHECK-NONARM: invalid operand for instruction -// CHECK-NONARM: invalid operand for instruction // CHECK-NONARM: error: invalid operand for instruction // CHECK-NONARM-NEXT: movs pc, r0, lsl #0 -// CHECK-NONARM: error: invalid instruction, any one of the following would fix this: +// CHECK-NONARM: error: invalid operand for instruction // CHECK-NONARM-NEXT: movs r0, pc, lsl #0 -// CHECK-NONARM: invalid operand for instruction -// CHECK-NONARM: invalid operand for instruction // CHECK-NONARM: error: invalid operand for instruction // CHECK-NONARM-NEXT: movs pc, pc, lsl #0 @@ -89,22 +68,14 @@ lsls r0, sp, #0 lsls sp, r0, #0 -// CHECK-THUMBV7: error: invalid instruction, any one of the following would fix this: +// CHECK-THUMBV7: error: instruction variant requires ARMv8 or later // CHECK-THUMBV7-NEXT: lsl sp, sp, #0 -// CHECK-THUMBV7: instruction requires: arm-mode -// CHECK-THUMBV7: instruction variant requires ARMv8 or later -// CHECK-THUMBV7: error: invalid instruction, any one of the following would fix this: +// CHECK-THUMBV7: error: instruction variant requires ARMv8 or later // CHECK-THUMBV7-NEXT: lsls sp, sp, #0 -// CHECK-THUMBV7: instruction requires: arm-mode -// CHECK-THUMBV7: instruction variant requires ARMv8 or later -// CHECK-THUMBV7: error: invalid instruction, any one of the following would fix this: +// CHECK-THUMBV7: error: instruction variant requires ARMv8 or later // CHECK-THUMBV7-NEXT: lsls r0, sp, #0 -// CHECK-THUMBV7: instruction requires: arm-mode -// CHECK-THUMBV7: instruction variant requires ARMv8 or later -// CHECK-THUMBV7: error: invalid instruction, any one of the following would fix this: +// CHECK-THUMBV7: error: instruction variant requires ARMv8 or later // CHECK-THUMBV7-NEXT: lsls sp, r0, #0 -// CHECK-THUMBV7: instruction requires: arm-mode -// CHECK-THUMBV7: instruction variant requires ARMv8 or later // CHECK-ARM: mov sp, sp @ encoding: [0x0d,0xd0,0xa0,0xe1] // CHECK-ARM: movs sp, sp @ encoding: [0x0d,0xd0,0xb0,0xe1] @@ -117,17 +88,13 @@ movs sp, r0, lsl #0 // FIXME: We should consistently have the "requires ARMv8" error here -// CHECK-THUMBV7: error: invalid instruction, any one of the following would fix this: -// CHECK-THUMBV7: invalid operand for instruction +// CHECK-THUMBV7: error: invalid operand for instruction // CHECK-THUMBV7-NEXT: mov sp, sp, lsl #0 -// CHECK-THUMBV7: error: invalid instruction, any one of the following would fix this: -// CHECK-THUMBV7: invalid operand for instruction +// CHECK-THUMBV7: error: invalid operand for instruction // CHECK-THUMBV7-NEXT: movs sp, sp, lsl #0 -// CHECK-THUMBV7: error: invalid instruction, any one of the following would fix this: -// CHECK-THUMBV7: instruction variant requires ARMv8 or later +// CHECK-THUMBV7: error: instruction variant requires ARMv8 or later // CHECK-THUMBV7-NEXT: movs r0, sp, lsl #0 -// CHECK-THUMBV7: error: invalid instruction, any one of the following would fix this: -// CHECK-THUMBV7: invalid operand for instruction +// CHECK-THUMBV7: error: invalid operand for instruction // CHECK-THUMBV7-NEXT: movs sp, r0, lsl #0 // CHECK-ARM: mov sp, sp @ encoding: [0x0d,0xd0,0xa0,0xe1] Index: test/MC/ARM/negative-immediates-fail.s =================================================================== --- test/MC/ARM/negative-immediates-fail.s +++ test/MC/ARM/negative-immediates-fail.s @@ -10,11 +10,9 @@ # CHECK: error: invalid operand for instruction ADD.W r0, r0, #0xFF01FF01 -# CHECK: invalid operand for instruction +# CHECK: error: immediate operand must be in the range [0,7] ORR r0, r1, #0xFFFFFF00 -# CHECK: error: invalid instruction, any one of the following would fix this: -# CHECK: note: invalid operand for instruction -# CHECK: note: instruction requires: thumb2 +# CHECK: error: instruction requires: thumb2 ORN r0, r1, #0xFFFFFF00 # CHECK: error: instruction requires: thumb2 Index: test/MC/ARM/negative-immediates-thumb1-fail.s =================================================================== --- test/MC/ARM/negative-immediates-thumb1-fail.s +++ test/MC/ARM/negative-immediates-thumb1-fail.s @@ -3,30 +3,18 @@ .thumb ADDs r1, r0, #0xFFFFFFF5 -# CHECK: error: invalid instruction, any one of the following would fix this: -# CHECK-DAG: note: instruction requires: thumb2 -# CHECK-DAG: note: invalid operand for instruction -# CHECK-DAG: note: immediate operand must be in the range [0,7] +# CHECK: error: instruction requires: arm-mode ADDs r0, #0xFFFFFEFF -# CHECK: error: invalid instruction, any one of the following would fix this: -# CHECK-DAG: note: invalid operand for instruction -# CHECK-DAG: note: immediate operand must be in the range [0,255] +# CHECK: error: immediate operand must be in the range [0,255] SUBs r1, r0, #0xFFFFFFF5 -# CHECK: error: invalid instruction, any one of the following would fix this: -# CHECK-DAG: note: invalid operand for instruction -# CHECK-DAG: note: immediate operand must be in the range [0,7] +# CHECK: error: instruction requires: arm-mode SUBs r0, #0xFFFFFEFF -# CHECK: error: invalid instruction, any one of the following would fix this: -# CHECK-DAG: note: invalid operand for instruction -# CHECK-DAG: note: immediate operand must be in the range [0,255] +# CHECK: error: immediate operand must be in the range [0,255] ORRs r0, r1, #0xFFFFFF00 -# CHECK: error: invalid instruction, any one of the following would fix this: -# CHECK-DAG: note: instruction requires: thumb2 -# CHECK-DAG: note: too many operands for instruction - +# CHECK: error: instruction requires: thumb2 ORNs r0, r1, #0xFFFFFF00 # CHECK: error: instruction requires: thumb2 Index: test/MC/ARM/negative-immediates-thumb1.s =================================================================== --- test/MC/ARM/negative-immediates-thumb1.s +++ test/MC/ARM/negative-immediates-thumb1.s @@ -5,15 +5,15 @@ ADDs r1, r0, #0xFFFFFFF9 # CHECK: subs r1, r0, #7 -# CHECK-DISABLED: note: instruction requires: NegativeImmediates +# CHECK-DISABLED: error: instruction requires: NegativeImmediates ADDs r0, #0xFFFFFF01 # CHECK: subs r0, #255 -# CHECK-DISABLED: note: instruction requires: NegativeImmediates +# CHECK-DISABLED: error: instruction requires: NegativeImmediates SUBs r0, #0xFFFFFF01 # CHECK: adds r0, #255 -# CHECK-DISABLED: note: instruction requires: NegativeImmediates +# CHECK-DISABLED: error: instruction requires: NegativeImmediates SUBs r1, r0, #0xFFFFFFF9 # CHECK: adds r1, r0, #7 -# CHECK-DISABLED: note: instruction requires: NegativeImmediates +# CHECK-DISABLED: error: instruction requires: NegativeImmediates Index: test/MC/ARM/negative-immediates.s =================================================================== --- test/MC/ARM/negative-immediates.s +++ test/MC/ARM/negative-immediates.s @@ -5,140 +5,140 @@ ADC r0, r1, #0xFFFFFF00 # CHECK: sbc r0, r1, #255 -# CHECK-DISABLED: note: instruction requires: NegativeImmediates +# CHECK-DISABLED: error: instruction requires: NegativeImmediates # CHECK-DISABLED: ADC ADC r0, r1, #0xFFFFFE03 # CHECK: sbc r0, r1, #508 -# CHECK-DISABLED: note: instruction requires: NegativeImmediates +# CHECK-DISABLED: error: instruction requires: NegativeImmediates # CHECK-DISABLED: ADC ADD r0, r1, #0xFFFFFF01 # CHECK: sub r0, r1, #255 -# CHECK-DISABLED: note: instruction requires: NegativeImmediates +# CHECK-DISABLED: error: instruction requires: NegativeImmediates # CHECK-DISABLED: ADD AND r0, r1, #0xFFFFFF00 # CHECK: bic r0, r1, #255 -# CHECK-DISABLED: note: instruction requires: NegativeImmediates +# CHECK-DISABLED: error: instruction requires: NegativeImmediates # CHECK-DISABLED: AND BIC r0, r1, #0xFFFFFF00 # CHECK: and r0, r1, #255 -# CHECK-DISABLED: note: instruction requires: NegativeImmediates +# CHECK-DISABLED: error: instruction requires: NegativeImmediates # CHECK-DISABLED: BIC CMP r0, #0xFFFFFF01 # CHECK: cmn r0, #255 -# CHECK-DISABLED: note: instruction requires: NegativeImmediates +# CHECK-DISABLED: error: instruction requires: NegativeImmediates # CHECK-DISABLED: CMP CMN r0, #0xFFFFFF01 # CHECK: cmp r0, #255 -# CHECK-DISABLED: note: instruction requires: NegativeImmediates +# CHECK-DISABLED: error: instruction requires: NegativeImmediates # CHECK-DISABLED: CMN MOV r0, #0xFFFFFF00 # CHECK: mvn r0, #255 -# CHECK-DISABLED: note: instruction requires: NegativeImmediates +# CHECK-DISABLED: error: instruction requires: NegativeImmediates # CHECK-DISABLED: MOV MVN r0, #0xFFFFFF00 # CHECK: mov r0, #255 -# CHECK-DISABLED: note: instruction requires: NegativeImmediates +# CHECK-DISABLED: error: instruction requires: NegativeImmediates # CHECK-DISABLED: MVN SBC r0, r1, #0xFFFFFF00 # CHECK: adc r0, r1, #255 -# CHECK-DISABLED: note: instruction requires: NegativeImmediates +# CHECK-DISABLED: error: instruction requires: NegativeImmediates # CHECK-DISABLED: SBC SUB r0, r1, #0xFFFFFF01 # CHECK: add r0, r1, #255 -# CHECK-DISABLED: note: instruction requires: NegativeImmediates +# CHECK-DISABLED: error: instruction requires: NegativeImmediates # CHECK-DISABLED: SUB .thumb ADC r0, r1, #0xFFFFFF00 # CHECK: sbc r0, r1, #255 -# CHECK-DISABLED: note: instruction requires: NegativeImmediates +# CHECK-DISABLED: error: instruction requires: NegativeImmediates # CHECK-DISABLED: ADC ADC r0, r1, #0xFFFF00FF # CHECK: sbc r0, r1, #65280 -# CHECK-DISABLED: note: instruction requires: NegativeImmediates +# CHECK-DISABLED: error: instruction requires: NegativeImmediates # CHECK-DISABLED: ADC ADC r0, r1, #0xFFFEFFFE # CHECK: sbc r0, r1, #65537 @ encoding: [0x61,0xf1,0x01,0x10] -# CHECK-DISABLED: note: instruction requires: NegativeImmediates +# CHECK-DISABLED: error: instruction requires: NegativeImmediates # CHECK-DISABLED: ADC ADC r0, r1, #0xFEFFFEFF # CHECK: sbc r0, r1, #16777472 @ encoding: [0x61,0xf1,0x01,0x20] -# CHECK-DISABLED: note: instruction requires: NegativeImmediates +# CHECK-DISABLED: error: instruction requires: NegativeImmediates # CHECK-DISABLED: ADC ADD.W r0, r0, #0xFFFFFF01 # CHECK: sub.w r0, r0, #255 -# CHECK-DISABLED: note: instruction requires: NegativeImmediates +# CHECK-DISABLED: error: instruction requires: NegativeImmediates # CHECK-DISABLED: ADD.W ADD.W r0, r0, #0xFF01FF02 # CHECK: sub.w r0, r0, #16646398 @ encoding: [0xa0,0xf1,0xfe,0x10] -# CHECK-DISABLED: note: instruction requires: NegativeImmediates +# CHECK-DISABLED: error: instruction requires: NegativeImmediates # CHECK-DISABLED: ADD.W ADDW r0, r1, #0xFFFFFF01 # CHECK: subw r0, r1, #255 @ encoding: [0xa1,0xf2,0xff,0x00] -# CHECK-DISABLED: note: instruction requires: NegativeImmediates +# CHECK-DISABLED: error: instruction requires: NegativeImmediates # CHECK-DISABLED: ADDW ADD.W r0, r1, #0xFFFFFF01 # CHECK: sub.w r0, r1, #255 @ encoding: [0xa1,0xf1,0xff,0x00] -# CHECK-DISABLED: note: instruction requires: NegativeImmediates +# CHECK-DISABLED: error: instruction requires: NegativeImmediates # CHECK-DISABLED: ADD.W AND r0, r1, #0xFFFFFF00 -# CHECK-DISABLED: note: instruction requires: NegativeImmediates +# CHECK-DISABLED: error: instruction requires: NegativeImmediates # CHECK-DISABLED: AND # CHECK: bic r0, r1, #255 AND r0, r1, #0xFEFFFEFF # CHECK: bic r0, r1, #16777472 @ encoding: [0x21,0xf0,0x01,0x20] -# CHECK-DISABLED: note: instruction requires: NegativeImmediates +# CHECK-DISABLED: error: instruction requires: NegativeImmediates # CHECK-DISABLED: AND BIC r0, r1, #0xFFFFFF00 # CHECK: and r0, r1, #255 -# CHECK-DISABLED: note: instruction requires: NegativeImmediates +# CHECK-DISABLED: error: instruction requires: NegativeImmediates # CHECK-DISABLED: BIC BIC r0, r1, #0xFEFFFEFF # CHECK: and r0, r1, #16777472 @ encoding: [0x01,0xf0,0x01,0x20] -# CHECK-DISABLED: note: instruction requires: NegativeImmediates +# CHECK-DISABLED: error: instruction requires: NegativeImmediates # CHECK-DISABLED: BIC ORR r0, r1, #0xFFFFFF00 -# CHECK-DISABLED: note: instruction requires: NegativeImmediates +# CHECK-DISABLED: error: instruction requires: NegativeImmediates # CHECK-DISABLED: ORR # CHECK: orn r0, r1, #255 ORR r0, r1, #0xFEFFFEFF # CHECK: orn r0, r1, #16777472 @ encoding: [0x61,0xf0,0x01,0x20] -# CHECK-DISABLED: note: instruction requires: NegativeImmediates +# CHECK-DISABLED: error: instruction requires: NegativeImmediates # CHECK-DISABLED: ORR ORN r0, r1, #0xFFFFFF00 # CHECK: orr r0, r1, #255 -# CHECK-DISABLED: note: instruction requires: NegativeImmediates +# CHECK-DISABLED: error: instruction requires: NegativeImmediates # CHECK-DISABLED: ORN ORN r0, r1, #0xFEFFFEFF # CHECK: orr r0, r1, #16777472 @ encoding: [0x41,0xf0,0x01,0x20] -# CHECK-DISABLED: note: instruction requires: NegativeImmediates +# CHECK-DISABLED: error: instruction requires: NegativeImmediates # CHECK-DISABLED: ORN CMP r0, #0xFFFFFF01 # CHECK: cmn.w r0, #255 -# CHECK-DISABLED: note: instruction requires: NegativeImmediates +# CHECK-DISABLED: error: instruction requires: NegativeImmediates # CHECK-DISABLED: CMP CMN r0, #0xFFFFFF01 # CHECK: cmp.w r0, #255 -# CHECK-DISABLED: note: instruction requires: NegativeImmediates +# CHECK-DISABLED: error: instruction requires: NegativeImmediates # CHECK-DISABLED: CMN MOV r0, #0xFFFFFF00 # CHECK: mvn r0, #255 -# CHECK-DISABLED: note: instruction requires: NegativeImmediates +# CHECK-DISABLED: error: instruction requires: NegativeImmediates # CHECK-DISABLED: MOV MVN r0, #0xFFFFFF00 # CHECK: mov.w r0, #255 -# CHECK-DISABLED: note: instruction requires: NegativeImmediates +# CHECK-DISABLED: error: instruction requires: NegativeImmediates # CHECK-DISABLED: MVN SBC r0, r1, #0xFFFFFF00 # CHECK: adc r0, r1, #255 -# CHECK-DISABLED: note: instruction requires: NegativeImmediates +# CHECK-DISABLED: error: instruction requires: NegativeImmediates # CHECK-DISABLED: SBC SUBW r0, r1, #0xFFFFFF01 # CHECK: addw r0, r1, #255 -# CHECK-DISABLED: note: instruction requires: NegativeImmediates +# CHECK-DISABLED: error: instruction requires: NegativeImmediates # CHECK-DISABLED: SUBW SUB.W r0, r1, #0xFFFFFF01 # CHECK: add.w r0, r1, #255 -# CHECK-DISABLED: note: instruction requires: NegativeImmediates +# CHECK-DISABLED: error: instruction requires: NegativeImmediates # CHECK-DISABLED: SUB.W Index: test/MC/ARM/neon-complex.s =================================================================== --- test/MC/ARM/neon-complex.s +++ test/MC/ARM/neon-complex.s @@ -1,12 +1,12 @@ // RUN: not llvm-mc -triple thumb-none-linux-gnu -mattr=+v8.3a,+neon,+fullfp16 -show-encoding < %s 2>%t | FileCheck %s --check-prefix=THUMB --check-prefix=FP16-THUMB -// RUN: FileCheck --check-prefix=STDERR --check-prefix=NEON-STDERR <%t %s +// RUN: FileCheck --check-prefix=STDERR <%t %s // RUN: not llvm-mc -triple arm-none-linux-gnu -mattr=+v8.3a,+neon,+fullfp16 -show-encoding < %s 2>%t | FileCheck %s --check-prefix=ARM --check-prefix=FP16-ARM -// RUN: FileCheck --check-prefix=STDERR --check-prefix=NEON-STDERR <%t %s +// RUN: FileCheck --check-prefix=STDERR <%t %s // RUN: not llvm-mc -triple thumb-none-linux-gnu -mattr=+v8.3a,+neon,-fullfp16 -show-encoding < %s 2>%t | FileCheck %s --check-prefix=THUMB -// RUN: FileCheck --check-prefix=STDERR --check-prefix=NO-FP16-STDERR --check-prefix=NEON-STDERR <%t %s +// RUN: FileCheck --check-prefix=STDERR --check-prefix=NO-FP16-STDERR <%t %s // RUN: not llvm-mc -triple arm-none-linux-gnu -mattr=+v8.3a,+neon,-fullfp16 -show-encoding < %s 2>%t | FileCheck %s --check-prefix=ARM -// RUN: FileCheck --check-prefix=STDERR --check-prefix=NO-FP16-STDERR --check-prefix=NEON-STDERR <%t %s +// RUN: FileCheck --check-prefix=STDERR --check-prefix=NO-FP16-STDERR <%t %s // RUN: not llvm-mc -triple thumb-none-linux-gnu -mattr=+v8.3a,-neon,+fullfp16 -show-encoding < %s 2>%t // RUN: FileCheck --check-prefix=STDERR --check-prefix=NO-NEON-STDERR <%t %s @@ -22,13 +22,13 @@ vcmla.f16 d0, d1, d2, #0 // FP16-ARM: vcmla.f16 d0, d1, d2, #0 @ encoding: [0x02,0x08,0x21,0xfc] // FP16-THUMB: vcmla.f16 d0, d1, d2, #0 @ encoding: [0x21,0xfc,0x02,0x08] -// NO-FP16-STDERR: :[[@LINE-3]]:{{[0-9]*}}: note: instruction requires: full half-float +// NO-FP16-STDERR: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: full half-float // V82A: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: armv8.3a // NO-NEON_STDERR: :[[@LINE-5]]:{{[0-9]*}}: error: instruction requires: NEON vcmla.f16 q0, q1, q2, #0 // FP16-ARM: vcmla.f16 q0, q1, q2, #0 @ encoding: [0x44,0x08,0x22,0xfc] // FP16-THUMB: vcmla.f16 q0, q1, q2, #0 @ encoding: [0x22,0xfc,0x44,0x08] -// NO-FP16-STDERR: :[[@LINE-3]]:{{[0-9]*}}: note: instruction requires: full half-float +// NO-FP16-STDERR: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: full half-float // V82A: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: armv8.3a // NO-NEON_STDERR: :[[@LINE-5]]:{{[0-9]*}}: error: instruction requires: NEON vcmla.f32 d0, d1, d2, #0 @@ -61,14 +61,11 @@ // Invalid rotations vcmla.f32 d0, d1, d2, #-90 -// NEON-STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270 -// NO-NEON-STDERR: :[[@LINE-2]]:{{[0-9]*}}: error: invalid instruction +// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270 vcmla.f32 d0, d1, d2, #1 -// NEON-STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270 -// NO-NEON-STDERR: :[[@LINE-2]]:{{[0-9]*}}: error: invalid instruction +// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270 vcmla.f32 d0, d1, d2, #360 -// NEON-STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270 -// NO-NEON-STDERR: :[[@LINE-2]]:{{[0-9]*}}: error: invalid instruction +// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270 /* ==== VCADD vector ==== */ @@ -76,13 +73,13 @@ vcadd.f16 d0, d1, d2, #90 // FP16-ARM: vcadd.f16 d0, d1, d2, #90 @ encoding: [0x02,0x08,0x81,0xfc] // FP16-THUMB: vcadd.f16 d0, d1, d2, #90 @ encoding: [0x81,0xfc,0x02,0x08] -// NO-FP16-STDERR: :[[@LINE-3]]:{{[0-9]*}}: note: instruction requires: full half-float +// NO-FP16-STDERR: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: full half-float // V82A: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: armv8.3a // NO-NEON_STDERR: :[[@LINE-5]]:{{[0-9]*}}: error: instruction requires: NEON vcadd.f16 q0, q1, q2, #90 // FP16-ARM: vcadd.f16 q0, q1, q2, #90 @ encoding: [0x44,0x08,0x82,0xfc] // FP16-THUMB: vcadd.f16 q0, q1, q2, #90 @ encoding: [0x82,0xfc,0x44,0x08] -// NO-FP16-STDERR: :[[@LINE-3]]:{{[0-9]*}}: note: instruction requires: full half-float +// NO-FP16-STDERR: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: full half-float // V82A: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: armv8.3a // NO-NEON_STDERR: :[[@LINE-5]]:{{[0-9]*}}: error: instruction requires: NEON vcadd.f32 d0, d1, d2, #90 @@ -105,20 +102,15 @@ // Invalid rotations vcadd.f32 d0, d1, d2, #0 -// NEON-STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 90 or 270 -// NO-NEON-STDERR: :[[@LINE-2]]:{{[0-9]*}}: error: invalid instruction +// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 90 or 270 vcadd.f32 d0, d1, d2, #180 -// NEON-STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 90 or 270 -// NO-NEON-STDERR: :[[@LINE-2]]:{{[0-9]*}}: error: invalid instruction +// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 90 or 270 vcadd.f32 d0, d1, d2, #-90 -// NEON-STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 90 or 270 -// NO-NEON-STDERR: :[[@LINE-2]]:{{[0-9]*}}: error: invalid instruction +// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 90 or 270 vcadd.f32 d0, d1, d2, #1 -// NEON-STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 90 or 270 -// NO-NEON-STDERR: :[[@LINE-2]]:{{[0-9]*}}: error: invalid instruction +// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 90 or 270 vcadd.f32 d0, d1, d2, #360 -// NEON-STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 90 or 270 -// NO-NEON-STDERR: :[[@LINE-2]]:{{[0-9]*}}: error: invalid instruction +// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 90 or 270 /* ==== VCMLA indexed ==== */ @@ -127,13 +119,13 @@ vcmla.f16 d0, d1, d2[0], #0 // FP16-ARM: vcmla.f16 d0, d1, d2[0], #0 @ encoding: [0x02,0x08,0x01,0xfe] // FP16-THUMB: vcmla.f16 d0, d1, d2[0], #0 @ encoding: [0x01,0xfe,0x02,0x08] -// NO-FP16-STDERR: :[[@LINE-3]]:{{[0-9]*}}: note: instruction requires: full half-float +// NO-FP16-STDERR: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: full half-float // V82A: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: armv8.3a // NO-NEON_STDERR: :[[@LINE-5]]:{{[0-9]*}}: error: instruction requires: NEON vcmla.f16 q0, q1, d2[0], #0 // FP16-ARM: vcmla.f16 q0, q1, d2[0], #0 @ encoding: [0x42,0x08,0x02,0xfe] // FP16-THUMB: vcmla.f16 q0, q1, d2[0], #0 @ encoding: [0x02,0xfe,0x42,0x08] -// NO-FP16-STDERR: :[[@LINE-3]]:{{[0-9]*}}: note: instruction requires: full half-float +// NO-FP16-STDERR: :[[@LINE-3]]:{{[0-9]*}}: error: instruction requires: full half-float // V82A: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: armv8.3a // NO-NEON_STDERR: :[[@LINE-5]]:{{[0-9]*}}: error: instruction requires: NEON vcmla.f32 d0, d1, d2[0], #0 @@ -166,14 +158,11 @@ // Invalid rotations vcmla.f32 d0, d1, d2[0], #-90 -// NEON-STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270 -// NO-NEON-STDERR: :[[@LINE-2]]:{{[0-9]*}}: error: invalid instruction +// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270 vcmla.f32 d0, d1, d2[0], #1 -// NEON-STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270 -// NO-NEON-STDERR: :[[@LINE-2]]:{{[0-9]*}}: error: invalid instruction +// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270 vcmla.f32 d0, d1, d2[0], #360 -// NEON-STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270 -// NO-NEON-STDERR: :[[@LINE-2]]:{{[0-9]*}}: error: invalid instruction +// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270 // Valid indices vcmla.f16 d0, d1, d2[1], #0 @@ -183,8 +172,9 @@ // NO-NEON_STDERR: :[[@LINE-4]]:{{[0-9]*}}: error: instruction requires: NEON // Invalid indices -// The text of these errors vary depending on whether fullfp16 is present. +// FIXME: These error messages are emitted because the index operand is not +// valid as a rotation, so they are a bit unintuitive. Can we do better? vcmla.f16 d0, d1, d2[2], #0 -// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: +// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270 vcmla.f32 d0, d1, d2[1], #0 -// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: +// STDERR: :[[@LINE-1]]:{{[0-9]*}}: error: complex rotation must be 0, 90, 180 or 270 Index: test/MC/ARM/neon-vld-vst-align.s =================================================================== --- test/MC/ARM/neon-vld-vst-align.s +++ test/MC/ARM/neon-vld-vst-align.s @@ -10,17 +10,17 @@ vld1.8 {d0}, [r4:256] @ CHECK: vld1.8 {d0}, [r4] @ encoding: [0x24,0xf9,0x0f,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.8 {d0}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.8 {d0}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld1.8 {d0}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.8 {d0}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.8 {d0}, [r4:256] @ CHECK-ERRORS: ^ @@ -32,17 +32,17 @@ vld1.8 {d0}, [r4:256]! @ CHECK: vld1.8 {d0}, [r4]! @ encoding: [0x24,0xf9,0x0d,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.8 {d0}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.8 {d0}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld1.8 {d0}, [r4:64]! @ encoding: [0x24,0xf9,0x1d,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.8 {d0}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.8 {d0}, [r4:256]! @ CHECK-ERRORS: ^ @@ -54,17 +54,17 @@ vld1.8 {d0}, [r4:256], r6 @ CHECK: vld1.8 {d0}, [r4], r6 @ encoding: [0x24,0xf9,0x06,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.8 {d0}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.8 {d0}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld1.8 {d0}, [r4:64], r6 @ encoding: [0x24,0xf9,0x16,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.8 {d0}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.8 {d0}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -76,15 +76,15 @@ vld1.8 {d0, d1}, [r4:256] @ CHECK: vld1.8 {d0, d1}, [r4] @ encoding: [0x24,0xf9,0x0f,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld1.8 {d0, d1}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x0a] @ CHECK: vld1.8 {d0, d1}, [r4:128] @ encoding: [0x24,0xf9,0x2f,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:256] @ CHECK-ERRORS: ^ @@ -96,15 +96,15 @@ vld1.8 {d0, d1}, [r4:256]! @ CHECK: vld1.8 {d0, d1}, [r4]! @ encoding: [0x24,0xf9,0x0d,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld1.8 {d0, d1}, [r4:64]! @ encoding: [0x24,0xf9,0x1d,0x0a] @ CHECK: vld1.8 {d0, d1}, [r4:128]! @ encoding: [0x24,0xf9,0x2d,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:256]! @ CHECK-ERRORS: ^ @@ -116,15 +116,15 @@ vld1.8 {d0, d1}, [r4:256], r6 @ CHECK: vld1.8 {d0, d1}, [r4], r6 @ encoding: [0x24,0xf9,0x06,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld1.8 {d0, d1}, [r4:64], r6 @ encoding: [0x24,0xf9,0x16,0x0a] @ CHECK: vld1.8 {d0, d1}, [r4:128], r6 @ encoding: [0x24,0xf9,0x26,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld1.8 {d0, d1}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -136,17 +136,17 @@ vld1.8 {d0, d1, d2}, [r4:256] @ CHECK: vld1.8 {d0, d1, d2}, [r4] @ encoding: [0x24,0xf9,0x0f,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld1.8 {d0, d1, d2}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:256] @ CHECK-ERRORS: ^ @@ -158,17 +158,17 @@ vld1.8 {d0, d1, d2}, [r4:256]! @ CHECK: vld1.8 {d0, d1, d2}, [r4]! @ encoding: [0x24,0xf9,0x0d,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld1.8 {d0, d1, d2}, [r4:64]! @ encoding: [0x24,0xf9,0x1d,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:256]! @ CHECK-ERRORS: ^ @@ -180,17 +180,17 @@ vld1.8 {d0, d1, d2}, [r4:256], r6 @ CHECK: vld1.8 {d0, d1, d2}, [r4], r6 @ encoding: [0x24,0xf9,0x06,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld1.8 {d0, d1, d2}, [r4:64], r6 @ encoding: [0x24,0xf9,0x16,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.8 {d0, d1, d2}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -202,10 +202,10 @@ vld1.8 {d0, d1, d2, d3}, [r4:256] @ CHECK: vld1.8 {d0, d1, d2, d3}, [r4] @ encoding: [0x24,0xf9,0x0f,0x02] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld1.8 {d0, d1, d2, d3}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld1.8 {d0, d1, d2, d3}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld1.8 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x02] @@ -220,10 +220,10 @@ vld1.8 {d0, d1, d2, d3}, [r4:256]! @ CHECK: vld1.8 {d0, d1, d2, d3}, [r4]! @ encoding: [0x24,0xf9,0x0d,0x02] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld1.8 {d0, d1, d2, d3}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld1.8 {d0, d1, d2, d3}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld1.8 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x24,0xf9,0x1d,0x02] @@ -238,10 +238,10 @@ vld1.8 {d0, d1, d2, d3}, [r4:256], r6 @ CHECK: vld1.8 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x24,0xf9,0x06,0x02] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld1.8 {d0, d1, d2, d3}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld1.8 {d0, d1, d2, d3}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld1.8 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x24,0xf9,0x16,0x02] @@ -256,19 +256,19 @@ vld1.8 {d0[2]}, [r4:256] @ CHECK: vld1.8 {d0[2]}, [r4] @ encoding: [0xa4,0xf9,0x4f,0x00] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:32] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:64] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:256] @ CHECK-ERRORS: ^ @@ -280,19 +280,19 @@ vld1.8 {d0[2]}, [r4:256]! @ CHECK: vld1.8 {d0[2]}, [r4]! @ encoding: [0xa4,0xf9,0x4d,0x00] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:32]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:64]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -304,19 +304,19 @@ vld1.8 {d0[2]}, [r4:256], r6 @ CHECK: vld1.8 {d0[2]}, [r4], r6 @ encoding: [0xa4,0xf9,0x46,0x00] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:32], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:64], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld1.8 {d0[2]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -328,19 +328,19 @@ vld1.8 {d0[]}, [r4:256] @ CHECK: vld1.8 {d0[]}, [r4] @ encoding: [0xa4,0xf9,0x0f,0x0c] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:32] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:64] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:256] @ CHECK-ERRORS: ^ @@ -352,19 +352,19 @@ vld1.8 {d0[]}, [r4:256]! @ CHECK: vld1.8 {d0[]}, [r4]! @ encoding: [0xa4,0xf9,0x0d,0x0c] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:32]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:64]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -376,19 +376,19 @@ vld1.8 {d0[]}, [r4:256], r6 @ CHECK: vld1.8 {d0[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x06,0x0c] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:32], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:64], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld1.8 {d0[]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -400,19 +400,19 @@ vld1.8 {d0[], d1[]}, [r4:256] @ CHECK: vld1.8 {d0[], d1[]}, [r4] @ encoding: [0xa4,0xf9,0x2f,0x0c] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:32] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:64] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:256] @ CHECK-ERRORS: ^ @@ -424,19 +424,19 @@ vld1.8 {d0[], d1[]}, [r4:256]! @ CHECK: vld1.8 {d0[], d1[]}, [r4]! @ encoding: [0xa4,0xf9,0x2d,0x0c] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:32]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:64]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -448,19 +448,19 @@ vld1.8 {d0[], d1[]}, [r4:256], r6 @ CHECK: vld1.8 {d0[], d1[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x26,0x0c] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:32], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:64], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld1.8 {d0[], d1[]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -472,17 +472,17 @@ vld1.16 {d0}, [r4:256] @ CHECK: vld1.16 {d0}, [r4] @ encoding: [0x24,0xf9,0x4f,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.16 {d0}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.16 {d0}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld1.16 {d0}, [r4:64] @ encoding: [0x24,0xf9,0x5f,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.16 {d0}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.16 {d0}, [r4:256] @ CHECK-ERRORS: ^ @@ -494,17 +494,17 @@ vld1.16 {d0}, [r4:256]! @ CHECK: vld1.16 {d0}, [r4]! @ encoding: [0x24,0xf9,0x4d,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.16 {d0}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.16 {d0}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld1.16 {d0}, [r4:64]! @ encoding: [0x24,0xf9,0x5d,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.16 {d0}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.16 {d0}, [r4:256]! @ CHECK-ERRORS: ^ @@ -516,17 +516,17 @@ vld1.16 {d0}, [r4:256], r6 @ CHECK: vld1.16 {d0}, [r4], r6 @ encoding: [0x24,0xf9,0x46,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.16 {d0}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.16 {d0}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld1.16 {d0}, [r4:64], r6 @ encoding: [0x24,0xf9,0x56,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.16 {d0}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.16 {d0}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -538,15 +538,15 @@ vld1.16 {d0, d1}, [r4:256] @ CHECK: vld1.16 {d0, d1}, [r4] @ encoding: [0x24,0xf9,0x4f,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld1.16 {d0, d1}, [r4:64] @ encoding: [0x24,0xf9,0x5f,0x0a] @ CHECK: vld1.16 {d0, d1}, [r4:128] @ encoding: [0x24,0xf9,0x6f,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:256] @ CHECK-ERRORS: ^ @@ -558,15 +558,15 @@ vld1.16 {d0, d1}, [r4:256]! @ CHECK: vld1.16 {d0, d1}, [r4]! @ encoding: [0x24,0xf9,0x4d,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld1.16 {d0, d1}, [r4:64]! @ encoding: [0x24,0xf9,0x5d,0x0a] @ CHECK: vld1.16 {d0, d1}, [r4:128]! @ encoding: [0x24,0xf9,0x6d,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:256]! @ CHECK-ERRORS: ^ @@ -578,15 +578,15 @@ vld1.16 {d0, d1}, [r4:256], r6 @ CHECK: vld1.16 {d0, d1}, [r4], r6 @ encoding: [0x24,0xf9,0x46,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld1.16 {d0, d1}, [r4:64], r6 @ encoding: [0x24,0xf9,0x56,0x0a] @ CHECK: vld1.16 {d0, d1}, [r4:128], r6 @ encoding: [0x24,0xf9,0x66,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld1.16 {d0, d1}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -598,17 +598,17 @@ vld1.16 {d0, d1, d2}, [r4:256] @ CHECK: vld1.16 {d0, d1, d2}, [r4] @ encoding: [0x24,0xf9,0x4f,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld1.16 {d0, d1, d2}, [r4:64] @ encoding: [0x24,0xf9,0x5f,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:256] @ CHECK-ERRORS: ^ @@ -620,17 +620,17 @@ vld1.16 {d0, d1, d2}, [r4:256]! @ CHECK: vld1.16 {d0, d1, d2}, [r4]! @ encoding: [0x24,0xf9,0x4d,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld1.16 {d0, d1, d2}, [r4:64]! @ encoding: [0x24,0xf9,0x5d,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:256]! @ CHECK-ERRORS: ^ @@ -642,17 +642,17 @@ vld1.16 {d0, d1, d2}, [r4:256], r6 @ CHECK: vld1.16 {d0, d1, d2}, [r4], r6 @ encoding: [0x24,0xf9,0x46,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld1.16 {d0, d1, d2}, [r4:64], r6 @ encoding: [0x24,0xf9,0x56,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.16 {d0, d1, d2}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -664,10 +664,10 @@ vld1.16 {d0, d1, d2, d3}, [r4:256] @ CHECK: vld1.16 {d0, d1, d2, d3}, [r4] @ encoding: [0x24,0xf9,0x4f,0x02] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld1.16 {d0, d1, d2, d3}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld1.16 {d0, d1, d2, d3}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld1.16 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x24,0xf9,0x5f,0x02] @@ -684,7 +684,7 @@ @ CHECK: vld1.16 {d0, d1, d2, d3}, [r4]! @ encoding: [0x24,0xf9,0x4d,0x02] @ CHECK-ERRORS: vld1.16 {d0, d1, d2, d3}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld1.16 {d0, d1, d2, d3}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld1.16 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x24,0xf9,0x5d,0x02] @@ -699,10 +699,10 @@ vld1.16 {d0, d1, d2, d3}, [r4:256], r6 @ CHECK: vld1.16 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x24,0xf9,0x46,0x02] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld1.16 {d0, d1, d2, d3}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld1.16 {d0, d1, d2, d3}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld1.16 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x24,0xf9,0x56,0x02] @@ -718,16 +718,16 @@ @ CHECK: vld1.16 {d0[2]}, [r4] @ encoding: [0xa4,0xf9,0x8f,0x04] @ CHECK: vld1.16 {d0[2]}, [r4:16] @ encoding: [0xa4,0xf9,0x9f,0x04] -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:32] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:64] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:256] @ CHECK-ERRORS: ^ @@ -740,16 +740,16 @@ @ CHECK: vld1.16 {d0[2]}, [r4]! @ encoding: [0xa4,0xf9,0x8d,0x04] @ CHECK: vld1.16 {d0[2]}, [r4:16]! @ encoding: [0xa4,0xf9,0x9d,0x04] -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:32]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:64]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -762,16 +762,16 @@ @ CHECK: vld1.16 {d0[2]}, [r4], r6 @ encoding: [0xa4,0xf9,0x86,0x04] @ CHECK: vld1.16 {d0[2]}, [r4:16], r6 @ encoding: [0xa4,0xf9,0x96,0x04] -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:32], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:64], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld1.16 {d0[2]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -784,16 +784,16 @@ @ CHECK: vld1.16 {d0[]}, [r4] @ encoding: [0xa4,0xf9,0x4f,0x0c] @ CHECK: vld1.16 {d0[]}, [r4:16] @ encoding: [0xa4,0xf9,0x5f,0x0c] -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld1.16 {d0[]}, [r4:32] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld1.16 {d0[]}, [r4:64] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld1.16 {d0[]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld1.16 {d0[]}, [r4:256] @ CHECK-ERRORS: ^ @@ -806,16 +806,16 @@ @ CHECK: vld1.16 {d0[]}, [r4]! @ encoding: [0xa4,0xf9,0x4d,0x0c] @ CHECK: vld1.16 {d0[]}, [r4:16]! @ encoding: [0xa4,0xf9,0x5d,0x0c] -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld1.16 {d0[]}, [r4:32]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld1.16 {d0[]}, [r4:64]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld1.16 {d0[]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld1.16 {d0[]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -828,16 +828,16 @@ @ CHECK: vld1.16 {d0[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x46,0x0c] @ CHECK: vld1.16 {d0[]}, [r4:16], r6 @ encoding: [0xa4,0xf9,0x56,0x0c] -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld1.16 {d0[]}, [r4:32], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld1.16 {d0[]}, [r4:64], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld1.16 {d0[]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld1.16 {d0[]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -850,16 +850,16 @@ @ CHECK: vld1.16 {d0[], d1[]}, [r4] @ encoding: [0xa4,0xf9,0x6f,0x0c] @ CHECK: vld1.16 {d0[], d1[]}, [r4:16] @ encoding: [0xa4,0xf9,0x7f,0x0c] -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld1.16 {d0[], d1[]}, [r4:32] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld1.16 {d0[], d1[]}, [r4:64] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld1.16 {d0[], d1[]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld1.16 {d0[], d1[]}, [r4:256] @ CHECK-ERRORS: ^ @@ -872,16 +872,16 @@ @ CHECK: vld1.16 {d0[], d1[]}, [r4]! @ encoding: [0xa4,0xf9,0x6d,0x0c] @ CHECK: vld1.16 {d0[], d1[]}, [r4:16]! @ encoding: [0xa4,0xf9,0x7d,0x0c] -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld1.16 {d0[], d1[]}, [r4:32]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld1.16 {d0[], d1[]}, [r4:64]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld1.16 {d0[], d1[]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld1.16 {d0[], d1[]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -894,16 +894,16 @@ @ CHECK: vld1.16 {d0[], d1[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x66,0x0c] @ CHECK: vld1.16 {d0[], d1[]}, [r4:16], r6 @ encoding: [0xa4,0xf9,0x76,0x0c] -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld1.16 {d0[], d1[]}, [r4:32], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld1.16 {d0[], d1[]}, [r4:64], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld1.16 {d0[], d1[]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld1.16 {d0[], d1[]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -915,17 +915,17 @@ vld1.32 {d0}, [r4:256] @ CHECK: vld1.32 {d0}, [r4] @ encoding: [0x24,0xf9,0x8f,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.32 {d0}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.32 {d0}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld1.32 {d0}, [r4:64] @ encoding: [0x24,0xf9,0x9f,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.32 {d0}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.32 {d0}, [r4:256] @ CHECK-ERRORS: ^ @@ -937,17 +937,17 @@ vld1.32 {d0}, [r4:256]! @ CHECK: vld1.32 {d0}, [r4]! @ encoding: [0x24,0xf9,0x8d,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.32 {d0}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.32 {d0}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld1.32 {d0}, [r4:64]! @ encoding: [0x24,0xf9,0x9d,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.32 {d0}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.32 {d0}, [r4:256]! @ CHECK-ERRORS: ^ @@ -959,17 +959,17 @@ vld1.32 {d0}, [r4:256], r6 @ CHECK: vld1.32 {d0}, [r4], r6 @ encoding: [0x24,0xf9,0x86,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.32 {d0}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.32 {d0}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld1.32 {d0}, [r4:64], r6 @ encoding: [0x24,0xf9,0x96,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.32 {d0}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.32 {d0}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -981,15 +981,15 @@ vld1.32 {d0, d1}, [r4:256] @ CHECK: vld1.32 {d0, d1}, [r4] @ encoding: [0x24,0xf9,0x8f,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld1.32 {d0, d1}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld1.32 {d0, d1}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld1.32 {d0, d1}, [r4:64] @ encoding: [0x24,0xf9,0x9f,0x0a] @ CHECK: vld1.32 {d0, d1}, [r4:128] @ encoding: [0x24,0xf9,0xaf,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld1.32 {d0, d1}, [r4:256] @ CHECK-ERRORS: ^ @@ -1001,15 +1001,15 @@ vld1.32 {d0, d1}, [r4:256]! @ CHECK: vld1.32 {d0, d1}, [r4]! @ encoding: [0x24,0xf9,0x8d,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld1.32 {d0, d1}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld1.32 {d0, d1}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld1.32 {d0, d1}, [r4:64]! @ encoding: [0x24,0xf9,0x9d,0x0a] @ CHECK: vld1.32 {d0, d1}, [r4:128]! @ encoding: [0x24,0xf9,0xad,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld1.32 {d0, d1}, [r4:256]! @ CHECK-ERRORS: ^ @@ -1021,15 +1021,15 @@ vld1.32 {d0, d1}, [r4:256], r6 @ CHECK: vld1.32 {d0, d1}, [r4], r6 @ encoding: [0x24,0xf9,0x86,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld1.32 {d0, d1}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld1.32 {d0, d1}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld1.32 {d0, d1}, [r4:64], r6 @ encoding: [0x24,0xf9,0x96,0x0a] @ CHECK: vld1.32 {d0, d1}, [r4:128], r6 @ encoding: [0x24,0xf9,0xa6,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld1.32 {d0, d1}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -1041,17 +1041,17 @@ vld1.32 {d0, d1, d2}, [r4:256] @ CHECK: vld1.32 {d0, d1, d2}, [r4] @ encoding: [0x24,0xf9,0x8f,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.32 {d0, d1, d2}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.32 {d0, d1, d2}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld1.32 {d0, d1, d2}, [r4:64] @ encoding: [0x24,0xf9,0x9f,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.32 {d0, d1, d2}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.32 {d0, d1, d2}, [r4:256] @ CHECK-ERRORS: ^ @@ -1063,17 +1063,17 @@ vld1.32 {d0, d1, d2}, [r4:256]! @ CHECK: vld1.32 {d0, d1, d2}, [r4]! @ encoding: [0x24,0xf9,0x8d,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.32 {d0, d1, d2}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.32 {d0, d1, d2}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld1.32 {d0, d1, d2}, [r4:64]! @ encoding: [0x24,0xf9,0x9d,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.32 {d0, d1, d2}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.32 {d0, d1, d2}, [r4:256]! @ CHECK-ERRORS: ^ @@ -1085,17 +1085,17 @@ vld1.32 {d0, d1, d2}, [r4:256], r6 @ CHECK: vld1.32 {d0, d1, d2}, [r4], r6 @ encoding: [0x24,0xf9,0x86,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.32 {d0, d1, d2}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.32 {d0, d1, d2}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld1.32 {d0, d1, d2}, [r4:64], r6 @ encoding: [0x24,0xf9,0x96,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.32 {d0, d1, d2}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.32 {d0, d1, d2}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -1107,10 +1107,10 @@ vld1.32 {d0, d1, d2, d3}, [r4:256] @ CHECK: vld1.32 {d0, d1, d2, d3}, [r4] @ encoding: [0x24,0xf9,0x8f,0x02] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld1.32 {d0, d1, d2, d3}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld1.32 {d0, d1, d2, d3}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld1.32 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x24,0xf9,0x9f,0x02] @@ -1125,10 +1125,10 @@ vld1.32 {d0, d1, d2, d3}, [r4:256]! @ CHECK: vld1.32 {d0, d1, d2, d3}, [r4]! @ encoding: [0x24,0xf9,0x8d,0x02] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld1.32 {d0, d1, d2, d3}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld1.32 {d0, d1, d2, d3}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld1.32 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x24,0xf9,0x9d,0x02] @@ -1143,10 +1143,10 @@ vld1.32 {d0, d1, d2, d3}, [r4:256], r6 @ CHECK: vld1.32 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x24,0xf9,0x86,0x02] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld1.32 {d0, d1, d2, d3}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld1.32 {d0, d1, d2, d3}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld1.32 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x24,0xf9,0x96,0x02] @@ -1161,17 +1161,17 @@ vld1.32 {d0[1]}, [r4:256] @ CHECK: vld1.32 {d0[1]}, [r4] @ encoding: [0xa4,0xf9,0x8f,0x08] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:16] @ CHECK-ERRORS: ^ @ CHECK: vld1.32 {d0[1]}, [r4:32] @ encoding: [0xa4,0xf9,0xbf,0x08] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:64] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:256] @ CHECK-ERRORS: ^ @@ -1183,17 +1183,17 @@ vld1.32 {d0[1]}, [r4:256]! @ CHECK: vld1.32 {d0[1]}, [r4]! @ encoding: [0xa4,0xf9,0x8d,0x08] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:16]! @ CHECK-ERRORS: ^ @ CHECK: vld1.32 {d0[1]}, [r4:32]! @ encoding: [0xa4,0xf9,0xbd,0x08] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:64]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -1205,17 +1205,17 @@ vld1.32 {d0[1]}, [r4:256], r6 @ CHECK: vld1.32 {d0[1]}, [r4], r6 @ encoding: [0xa4,0xf9,0x86,0x08] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:16], r6 @ CHECK-ERRORS: ^ @ CHECK: vld1.32 {d0[1]}, [r4:32], r6 @ encoding: [0xa4,0xf9,0xb6,0x08] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:64], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -1227,17 +1227,17 @@ vld1.32 {d0[]}, [r4:256] @ CHECK: vld1.32 {d0[]}, [r4] @ encoding: [0xa4,0xf9,0x8f,0x0c] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[]}, [r4:16] @ CHECK-ERRORS: ^ @ CHECK: vld1.32 {d0[]}, [r4:32] @ encoding: [0xa4,0xf9,0x9f,0x0c] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[]}, [r4:64] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[]}, [r4:256] @ CHECK-ERRORS: ^ @@ -1249,17 +1249,17 @@ vld1.32 {d0[]}, [r4:256]! @ CHECK: vld1.32 {d0[]}, [r4]! @ encoding: [0xa4,0xf9,0x8d,0x0c] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[]}, [r4:16]! @ CHECK-ERRORS: ^ @ CHECK: vld1.32 {d0[]}, [r4:32]! @ encoding: [0xa4,0xf9,0x9d,0x0c] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[]}, [r4:64]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -1271,17 +1271,17 @@ vld1.32 {d0[]}, [r4:256], r6 @ CHECK: vld1.32 {d0[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x86,0x0c] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[]}, [r4:16], r6 @ CHECK-ERRORS: ^ @ CHECK: vld1.32 {d0[]}, [r4:32], r6 @ encoding: [0xa4,0xf9,0x96,0x0c] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[]}, [r4:64], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -1293,17 +1293,17 @@ vld1.32 {d0[], d1[]}, [r4:256] @ CHECK: vld1.32 {d0[], d1[]}, [r4] @ encoding: [0xa4,0xf9,0xaf,0x0c] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[], d1[]}, [r4:16] @ CHECK-ERRORS: ^ @ CHECK: vld1.32 {d0[], d1[]}, [r4:32] @ encoding: [0xa4,0xf9,0xbf,0x0c] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[], d1[]}, [r4:64] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[], d1[]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[], d1[]}, [r4:256] @ CHECK-ERRORS: ^ @@ -1315,17 +1315,17 @@ vld1.32 {d0[], d1[]}, [r4:256]! @ CHECK: vld1.32 {d0[], d1[]}, [r4]! @ encoding: [0xa4,0xf9,0xad,0x0c] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[], d1[]}, [r4:16]! @ CHECK-ERRORS: ^ @ CHECK: vld1.32 {d0[], d1[]}, [r4:32]! @ encoding: [0xa4,0xf9,0xbd,0x0c] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[], d1[]}, [r4:64]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[], d1[]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[], d1[]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -1337,17 +1337,17 @@ vld1.32 {d0[], d1[]}, [r4:256], r6 @ CHECK: vld1.32 {d0[], d1[]}, [r4], r6 @ encoding: [0xa4,0xf9,0xa6,0x0c] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[], d1[]}, [r4:16], r6 @ CHECK-ERRORS: ^ @ CHECK: vld1.32 {d0[], d1[]}, [r4:32], r6 @ encoding: [0xa4,0xf9,0xb6,0x0c] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[], d1[]}, [r4:64], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[], d1[]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[], d1[]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -1359,17 +1359,17 @@ vld1.32 {d0[1]}, [r4:256] @ CHECK: vld1.32 {d0[1]}, [r4] @ encoding: [0xa4,0xf9,0x8f,0x08] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:16] @ CHECK-ERRORS: ^ @ CHECK: vld1.32 {d0[1]}, [r4:32] @ encoding: [0xa4,0xf9,0xbf,0x08] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:64] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:256] @ CHECK-ERRORS: ^ @@ -1381,17 +1381,17 @@ vld1.32 {d0[1]}, [r4:256]! @ CHECK: vld1.32 {d0[1]}, [r4]! @ encoding: [0xa4,0xf9,0x8d,0x08] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:16]! @ CHECK-ERRORS: ^ @ CHECK: vld1.32 {d0[1]}, [r4:32]! @ encoding: [0xa4,0xf9,0xbd,0x08] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:64]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -1403,17 +1403,17 @@ vld1.32 {d0[1]}, [r4:256], r6 @ CHECK: vld1.32 {d0[1]}, [r4], r6 @ encoding: [0xa4,0xf9,0x86,0x08] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:16], r6 @ CHECK-ERRORS: ^ @ CHECK: vld1.32 {d0[1]}, [r4:32], r6 @ encoding: [0xa4,0xf9,0xb6,0x08] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:64], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld1.32 {d0[1]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -1425,17 +1425,17 @@ vld1.64 {d0}, [r4:256] @ CHECK: vld1.64 {d0}, [r4] @ encoding: [0x24,0xf9,0xcf,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.64 {d0}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.64 {d0}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld1.64 {d0}, [r4:64] @ encoding: [0x24,0xf9,0xdf,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.64 {d0}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.64 {d0}, [r4:256] @ CHECK-ERRORS: ^ @@ -1447,17 +1447,17 @@ vld1.64 {d0}, [r4:256]! @ CHECK: vld1.64 {d0}, [r4]! @ encoding: [0x24,0xf9,0xcd,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.64 {d0}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.64 {d0}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld1.64 {d0}, [r4:64]! @ encoding: [0x24,0xf9,0xdd,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.64 {d0}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.64 {d0}, [r4:256]! @ CHECK-ERRORS: ^ @@ -1469,17 +1469,17 @@ vld1.64 {d0}, [r4:256], r6 @ CHECK: vld1.64 {d0}, [r4], r6 @ encoding: [0x24,0xf9,0xc6,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.64 {d0}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.64 {d0}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld1.64 {d0}, [r4:64], r6 @ encoding: [0x24,0xf9,0xd6,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.64 {d0}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.64 {d0}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -1491,15 +1491,15 @@ vld1.64 {d0, d1}, [r4:256] @ CHECK: vld1.64 {d0, d1}, [r4] @ encoding: [0x24,0xf9,0xcf,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld1.64 {d0, d1}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld1.64 {d0, d1}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld1.64 {d0, d1}, [r4:64] @ encoding: [0x24,0xf9,0xdf,0x0a] @ CHECK: vld1.64 {d0, d1}, [r4:128] @ encoding: [0x24,0xf9,0xef,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld1.64 {d0, d1}, [r4:256] @ CHECK-ERRORS: ^ @@ -1511,15 +1511,15 @@ vld1.64 {d0, d1}, [r4:256]! @ CHECK: vld1.64 {d0, d1}, [r4]! @ encoding: [0x24,0xf9,0xcd,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld1.64 {d0, d1}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld1.64 {d0, d1}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld1.64 {d0, d1}, [r4:64]! @ encoding: [0x24,0xf9,0xdd,0x0a] @ CHECK: vld1.64 {d0, d1}, [r4:128]! @ encoding: [0x24,0xf9,0xed,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld1.64 {d0, d1}, [r4:256]! @ CHECK-ERRORS: ^ @@ -1531,15 +1531,15 @@ vld1.64 {d0, d1}, [r4:256], r6 @ CHECK: vld1.64 {d0, d1}, [r4], r6 @ encoding: [0x24,0xf9,0xc6,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld1.64 {d0, d1}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld1.64 {d0, d1}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld1.64 {d0, d1}, [r4:64], r6 @ encoding: [0x24,0xf9,0xd6,0x0a] @ CHECK: vld1.64 {d0, d1}, [r4:128], r6 @ encoding: [0x24,0xf9,0xe6,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld1.64 {d0, d1}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -1551,17 +1551,17 @@ vld1.64 {d0, d1, d2}, [r4:256] @ CHECK: vld1.64 {d0, d1, d2}, [r4] @ encoding: [0x24,0xf9,0xcf,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.64 {d0, d1, d2}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.64 {d0, d1, d2}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld1.64 {d0, d1, d2}, [r4:64] @ encoding: [0x24,0xf9,0xdf,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.64 {d0, d1, d2}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.64 {d0, d1, d2}, [r4:256] @ CHECK-ERRORS: ^ @@ -1573,17 +1573,17 @@ vld1.64 {d0, d1, d2}, [r4:256]! @ CHECK: vld1.64 {d0, d1, d2}, [r4]! @ encoding: [0x24,0xf9,0xcd,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.64 {d0, d1, d2}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.64 {d0, d1, d2}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld1.64 {d0, d1, d2}, [r4:64]! @ encoding: [0x24,0xf9,0xdd,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.64 {d0, d1, d2}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.64 {d0, d1, d2}, [r4:256]! @ CHECK-ERRORS: ^ @@ -1595,17 +1595,17 @@ vld1.64 {d0, d1, d2}, [r4:256], r6 @ CHECK: vld1.64 {d0, d1, d2}, [r4], r6 @ encoding: [0x24,0xf9,0xc6,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.64 {d0, d1, d2}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.64 {d0, d1, d2}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld1.64 {d0, d1, d2}, [r4:64], r6 @ encoding: [0x24,0xf9,0xd6,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.64 {d0, d1, d2}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld1.64 {d0, d1, d2}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -1617,10 +1617,10 @@ vld1.64 {d0, d1, d2, d3}, [r4:256] @ CHECK: vld1.64 {d0, d1, d2, d3}, [r4] @ encoding: [0x24,0xf9,0xcf,0x02] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld1.64 {d0, d1, d2, d3}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld1.64 {d0, d1, d2, d3}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld1.64 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x24,0xf9,0xdf,0x02] @@ -1635,10 +1635,10 @@ vld1.64 {d0, d1, d2, d3}, [r4:256]! @ CHECK: vld1.64 {d0, d1, d2, d3}, [r4]! @ encoding: [0x24,0xf9,0xcd,0x02] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld1.64 {d0, d1, d2, d3}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld1.64 {d0, d1, d2, d3}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld1.64 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x24,0xf9,0xdd,0x02] @@ -1653,10 +1653,10 @@ vld1.64 {d0, d1, d2, d3}, [r4:256], r6 @ CHECK: vld1.64 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x24,0xf9,0xc6,0x02] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld1.64 {d0, d1, d2, d3}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld1.64 {d0, d1, d2, d3}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld1.64 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x24,0xf9,0xd6,0x02] @@ -1671,15 +1671,15 @@ vld2.8 {d0, d1}, [r4:256] @ CHECK: vld2.8 {d0, d1}, [r4] @ encoding: [0x24,0xf9,0x0f,0x08] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.8 {d0, d1}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.8 {d0, d1}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld2.8 {d0, d1}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x08] @ CHECK: vld2.8 {d0, d1}, [r4:128] @ encoding: [0x24,0xf9,0x2f,0x08] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.8 {d0, d1}, [r4:256] @ CHECK-ERRORS: ^ @@ -1691,15 +1691,15 @@ vld2.8 {d0, d1}, [r4:256]! @ CHECK: vld2.8 {d0, d1}, [r4]! @ encoding: [0x24,0xf9,0x0d,0x08] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.8 {d0, d1}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.8 {d0, d1}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld2.8 {d0, d1}, [r4:64]! @ encoding: [0x24,0xf9,0x1d,0x08] @ CHECK: vld2.8 {d0, d1}, [r4:128]! @ encoding: [0x24,0xf9,0x2d,0x08] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.8 {d0, d1}, [r4:256]! @ CHECK-ERRORS: ^ @@ -1711,15 +1711,15 @@ vld2.8 {d0, d1}, [r4:256], r6 @ CHECK: vld2.8 {d0, d1}, [r4], r6 @ encoding: [0x24,0xf9,0x06,0x08] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.8 {d0, d1}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.8 {d0, d1}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld2.8 {d0, d1}, [r4:64], r6 @ encoding: [0x24,0xf9,0x16,0x08] @ CHECK: vld2.8 {d0, d1}, [r4:128], r6 @ encoding: [0x24,0xf9,0x26,0x08] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.8 {d0, d1}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -1731,15 +1731,15 @@ vld2.8 {d0, d2}, [r4:256] @ CHECK: vld2.8 {d0, d2}, [r4] @ encoding: [0x24,0xf9,0x0f,0x09] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.8 {d0, d2}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.8 {d0, d2}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld2.8 {d0, d2}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x09] @ CHECK: vld2.8 {d0, d2}, [r4:128] @ encoding: [0x24,0xf9,0x2f,0x09] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.8 {d0, d2}, [r4:256] @ CHECK-ERRORS: ^ @@ -1751,15 +1751,15 @@ vld2.8 {d0, d2}, [r4:256]! @ CHECK: vld2.8 {d0, d2}, [r4]! @ encoding: [0x24,0xf9,0x0d,0x09] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.8 {d0, d2}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.8 {d0, d2}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld2.8 {d0, d2}, [r4:64]! @ encoding: [0x24,0xf9,0x1d,0x09] @ CHECK: vld2.8 {d0, d2}, [r4:128]! @ encoding: [0x24,0xf9,0x2d,0x09] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.8 {d0, d2}, [r4:256]! @ CHECK-ERRORS: ^ @@ -1771,15 +1771,15 @@ vld2.8 {d0, d2}, [r4:256], r6 @ CHECK: vld2.8 {d0, d2}, [r4], r6 @ encoding: [0x24,0xf9,0x06,0x09] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.8 {d0, d2}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.8 {d0, d2}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld2.8 {d0, d2}, [r4:64], r6 @ encoding: [0x24,0xf9,0x16,0x09] @ CHECK: vld2.8 {d0, d2}, [r4:128], r6 @ encoding: [0x24,0xf9,0x26,0x09] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.8 {d0, d2}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -1791,10 +1791,10 @@ vld2.8 {d0, d1, d2, d3}, [r4:256] @ CHECK: vld2.8 {d0, d1, d2, d3}, [r4] @ encoding: [0x24,0xf9,0x0f,0x03] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld2.8 {d0, d1, d2, d3}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld2.8 {d0, d1, d2, d3}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld2.8 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x03] @@ -1809,10 +1809,10 @@ vld2.8 {d0, d1, d2, d3}, [r4:256]! @ CHECK: vld2.8 {d0, d1, d2, d3}, [r4]! @ encoding: [0x24,0xf9,0x0d,0x03] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld2.8 {d0, d1, d2, d3}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld2.8 {d0, d1, d2, d3}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld2.8 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x24,0xf9,0x1d,0x03] @@ -1827,10 +1827,10 @@ vld2.8 {d0, d1, d2, d3}, [r4:256], r6 @ CHECK: vld2.8 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x24,0xf9,0x06,0x03] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld2.8 {d0, d1, d2, d3}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld2.8 {d0, d1, d2, d3}, [r4:32], r6 @ CHECK: vld2.8 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x24,0xf9,0x16,0x03] @ CHECK: vld2.8 {d0, d1, d2, d3}, [r4:128], r6 @ encoding: [0x24,0xf9,0x26,0x03] @@ -1845,16 +1845,16 @@ @ CHECK: vld2.8 {d0[2], d1[2]}, [r4] @ encoding: [0xa4,0xf9,0x4f,0x01] @ CHECK: vld2.8 {d0[2], d1[2]}, [r4:16] @ encoding: [0xa4,0xf9,0x5f,0x01] -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld2.8 {d0[2], d1[2]}, [r4:32] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld2.8 {d0[2], d1[2]}, [r4:64] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld2.8 {d0[2], d1[2]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld2.8 {d0[2], d1[2]}, [r4:256] @ CHECK-ERRORS: ^ @@ -1867,16 +1867,16 @@ @ CHECK: vld2.8 {d0[2], d1[2]}, [r4]! @ encoding: [0xa4,0xf9,0x4d,0x01] @ CHECK: vld2.8 {d0[2], d1[2]}, [r4:16]! @ encoding: [0xa4,0xf9,0x5d,0x01] -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld2.8 {d0[2], d1[2]}, [r4:32]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld2.8 {d0[2], d1[2]}, [r4:64]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld2.8 {d0[2], d1[2]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld2.8 {d0[2], d1[2]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -1889,16 +1889,16 @@ @ CHECK: vld2.8 {d0[2], d1[2]}, [r4], r6 @ encoding: [0xa4,0xf9,0x46,0x01] @ CHECK: vld2.8 {d0[2], d1[2]}, [r4:16], r6 @ encoding: [0xa4,0xf9,0x56,0x01] -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld2.8 {d0[2], d1[2]}, [r4:32], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld2.8 {d0[2], d1[2]}, [r4:64], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld2.8 {d0[2], d1[2]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld2.8 {d0[2], d1[2]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -1911,16 +1911,16 @@ @ CHECK: vld2.8 {d0[], d1[]}, [r4] @ encoding: [0xa4,0xf9,0x0f,0x0d] @ CHECK: vld2.8 {d0[], d1[]}, [r4:16] @ encoding: [0xa4,0xf9,0x1f,0x0d] -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld2.8 {d0[], d1[]}, [r4:32] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld2.8 {d0[], d1[]}, [r4:64] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld2.8 {d0[], d1[]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld2.8 {d0[], d1[]}, [r4:256] @ CHECK-ERRORS: ^ @@ -1933,16 +1933,16 @@ @ CHECK: vld2.8 {d0[], d1[]}, [r4]! @ encoding: [0xa4,0xf9,0x0d,0x0d] @ CHECK: vld2.8 {d0[], d1[]}, [r4:16]! @ encoding: [0xa4,0xf9,0x1d,0x0d] -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld2.8 {d0[], d1[]}, [r4:32]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld2.8 {d0[], d1[]}, [r4:64]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld2.8 {d0[], d1[]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld2.8 {d0[], d1[]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -1955,16 +1955,16 @@ @ CHECK: vld2.8 {d0[], d1[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x06,0x0d] @ CHECK: vld2.8 {d0[], d1[]}, [r4:16], r6 @ encoding: [0xa4,0xf9,0x16,0x0d] -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld2.8 {d0[], d1[]}, [r4:32], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld2.8 {d0[], d1[]}, [r4:64], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld2.8 {d0[], d1[]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld2.8 {d0[], d1[]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -1977,16 +1977,16 @@ @ CHECK: vld2.8 {d0[], d2[]}, [r4] @ encoding: [0xa4,0xf9,0x2f,0x0d] @ CHECK: vld2.8 {d0[], d2[]}, [r4:16] @ encoding: [0xa4,0xf9,0x3f,0x0d] -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld2.8 {d0[], d2[]}, [r4:32] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld2.8 {d0[], d2[]}, [r4:64] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld2.8 {d0[], d2[]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld2.8 {d0[], d2[]}, [r4:256] @ CHECK-ERRORS: ^ @@ -1999,16 +1999,16 @@ @ CHECK: vld2.8 {d0[], d2[]}, [r4]! @ encoding: [0xa4,0xf9,0x2d,0x0d] @ CHECK: vld2.8 {d0[], d2[]}, [r4:16]! @ encoding: [0xa4,0xf9,0x3d,0x0d] -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld2.8 {d0[], d2[]}, [r4:32]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld2.8 {d0[], d2[]}, [r4:64]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld2.8 {d0[], d2[]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld2.8 {d0[], d2[]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -2021,16 +2021,16 @@ @ CHECK: vld2.8 {d0[], d2[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x26,0x0d] @ CHECK: vld2.8 {d0[], d2[]}, [r4:16], r6 @ encoding: [0xa4,0xf9,0x36,0x0d] -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld2.8 {d0[], d2[]}, [r4:32], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld2.8 {d0[], d2[]}, [r4:64], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld2.8 {d0[], d2[]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vld2.8 {d0[], d2[]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -2042,15 +2042,15 @@ vld2.16 {d0, d1}, [r4:256] @ CHECK: vld2.16 {d0, d1}, [r4] @ encoding: [0x24,0xf9,0x4f,0x08] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.16 {d0, d1}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.16 {d0, d1}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld2.16 {d0, d1}, [r4:64] @ encoding: [0x24,0xf9,0x5f,0x08] @ CHECK: vld2.16 {d0, d1}, [r4:128] @ encoding: [0x24,0xf9,0x6f,0x08] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.16 {d0, d1}, [r4:256] @ CHECK-ERRORS: ^ @@ -2062,15 +2062,15 @@ vld2.16 {d0, d1}, [r4:256]! @ CHECK: vld2.16 {d0, d1}, [r4]! @ encoding: [0x24,0xf9,0x4d,0x08] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.16 {d0, d1}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.16 {d0, d1}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld2.16 {d0, d1}, [r4:64]! @ encoding: [0x24,0xf9,0x5d,0x08] @ CHECK: vld2.16 {d0, d1}, [r4:128]! @ encoding: [0x24,0xf9,0x6d,0x08] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.16 {d0, d1}, [r4:256]! @ CHECK-ERRORS: ^ @@ -2082,15 +2082,15 @@ vld2.16 {d0, d1}, [r4:256], r6 @ CHECK: vld2.16 {d0, d1}, [r4], r6 @ encoding: [0x24,0xf9,0x46,0x08] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.16 {d0, d1}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.16 {d0, d1}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld2.16 {d0, d1}, [r4:64], r6 @ encoding: [0x24,0xf9,0x56,0x08] @ CHECK: vld2.16 {d0, d1}, [r4:128], r6 @ encoding: [0x24,0xf9,0x66,0x08] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.16 {d0, d1}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -2102,15 +2102,15 @@ vld2.16 {d0, d2}, [r4:256] @ CHECK: vld2.16 {d0, d2}, [r4] @ encoding: [0x24,0xf9,0x4f,0x09] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.16 {d0, d2}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.16 {d0, d2}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld2.16 {d0, d2}, [r4:64] @ encoding: [0x24,0xf9,0x5f,0x09] @ CHECK: vld2.16 {d0, d2}, [r4:128] @ encoding: [0x24,0xf9,0x6f,0x09] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.16 {d0, d2}, [r4:256] @ CHECK-ERRORS: ^ @@ -2122,15 +2122,15 @@ vld2.16 {d0, d2}, [r4:256]! @ CHECK: vld2.16 {d0, d2}, [r4]! @ encoding: [0x24,0xf9,0x4d,0x09] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.16 {d0, d2}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.16 {d0, d2}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld2.16 {d0, d2}, [r4:64]! @ encoding: [0x24,0xf9,0x5d,0x09] @ CHECK: vld2.16 {d0, d2}, [r4:128]! @ encoding: [0x24,0xf9,0x6d,0x09] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.16 {d0, d2}, [r4:256]! @ CHECK-ERRORS: ^ @@ -2142,15 +2142,15 @@ vld2.16 {d0, d2}, [r4:256], r6 @ CHECK: vld2.16 {d0, d2}, [r4], r6 @ encoding: [0x24,0xf9,0x46,0x09] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.16 {d0, d2}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.16 {d0, d2}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld2.16 {d0, d2}, [r4:64], r6 @ encoding: [0x24,0xf9,0x56,0x09] @ CHECK: vld2.16 {d0, d2}, [r4:128], r6 @ encoding: [0x24,0xf9,0x66,0x09] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.16 {d0, d2}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -2162,10 +2162,10 @@ vld2.16 {d0, d1, d2, d3}, [r4:256] @ CHECK: vld2.16 {d0, d1, d2, d3}, [r4] @ encoding: [0x24,0xf9,0x4f,0x03] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld2.16 {d0, d1, d2, d3}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld2.16 {d0, d1, d2, d3}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld2.16 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x24,0xf9,0x5f,0x03] @@ -2180,10 +2180,10 @@ vld2.16 {d0, d1, d2, d3}, [r4:256]! @ CHECK: vld2.16 {d0, d1, d2, d3}, [r4]! @ encoding: [0x24,0xf9,0x4d,0x03] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld2.16 {d0, d1, d2, d3}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld2.16 {d0, d1, d2, d3}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld2.16 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x24,0xf9,0x5d,0x03] @@ -2198,10 +2198,10 @@ vld2.16 {d0, d1, d2, d3}, [r4:256], r6 @ CHECK: vld2.16 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x24,0xf9,0x46,0x03] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld2.16 {d0, d1, d2, d3}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld2.16 {d0, d1, d2, d3}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld2.16 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x24,0xf9,0x56,0x03] @@ -2216,17 +2216,17 @@ vld2.16 {d0[2], d1[2]}, [r4:256] @ CHECK: vld2.16 {d0[2], d1[2]}, [r4] @ encoding: [0xa4,0xf9,0x8f,0x05] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[2], d1[2]}, [r4:16] @ CHECK-ERRORS: ^ @ CHECK: vld2.16 {d0[2], d1[2]}, [r4:32] @ encoding: [0xa4,0xf9,0x9f,0x05] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[2], d1[2]}, [r4:64] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[2], d1[2]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[2], d1[2]}, [r4:256] @ CHECK-ERRORS: ^ @@ -2238,17 +2238,17 @@ vld2.16 {d0[2], d1[2]}, [r4:256]! @ CHECK: vld2.16 {d0[2], d1[2]}, [r4]! @ encoding: [0xa4,0xf9,0x8d,0x05] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[2], d1[2]}, [r4:16]! @ CHECK-ERRORS: ^ @ CHECK: vld2.16 {d0[2], d1[2]}, [r4:32]! @ encoding: [0xa4,0xf9,0x9d,0x05] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[2], d1[2]}, [r4:64]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[2], d1[2]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[2], d1[2]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -2260,17 +2260,17 @@ vld2.16 {d0[2], d1[2]}, [r4:256], r6 @ CHECK: vld2.16 {d0[2], d1[2]}, [r4], r6 @ encoding: [0xa4,0xf9,0x86,0x05] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[2], d1[2]}, [r4:16], r6 @ CHECK-ERRORS: ^ @ CHECK: vld2.16 {d0[2], d1[2]}, [r4:32], r6 @ encoding: [0xa4,0xf9,0x96,0x05] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[2], d1[2]}, [r4:64], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[2], d1[2]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[2], d1[2]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -2282,17 +2282,17 @@ vld2.16 {d0[2], d2[2]}, [r4:256] @ CHECK: vld2.16 {d0[2], d2[2]}, [r4] @ encoding: [0xa4,0xf9,0xaf,0x05] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[2], d2[2]}, [r4:16] @ CHECK-ERRORS: ^ @ CHECK: vld2.16 {d0[2], d2[2]}, [r4:32] @ encoding: [0xa4,0xf9,0xbf,0x05] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[2], d2[2]}, [r4:64] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[2], d2[2]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[2], d2[2]}, [r4:256] @ CHECK-ERRORS: ^ @@ -2304,17 +2304,17 @@ vld2.16 {d0[2], d2[2]}, [r4:256]! @ CHECK: vld2.16 {d0[2], d1[2]}, [r4]! @ encoding: [0xa4,0xf9,0xad,0x05] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[2], d2[2]}, [r4:16]! @ CHECK-ERRORS: ^ @ CHECK: vld2.16 {d0[2], d1[2]}, [r4:32]! @ encoding: [0xa4,0xf9,0xbd,0x05] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[2], d2[2]}, [r4:64]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[2], d2[2]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[2], d2[2]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -2326,17 +2326,17 @@ vld2.16 {d0[2], d2[2]}, [r4:256], r6 @ CHECK: vld2.16 {d0[2], d2[2]}, [r4], r6 @ encoding: [0xa4,0xf9,0xa6,0x05] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[2], d2[2]}, [r4:16], r6 @ CHECK-ERRORS: ^ @ CHECK: vld2.16 {d0[2], d2[2]}, [r4:32], r6 @ encoding: [0xa4,0xf9,0xb6,0x05] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[2], d2[2]}, [r4:64], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[2], d2[2]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[2], d2[2]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -2348,17 +2348,17 @@ vld2.16 {d0[], d1[]}, [r4:256] @ CHECK: vld2.16 {d0[], d1[]}, [r4] @ encoding: [0xa4,0xf9,0x4f,0x0d] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[], d1[]}, [r4:16] @ CHECK-ERRORS: ^ @ CHECK: vld2.16 {d0[], d1[]}, [r4:32] @ encoding: [0xa4,0xf9,0x5f,0x0d] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[], d1[]}, [r4:64] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[], d1[]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[], d1[]}, [r4:256] @ CHECK-ERRORS: ^ @@ -2370,17 +2370,17 @@ vld2.16 {d0[], d1[]}, [r4:256]! @ CHECK: vld2.16 {d0[], d1[]}, [r4]! @ encoding: [0xa4,0xf9,0x4d,0x0d] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[], d1[]}, [r4:16]! @ CHECK-ERRORS: ^ @ CHECK: vld2.16 {d0[], d1[]}, [r4:32]! @ encoding: [0xa4,0xf9,0x5d,0x0d] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[], d1[]}, [r4:64]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[], d1[]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[], d1[]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -2392,17 +2392,17 @@ vld2.16 {d0[], d1[]}, [r4:256], r6 @ CHECK: vld2.16 {d0[], d1[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x46,0x0d] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[], d1[]}, [r4:16], r6 @ CHECK-ERRORS: ^ @ CHECK: vld2.16 {d0[], d1[]}, [r4:32], r6 @ encoding: [0xa4,0xf9,0x56,0x0d] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[], d1[]}, [r4:64], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[], d1[]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[], d1[]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -2414,17 +2414,17 @@ vld2.16 {d0[], d2[]}, [r4:256] @ CHECK: vld2.16 {d0[], d2[]}, [r4] @ encoding: [0xa4,0xf9,0x6f,0x0d] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[], d2[]}, [r4:16] @ CHECK-ERRORS: ^ @ CHECK: vld2.16 {d0[], d2[]}, [r4:32] @ encoding: [0xa4,0xf9,0x7f,0x0d] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[], d2[]}, [r4:64] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[], d2[]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[], d2[]}, [r4:256] @ CHECK-ERRORS: ^ @@ -2436,17 +2436,17 @@ vld2.16 {d0[], d2[]}, [r4:256]! @ CHECK: vld2.16 {d0[], d2[]}, [r4]! @ encoding: [0xa4,0xf9,0x6d,0x0d] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[], d2[]}, [r4:16]! @ CHECK-ERRORS: ^ @ CHECK: vld2.16 {d0[], d2[]}, [r4:32]! @ encoding: [0xa4,0xf9,0x7d,0x0d] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[], d2[]}, [r4:64]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[], d2[]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[], d2[]}, [r4:256]! vld2.16 {d0[], d2[]}, [r4], r6 @@ -2457,17 +2457,17 @@ vld2.16 {d0[], d2[]}, [r4:256], r6 @ CHECK: vld2.16 {d0[], d2[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x66,0x0d] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[], d2[]}, [r4:16], r6 @ CHECK-ERRORS: ^ @ CHECK: vld2.16 {d0[], d2[]}, [r4:32], r6 @ encoding: [0xa4,0xf9,0x76,0x0d] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[], d2[]}, [r4:64], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[], d2[]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld2.16 {d0[], d2[]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -2479,15 +2479,15 @@ vld2.32 {d0, d1}, [r4:256] @ CHECK: vld2.32 {d0, d1}, [r4] @ encoding: [0x24,0xf9,0x8f,0x08] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.32 {d0, d1}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.32 {d0, d1}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld2.32 {d0, d1}, [r4:64] @ encoding: [0x24,0xf9,0x9f,0x08] @ CHECK: vld2.32 {d0, d1}, [r4:128] @ encoding: [0x24,0xf9,0xaf,0x08] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.32 {d0, d1}, [r4:256] @ CHECK-ERRORS: ^ @@ -2499,15 +2499,15 @@ vld2.32 {d0, d1}, [r4:256]! @ CHECK: vld2.32 {d0, d1}, [r4]! @ encoding: [0x24,0xf9,0x8d,0x08] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.32 {d0, d1}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.32 {d0, d1}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld2.32 {d0, d1}, [r4:64]! @ encoding: [0x24,0xf9,0x9d,0x08] @ CHECK: vld2.32 {d0, d1}, [r4:128]! @ encoding: [0x24,0xf9,0xad,0x08] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.32 {d0, d1}, [r4:256]! @ CHECK-ERRORS: ^ @@ -2519,15 +2519,15 @@ vld2.32 {d0, d1}, [r4:256], r6 @ CHECK: vld2.32 {d0, d1}, [r4], r6 @ encoding: [0x24,0xf9,0x86,0x08] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.32 {d0, d1}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.32 {d0, d1}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld2.32 {d0, d1}, [r4:64], r6 @ encoding: [0x24,0xf9,0x96,0x08] @ CHECK: vld2.32 {d0, d1}, [r4:128], r6 @ encoding: [0x24,0xf9,0xa6,0x08] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.32 {d0, d1}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -2539,15 +2539,15 @@ vld2.32 {d0, d2}, [r4:256] @ CHECK: vld2.32 {d0, d2}, [r4] @ encoding: [0x24,0xf9,0x8f,0x09] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.32 {d0, d2}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.32 {d0, d2}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld2.32 {d0, d2}, [r4:64] @ encoding: [0x24,0xf9,0x9f,0x09] @ CHECK: vld2.32 {d0, d2}, [r4:128] @ encoding: [0x24,0xf9,0xaf,0x09] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.32 {d0, d2}, [r4:256] @ CHECK-ERRORS: ^ @@ -2559,15 +2559,15 @@ vld2.32 {d0, d2}, [r4:256]! @ CHECK: vld2.32 {d0, d2}, [r4]! @ encoding: [0x24,0xf9,0x8d,0x09] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.32 {d0, d2}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.32 {d0, d2}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld2.32 {d0, d2}, [r4:64]! @ encoding: [0x24,0xf9,0x9d,0x09] @ CHECK: vld2.32 {d0, d2}, [r4:128]! @ encoding: [0x24,0xf9,0xad,0x09] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.32 {d0, d2}, [r4:256]! @ CHECK-ERRORS: ^ @@ -2579,15 +2579,15 @@ vld2.32 {d0, d2}, [r4:256], r6 @ CHECK: vld2.32 {d0, d2}, [r4], r6 @ encoding: [0x24,0xf9,0x86,0x09] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.32 {d0, d2}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.32 {d0, d2}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld2.32 {d0, d2}, [r4:64], r6 @ encoding: [0x24,0xf9,0x96,0x09] @ CHECK: vld2.32 {d0, d2}, [r4:128], r6 @ encoding: [0x24,0xf9,0xa6,0x09] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld2.32 {d0, d2}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -2599,10 +2599,10 @@ vld2.32 {d0, d1, d2, d3}, [r4:256] @ CHECK: vld2.32 {d0, d1, d2, d3}, [r4] @ encoding: [0x24,0xf9,0x8f,0x03] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld2.32 {d0, d1, d2, d3}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld2.32 {d0, d1, d2, d3}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld2.32 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x24,0xf9,0x9f,0x03] @@ -2617,10 +2617,10 @@ vld2.32 {d0, d1, d2, d3}, [r4:256]! @ CHECK: vld2.32 {d0, d1, d2, d3}, [r4]! @ encoding: [0x24,0xf9,0x8d,0x03] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld2.32 {d0, d1, d2, d3}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld2.32 {d0, d1, d2, d3}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld2.32 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x24,0xf9,0x9d,0x03] @@ -2635,10 +2635,10 @@ vld2.32 {d0, d1, d2, d3}, [r4:256], r6 @ CHECK: vld2.32 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x24,0xf9,0x86,0x03] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld2.32 {d0, d1, d2, d3}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld2.32 {d0, d1, d2, d3}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld2.32 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x24,0xf9,0x96,0x03] @@ -2653,17 +2653,17 @@ vld2.32 {d0[1], d1[1]}, [r4:256] @ CHECK: vld2.32 {d0[1], d1[1]}, [r4] @ encoding: [0xa4,0xf9,0x8f,0x09] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[1], d1[1]}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[1], d1[1]}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld2.32 {d0[1], d1[1]}, [r4:64] @ encoding: [0xa4,0xf9,0x9f,0x09] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[1], d1[1]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[1], d1[1]}, [r4:256] @ CHECK-ERRORS: ^ @@ -2675,17 +2675,17 @@ vld2.32 {d0[1], d1[1]}, [r4:256]! @ CHECK: vld2.32 {d0[1], d1[1]}, [r4]! @ encoding: [0xa4,0xf9,0x8d,0x09] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[1], d1[1]}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[1], d1[1]}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld2.32 {d0[1], d1[1]}, [r4:64]! @ encoding: [0xa4,0xf9,0x9d,0x09] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[1], d1[1]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[1], d1[1]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -2697,17 +2697,17 @@ vld2.32 {d0[1], d1[1]}, [r4:256], r6 @ CHECK: vld2.32 {d0[1], d1[1]}, [r4], r6 @ encoding: [0xa4,0xf9,0x86,0x09] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[1], d1[1]}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[1], d1[1]}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld2.32 {d0[1], d1[1]}, [r4:64], r6 @ encoding: [0xa4,0xf9,0x96,0x09] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[1], d1[1]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[1], d1[1]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -2719,17 +2719,17 @@ vld2.32 {d0[1], d2[1]}, [r4:256] @ CHECK: vld2.32 {d0[1], d2[1]}, [r4] @ encoding: [0xa4,0xf9,0xcf,0x09] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[1], d2[1]}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[1], d2[1]}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld2.32 {d0[1], d2[1]}, [r4:64] @ encoding: [0xa4,0xf9,0xdf,0x09] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[1], d2[1]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[1], d2[1]}, [r4:256] @ CHECK-ERRORS: ^ @@ -2741,17 +2741,17 @@ vld2.32 {d0[1], d2[1]}, [r4:256]! @ CHECK: vld2.32 {d0[1], d2[1]}, [r4]! @ encoding: [0xa4,0xf9,0xcd,0x09] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[1], d2[1]}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[1], d2[1]}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld2.32 {d0[1], d2[1]}, [r4:64]! @ encoding: [0xa4,0xf9,0xdd,0x09] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[1], d2[1]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[1], d2[1]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -2763,17 +2763,17 @@ vld2.32 {d0[1], d2[1]}, [r4:256], r6 @ CHECK: vld2.32 {d0[1], d2[1]}, [r4], r6 @ encoding: [0xa4,0xf9,0xc6,0x09] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[1], d2[1]}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[1], d2[1]}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld2.32 {d0[1], d2[1]}, [r4:64], r6 @ encoding: [0xa4,0xf9,0xd6,0x09] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[1], d2[1]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[1], d2[1]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -2785,17 +2785,17 @@ vld2.32 {d0[], d1[]}, [r4:256] @ CHECK: vld2.32 {d0[], d1[]}, [r4] @ encoding: [0xa4,0xf9,0x8f,0x0d] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[], d1[]}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[], d1[]}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld2.32 {d0[], d1[]}, [r4:64] @ encoding: [0xa4,0xf9,0x9f,0x0d] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[], d1[]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[], d1[]}, [r4:256] @ CHECK-ERRORS: ^ @@ -2807,17 +2807,17 @@ vld2.32 {d0[], d1[]}, [r4:256]! @ CHECK: vld2.32 {d0[], d1[]}, [r4]! @ encoding: [0xa4,0xf9,0x8d,0x0d] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[], d1[]}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[], d1[]}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld2.32 {d0[], d1[]}, [r4:64]! @ encoding: [0xa4,0xf9,0x9d,0x0d] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[], d1[]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[], d1[]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -2829,17 +2829,17 @@ vld2.32 {d0[], d1[]}, [r4:256], r6 @ CHECK: vld2.32 {d0[], d1[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x86,0x0d] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[], d1[]}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[], d1[]}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld2.32 {d0[], d1[]}, [r4:64], r6 @ encoding: [0xa4,0xf9,0x96,0x0d] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[], d1[]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[], d1[]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -2851,17 +2851,17 @@ vld2.32 {d0[], d2[]}, [r4:256] @ CHECK: vld2.32 {d0[], d2[]}, [r4] @ encoding: [0xa4,0xf9,0xaf,0x0d] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[], d2[]}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[], d2[]}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld2.32 {d0[], d2[]}, [r4:64] @ encoding: [0xa4,0xf9,0xbf,0x0d] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[], d2[]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[], d2[]}, [r4:256] @ CHECK-ERRORS: ^ @@ -2873,17 +2873,17 @@ vld2.32 {d0[], d2[]}, [r4:256]! @ CHECK: vld2.32 {d0[], d2[]}, [r4]! @ encoding: [0xa4,0xf9,0xad,0x0d] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[], d2[]}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[], d2[]}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld2.32 {d0[], d2[]}, [r4:64]! @ encoding: [0xa4,0xf9,0xbd,0x0d] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[], d2[]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[], d2[]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -2895,17 +2895,17 @@ vld2.32 {d0[], d2[]}, [r4:256], r6 @ CHECK: vld2.32 {d0[], d2[]}, [r4], r6 @ encoding: [0xa4,0xf9,0xa6,0x0d] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[], d2[]}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[], d2[]}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld2.32 {d0[], d2[]}, [r4:64], r6 @ encoding: [0xa4,0xf9,0xb6,0x0d] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[], d2[]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld2.32 {d0[], d2[]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -2917,17 +2917,17 @@ vld3.8 {d0, d1, d2}, [r4:256] @ CHECK: vld3.8 {d0, d1, d2}, [r4] @ encoding: [0x24,0xf9,0x0f,0x04] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.8 {d0, d1, d2}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.8 {d0, d1, d2}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld3.8 {d0, d1, d2}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x04] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.8 {d0, d1, d2}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.8 {d0, d1, d2}, [r4:256] @ CHECK-ERRORS: ^ @@ -2939,17 +2939,17 @@ vld3.8 {d0, d1, d2}, [r4:256]! @ CHECK: vld3.8 {d0, d1, d2}, [r4]! @ encoding: [0x24,0xf9,0x0d,0x04] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.8 {d0, d1, d2}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.8 {d0, d1, d2}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld3.8 {d0, d1, d2}, [r4:64]! @ encoding: [0x24,0xf9,0x1d,0x04] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.8 {d0, d1, d2}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.8 {d0, d1, d2}, [r4:256]! @ CHECK-ERRORS: ^ @@ -2961,17 +2961,17 @@ vld3.8 {d0, d1, d2}, [r4:256], r6 @ CHECK: vld3.8 {d0, d1, d2}, [r4], r6 @ encoding: [0x24,0xf9,0x06,0x04] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.8 {d0, d1, d2}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.8 {d0, d1, d2}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld3.8 {d0, d1, d2}, [r4:64], r6 @ encoding: [0x24,0xf9,0x16,0x04] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.8 {d0, d1, d2}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.8 {d0, d1, d2}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -2983,17 +2983,17 @@ vld3.8 {d0, d2, d4}, [r4:256] @ CHECK: vld3.8 {d0, d2, d4}, [r4] @ encoding: [0x24,0xf9,0x0f,0x05] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.8 {d0, d2, d4}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.8 {d0, d2, d4}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld3.8 {d0, d2, d4}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x05] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.8 {d0, d2, d4}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.8 {d0, d2, d4}, [r4:256] @ CHECK-ERRORS: ^ @@ -3005,17 +3005,17 @@ vld3.8 {d0, d2, d4}, [r4:256]! @ CHECK: vld3.8 {d0, d2, d4}, [r4]! @ encoding: [0x24,0xf9,0x0d,0x05] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.8 {d0, d2, d4}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.8 {d0, d2, d4}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld3.8 {d0, d2, d4}, [r4:64]! @ encoding: [0x24,0xf9,0x1d,0x05] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.8 {d0, d2, d4}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.8 {d0, d2, d4}, [r4:256]! @ CHECK-ERRORS: ^ @@ -3027,17 +3027,17 @@ vld3.8 {d0, d2, d4}, [r4:256], r6 @ CHECK: vld3.8 {d0, d2, d4}, [r4], r6 @ encoding: [0x24,0xf9,0x06,0x05] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.8 {d0, d2, d4}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.8 {d0, d2, d4}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld3.8 {d0, d2, d4}, [r4:64], r6 @ encoding: [0x24,0xf9,0x16,0x05] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.8 {d0, d2, d4}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.8 {d0, d2, d4}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -3049,19 +3049,19 @@ vld3.8 {d0[1], d1[1], d2[1]}, [r4:256] @ CHECK: vld3.8 {d0[1], d1[1], d2[1]}, [r4] @ encoding: [0xa4,0xf9,0x2f,0x02] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.8 {d0[1], d1[1], d2[1]}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.8 {d0[1], d1[1], d2[1]}, [r4:32] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.8 {d0[1], d1[1], d2[1]}, [r4:64] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.8 {d0[1], d1[1], d2[1]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.8 {d0[1], d1[1], d2[1]}, [r4:256] @ CHECK-ERRORS: ^ @@ -3073,19 +3073,19 @@ vld3.8 {d0[1], d1[1], d2[1]}, [r4:256]! @ CHECK: vld3.8 {d0[1], d1[1], d2[1]}, [r4]! @ encoding: [0xa4,0xf9,0x2d,0x02] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.8 {d0[1], d1[1], d2[1]}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.8 {d0[1], d1[1], d2[1]}, [r4:32]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.8 {d0[1], d1[1], d2[1]}, [r4:64]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.8 {d0[1], d1[1], d2[1]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.8 {d0[1], d1[1], d2[1]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -3097,19 +3097,19 @@ vld3.8 {d0[1], d1[1], d2[1]}, [r4:256], r6 @ CHECK: vld3.8 {d0[1], d1[1], d2[1]}, [r4], r6 @ encoding: [0xa4,0xf9,0x26,0x02] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.8 {d0[1], d1[1], d2[1]}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.8 {d0[1], d1[1], d2[1]}, [r4:32], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.8 {d0[1], d1[1], d2[1]}, [r4:64], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.8 {d0[1], d1[1], d2[1]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.8 {d0[1], d1[1], d2[1]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -3121,19 +3121,19 @@ vld3.8 {d0[], d1[], d2[]}, [r4:256] @ CHECK: vld3.8 {d0[], d1[], d2[]}, [r4] @ encoding: [0xa4,0xf9,0x0f,0x0e] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.8 {d0[], d1[], d2[]}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.8 {d0[], d1[], d2[]}, [r4:32] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.8 {d0[], d1[], d2[]}, [r4:64] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.8 {d0[], d1[], d2[]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.8 {d0[], d1[], d2[]}, [r4:256] @ CHECK-ERRORS: ^ @@ -3145,19 +3145,19 @@ vld3.8 {d0[], d1[], d2[]}, [r4:256]! @ CHECK: vld3.8 {d0[], d1[], d2[]}, [r4]! @ encoding: [0xa4,0xf9,0x0d,0x0e] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.8 {d0[], d1[], d2[]}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.8 {d0[], d1[], d2[]}, [r4:32]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.8 {d0[], d1[], d2[]}, [r4:64]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.8 {d0[], d1[], d2[]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.8 {d0[], d1[], d2[]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -3169,19 +3169,19 @@ vld3.8 {d0[], d1[], d2[]}, [r4:256], r6 @ CHECK: vld3.8 {d0[], d1[], d2[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x06,0x0e] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.8 {d0[], d1[], d2[]}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.8 {d0[], d1[], d2[]}, [r4:32], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.8 {d0[], d1[], d2[]}, [r4:64], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.8 {d0[], d1[], d2[]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.8 {d0[], d1[], d2[]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -3193,19 +3193,19 @@ vld3.8 {d0[], d2[], d4[]}, [r4:256] @ CHECK: vld3.8 {d0[], d2[], d4[]}, [r4] @ encoding: [0xa4,0xf9,0x2f,0x0e] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.8 {d0[], d2[], d4[]}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.8 {d0[], d2[], d4[]}, [r4:32] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.8 {d0[], d2[], d4[]}, [r4:64] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.8 {d0[], d2[], d4[]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.8 {d0[], d2[], d4[]}, [r4:256] @ CHECK-ERRORS: ^ @@ -3217,19 +3217,19 @@ vld3.8 {d0[], d2[], d4[]}, [r4:256]! @ CHECK: vld3.8 {d0[], d1[], d2[]}, [r4]! @ encoding: [0xa4,0xf9,0x2d,0x0e] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.8 {d0[], d2[], d4[]}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.8 {d0[], d2[], d4[]}, [r4:32]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.8 {d0[], d2[], d4[]}, [r4:64]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.8 {d0[], d2[], d4[]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.8 {d0[], d2[], d4[]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -3241,19 +3241,19 @@ vld3.8 {d0[], d2[], d4[]}, [r4:256], r6 @ CHECK: vld3.8 {d0[], d2[], d4[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x26,0x0e] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.8 {d0[], d2[], d4[]}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.8 {d0[], d2[], d4[]}, [r4:32], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.8 {d0[], d2[], d4[]}, [r4:64], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.8 {d0[], d2[], d4[]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.8 {d0[], d2[], d4[]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -3265,17 +3265,17 @@ vld3.16 {d0, d1, d2}, [r4:256] @ CHECK: vld3.16 {d0, d1, d2}, [r4] @ encoding: [0x24,0xf9,0x4f,0x04] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.16 {d0, d1, d2}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.16 {d0, d1, d2}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld3.16 {d0, d1, d2}, [r4:64] @ encoding: [0x24,0xf9,0x5f,0x04] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.16 {d0, d1, d2}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.16 {d0, d1, d2}, [r4:256] @ CHECK-ERRORS: ^ @@ -3287,17 +3287,17 @@ vld3.16 {d0, d1, d2}, [r4:256]! @ CHECK: vld3.16 {d0, d1, d2}, [r4]! @ encoding: [0x24,0xf9,0x4d,0x04] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.16 {d0, d1, d2}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.16 {d0, d1, d2}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld3.16 {d0, d1, d2}, [r4:64]! @ encoding: [0x24,0xf9,0x5d,0x04] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.16 {d0, d1, d2}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.16 {d0, d1, d2}, [r4:256]! @ CHECK-ERRORS: ^ @@ -3309,17 +3309,17 @@ vld3.16 {d0, d1, d2}, [r4:256], r6 @ CHECK: vld3.16 {d0, d1, d2}, [r4], r6 @ encoding: [0x24,0xf9,0x46,0x04] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.16 {d0, d1, d2}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.16 {d0, d1, d2}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld3.16 {d0, d1, d2}, [r4:64], r6 @ encoding: [0x24,0xf9,0x56,0x04] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.16 {d0, d1, d2}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.16 {d0, d1, d2}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -3331,17 +3331,17 @@ vld3.16 {d0, d2, d4}, [r4:256] @ CHECK: vld3.16 {d0, d2, d4}, [r4] @ encoding: [0x24,0xf9,0x4f,0x05] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.16 {d0, d2, d4}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.16 {d0, d2, d4}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld3.16 {d0, d2, d4}, [r4:64] @ encoding: [0x24,0xf9,0x5f,0x05] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.16 {d0, d2, d4}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.16 {d0, d2, d4}, [r4:256] @ CHECK-ERRORS: ^ @@ -3353,17 +3353,17 @@ vld3.16 {d0, d2, d4}, [r4:256]! @ CHECK: vld3.16 {d0, d2, d4}, [r4]! @ encoding: [0x24,0xf9,0x4d,0x05] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.16 {d0, d2, d4}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.16 {d0, d2, d4}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld3.16 {d0, d2, d4}, [r4:64]! @ encoding: [0x24,0xf9,0x5d,0x05] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.16 {d0, d2, d4}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.16 {d0, d2, d4}, [r4:256]! @ CHECK-ERRORS: ^ @@ -3375,17 +3375,17 @@ vld3.16 {d0, d2, d4}, [r4:256], r6 @ CHECK: vld3.16 {d0, d2, d4}, [r4], r6 @ encoding: [0x24,0xf9,0x46,0x05] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.16 {d0, d2, d4}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.16 {d0, d2, d4}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld3.16 {d0, d2, d4}, [r4:64], r6 @ encoding: [0x24,0xf9,0x56,0x05] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.16 {d0, d2, d4}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.16 {d0, d2, d4}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -3397,19 +3397,19 @@ vld3.16 {d0[1], d1[1], d2[1]}, [r4:256] @ CHECK: vld3.16 {d0[1], d1[1], d2[1]}, [r4] @ encoding: [0xa4,0xf9,0x4f,0x06] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[1], d1[1], d2[1]}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[1], d1[1], d2[1]}, [r4:32] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[1], d1[1], d2[1]}, [r4:64] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[1], d1[1], d2[1]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[1], d1[1], d2[1]}, [r4:256] @ CHECK-ERRORS: ^ @@ -3421,19 +3421,19 @@ vld3.16 {d0[1], d1[1], d2[1]}, [r4:256]! @ CHECK: vld3.16 {d0[1], d1[1], d2[1]}, [r4]! @ encoding: [0xa4,0xf9,0x4d,0x06] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[1], d1[1], d2[1]}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[1], d1[1], d2[1]}, [r4:32]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[1], d1[1], d2[1]}, [r4:64]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[1], d1[1], d2[1]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[1], d1[1], d2[1]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -3445,19 +3445,19 @@ vld3.16 {d0[1], d1[1], d2[1]}, [r4:256], r6 @ CHECK: vld3.16 {d0[1], d1[1], d2[1]}, [r4], r6 @ encoding: [0xa4,0xf9,0x46,0x06] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[1], d1[1], d2[1]}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[1], d1[1], d2[1]}, [r4:32], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[1], d1[1], d2[1]}, [r4:64], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[1], d1[1], d2[1]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[1], d1[1], d2[1]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -3469,19 +3469,19 @@ vld3.16 {d0[1], d2[1], d4[1]}, [r4:256] @ CHECK: vld3.16 {d0[1], d2[1], d4[1]}, [r4] @ encoding: [0xa4,0xf9,0x6f,0x06] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[1], d2[1], d4[1]}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[1], d2[1], d4[1]}, [r4:32] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[1], d2[1], d4[1]}, [r4:64] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[1], d2[1], d4[1]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[1], d2[1], d4[1]}, [r4:256] @ CHECK-ERRORS: ^ @@ -3493,19 +3493,19 @@ vld3.16 {d0[1], d2[1], d4[1]}, [r4:256]! @ CHECK: vld3.16 {d0[1], d1[1], d2[1]}, [r4]! @ encoding: [0xa4,0xf9,0x6d,0x06] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[1], d2[1], d4[1]}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[1], d2[1], d4[1]}, [r4:32]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[1], d2[1], d4[1]}, [r4:64]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[1], d2[1], d4[1]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[1], d2[1], d4[1]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -3517,19 +3517,19 @@ vld3.16 {d0[1], d2[1], d4[1]}, [r4:256], r6 @ CHECK: vld3.16 {d0[1], d2[1], d4[1]}, [r4], r6 @ encoding: [0xa4,0xf9,0x66,0x06] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[1], d2[1], d4[1]}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[1], d2[1], d4[1]}, [r4:32], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[1], d2[1], d4[1]}, [r4:64], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[1], d2[1], d4[1]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[1], d2[1], d4[1]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -3541,19 +3541,19 @@ vld3.16 {d0[], d1[], d2[]}, [r4:256] @ CHECK: vld3.16 {d0[], d1[], d2[]}, [r4] @ encoding: [0xa4,0xf9,0x4f,0x0e] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[], d1[], d2[]}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[], d1[], d2[]}, [r4:32] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[], d1[], d2[]}, [r4:64] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[], d1[], d2[]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[], d1[], d2[]}, [r4:256] @ CHECK-ERRORS: ^ @@ -3565,19 +3565,19 @@ vld3.16 {d0[], d1[], d2[]}, [r4:256]! @ CHECK: vld3.16 {d0[], d1[], d2[]}, [r4]! @ encoding: [0xa4,0xf9,0x4d,0x0e] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[], d1[], d2[]}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[], d1[], d2[]}, [r4:32]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[], d1[], d2[]}, [r4:64]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[], d1[], d2[]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[], d1[], d2[]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -3589,19 +3589,19 @@ vld3.16 {d0[], d1[], d2[]}, [r4:256], r6 @ CHECK: vld3.16 {d0[], d1[], d2[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x46,0x0e] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[], d1[], d2[]}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[], d1[], d2[]}, [r4:32], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[], d1[], d2[]}, [r4:64], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[], d1[], d2[]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[], d1[], d2[]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -3613,19 +3613,19 @@ vld3.16 {d0[], d2[], d4[]}, [r4:256] @ CHECK: vld3.16 {d0[], d2[], d4[]}, [r4] @ encoding: [0xa4,0xf9,0x6f,0x0e] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[], d2[], d4[]}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[], d2[], d4[]}, [r4:32] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[], d2[], d4[]}, [r4:64] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[], d2[], d4[]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[], d2[], d4[]}, [r4:256] @ CHECK-ERRORS: ^ @@ -3637,19 +3637,19 @@ vld3.16 {d0[], d2[], d4[]}, [r4:256]! @ CHECK: vld3.16 {d0[], d2[], d4[]}, [r4]! @ encoding: [0xa4,0xf9,0x6d,0x0e] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[], d2[], d4[]}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[], d2[], d4[]}, [r4:32]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[], d2[], d4[]}, [r4:64]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[], d2[], d4[]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[], d2[], d4[]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -3661,19 +3661,19 @@ vld3.16 {d0[], d2[], d4[]}, [r4:256], r6 @ CHECK: vld3.16 {d0[], d2[], d4[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x66,0x0e] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[], d2[], d4[]}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[], d2[], d4[]}, [r4:32], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[], d2[], d4[]}, [r4:64], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[], d2[], d4[]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.16 {d0[], d2[], d4[]}, [r4:256], r6 vld3.32 {d0, d1, d2}, [r4] @@ -3684,17 +3684,17 @@ vld3.32 {d0, d1, d2}, [r4:256] @ CHECK: vld3.32 {d0, d1, d2}, [r4] @ encoding: [0x24,0xf9,0x8f,0x04] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.32 {d0, d1, d2}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.32 {d0, d1, d2}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld3.32 {d0, d1, d2}, [r4:64] @ encoding: [0x24,0xf9,0x9f,0x04] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.32 {d0, d1, d2}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.32 {d0, d1, d2}, [r4:256] @ CHECK-ERRORS: ^ @@ -3706,17 +3706,17 @@ vld3.32 {d0, d1, d2}, [r4:256]! @ CHECK: vld3.32 {d0, d1, d2}, [r4]! @ encoding: [0x24,0xf9,0x8d,0x04] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.32 {d0, d1, d2}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.32 {d0, d1, d2}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld3.32 {d0, d1, d2}, [r4:64]! @ encoding: [0x24,0xf9,0x9d,0x04] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.32 {d0, d1, d2}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.32 {d0, d1, d2}, [r4:256]! @ CHECK-ERRORS: ^ @@ -3728,17 +3728,17 @@ vld3.32 {d0, d1, d2}, [r4:256], r6 @ CHECK: vld3.32 {d0, d1, d2}, [r4], r6 @ encoding: [0x24,0xf9,0x86,0x04] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.32 {d0, d1, d2}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.32 {d0, d1, d2}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld3.32 {d0, d1, d2}, [r4:64], r6 @ encoding: [0x24,0xf9,0x96,0x04] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.32 {d0, d1, d2}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.32 {d0, d1, d2}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -3750,17 +3750,17 @@ vld3.32 {d0, d2, d4}, [r4:256] @ CHECK: vld3.32 {d0, d2, d4}, [r4] @ encoding: [0x24,0xf9,0x8f,0x05] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.32 {d0, d2, d4}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.32 {d0, d2, d4}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld3.32 {d0, d2, d4}, [r4:64] @ encoding: [0x24,0xf9,0x9f,0x05] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.32 {d0, d2, d4}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.32 {d0, d2, d4}, [r4:256] @ CHECK-ERRORS: ^ @@ -3772,17 +3772,17 @@ vld3.32 {d0, d2, d4}, [r4:256]! @ CHECK: vld3.32 {d0, d2, d4}, [r4]! @ encoding: [0x24,0xf9,0x8d,0x05] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.32 {d0, d2, d4}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.32 {d0, d2, d4}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld3.32 {d0, d2, d4}, [r4:64]! @ encoding: [0x24,0xf9,0x9d,0x05] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.32 {d0, d2, d4}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.32 {d0, d2, d4}, [r4:256]! @ CHECK-ERRORS: ^ @@ -3794,17 +3794,17 @@ vld3.32 {d0, d2, d4}, [r4:256], r6 @ CHECK: vld3.32 {d0, d2, d4}, [r4], r6 @ encoding: [0x24,0xf9,0x86,0x05] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.32 {d0, d2, d4}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.32 {d0, d2, d4}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld3.32 {d0, d2, d4}, [r4:64], r6 @ encoding: [0x24,0xf9,0x96,0x05] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.32 {d0, d2, d4}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld3.32 {d0, d2, d4}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -3816,19 +3816,19 @@ vld3.32 {d0[1], d1[1], d2[1]}, [r4:256] @ CHECK: vld3.32 {d0[1], d1[1], d2[1]}, [r4] @ encoding: [0xa4,0xf9,0x8f,0x0a] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[1], d1[1], d2[1]}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[1], d1[1], d2[1]}, [r4:32] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[1], d1[1], d2[1]}, [r4:64] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[1], d1[1], d2[1]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[1], d1[1], d2[1]}, [r4:256] @ CHECK-ERRORS: ^ @@ -3840,19 +3840,19 @@ vld3.32 {d0[1], d1[1], d2[1]}, [r4:256]! @ CHECK: vld3.32 {d0[1], d1[1], d2[1]}, [r4]! @ encoding: [0xa4,0xf9,0x8d,0x0a] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[1], d1[1], d2[1]}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[1], d1[1], d2[1]}, [r4:32]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[1], d1[1], d2[1]}, [r4:64]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[1], d1[1], d2[1]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[1], d1[1], d2[1]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -3864,19 +3864,19 @@ vld3.32 {d0[1], d1[1], d2[1]}, [r4:256], r6 @ CHECK: vld3.32 {d0[1], d1[1], d2[1]}, [r4], r6 @ encoding: [0xa4,0xf9,0x86,0x0a] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[1], d1[1], d2[1]}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[1], d1[1], d2[1]}, [r4:32], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[1], d1[1], d2[1]}, [r4:64], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[1], d1[1], d2[1]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[1], d1[1], d2[1]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -3888,19 +3888,19 @@ vld3.32 {d0[1], d2[1], d4[1]}, [r4:256] @ CHECK: vld3.32 {d0[1], d2[1], d4[1]}, [r4] @ encoding: [0xa4,0xf9,0xcf,0x0a] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[1], d2[1], d4[1]}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[1], d2[1], d4[1]}, [r4:32] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[1], d2[1], d4[1]}, [r4:64] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[1], d2[1], d4[1]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[1], d2[1], d4[1]}, [r4:256] @ CHECK-ERRORS: ^ @@ -3912,19 +3912,19 @@ vld3.32 {d0[1], d2[1], d4[1]}, [r4:256]! @ CHECK: vld3.32 {d0[1], d2[1], d4[1]}, [r4]! @ encoding: [0xa4,0xf9,0xcd,0x0a] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[1], d2[1], d4[1]}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[1], d2[1], d4[1]}, [r4:32]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[1], d2[1], d4[1]}, [r4:64]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[1], d2[1], d4[1]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[1], d2[1], d4[1]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -3936,19 +3936,19 @@ vld3.32 {d0[1], d2[1], d4[1]}, [r4:256], r6 @ CHECK: vld3.32 {d0[1], d2[1], d4[1]}, [r4], r6 @ encoding: [0xa4,0xf9,0xc6,0x0a] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[1], d2[1], d4[1]}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[1], d2[1], d4[1]}, [r4:32], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[1], d2[1], d4[1]}, [r4:64], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[1], d2[1], d4[1]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[1], d2[1], d4[1]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -3960,19 +3960,19 @@ vld3.32 {d0[], d1[], d2[]}, [r4:256] @ CHECK: vld3.32 {d0[], d1[], d2[]}, [r4] @ encoding: [0xa4,0xf9,0x8f,0x0e] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[], d1[], d2[]}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[], d1[], d2[]}, [r4:32] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[], d1[], d2[]}, [r4:64] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[], d1[], d2[]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[], d1[], d2[]}, [r4:256] @ CHECK-ERRORS: ^ @@ -3984,19 +3984,19 @@ vld3.32 {d0[], d1[], d2[]}, [r4:256]! @ CHECK: vld3.32 {d0[], d1[], d2[]}, [r4]! @ encoding: [0xa4,0xf9,0x8d,0x0e] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[], d1[], d2[]}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[], d1[], d2[]}, [r4:32]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[], d1[], d2[]}, [r4:64]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[], d1[], d2[]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[], d1[], d2[]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -4008,19 +4008,19 @@ vld3.32 {d0[], d1[], d2[]}, [r4:256], r6 @ CHECK: vld3.32 {d0[], d1[], d2[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x86,0x0e] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[], d1[], d2[]}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[], d1[], d2[]}, [r4:32], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[], d1[], d2[]}, [r4:64], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[], d1[], d2[]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[], d1[], d2[]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -4032,19 +4032,19 @@ vld3.32 {d0[], d2[], d4[]}, [r4:256] @ CHECK: vld3.32 {d0[], d2[], d4[]}, [r4] @ encoding: [0xa4,0xf9,0xaf,0x0e] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[], d2[], d4[]}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[], d2[], d4[]}, [r4:32] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[], d2[], d4[]}, [r4:64] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[], d2[], d4[]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[], d2[], d4[]}, [r4:256] @ CHECK-ERRORS: ^ @@ -4056,19 +4056,19 @@ vld3.32 {d0[], d2[], d4[]}, [r4:256]! @ CHECK: vld3.32 {d0[], d2[], d4[]}, [r4]! @ encoding: [0xa4,0xf9,0xad,0x0e] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[], d2[], d4[]}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[], d2[], d4[]}, [r4:32]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[], d2[], d4[]}, [r4:64]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[], d2[], d4[]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[], d2[], d4[]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -4080,19 +4080,19 @@ vld3.32 {d0[], d2[], d4[]}, [r4:256], r6 @ CHECK: vld3.32 {d0[], d2[], d4[]}, [r4], r6 @ encoding: [0xa4,0xf9,0xa6,0x0e] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[], d2[], d4[]}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[], d2[], d4[]}, [r4:32], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[], d2[], d4[]}, [r4:64], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[], d2[], d4[]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vld3.32 {d0[], d2[], d4[]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -4104,10 +4104,10 @@ vld4.8 {d0, d1, d2, d3}, [r4:256] @ CHECK: vld4.8 {d0, d1, d2, d3}, [r4] @ encoding: [0x24,0xf9,0x0f,0x00] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld4.8 {d0, d1, d2, d3}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld4.8 {d0, d1, d2, d3}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld4.8 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x00] @@ -4122,10 +4122,10 @@ vld4.8 {d0, d1, d2, d3}, [r4:256]! @ CHECK: vld4.8 {d0, d1, d2, d3}, [r4]! @ encoding: [0x24,0xf9,0x0d,0x00] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld4.8 {d0, d1, d2, d3}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld4.8 {d0, d1, d2, d3}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld4.8 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x24,0xf9,0x1d,0x00] @@ -4140,10 +4140,10 @@ vld4.8 {d0, d1, d2, d3}, [r4:256], r6 @ CHECK: vld4.8 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x24,0xf9,0x06,0x00] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld4.8 {d0, d1, d2, d3}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld4.8 {d0, d1, d2, d3}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld4.8 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x24,0xf9,0x16,0x00] @@ -4158,10 +4158,10 @@ vld4.8 {d0, d2, d4, d6}, [r4:256] @ CHECK: vld4.8 {d0, d2, d4, d6}, [r4] @ encoding: [0x24,0xf9,0x0f,0x01] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld4.8 {d0, d2, d4, d6}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld4.8 {d0, d2, d4, d6}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld4.8 {d0, d2, d4, d6}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x01] @@ -4176,10 +4176,10 @@ vld4.8 {d0, d2, d4, d6}, [r4:256]! @ CHECK: vld4.8 {d0, d2, d4, d6}, [r4]! @ encoding: [0x24,0xf9,0x0d,0x01] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld4.8 {d0, d2, d4, d6}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld4.8 {d0, d2, d4, d6}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld4.8 {d0, d2, d4, d6}, [r4:64]! @ encoding: [0x24,0xf9,0x1d,0x01] @@ -4194,10 +4194,10 @@ vld4.8 {d0, d2, d4, d6}, [r4:256], r6 @ CHECK: vld4.8 {d0, d2, d4, d6}, [r4], r6 @ encoding: [0x24,0xf9,0x06,0x01] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld4.8 {d0, d2, d4, d6}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld4.8 {d0, d2, d4, d6}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld4.8 {d0, d2, d4, d6}, [r4:64], r6 @ encoding: [0x24,0xf9,0x16,0x01] @@ -4212,17 +4212,17 @@ vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:256] @ CHECK: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4] @ encoding: [0xa4,0xf9,0x2f,0x03] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:16] @ CHECK-ERRORS: ^ @ CHECK: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32] @ encoding: [0xa4,0xf9,0x3f,0x03] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:64] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:256] @ CHECK-ERRORS: ^ @@ -4234,17 +4234,17 @@ vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]! @ CHECK: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4]! @ encoding: [0xa4,0xf9,0x2d,0x03] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:16]! @ CHECK-ERRORS: ^ @ CHECK: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]! @ encoding: [0xa4,0xf9,0x3d,0x03] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -4256,17 +4256,17 @@ vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:256], r6 @ CHECK: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6 @ encoding: [0xa4,0xf9,0x26,0x03] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:16], r6 @ CHECK-ERRORS: ^ @ CHECK: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32], r6 @ encoding: [0xa4,0xf9,0x36,0x03] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -4278,17 +4278,17 @@ vld4.8 {d0[], d1[], d2[], d3[]}, [r4:256] @ CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4] @ encoding: [0xa4,0xf9,0x0f,0x0f] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:16] @ CHECK-ERRORS: ^ @ CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:32] @ encoding: [0xa4,0xf9,0x1f,0x0f] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:64] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:256] @ CHECK-ERRORS: ^ @@ -4300,17 +4300,17 @@ vld4.8 {d0[], d1[], d2[], d3[]}, [r4:256]! @ CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4]! @ encoding: [0xa4,0xf9,0x0d,0x0f] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:16]! @ CHECK-ERRORS: ^ @ CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:32]! @ encoding: [0xa4,0xf9,0x1d,0x0f] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:64]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -4322,17 +4322,17 @@ vld4.8 {d0[], d1[], d2[], d3[]}, [r4:256], r6 @ CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x06,0x0f] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:16], r6 @ CHECK-ERRORS: ^ @ CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:32], r6 @ encoding: [0xa4,0xf9,0x16,0x0f] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:64], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -4344,17 +4344,17 @@ vld4.8 {d0[], d2[], d4[], d6[]}, [r4:256] @ CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4] @ encoding: [0xa4,0xf9,0x2f,0x0f] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:16] @ CHECK-ERRORS: ^ @ CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32] @ encoding: [0xa4,0xf9,0x3f,0x0f] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:64] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:256] @ CHECK-ERRORS: ^ @@ -4366,17 +4366,17 @@ vld4.8 {d0[], d2[], d4[], d6[]}, [r4:256]! @ CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4]! @ encoding: [0xa4,0xf9,0x2d,0x0f] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:16]! @ CHECK-ERRORS: ^ @ CHECK: vld4.8 {d0[], d1[], d2[], d3[]}, [r4:32]! @ encoding: [0xa4,0xf9,0x3d,0x0f] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:64]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -4388,17 +4388,17 @@ vld4.8 {d0[], d2[], d4[], d6[]}, [r4:256], r6 @ CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x26,0x0f] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:16], r6 @ CHECK-ERRORS: ^ @ CHECK: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32], r6 @ encoding: [0xa4,0xf9,0x36,0x0f] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:64], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vld4.8 {d0[], d2[], d4[], d6[]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -4410,10 +4410,10 @@ vld4.16 {d0, d1, d2, d3}, [r4:256] @ CHECK: vld4.16 {d0, d1, d2, d3}, [r4] @ encoding: [0x24,0xf9,0x4f,0x00] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld4.16 {d0, d1, d2, d3}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld4.16 {d0, d1, d2, d3}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld4.16 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x24,0xf9,0x5f,0x00] @@ -4428,10 +4428,10 @@ vld4.16 {d0, d1, d2, d3}, [r4:256]! @ CHECK: vld4.16 {d0, d1, d2, d3}, [r4]! @ encoding: [0x24,0xf9,0x4d,0x00] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld4.16 {d0, d1, d2, d3}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld4.16 {d0, d1, d2, d3}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld4.16 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x24,0xf9,0x5d,0x00] @@ -4446,10 +4446,10 @@ vld4.16 {d0, d1, d2, d3}, [r4:256], r6 @ CHECK: vld4.16 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x24,0xf9,0x46,0x00] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld4.16 {d0, d1, d2, d3}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld4.16 {d0, d1, d2, d3}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld4.16 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x24,0xf9,0x56,0x00] @@ -4464,10 +4464,10 @@ vld4.16 {d0, d2, d4, d6}, [r4:256] @ CHECK: vld4.16 {d0, d2, d4, d6}, [r4] @ encoding: [0x24,0xf9,0x4f,0x01] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld4.16 {d0, d2, d4, d6}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld4.16 {d0, d2, d4, d6}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld4.16 {d0, d2, d4, d6}, [r4:64] @ encoding: [0x24,0xf9,0x5f,0x01] @@ -4482,10 +4482,10 @@ vld4.16 {d0, d2, d4, d6}, [r4:256]! @ CHECK: vld4.16 {d0, d2, d4, d6}, [r4]! @ encoding: [0x24,0xf9,0x4d,0x01] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld4.16 {d0, d2, d4, d6}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld4.16 {d0, d2, d4, d6}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld4.16 {d0, d2, d4, d6}, [r4:64]! @ encoding: [0x24,0xf9,0x5d,0x01] @@ -4500,10 +4500,10 @@ vld4.16 {d0, d2, d4, d6}, [r4:256], r6 @ CHECK: vld4.16 {d0, d2, d4, d6}, [r4], r6 @ encoding: [0x24,0xf9,0x46,0x01] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld4.16 {d0, d2, d4, d6}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld4.16 {d0, d2, d4, d6}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld4.16 {d0, d2, d4, d6}, [r4:64], r6 @ encoding: [0x24,0xf9,0x56,0x01] @@ -4518,17 +4518,17 @@ vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:256] @ CHECK: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4] @ encoding: [0xa4,0xf9,0x4f,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64] @ encoding: [0xa4,0xf9,0x5f,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:256] @ CHECK-ERRORS: ^ @@ -4540,17 +4540,17 @@ vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]! @ CHECK: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4]! @ encoding: [0xa4,0xf9,0x4d,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]! @ encoding: [0xa4,0xf9,0x5d,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -4562,17 +4562,17 @@ vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:256], r6 @ CHECK: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6 @ encoding: [0xa4,0xf9,0x46,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6 @ encoding: [0xa4,0xf9,0x56,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -4584,17 +4584,17 @@ vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:256] @ CHECK: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4] @ encoding: [0xa4,0xf9,0x6f,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64] @ encoding: [0xa4,0xf9,0x7f,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:256] @ CHECK-ERRORS: ^ @@ -4606,17 +4606,17 @@ vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:256]! @ CHECK: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4]! @ encoding: [0xa4,0xf9,0x6d,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]! @ encoding: [0xa4,0xf9,0x7d,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -4628,17 +4628,17 @@ vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:256], r6 @ CHECK: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6 @ encoding: [0xa4,0xf9,0x66,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6 @ encoding: [0xa4,0xf9,0x76,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -4650,17 +4650,17 @@ vld4.16 {d0[], d1[], d2[], d3[]}, [r4:256] @ CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4] @ encoding: [0xa4,0xf9,0x4f,0x0f] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:64] @ encoding: [0xa4,0xf9,0x5f,0x0f] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:256] @ CHECK-ERRORS: ^ @@ -4672,17 +4672,17 @@ vld4.16 {d0[], d1[], d2[], d3[]}, [r4:256]! @ CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4]! @ encoding: [0xa4,0xf9,0x4d,0x0f] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:64]! @ encoding: [0xa4,0xf9,0x5d,0x0f] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -4694,17 +4694,17 @@ vld4.16 {d0[], d1[], d2[], d3[]}, [r4:256], r6 @ CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x46,0x0f] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:64], r6 @ encoding: [0xa4,0xf9,0x56,0x0f] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -4716,17 +4716,17 @@ vld4.16 {d0[], d2[], d4[], d6[]}, [r4:256] @ CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4] @ encoding: [0xa4,0xf9,0x6f,0x0f] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64] @ encoding: [0xa4,0xf9,0x7f,0x0f] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:256] @ CHECK-ERRORS: ^ @@ -4738,17 +4738,17 @@ vld4.16 {d0[], d2[], d4[], d6[]}, [r4:256]! @ CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4]! @ encoding: [0xa4,0xf9,0x6d,0x0f] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld4.16 {d0[], d1[], d2[], d3[]}, [r4:64]! @ encoding: [0xa4,0xf9,0x7d,0x0f] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -4760,17 +4760,17 @@ vld4.16 {d0[], d2[], d4[], d6[]}, [r4:256], r6 @ CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x66,0x0f] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64], r6 @ encoding: [0xa4,0xf9,0x76,0x0f] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vld4.16 {d0[], d2[], d4[], d6[]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -4782,10 +4782,10 @@ vld4.32 {d0, d1, d2, d3}, [r4:256] @ CHECK: vld4.32 {d0, d1, d2, d3}, [r4] @ encoding: [0x24,0xf9,0x8f,0x00] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld4.32 {d0, d1, d2, d3}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld4.32 {d0, d1, d2, d3}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld4.32 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x24,0xf9,0x9f,0x00] @@ -4800,10 +4800,10 @@ vld4.32 {d0, d1, d2, d3}, [r4:256]! @ CHECK: vld4.32 {d0, d1, d2, d3}, [r4]! @ encoding: [0x24,0xf9,0x8d,0x00] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld4.32 {d0, d1, d2, d3}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld4.32 {d0, d1, d2, d3}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld4.32 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x24,0xf9,0x9d,0x00] @@ -4818,10 +4818,10 @@ vld4.32 {d0, d1, d2, d3}, [r4:256], r6 @ CHECK: vld4.32 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x24,0xf9,0x86,0x00] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld4.32 {d0, d1, d2, d3}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld4.32 {d0, d1, d2, d3}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld4.32 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x24,0xf9,0x96,0x00] @@ -4836,10 +4836,10 @@ vld4.32 {d0, d2, d4, d6}, [r4:256] @ CHECK: vld4.32 {d0, d2, d4, d6}, [r4] @ encoding: [0x24,0xf9,0x8f,0x01] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld4.32 {d0, d2, d4, d6}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld4.32 {d0, d2, d4, d6}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld4.32 {d0, d2, d4, d6}, [r4:64] @ encoding: [0x24,0xf9,0x9f,0x01] @@ -4854,10 +4854,10 @@ vld4.32 {d0, d2, d4, d6}, [r4:256]! @ CHECK: vld4.32 {d0, d2, d4, d6}, [r4]! @ encoding: [0x24,0xf9,0x8d,0x01] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld4.32 {d0, d2, d4, d6}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld4.32 {d0, d2, d4, d6}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld4.32 {d0, d2, d4, d6}, [r4:64]! @ encoding: [0x24,0xf9,0x9d,0x01] @@ -4872,10 +4872,10 @@ vld4.32 {d0, d2, d4, d6}, [r4:256], r6 @ CHECK: vld4.32 {d0, d2, d4, d6}, [r4], r6 @ encoding: [0x24,0xf9,0x86,0x01] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld4.32 {d0, d2, d4, d6}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vld4.32 {d0, d2, d4, d6}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld4.32 {d0, d2, d4, d6}, [r4:64], r6 @ encoding: [0x24,0xf9,0x96,0x01] @@ -4890,15 +4890,15 @@ vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:256] @ CHECK: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4] @ encoding: [0xa4,0xf9,0x8f,0x0b] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64] @ encoding: [0xa4,0xf9,0x9f,0x0b] @ CHECK: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128] @ encoding: [0xa4,0xf9,0xaf,0x0b] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:256] @ CHECK-ERRORS: ^ @@ -4910,15 +4910,15 @@ vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]! @ CHECK: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4]! @ encoding: [0xa4,0xf9,0x8d,0x0b] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]! @ encoding: [0xa4,0xf9,0x9d,0x0b] @ CHECK: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]! @ encoding: [0xa4,0xf9,0xad,0x0b] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -4930,15 +4930,15 @@ vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:256], r6 @ CHECK: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6 @ encoding: [0xa4,0xf9,0x86,0x0b] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6 @ encoding: [0xa4,0xf9,0x96,0x0b] @ CHECK: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6 @ encoding: [0xa4,0xf9,0xa6,0x0b] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -4950,15 +4950,15 @@ vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256] @ CHECK: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4] @ encoding: [0xa4,0xf9,0xcf,0x0b] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64] @ encoding: [0xa4,0xf9,0xdf,0x0b] @ CHECK: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128] @ encoding: [0xa4,0xf9,0xef,0x0b] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256] @ CHECK-ERRORS: ^ @@ -4970,15 +4970,15 @@ vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256]! @ CHECK: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]! @ encoding: [0xa4,0xf9,0xcd,0x0b] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]! @ encoding: [0xa4,0xf9,0xdd,0x0b] @ CHECK: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]! @ encoding: [0xa4,0xf9,0xed,0x0b] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -4990,15 +4990,15 @@ vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256], r6 @ CHECK: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6 @ encoding: [0xa4,0xf9,0xc6,0x0b] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6 @ encoding: [0xa4,0xf9,0xd6,0x0b] @ CHECK: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128], r6 @ encoding: [0xa4,0xf9,0xe6,0x0b] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -5010,15 +5010,15 @@ vld4.32 {d0[], d1[], d2[], d3[]}, [r4:256] @ CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4] @ encoding: [0xa4,0xf9,0x8f,0x0f] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:64] @ encoding: [0xa4,0xf9,0x9f,0x0f] @ CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:128] @ encoding: [0xa4,0xf9,0xdf,0x0f] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:256] @ CHECK-ERRORS: ^ @@ -5030,15 +5030,15 @@ vld4.32 {d0[], d1[], d2[], d3[]}, [r4:256]! @ CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4]! @ encoding: [0xa4,0xf9,0x8d,0x0f] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:64]! @ encoding: [0xa4,0xf9,0x9d,0x0f] @ CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:128]! @ encoding: [0xa4,0xf9,0xdd,0x0f] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -5050,15 +5050,15 @@ vld4.32 {d0[], d1[], d2[], d3[]}, [r4:256], r6 @ CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4], r6 @ encoding: [0xa4,0xf9,0x86,0x0f] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:64], r6 @ encoding: [0xa4,0xf9,0x96,0x0f] @ CHECK: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:128], r6 @ encoding: [0xa4,0xf9,0xd6,0x0f] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld4.32 {d0[], d1[], d2[], d3[]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -5070,15 +5070,15 @@ vld4.32 {d0[], d2[], d4[], d6[]}, [r4:256] @ CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4] @ encoding: [0xa4,0xf9,0xaf,0x0f] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:64] @ encoding: [0xa4,0xf9,0xbf,0x0f] @ CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:128] @ encoding: [0xa4,0xf9,0xff,0x0f] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:256] @ CHECK-ERRORS: ^ @@ -5090,15 +5090,15 @@ vld4.32 {d0[], d2[], d4[], d6[]}, [r4:256]! @ CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4]! @ encoding: [0xa4,0xf9,0xad,0x0f] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:64]! @ encoding: [0xa4,0xf9,0xbd,0x0f] @ CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:128]! @ encoding: [0xa4,0xf9,0xfd,0x0f] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -5110,15 +5110,15 @@ vld4.32 {d0[], d2[], d4[], d6[]}, [r4:256], r6 @ CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4], r6 @ encoding: [0xa4,0xf9,0xa6,0x0f] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:64], r6 @ encoding: [0xa4,0xf9,0xb6,0x0f] @ CHECK: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:128], r6 @ encoding: [0xa4,0xf9,0xf6,0x0f] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vld4.32 {d0[], d2[], d4[], d6[]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -5130,17 +5130,17 @@ vst1.8 {d0}, [r4:256] @ CHECK: vst1.8 {d0}, [r4] @ encoding: [0x04,0xf9,0x0f,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.8 {d0}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.8 {d0}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vst1.8 {d0}, [r4:64] @ encoding: [0x04,0xf9,0x1f,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.8 {d0}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.8 {d0}, [r4:256] @ CHECK-ERRORS: ^ @@ -5152,17 +5152,17 @@ vst1.8 {d0}, [r4:256]! @ CHECK: vst1.8 {d0}, [r4]! @ encoding: [0x04,0xf9,0x0d,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.8 {d0}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.8 {d0}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vst1.8 {d0}, [r4:64]! @ encoding: [0x04,0xf9,0x1d,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.8 {d0}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.8 {d0}, [r4:256]! @ CHECK-ERRORS: ^ @@ -5174,17 +5174,17 @@ vst1.8 {d0}, [r4:256], r6 @ CHECK: vst1.8 {d0}, [r4], r6 @ encoding: [0x04,0xf9,0x06,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.8 {d0}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.8 {d0}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vst1.8 {d0}, [r4:64], r6 @ encoding: [0x04,0xf9,0x16,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.8 {d0}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.8 {d0}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -5196,15 +5196,15 @@ vst1.8 {d0, d1}, [r4:256] @ CHECK: vst1.8 {d0, d1}, [r4] @ encoding: [0x04,0xf9,0x0f,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst1.8 {d0, d1}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst1.8 {d0, d1}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vst1.8 {d0, d1}, [r4:64] @ encoding: [0x04,0xf9,0x1f,0x0a] @ CHECK: vst1.8 {d0, d1}, [r4:128] @ encoding: [0x04,0xf9,0x2f,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst1.8 {d0, d1}, [r4:256] @ CHECK-ERRORS: ^ @@ -5216,15 +5216,15 @@ vst1.8 {d0, d1}, [r4:256]! @ CHECK: vst1.8 {d0, d1}, [r4]! @ encoding: [0x04,0xf9,0x0d,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst1.8 {d0, d1}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst1.8 {d0, d1}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vst1.8 {d0, d1}, [r4:64]! @ encoding: [0x04,0xf9,0x1d,0x0a] @ CHECK: vst1.8 {d0, d1}, [r4:128]! @ encoding: [0x04,0xf9,0x2d,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst1.8 {d0, d1}, [r4:256]! @ CHECK-ERRORS: ^ @@ -5236,15 +5236,15 @@ vst1.8 {d0, d1}, [r4:256], r6 @ CHECK: vst1.8 {d0, d1}, [r4], r6 @ encoding: [0x04,0xf9,0x06,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst1.8 {d0, d1}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst1.8 {d0, d1}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vst1.8 {d0, d1}, [r4:64], r6 @ encoding: [0x04,0xf9,0x16,0x0a] @ CHECK: vst1.8 {d0, d1}, [r4:128], r6 @ encoding: [0x04,0xf9,0x26,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst1.8 {d0, d1}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -5256,17 +5256,17 @@ vst1.8 {d0, d1, d2}, [r4:256] @ CHECK: vst1.8 {d0, d1, d2}, [r4] @ encoding: [0x04,0xf9,0x0f,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.8 {d0, d1, d2}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.8 {d0, d1, d2}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vst1.8 {d0, d1, d2}, [r4:64] @ encoding: [0x04,0xf9,0x1f,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.8 {d0, d1, d2}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.8 {d0, d1, d2}, [r4:256] @ CHECK-ERRORS: ^ @@ -5278,17 +5278,17 @@ vst1.8 {d0, d1, d2}, [r4:256]! @ CHECK: vst1.8 {d0, d1, d2}, [r4]! @ encoding: [0x04,0xf9,0x0d,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.8 {d0, d1, d2}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.8 {d0, d1, d2}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vst1.8 {d0, d1, d2}, [r4:64]! @ encoding: [0x04,0xf9,0x1d,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.8 {d0, d1, d2}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.8 {d0, d1, d2}, [r4:256]! @ CHECK-ERRORS: ^ @@ -5300,17 +5300,17 @@ vst1.8 {d0, d1, d2}, [r4:256], r6 @ CHECK: vst1.8 {d0, d1, d2}, [r4], r6 @ encoding: [0x04,0xf9,0x06,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.8 {d0, d1, d2}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.8 {d0, d1, d2}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vst1.8 {d0, d1, d2}, [r4:64], r6 @ encoding: [0x04,0xf9,0x16,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.8 {d0, d1, d2}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.8 {d0, d1, d2}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -5322,10 +5322,10 @@ vst1.8 {d0, d1, d2, d3}, [r4:256] @ CHECK: vst1.8 {d0, d1, d2, d3}, [r4] @ encoding: [0x04,0xf9,0x0f,0x02] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst1.8 {d0, d1, d2, d3}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst1.8 {d0, d1, d2, d3}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vst1.8 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x04,0xf9,0x1f,0x02] @@ -5340,10 +5340,10 @@ vst1.8 {d0, d1, d2, d3}, [r4:256]! @ CHECK: vst1.8 {d0, d1, d2, d3}, [r4]! @ encoding: [0x04,0xf9,0x0d,0x02] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst1.8 {d0, d1, d2, d3}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst1.8 {d0, d1, d2, d3}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vst1.8 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x04,0xf9,0x1d,0x02] @@ -5358,10 +5358,10 @@ vst1.8 {d0, d1, d2, d3}, [r4:256], r6 @ CHECK: vst1.8 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x04,0xf9,0x06,0x02] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst1.8 {d0, d1, d2, d3}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst1.8 {d0, d1, d2, d3}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vst1.8 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x04,0xf9,0x16,0x02] @@ -5376,19 +5376,19 @@ vst1.8 {d0[2]}, [r4:256] @ CHECK: vst1.8 {d0[2]}, [r4] @ encoding: [0x84,0xf9,0x4f,0x00] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst1.8 {d0[2]}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst1.8 {d0[2]}, [r4:32] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst1.8 {d0[2]}, [r4:64] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst1.8 {d0[2]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst1.8 {d0[2]}, [r4:256] @ CHECK-ERRORS: ^ @@ -5400,19 +5400,19 @@ vst1.8 {d0[2]}, [r4:256]! @ CHECK: vst1.8 {d0[2]}, [r4]! @ encoding: [0x84,0xf9,0x4d,0x00] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst1.8 {d0[2]}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst1.8 {d0[2]}, [r4:32]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst1.8 {d0[2]}, [r4:64]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst1.8 {d0[2]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst1.8 {d0[2]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -5424,19 +5424,19 @@ vst1.8 {d0[2]}, [r4:256], r6 @ CHECK: vst1.8 {d0[2]}, [r4], r6 @ encoding: [0x84,0xf9,0x46,0x00] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst1.8 {d0[2]}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst1.8 {d0[2]}, [r4:32], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst1.8 {d0[2]}, [r4:64], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst1.8 {d0[2]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst1.8 {d0[2]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -5448,17 +5448,17 @@ vst1.16 {d0}, [r4:256] @ CHECK: vst1.16 {d0}, [r4] @ encoding: [0x04,0xf9,0x4f,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.16 {d0}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.16 {d0}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vst1.16 {d0}, [r4:64] @ encoding: [0x04,0xf9,0x5f,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.16 {d0}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.16 {d0}, [r4:256] @ CHECK-ERRORS: ^ @@ -5470,17 +5470,17 @@ vst1.16 {d0}, [r4:256]! @ CHECK: vst1.16 {d0}, [r4]! @ encoding: [0x04,0xf9,0x4d,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.16 {d0}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.16 {d0}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vst1.16 {d0}, [r4:64]! @ encoding: [0x04,0xf9,0x5d,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.16 {d0}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.16 {d0}, [r4:256]! @ CHECK-ERRORS: ^ @@ -5492,17 +5492,17 @@ vst1.16 {d0}, [r4:256], r6 @ CHECK: vst1.16 {d0}, [r4], r6 @ encoding: [0x04,0xf9,0x46,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.16 {d0}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.16 {d0}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vst1.16 {d0}, [r4:64], r6 @ encoding: [0x04,0xf9,0x56,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.16 {d0}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.16 {d0}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -5514,15 +5514,15 @@ vst1.16 {d0, d1}, [r4:256] @ CHECK: vst1.16 {d0, d1}, [r4] @ encoding: [0x04,0xf9,0x4f,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst1.16 {d0, d1}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst1.16 {d0, d1}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vst1.16 {d0, d1}, [r4:64] @ encoding: [0x04,0xf9,0x5f,0x0a] @ CHECK: vst1.16 {d0, d1}, [r4:128] @ encoding: [0x04,0xf9,0x6f,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst1.16 {d0, d1}, [r4:256] @ CHECK-ERRORS: ^ @@ -5534,15 +5534,15 @@ vst1.16 {d0, d1}, [r4:256]! @ CHECK: vst1.16 {d0, d1}, [r4]! @ encoding: [0x04,0xf9,0x4d,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst1.16 {d0, d1}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst1.16 {d0, d1}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vst1.16 {d0, d1}, [r4:64]! @ encoding: [0x04,0xf9,0x5d,0x0a] @ CHECK: vst1.16 {d0, d1}, [r4:128]! @ encoding: [0x04,0xf9,0x6d,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst1.16 {d0, d1}, [r4:256]! @ CHECK-ERRORS: ^ @@ -5554,15 +5554,15 @@ vst1.16 {d0, d1}, [r4:256], r6 @ CHECK: vst1.16 {d0, d1}, [r4], r6 @ encoding: [0x04,0xf9,0x46,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst1.16 {d0, d1}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst1.16 {d0, d1}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vst1.16 {d0, d1}, [r4:64], r6 @ encoding: [0x04,0xf9,0x56,0x0a] @ CHECK: vst1.16 {d0, d1}, [r4:128], r6 @ encoding: [0x04,0xf9,0x66,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst1.16 {d0, d1}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -5574,17 +5574,17 @@ vst1.16 {d0, d1, d2}, [r4:256] @ CHECK: vst1.16 {d0, d1, d2}, [r4] @ encoding: [0x04,0xf9,0x4f,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.16 {d0, d1, d2}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.16 {d0, d1, d2}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vst1.16 {d0, d1, d2}, [r4:64] @ encoding: [0x04,0xf9,0x5f,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.16 {d0, d1, d2}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.16 {d0, d1, d2}, [r4:256] @ CHECK-ERRORS: ^ @@ -5596,17 +5596,17 @@ vst1.16 {d0, d1, d2}, [r4:256]! @ CHECK: vst1.16 {d0, d1, d2}, [r4]! @ encoding: [0x04,0xf9,0x4d,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.16 {d0, d1, d2}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.16 {d0, d1, d2}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vst1.16 {d0, d1, d2}, [r4:64]! @ encoding: [0x04,0xf9,0x5d,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.16 {d0, d1, d2}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.16 {d0, d1, d2}, [r4:256]! @ CHECK-ERRORS: ^ @@ -5618,17 +5618,17 @@ vst1.16 {d0, d1, d2}, [r4:256], r6 @ CHECK: vst1.16 {d0, d1, d2}, [r4], r6 @ encoding: [0x04,0xf9,0x46,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.16 {d0, d1, d2}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.16 {d0, d1, d2}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vst1.16 {d0, d1, d2}, [r4:64], r6 @ encoding: [0x04,0xf9,0x56,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.16 {d0, d1, d2}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.16 {d0, d1, d2}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -5640,10 +5640,10 @@ vst1.16 {d0, d1, d2, d3}, [r4:256] @ CHECK: vst1.16 {d0, d1, d2, d3}, [r4] @ encoding: [0x04,0xf9,0x4f,0x02] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst1.16 {d0, d1, d2, d3}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst1.16 {d0, d1, d2, d3}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vst1.16 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x04,0xf9,0x5f,0x02] @@ -5658,10 +5658,10 @@ vst1.16 {d0, d1, d2, d3}, [r4:256]! @ CHECK: vst1.16 {d0, d1, d2, d3}, [r4]! @ encoding: [0x04,0xf9,0x4d,0x02] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst1.16 {d0, d1, d2, d3}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst1.16 {d0, d1, d2, d3}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vst1.16 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x04,0xf9,0x5d,0x02] @@ -5676,10 +5676,10 @@ vst1.16 {d0, d1, d2, d3}, [r4:256], r6 @ CHECK: vst1.16 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x04,0xf9,0x46,0x02] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst1.16 {d0, d1, d2, d3}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst1.16 {d0, d1, d2, d3}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vst1.16 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x04,0xf9,0x56,0x02] @@ -5695,16 +5695,16 @@ @ CHECK: vst1.16 {d0[2]}, [r4] @ encoding: [0x84,0xf9,0x8f,0x04] @ CHECK: vst1.16 {d0[2]}, [r4:16] @ encoding: [0x84,0xf9,0x9f,0x04] -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vst1.16 {d0[2]}, [r4:32] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vst1.16 {d0[2]}, [r4:64] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vst1.16 {d0[2]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vst1.16 {d0[2]}, [r4:256] @ CHECK-ERRORS: ^ @@ -5717,16 +5717,16 @@ @ CHECK: vst1.16 {d0[2]}, [r4]! @ encoding: [0x84,0xf9,0x8d,0x04] @ CHECK: vst1.16 {d0[2]}, [r4:16]! @ encoding: [0x84,0xf9,0x9d,0x04] -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vst1.16 {d0[2]}, [r4:32]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vst1.16 {d0[2]}, [r4:64]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vst1.16 {d0[2]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vst1.16 {d0[2]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -5739,16 +5739,16 @@ @ CHECK: vst1.16 {d0[2]}, [r4], r6 @ encoding: [0x84,0xf9,0x86,0x04] @ CHECK: vst1.16 {d0[2]}, [r4:16], r6 @ encoding: [0x84,0xf9,0x96,0x04] -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vst1.16 {d0[2]}, [r4:32], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vst1.16 {d0[2]}, [r4:64], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vst1.16 {d0[2]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vst1.16 {d0[2]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -5760,17 +5760,17 @@ vst1.32 {d0}, [r4:256] @ CHECK: vst1.32 {d0}, [r4] @ encoding: [0x04,0xf9,0x8f,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.32 {d0}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.32 {d0}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vst1.32 {d0}, [r4:64] @ encoding: [0x04,0xf9,0x9f,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.32 {d0}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.32 {d0}, [r4:256] @ CHECK-ERRORS: ^ @@ -5782,17 +5782,17 @@ vst1.32 {d0}, [r4:256]! @ CHECK: vst1.32 {d0}, [r4]! @ encoding: [0x04,0xf9,0x8d,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.32 {d0}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.32 {d0}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vst1.32 {d0}, [r4:64]! @ encoding: [0x04,0xf9,0x9d,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.32 {d0}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.32 {d0}, [r4:256]! @ CHECK-ERRORS: ^ @@ -5804,17 +5804,17 @@ vst1.32 {d0}, [r4:256], r6 @ CHECK: vst1.32 {d0}, [r4], r6 @ encoding: [0x04,0xf9,0x86,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.32 {d0}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.32 {d0}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vst1.32 {d0}, [r4:64], r6 @ encoding: [0x04,0xf9,0x96,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.32 {d0}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.32 {d0}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -5826,15 +5826,15 @@ vst1.32 {d0, d1}, [r4:256] @ CHECK: vst1.32 {d0, d1}, [r4] @ encoding: [0x04,0xf9,0x8f,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst1.32 {d0, d1}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst1.32 {d0, d1}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vst1.32 {d0, d1}, [r4:64] @ encoding: [0x04,0xf9,0x9f,0x0a] @ CHECK: vst1.32 {d0, d1}, [r4:128] @ encoding: [0x04,0xf9,0xaf,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst1.32 {d0, d1}, [r4:256] @ CHECK-ERRORS: ^ @@ -5846,15 +5846,15 @@ vst1.32 {d0, d1}, [r4:256]! @ CHECK: vst1.32 {d0, d1}, [r4]! @ encoding: [0x04,0xf9,0x8d,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst1.32 {d0, d1}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst1.32 {d0, d1}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vst1.32 {d0, d1}, [r4:64]! @ encoding: [0x04,0xf9,0x9d,0x0a] @ CHECK: vst1.32 {d0, d1}, [r4:128]! @ encoding: [0x04,0xf9,0xad,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst1.32 {d0, d1}, [r4:256]! @ CHECK-ERRORS: ^ @@ -5866,15 +5866,15 @@ vst1.32 {d0, d1}, [r4:256], r6 @ CHECK: vst1.32 {d0, d1}, [r4], r6 @ encoding: [0x04,0xf9,0x86,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst1.32 {d0, d1}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst1.32 {d0, d1}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vst1.32 {d0, d1}, [r4:64], r6 @ encoding: [0x04,0xf9,0x96,0x0a] @ CHECK: vst1.32 {d0, d1}, [r4:128], r6 @ encoding: [0x04,0xf9,0xa6,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst1.32 {d0, d1}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -5886,17 +5886,17 @@ vst1.32 {d0, d1, d2}, [r4:256] @ CHECK: vst1.32 {d0, d1, d2}, [r4] @ encoding: [0x04,0xf9,0x8f,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.32 {d0, d1, d2}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.32 {d0, d1, d2}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vst1.32 {d0, d1, d2}, [r4:64] @ encoding: [0x04,0xf9,0x9f,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.32 {d0, d1, d2}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.32 {d0, d1, d2}, [r4:256] @ CHECK-ERRORS: ^ @@ -5908,17 +5908,17 @@ vst1.32 {d0, d1, d2}, [r4:256]! @ CHECK: vst1.32 {d0, d1, d2}, [r4]! @ encoding: [0x04,0xf9,0x8d,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.32 {d0, d1, d2}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.32 {d0, d1, d2}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vst1.32 {d0, d1, d2}, [r4:64]! @ encoding: [0x04,0xf9,0x9d,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.32 {d0, d1, d2}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.32 {d0, d1, d2}, [r4:256]! @ CHECK-ERRORS: ^ @@ -5930,17 +5930,17 @@ vst1.32 {d0, d1, d2}, [r4:256], r6 @ CHECK: vst1.32 {d0, d1, d2}, [r4], r6 @ encoding: [0x04,0xf9,0x86,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.32 {d0, d1, d2}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.32 {d0, d1, d2}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vst1.32 {d0, d1, d2}, [r4:64], r6 @ encoding: [0x04,0xf9,0x96,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.32 {d0, d1, d2}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.32 {d0, d1, d2}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -5952,10 +5952,10 @@ vst1.32 {d0, d1, d2, d3}, [r4:256] @ CHECK: vst1.32 {d0, d1, d2, d3}, [r4] @ encoding: [0x04,0xf9,0x8f,0x02] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst1.32 {d0, d1, d2, d3}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst1.32 {d0, d1, d2, d3}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vst1.32 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x04,0xf9,0x9f,0x02] @@ -5970,10 +5970,10 @@ vst1.32 {d0, d1, d2, d3}, [r4:256]! @ CHECK: vst1.32 {d0, d1, d2, d3}, [r4]! @ encoding: [0x04,0xf9,0x8d,0x02] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst1.32 {d0, d1, d2, d3}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst1.32 {d0, d1, d2, d3}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vst1.32 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x04,0xf9,0x9d,0x02] @@ -5988,10 +5988,10 @@ vst1.32 {d0, d1, d2, d3}, [r4:256], r6 @ CHECK: vst1.32 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x04,0xf9,0x86,0x02] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst1.32 {d0, d1, d2, d3}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst1.32 {d0, d1, d2, d3}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vst1.32 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x04,0xf9,0x96,0x02] @@ -6006,17 +6006,17 @@ vst1.32 {d0[1]}, [r4:256] @ CHECK: vst1.32 {d0[1]}, [r4] @ encoding: [0x84,0xf9,0x8f,0x08] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vst1.32 {d0[1]}, [r4:16] @ CHECK-ERRORS: ^ @ CHECK: vst1.32 {d0[1]}, [r4:32] @ encoding: [0x84,0xf9,0xbf,0x08] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vst1.32 {d0[1]}, [r4:64] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vst1.32 {d0[1]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vst1.32 {d0[1]}, [r4:256] @ CHECK-ERRORS: ^ @@ -6028,17 +6028,17 @@ vst1.32 {d0[1]}, [r4:256]! @ CHECK: vst1.32 {d0[1]}, [r4]! @ encoding: [0x84,0xf9,0x8d,0x08] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vst1.32 {d0[1]}, [r4:16]! @ CHECK-ERRORS: ^ @ CHECK: vst1.32 {d0[1]}, [r4:32]! @ encoding: [0x84,0xf9,0xbd,0x08] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vst1.32 {d0[1]}, [r4:64]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vst1.32 {d0[1]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vst1.32 {d0[1]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -6050,17 +6050,17 @@ vst1.32 {d0[1]}, [r4:256], r6 @ CHECK: vst1.32 {d0[1]}, [r4], r6 @ encoding: [0x84,0xf9,0x86,0x08] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vst1.32 {d0[1]}, [r4:16], r6 @ CHECK-ERRORS: ^ @ CHECK: vst1.32 {d0[1]}, [r4:32], r6 @ encoding: [0x84,0xf9,0xb6,0x08] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vst1.32 {d0[1]}, [r4:64], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vst1.32 {d0[1]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vst1.32 {d0[1]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -6072,17 +6072,17 @@ vst1.64 {d0}, [r4:256] @ CHECK: vst1.64 {d0}, [r4] @ encoding: [0x04,0xf9,0xcf,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.64 {d0}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.64 {d0}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vst1.64 {d0}, [r4:64] @ encoding: [0x04,0xf9,0xdf,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.64 {d0}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.64 {d0}, [r4:256] @ CHECK-ERRORS: ^ @@ -6094,17 +6094,17 @@ vst1.64 {d0}, [r4:256]! @ CHECK: vst1.64 {d0}, [r4]! @ encoding: [0x04,0xf9,0xcd,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.64 {d0}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.64 {d0}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vst1.64 {d0}, [r4:64]! @ encoding: [0x04,0xf9,0xdd,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.64 {d0}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.64 {d0}, [r4:256]! @ CHECK-ERRORS: ^ @@ -6116,17 +6116,17 @@ vst1.64 {d0}, [r4:256], r6 @ CHECK: vst1.64 {d0}, [r4], r6 @ encoding: [0x04,0xf9,0xc6,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.64 {d0}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.64 {d0}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vst1.64 {d0}, [r4:64], r6 @ encoding: [0x04,0xf9,0xd6,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.64 {d0}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.64 {d0}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -6138,15 +6138,15 @@ vst1.64 {d0, d1}, [r4:256] @ CHECK: vst1.64 {d0, d1}, [r4] @ encoding: [0x04,0xf9,0xcf,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst1.64 {d0, d1}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst1.64 {d0, d1}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vst1.64 {d0, d1}, [r4:64] @ encoding: [0x04,0xf9,0xdf,0x0a] @ CHECK: vst1.64 {d0, d1}, [r4:128] @ encoding: [0x04,0xf9,0xef,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst1.64 {d0, d1}, [r4:256] @ CHECK-ERRORS: ^ @@ -6158,15 +6158,15 @@ vst1.64 {d0, d1}, [r4:256]! @ CHECK: vst1.64 {d0, d1}, [r4]! @ encoding: [0x04,0xf9,0xcd,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst1.64 {d0, d1}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst1.64 {d0, d1}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vst1.64 {d0, d1}, [r4:64]! @ encoding: [0x04,0xf9,0xdd,0x0a] @ CHECK: vst1.64 {d0, d1}, [r4:128]! @ encoding: [0x04,0xf9,0xed,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst1.64 {d0, d1}, [r4:256]! @ CHECK-ERRORS: ^ @@ -6178,15 +6178,15 @@ vst1.64 {d0, d1}, [r4:256], r6 @ CHECK: vst1.64 {d0, d1}, [r4], r6 @ encoding: [0x04,0xf9,0xc6,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst1.64 {d0, d1}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst1.64 {d0, d1}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vst1.64 {d0, d1}, [r4:64], r6 @ encoding: [0x04,0xf9,0xd6,0x0a] @ CHECK: vst1.64 {d0, d1}, [r4:128], r6 @ encoding: [0x04,0xf9,0xe6,0x0a] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst1.64 {d0, d1}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -6198,17 +6198,17 @@ vst1.64 {d0, d1, d2}, [r4:256] @ CHECK: vst1.64 {d0, d1, d2}, [r4] @ encoding: [0x04,0xf9,0xcf,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.64 {d0, d1, d2}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.64 {d0, d1, d2}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vst1.64 {d0, d1, d2}, [r4:64] @ encoding: [0x04,0xf9,0xdf,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.64 {d0, d1, d2}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.64 {d0, d1, d2}, [r4:256] @ CHECK-ERRORS: ^ @@ -6220,17 +6220,17 @@ vst1.64 {d0, d1, d2}, [r4:256]! @ CHECK: vst1.64 {d0, d1, d2}, [r4]! @ encoding: [0x04,0xf9,0xcd,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.64 {d0, d1, d2}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.64 {d0, d1, d2}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vst1.64 {d0, d1, d2}, [r4:64]! @ encoding: [0x04,0xf9,0xdd,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.64 {d0, d1, d2}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.64 {d0, d1, d2}, [r4:256]! @ CHECK-ERRORS: ^ @@ -6242,17 +6242,17 @@ vst1.64 {d0, d1, d2}, [r4:256], r6 @ CHECK: vst1.64 {d0, d1, d2}, [r4], r6 @ encoding: [0x04,0xf9,0xc6,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.64 {d0, d1, d2}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.64 {d0, d1, d2}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vst1.64 {d0, d1, d2}, [r4:64], r6 @ encoding: [0x04,0xf9,0xd6,0x06] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.64 {d0, d1, d2}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst1.64 {d0, d1, d2}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -6264,10 +6264,10 @@ vst1.64 {d0, d1, d2, d3}, [r4:256] @ CHECK: vst1.64 {d0, d1, d2, d3}, [r4] @ encoding: [0x04,0xf9,0xcf,0x02] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst1.64 {d0, d1, d2, d3}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst1.64 {d0, d1, d2, d3}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vst1.64 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x04,0xf9,0xdf,0x02] @@ -6282,10 +6282,10 @@ vst1.64 {d0, d1, d2, d3}, [r4:256]! @ CHECK: vst1.64 {d0, d1, d2, d3}, [r4]! @ encoding: [0x04,0xf9,0xcd,0x02] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst1.64 {d0, d1, d2, d3}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst1.64 {d0, d1, d2, d3}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vst1.64 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x04,0xf9,0xdd,0x02] @@ -6300,10 +6300,10 @@ vst1.64 {d0, d1, d2, d3}, [r4:256], r6 @ CHECK: vst1.64 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x04,0xf9,0xc6,0x02] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst1.64 {d0, d1, d2, d3}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst1.64 {d0, d1, d2, d3}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vst1.64 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x04,0xf9,0xd6,0x02] @@ -6318,15 +6318,15 @@ vst2.8 {d0, d1}, [r4:256] @ CHECK: vst2.8 {d0, d1}, [r4] @ encoding: [0x04,0xf9,0x0f,0x08] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst2.8 {d0, d1}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst2.8 {d0, d1}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vst2.8 {d0, d1}, [r4:64] @ encoding: [0x04,0xf9,0x1f,0x08] @ CHECK: vst2.8 {d0, d1}, [r4:128] @ encoding: [0x04,0xf9,0x2f,0x08] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst2.8 {d0, d1}, [r4:256] @ CHECK-ERRORS: ^ @@ -6338,15 +6338,15 @@ vst2.8 {d0, d1}, [r4:256]! @ CHECK: vst2.8 {d0, d1}, [r4]! @ encoding: [0x04,0xf9,0x0d,0x08] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst2.8 {d0, d1}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst2.8 {d0, d1}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vst2.8 {d0, d1}, [r4:64]! @ encoding: [0x04,0xf9,0x1d,0x08] @ CHECK: vst2.8 {d0, d1}, [r4:128]! @ encoding: [0x04,0xf9,0x2d,0x08] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst2.8 {d0, d1}, [r4:256]! @ CHECK-ERRORS: ^ @@ -6358,15 +6358,15 @@ vst2.8 {d0, d1}, [r4:256], r6 @ CHECK: vst2.8 {d0, d1}, [r4], r6 @ encoding: [0x04,0xf9,0x06,0x08] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst2.8 {d0, d1}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst2.8 {d0, d1}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vst2.8 {d0, d1}, [r4:64], r6 @ encoding: [0x04,0xf9,0x16,0x08] @ CHECK: vst2.8 {d0, d1}, [r4:128], r6 @ encoding: [0x04,0xf9,0x26,0x08] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst2.8 {d0, d1}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -6378,15 +6378,15 @@ vst2.8 {d0, d2}, [r4:256] @ CHECK: vst2.8 {d0, d2}, [r4] @ encoding: [0x04,0xf9,0x0f,0x09] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst2.8 {d0, d2}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst2.8 {d0, d2}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vst2.8 {d0, d2}, [r4:64] @ encoding: [0x04,0xf9,0x1f,0x09] @ CHECK: vst2.8 {d0, d2}, [r4:128] @ encoding: [0x04,0xf9,0x2f,0x09] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst2.8 {d0, d2}, [r4:256] @ CHECK-ERRORS: ^ @@ -6398,15 +6398,15 @@ vst2.8 {d0, d2}, [r4:256]! @ CHECK: vst2.8 {d0, d2}, [r4]! @ encoding: [0x04,0xf9,0x0d,0x09] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst2.8 {d0, d2}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst2.8 {d0, d2}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vst2.8 {d0, d2}, [r4:64]! @ encoding: [0x04,0xf9,0x1d,0x09] @ CHECK: vst2.8 {d0, d2}, [r4:128]! @ encoding: [0x04,0xf9,0x2d,0x09] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst2.8 {d0, d2}, [r4:256]! @ CHECK-ERRORS: ^ @@ -6418,15 +6418,15 @@ vst2.8 {d0, d2}, [r4:256], r6 @ CHECK: vst2.8 {d0, d2}, [r4], r6 @ encoding: [0x04,0xf9,0x06,0x09] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst2.8 {d0, d2}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst2.8 {d0, d2}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vst2.8 {d0, d2}, [r4:64], r6 @ encoding: [0x04,0xf9,0x16,0x09] @ CHECK: vst2.8 {d0, d2}, [r4:128], r6 @ encoding: [0x04,0xf9,0x26,0x09] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst2.8 {d0, d2}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -6438,10 +6438,10 @@ vst2.8 {d0, d1, d2, d3}, [r4:256] @ CHECK: vst2.8 {d0, d1, d2, d3}, [r4] @ encoding: [0x04,0xf9,0x0f,0x03] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst2.8 {d0, d1, d2, d3}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst2.8 {d0, d1, d2, d3}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vst2.8 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x04,0xf9,0x1f,0x03] @@ -6456,10 +6456,10 @@ vst2.8 {d0, d1, d2, d3}, [r4:256]! @ CHECK: vst2.8 {d0, d1, d2, d3}, [r4]! @ encoding: [0x04,0xf9,0x0d,0x03] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst2.8 {d0, d1, d2, d3}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst2.8 {d0, d1, d2, d3}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vst2.8 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x04,0xf9,0x1d,0x03] @@ -6474,10 +6474,10 @@ vst2.8 {d0, d1, d2, d3}, [r4:256], r6 @ CHECK: vst2.8 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x04,0xf9,0x06,0x03] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst2.8 {d0, d1, d2, d3}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst2.8 {d0, d1, d2, d3}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vst2.8 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x04,0xf9,0x16,0x03] @@ -6493,16 +6493,16 @@ @ CHECK: vst2.8 {d0[2], d1[2]}, [r4] @ encoding: [0x84,0xf9,0x4f,0x01] @ CHECK: vst2.8 {d0[2], d1[2]}, [r4:16] @ encoding: [0x84,0xf9,0x5f,0x01] -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vst2.8 {d0[2], d1[2]}, [r4:32] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vst2.8 {d0[2], d1[2]}, [r4:64] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vst2.8 {d0[2], d1[2]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vst2.8 {d0[2], d1[2]}, [r4:256] @ CHECK-ERRORS: ^ @@ -6515,16 +6515,16 @@ @ CHECK: vst2.8 {d0[2], d1[2]}, [r4]! @ encoding: [0x84,0xf9,0x4d,0x01] @ CHECK: vst2.8 {d0[2], d1[2]}, [r4:16]! @ encoding: [0x84,0xf9,0x5d,0x01] -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vst2.8 {d0[2], d1[2]}, [r4:32]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vst2.8 {d0[2], d1[2]}, [r4:64]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vst2.8 {d0[2], d1[2]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vst2.8 {d0[2], d1[2]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -6537,16 +6537,16 @@ @ CHECK: vst2.8 {d0[2], d1[2]}, [r4], r6 @ encoding: [0x84,0xf9,0x46,0x01] @ CHECK: vst2.8 {d0[2], d1[2]}, [r4:16], r6 @ encoding: [0x84,0xf9,0x56,0x01] -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vst2.8 {d0[2], d1[2]}, [r4:32], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vst2.8 {d0[2], d1[2]}, [r4:64], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vst2.8 {d0[2], d1[2]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 16 or omitted +@ CHECK-ERRORS: error: alignment must be 16 or omitted @ CHECK-ERRORS: vst2.8 {d0[2], d1[2]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -6558,15 +6558,15 @@ vst2.32 {d0, d1}, [r4:256] @ CHECK: vst2.32 {d0, d1}, [r4] @ encoding: [0x04,0xf9,0x8f,0x08] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst2.32 {d0, d1}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst2.32 {d0, d1}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vst2.32 {d0, d1}, [r4:64] @ encoding: [0x04,0xf9,0x9f,0x08] @ CHECK: vst2.32 {d0, d1}, [r4:128] @ encoding: [0x04,0xf9,0xaf,0x08] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst2.32 {d0, d1}, [r4:256] @ CHECK-ERRORS: ^ @@ -6578,15 +6578,15 @@ vst2.32 {d0, d1}, [r4:256]! @ CHECK: vst2.32 {d0, d1}, [r4]! @ encoding: [0x04,0xf9,0x8d,0x08] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst2.32 {d0, d1}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst2.32 {d0, d1}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vst2.32 {d0, d1}, [r4:64]! @ encoding: [0x04,0xf9,0x9d,0x08] @ CHECK: vst2.32 {d0, d1}, [r4:128]! @ encoding: [0x04,0xf9,0xad,0x08] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst2.32 {d0, d1}, [r4:256]! @ CHECK-ERRORS: ^ @@ -6598,15 +6598,15 @@ vst2.32 {d0, d1}, [r4:256], r6 @ CHECK: vst2.32 {d0, d1}, [r4], r6 @ encoding: [0x04,0xf9,0x86,0x08] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst2.32 {d0, d1}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst2.32 {d0, d1}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vst2.32 {d0, d1}, [r4:64], r6 @ encoding: [0x04,0xf9,0x96,0x08] @ CHECK: vst2.32 {d0, d1}, [r4:128], r6 @ encoding: [0x04,0xf9,0xa6,0x08] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst2.32 {d0, d1}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -6618,15 +6618,15 @@ vst2.32 {d0, d2}, [r4:256] @ CHECK: vst2.32 {d0, d2}, [r4] @ encoding: [0x04,0xf9,0x8f,0x09] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst2.32 {d0, d2}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst2.32 {d0, d2}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vst2.32 {d0, d2}, [r4:64] @ encoding: [0x04,0xf9,0x9f,0x09] @ CHECK: vst2.32 {d0, d2}, [r4:128] @ encoding: [0x04,0xf9,0xaf,0x09] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst2.32 {d0, d2}, [r4:256] @ CHECK-ERRORS: ^ @@ -6638,15 +6638,15 @@ vst2.32 {d0, d2}, [r4:256]! @ CHECK: vst2.32 {d0, d2}, [r4]! @ encoding: [0x04,0xf9,0x8d,0x09] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst2.32 {d0, d2}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst2.32 {d0, d2}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vst2.32 {d0, d2}, [r4:64]! @ encoding: [0x04,0xf9,0x9d,0x09] @ CHECK: vst2.32 {d0, d2}, [r4:128]! @ encoding: [0x04,0xf9,0xad,0x09] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst2.32 {d0, d2}, [r4:256]! @ CHECK-ERRORS: ^ @@ -6658,15 +6658,15 @@ vst2.32 {d0, d2}, [r4:256], r6 @ CHECK: vst2.32 {d0, d2}, [r4], r6 @ encoding: [0x04,0xf9,0x86,0x09] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst2.32 {d0, d2}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst2.32 {d0, d2}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vst2.32 {d0, d2}, [r4:64], r6 @ encoding: [0x04,0xf9,0x96,0x09] @ CHECK: vst2.32 {d0, d2}, [r4:128], r6 @ encoding: [0x04,0xf9,0xa6,0x09] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst2.32 {d0, d2}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -6678,10 +6678,10 @@ vst2.32 {d0, d1, d2, d3}, [r4:256] @ CHECK: vst2.32 {d0, d1, d2, d3}, [r4] @ encoding: [0x04,0xf9,0x8f,0x03] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst2.32 {d0, d1, d2, d3}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst2.32 {d0, d1, d2, d3}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vst2.32 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x04,0xf9,0x9f,0x03] @@ -6696,10 +6696,10 @@ vst2.32 {d0, d1, d2, d3}, [r4:256]! @ CHECK: vst2.32 {d0, d1, d2, d3}, [r4]! @ encoding: [0x04,0xf9,0x8d,0x03] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst2.32 {d0, d1, d2, d3}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst2.32 {d0, d1, d2, d3}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vst2.32 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x04,0xf9,0x9d,0x03] @@ -6714,10 +6714,10 @@ vst2.32 {d0, d1, d2, d3}, [r4:256], r6 @ CHECK: vst2.32 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x04,0xf9,0x86,0x03] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst2.32 {d0, d1, d2, d3}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst2.32 {d0, d1, d2, d3}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vst2.32 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x04,0xf9,0x96,0x03] @@ -6732,17 +6732,17 @@ vst2.32 {d0[1], d1[1]}, [r4:256] @ CHECK: vst2.32 {d0[1], d1[1]}, [r4] @ encoding: [0x84,0xf9,0x8f,0x09] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst2.32 {d0[1], d1[1]}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst2.32 {d0[1], d1[1]}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vst2.32 {d0[1], d1[1]}, [r4:64] @ encoding: [0x84,0xf9,0x9f,0x09] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst2.32 {d0[1], d1[1]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst2.32 {d0[1], d1[1]}, [r4:256] @ CHECK-ERRORS: ^ @@ -6754,17 +6754,17 @@ vst2.32 {d0[1], d1[1]}, [r4:256]! @ CHECK: vst2.32 {d0[1], d1[1]}, [r4]! @ encoding: [0x84,0xf9,0x8d,0x09] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst2.32 {d0[1], d1[1]}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst2.32 {d0[1], d1[1]}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vst2.32 {d0[1], d1[1]}, [r4:64]! @ encoding: [0x84,0xf9,0x9d,0x09] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst2.32 {d0[1], d1[1]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst2.32 {d0[1], d1[1]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -6776,17 +6776,17 @@ vst2.32 {d0[1], d1[1]}, [r4:256], r6 @ CHECK: vst2.32 {d0[1], d1[1]}, [r4], r6 @ encoding: [0x84,0xf9,0x86,0x09] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst2.32 {d0[1], d1[1]}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst2.32 {d0[1], d1[1]}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vst2.32 {d0[1], d1[1]}, [r4:64], r6 @ encoding: [0x84,0xf9,0x96,0x09] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst2.32 {d0[1], d1[1]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst2.32 {d0[1], d1[1]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -6798,17 +6798,17 @@ vst2.32 {d0[1], d2[1]}, [r4:256] @ CHECK: vst2.32 {d0[1], d2[1]}, [r4] @ encoding: [0x84,0xf9,0xcf,0x09] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst2.32 {d0[1], d2[1]}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst2.32 {d0[1], d2[1]}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vst2.32 {d0[1], d2[1]}, [r4:64] @ encoding: [0x84,0xf9,0xdf,0x09] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst2.32 {d0[1], d2[1]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst2.32 {d0[1], d2[1]}, [r4:256] @ CHECK-ERRORS: ^ @@ -6820,17 +6820,17 @@ vst2.32 {d0[1], d2[1]}, [r4:256]! @ CHECK: vst2.32 {d0[1], d2[1]}, [r4]! @ encoding: [0x84,0xf9,0xcd,0x09] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst2.32 {d0[1], d2[1]}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst2.32 {d0[1], d2[1]}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vst2.32 {d0[1], d2[1]}, [r4:64]! @ encoding: [0x84,0xf9,0xdd,0x09] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst2.32 {d0[1], d2[1]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst2.32 {d0[1], d2[1]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -6842,17 +6842,17 @@ vst2.32 {d0[1], d2[1]}, [r4:256], r6 @ CHECK: vst2.32 {d0[1], d2[1]}, [r4], r6 @ encoding: [0x84,0xf9,0xc6,0x09] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst2.32 {d0[1], d2[1]}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst2.32 {d0[1], d2[1]}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vst2.32 {d0[1], d2[1]}, [r4:64], r6 @ encoding: [0x84,0xf9,0xd6,0x09] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst2.32 {d0[1], d2[1]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst2.32 {d0[1], d2[1]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -6864,17 +6864,17 @@ vst3.8 {d0, d1, d2}, [r4:256] @ CHECK: vst3.8 {d0, d1, d2}, [r4] @ encoding: [0x04,0xf9,0x0f,0x04] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.8 {d0, d1, d2}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.8 {d0, d1, d2}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vst3.8 {d0, d1, d2}, [r4:64] @ encoding: [0x04,0xf9,0x1f,0x04] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.8 {d0, d1, d2}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.8 {d0, d1, d2}, [r4:256] @ CHECK-ERRORS: ^ @@ -6886,17 +6886,17 @@ vst3.8 {d0, d1, d2}, [r4:256]! @ CHECK: vst3.8 {d0, d1, d2}, [r4]! @ encoding: [0x04,0xf9,0x0d,0x04] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.8 {d0, d1, d2}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.8 {d0, d1, d2}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vst3.8 {d0, d1, d2}, [r4:64]! @ encoding: [0x04,0xf9,0x1d,0x04] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.8 {d0, d1, d2}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.8 {d0, d1, d2}, [r4:256]! @ CHECK-ERRORS: ^ @@ -6908,17 +6908,17 @@ vst3.8 {d0, d1, d2}, [r4:256], r6 @ CHECK: vst3.8 {d0, d1, d2}, [r4], r6 @ encoding: [0x04,0xf9,0x06,0x04] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.8 {d0, d1, d2}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.8 {d0, d1, d2}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vst3.8 {d0, d1, d2}, [r4:64], r6 @ encoding: [0x04,0xf9,0x16,0x04] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.8 {d0, d1, d2}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.8 {d0, d1, d2}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -6930,17 +6930,17 @@ vst3.8 {d0, d2, d4}, [r4:256] @ CHECK: vst3.8 {d0, d2, d4}, [r4] @ encoding: [0x04,0xf9,0x0f,0x05] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.8 {d0, d2, d4}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.8 {d0, d2, d4}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vst3.8 {d0, d2, d4}, [r4:64] @ encoding: [0x04,0xf9,0x1f,0x05] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.8 {d0, d2, d4}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.8 {d0, d2, d4}, [r4:256] @ CHECK-ERRORS: ^ @@ -6952,17 +6952,17 @@ vst3.8 {d0, d2, d4}, [r4:256]! @ CHECK: vst3.8 {d0, d2, d4}, [r4]! @ encoding: [0x04,0xf9,0x0d,0x05] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.8 {d0, d2, d4}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.8 {d0, d2, d4}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vst3.8 {d0, d2, d4}, [r4:64]! @ encoding: [0x04,0xf9,0x1d,0x05] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.8 {d0, d2, d4}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.8 {d0, d2, d4}, [r4:256]! @ CHECK-ERRORS: ^ @@ -6974,17 +6974,17 @@ vst3.8 {d0, d2, d4}, [r4:256], r6 @ CHECK: vst3.8 {d0, d2, d4}, [r4], r6 @ encoding: [0x04,0xf9,0x06,0x05] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.8 {d0, d2, d4}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.8 {d0, d2, d4}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vst3.8 {d0, d2, d4}, [r4:64], r6 @ encoding: [0x04,0xf9,0x16,0x05] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.8 {d0, d2, d4}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.8 {d0, d2, d4}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -6996,19 +6996,19 @@ vst3.8 {d0[1], d1[1], d2[1]}, [r4:256] @ CHECK: vst3.8 {d0[1], d1[1], d2[1]}, [r4] @ encoding: [0x84,0xf9,0x2f,0x02] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.8 {d0[1], d1[1], d2[1]}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.8 {d0[1], d1[1], d2[1]}, [r4:32] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.8 {d0[1], d1[1], d2[1]}, [r4:64] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.8 {d0[1], d1[1], d2[1]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.8 {d0[1], d1[1], d2[1]}, [r4:256] @ CHECK-ERRORS: ^ @@ -7020,19 +7020,19 @@ vst3.8 {d0[1], d1[1], d2[1]}, [r4:256]! @ CHECK: vst3.8 {d0[1], d1[1], d2[1]}, [r4]! @ encoding: [0x84,0xf9,0x2d,0x02] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.8 {d0[1], d1[1], d2[1]}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.8 {d0[1], d1[1], d2[1]}, [r4:32]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.8 {d0[1], d1[1], d2[1]}, [r4:64]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.8 {d0[1], d1[1], d2[1]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.8 {d0[1], d1[1], d2[1]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -7044,19 +7044,19 @@ vst3.8 {d0[1], d1[1], d2[1]}, [r4:256], r6 @ CHECK: vst3.8 {d0[1], d1[1], d2[1]}, [r4], r6 @ encoding: [0x84,0xf9,0x26,0x02] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.8 {d0[1], d1[1], d2[1]}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.8 {d0[1], d1[1], d2[1]}, [r4:32], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.8 {d0[1], d1[1], d2[1]}, [r4:64], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.8 {d0[1], d1[1], d2[1]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.8 {d0[1], d1[1], d2[1]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -7068,17 +7068,17 @@ vst3.16 {d0, d1, d2}, [r4:256] @ CHECK: vst3.16 {d0, d1, d2}, [r4] @ encoding: [0x04,0xf9,0x4f,0x04] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.16 {d0, d1, d2}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.16 {d0, d1, d2}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vst3.16 {d0, d1, d2}, [r4:64] @ encoding: [0x04,0xf9,0x5f,0x04] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.16 {d0, d1, d2}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.16 {d0, d1, d2}, [r4:256] @ CHECK-ERRORS: ^ @@ -7090,17 +7090,17 @@ vst3.16 {d0, d1, d2}, [r4:256]! @ CHECK: vst3.16 {d0, d1, d2}, [r4]! @ encoding: [0x04,0xf9,0x4d,0x04] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.16 {d0, d1, d2}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.16 {d0, d1, d2}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vst3.16 {d0, d1, d2}, [r4:64]! @ encoding: [0x04,0xf9,0x5d,0x04] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.16 {d0, d1, d2}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.16 {d0, d1, d2}, [r4:256]! @ CHECK-ERRORS: ^ @@ -7112,17 +7112,17 @@ vst3.16 {d0, d1, d2}, [r4:256], r6 @ CHECK: vst3.16 {d0, d1, d2}, [r4], r6 @ encoding: [0x04,0xf9,0x46,0x04] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.16 {d0, d1, d2}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.16 {d0, d1, d2}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vst3.16 {d0, d1, d2}, [r4:64], r6 @ encoding: [0x04,0xf9,0x56,0x04] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.16 {d0, d1, d2}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.16 {d0, d1, d2}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -7134,17 +7134,17 @@ vst3.16 {d0, d2, d4}, [r4:256] @ CHECK: vst3.16 {d0, d2, d4}, [r4] @ encoding: [0x04,0xf9,0x4f,0x05] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.16 {d0, d2, d4}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.16 {d0, d2, d4}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vst3.16 {d0, d2, d4}, [r4:64] @ encoding: [0x04,0xf9,0x5f,0x05] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.16 {d0, d2, d4}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.16 {d0, d2, d4}, [r4:256] @ CHECK-ERRORS: ^ @@ -7156,17 +7156,17 @@ vst3.16 {d0, d2, d4}, [r4:256]! @ CHECK: vst3.16 {d0, d2, d4}, [r4]! @ encoding: [0x04,0xf9,0x4d,0x05] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.16 {d0, d2, d4}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.16 {d0, d2, d4}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vst3.16 {d0, d2, d4}, [r4:64]! @ encoding: [0x04,0xf9,0x5d,0x05] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.16 {d0, d2, d4}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.16 {d0, d2, d4}, [r4:256]! @ CHECK-ERRORS: ^ @@ -7178,17 +7178,17 @@ vst3.16 {d0, d2, d4}, [r4:256], r6 @ CHECK: vst3.16 {d0, d2, d4}, [r4], r6 @ encoding: [0x04,0xf9,0x46,0x05] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.16 {d0, d2, d4}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.16 {d0, d2, d4}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vst3.16 {d0, d2, d4}, [r4:64], r6 @ encoding: [0x04,0xf9,0x56,0x05] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.16 {d0, d2, d4}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.16 {d0, d2, d4}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -7200,19 +7200,19 @@ vst3.16 {d0[1], d1[1], d2[1]}, [r4:256] @ CHECK: vst3.16 {d0[1], d1[1], d2[1]}, [r4] @ encoding: [0x84,0xf9,0x4f,0x06] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.16 {d0[1], d1[1], d2[1]}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.16 {d0[1], d1[1], d2[1]}, [r4:32] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.16 {d0[1], d1[1], d2[1]}, [r4:64] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.16 {d0[1], d1[1], d2[1]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.16 {d0[1], d1[1], d2[1]}, [r4:256] @ CHECK-ERRORS: ^ @@ -7224,19 +7224,19 @@ vst3.16 {d0[1], d1[1], d2[1]}, [r4:256]! @ CHECK: vst3.16 {d0[1], d1[1], d2[1]}, [r4]! @ encoding: [0x84,0xf9,0x4d,0x06] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.16 {d0[1], d1[1], d2[1]}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.16 {d0[1], d1[1], d2[1]}, [r4:32]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.16 {d0[1], d1[1], d2[1]}, [r4:64]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.16 {d0[1], d1[1], d2[1]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.16 {d0[1], d1[1], d2[1]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -7248,19 +7248,19 @@ vst3.16 {d0[1], d1[1], d2[1]}, [r4:256], r6 @ CHECK: vst3.16 {d0[1], d1[1], d2[1]}, [r4], r6 @ encoding: [0x84,0xf9,0x46,0x06] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.16 {d0[1], d1[1], d2[1]}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.16 {d0[1], d1[1], d2[1]}, [r4:32], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.16 {d0[1], d1[1], d2[1]}, [r4:64], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.16 {d0[1], d1[1], d2[1]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.16 {d0[1], d1[1], d2[1]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -7272,19 +7272,19 @@ vst3.16 {d0[1], d2[1], d4[1]}, [r4:256] @ CHECK: vst3.16 {d0[1], d2[1], d4[1]}, [r4] @ encoding: [0x84,0xf9,0x6f,0x06] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.16 {d0[1], d2[1], d4[1]}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.16 {d0[1], d2[1], d4[1]}, [r4:32] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.16 {d0[1], d2[1], d4[1]}, [r4:64] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.16 {d0[1], d2[1], d4[1]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.16 {d0[1], d2[1], d4[1]}, [r4:256] @ CHECK-ERRORS: ^ @@ -7296,19 +7296,19 @@ vst3.16 {d0[1], d2[1], d4[1]}, [r4:256]! @ CHECK: vst3.16 {d0[1], d1[1], d2[1]}, [r4]! @ encoding: [0x84,0xf9,0x6d,0x06] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.16 {d0[1], d2[1], d4[1]}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.16 {d0[1], d2[1], d4[1]}, [r4:32]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.16 {d0[1], d2[1], d4[1]}, [r4:64]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.16 {d0[1], d2[1], d4[1]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.16 {d0[1], d2[1], d4[1]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -7320,19 +7320,19 @@ vst3.16 {d0[1], d2[1], d4[1]}, [r4:256], r6 @ CHECK: vst3.16 {d0[1], d2[1], d4[1]}, [r4], r6 @ encoding: [0x84,0xf9,0x66,0x06] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.16 {d0[1], d2[1], d4[1]}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.16 {d0[1], d2[1], d4[1]}, [r4:32], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.16 {d0[1], d2[1], d4[1]}, [r4:64], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.16 {d0[1], d2[1], d4[1]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.16 {d0[1], d2[1], d4[1]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -7344,17 +7344,17 @@ vst3.32 {d0, d1, d2}, [r4:256] @ CHECK: vst3.32 {d0, d1, d2}, [r4] @ encoding: [0x04,0xf9,0x8f,0x04] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.32 {d0, d1, d2}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.32 {d0, d1, d2}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vst3.32 {d0, d1, d2}, [r4:64] @ encoding: [0x04,0xf9,0x9f,0x04] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.32 {d0, d1, d2}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.32 {d0, d1, d2}, [r4:256] @ CHECK-ERRORS: ^ @@ -7366,17 +7366,17 @@ vst3.32 {d0, d1, d2}, [r4:256]! @ CHECK: vst3.32 {d0, d1, d2}, [r4]! @ encoding: [0x04,0xf9,0x8d,0x04] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.32 {d0, d1, d2}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.32 {d0, d1, d2}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vst3.32 {d0, d1, d2}, [r4:64]! @ encoding: [0x04,0xf9,0x9d,0x04] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.32 {d0, d1, d2}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.32 {d0, d1, d2}, [r4:256]! @ CHECK-ERRORS: ^ @@ -7388,17 +7388,17 @@ vst3.32 {d0, d1, d2}, [r4:256], r6 @ CHECK: vst3.32 {d0, d1, d2}, [r4], r6 @ encoding: [0x04,0xf9,0x86,0x04] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.32 {d0, d1, d2}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.32 {d0, d1, d2}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vst3.32 {d0, d1, d2}, [r4:64], r6 @ encoding: [0x04,0xf9,0x96,0x04] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.32 {d0, d1, d2}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.32 {d0, d1, d2}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -7410,17 +7410,17 @@ vst3.32 {d0, d2, d4}, [r4:256] @ CHECK: vst3.32 {d0, d2, d4}, [r4] @ encoding: [0x04,0xf9,0x8f,0x05] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.32 {d0, d2, d4}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.32 {d0, d2, d4}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vst3.32 {d0, d2, d4}, [r4:64] @ encoding: [0x04,0xf9,0x9f,0x05] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.32 {d0, d2, d4}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.32 {d0, d2, d4}, [r4:256] @ CHECK-ERRORS: ^ @@ -7432,17 +7432,17 @@ vst3.32 {d0, d2, d4}, [r4:256]! @ CHECK: vst3.32 {d0, d2, d4}, [r4]! @ encoding: [0x04,0xf9,0x8d,0x05] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.32 {d0, d2, d4}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.32 {d0, d2, d4}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vst3.32 {d0, d2, d4}, [r4:64]! @ encoding: [0x04,0xf9,0x9d,0x05] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.32 {d0, d2, d4}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.32 {d0, d2, d4}, [r4:256]! @ CHECK-ERRORS: ^ @@ -7454,17 +7454,17 @@ vst3.32 {d0, d2, d4}, [r4:256], r6 @ CHECK: vst3.32 {d0, d2, d4}, [r4], r6 @ encoding: [0x04,0xf9,0x86,0x05] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.32 {d0, d2, d4}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.32 {d0, d2, d4}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vst3.32 {d0, d2, d4}, [r4:64], r6 @ encoding: [0x04,0xf9,0x96,0x05] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.32 {d0, d2, d4}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst3.32 {d0, d2, d4}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -7476,19 +7476,19 @@ vst3.32 {d0[1], d1[1], d2[1]}, [r4:256] @ CHECK: vst3.32 {d0[1], d1[1], d2[1]}, [r4] @ encoding: [0x84,0xf9,0x8f,0x0a] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.32 {d0[1], d1[1], d2[1]}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.32 {d0[1], d1[1], d2[1]}, [r4:32] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.32 {d0[1], d1[1], d2[1]}, [r4:64] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.32 {d0[1], d1[1], d2[1]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.32 {d0[1], d1[1], d2[1]}, [r4:256] @ CHECK-ERRORS: ^ @@ -7500,19 +7500,19 @@ vst3.32 {d0[1], d1[1], d2[1]}, [r4:256]! @ CHECK: vst3.32 {d0[1], d1[1], d2[1]}, [r4]! @ encoding: [0x84,0xf9,0x8d,0x0a] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.32 {d0[1], d1[1], d2[1]}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.32 {d0[1], d1[1], d2[1]}, [r4:32]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.32 {d0[1], d1[1], d2[1]}, [r4:64]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.32 {d0[1], d1[1], d2[1]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.32 {d0[1], d1[1], d2[1]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -7524,19 +7524,19 @@ vst3.32 {d0[1], d1[1], d2[1]}, [r4:256], r6 @ CHECK: vst3.32 {d0[1], d1[1], d2[1]}, [r4], r6 @ encoding: [0x84,0xf9,0x86,0x0a] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.32 {d0[1], d1[1], d2[1]}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.32 {d0[1], d1[1], d2[1]}, [r4:32], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.32 {d0[1], d1[1], d2[1]}, [r4:64], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.32 {d0[1], d1[1], d2[1]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.32 {d0[1], d1[1], d2[1]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -7548,19 +7548,19 @@ vst3.32 {d0[1], d2[1], d4[1]}, [r4:256] @ CHECK: vst3.32 {d0[1], d2[1], d4[1]}, [r4] @ encoding: [0x84,0xf9,0xcf,0x0a] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.32 {d0[1], d2[1], d4[1]}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.32 {d0[1], d2[1], d4[1]}, [r4:32] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.32 {d0[1], d2[1], d4[1]}, [r4:64] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.32 {d0[1], d2[1], d4[1]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.32 {d0[1], d2[1], d4[1]}, [r4:256] @ CHECK-ERRORS: ^ @@ -7572,19 +7572,19 @@ vst3.32 {d0[1], d2[1], d4[1]}, [r4:256]! @ CHECK: vst3.32 {d0[1], d2[1], d4[1]}, [r4]! @ encoding: [0x84,0xf9,0xcd,0x0a] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.32 {d0[1], d2[1], d4[1]}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.32 {d0[1], d2[1], d4[1]}, [r4:32]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.32 {d0[1], d2[1], d4[1]}, [r4:64]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.32 {d0[1], d2[1], d4[1]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.32 {d0[1], d2[1], d4[1]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -7596,19 +7596,19 @@ vst3.32 {d0[1], d2[1], d4[1]}, [r4:256], r6 @ CHECK: vst3.32 {d0[1], d2[1], d4[1]}, [r4], r6 @ encoding: [0x84,0xf9,0xc6,0x0a] -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.32 {d0[1], d2[1], d4[1]}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.32 {d0[1], d2[1], d4[1]}, [r4:32], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.32 {d0[1], d2[1], d4[1]}, [r4:64], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.32 {d0[1], d2[1], d4[1]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be omitted +@ CHECK-ERRORS: error: alignment must be omitted @ CHECK-ERRORS: vst3.32 {d0[1], d2[1], d4[1]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -7620,10 +7620,10 @@ vst4.8 {d0, d1, d2, d3}, [r4:256] @ CHECK: vst4.8 {d0, d1, d2, d3}, [r4] @ encoding: [0x04,0xf9,0x0f,0x00] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst4.8 {d0, d1, d2, d3}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst4.8 {d0, d1, d2, d3}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vst4.8 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x04,0xf9,0x1f,0x00] @@ -7638,10 +7638,10 @@ vst4.8 {d0, d1, d2, d3}, [r4:256]! @ CHECK: vst4.8 {d0, d1, d2, d3}, [r4]! @ encoding: [0x04,0xf9,0x0d,0x00] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst4.8 {d0, d1, d2, d3}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst4.8 {d0, d1, d2, d3}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vst4.8 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x04,0xf9,0x1d,0x00] @@ -7656,10 +7656,10 @@ vst4.8 {d0, d1, d2, d3}, [r4:256], r6 @ CHECK: vst4.8 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x04,0xf9,0x06,0x00] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst4.8 {d0, d1, d2, d3}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst4.8 {d0, d1, d2, d3}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vst4.8 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x04,0xf9,0x16,0x00] @@ -7674,10 +7674,10 @@ vst4.8 {d0, d2, d4, d6}, [r4:256] @ CHECK: vst4.8 {d0, d2, d4, d6}, [r4] @ encoding: [0x04,0xf9,0x0f,0x01] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst4.8 {d0, d2, d4, d6}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst4.8 {d0, d2, d4, d6}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vst4.8 {d0, d2, d4, d6}, [r4:64] @ encoding: [0x04,0xf9,0x1f,0x01] @@ -7692,10 +7692,10 @@ vst4.8 {d0, d2, d4, d6}, [r4:256]! @ CHECK: vst4.8 {d0, d2, d4, d6}, [r4]! @ encoding: [0x04,0xf9,0x0d,0x01] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst4.8 {d0, d2, d4, d6}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst4.8 {d0, d2, d4, d6}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vst4.8 {d0, d2, d4, d6}, [r4:64]! @ encoding: [0x04,0xf9,0x1d,0x01] @@ -7710,10 +7710,10 @@ vst4.8 {d0, d2, d4, d6}, [r4:256], r6 @ CHECK: vst4.8 {d0, d2, d4, d6}, [r4], r6 @ encoding: [0x04,0xf9,0x06,0x01] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst4.8 {d0, d2, d4, d6}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst4.8 {d0, d2, d4, d6}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vst4.8 {d0, d2, d4, d6}, [r4:64], r6 @ encoding: [0x04,0xf9,0x16,0x01] @@ -7728,17 +7728,17 @@ vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:256] @ CHECK: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4] @ encoding: [0x84,0xf9,0x2f,0x03] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:16] @ CHECK-ERRORS: ^ @ CHECK: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32] @ encoding: [0x84,0xf9,0x3f,0x03] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:64] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:256] @ CHECK-ERRORS: ^ @@ -7750,17 +7750,17 @@ vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]! @ CHECK: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4]! @ encoding: [0x84,0xf9,0x2d,0x03] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:16]! @ CHECK-ERRORS: ^ @ CHECK: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]! @ encoding: [0x84,0xf9,0x3d,0x03] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -7772,17 +7772,17 @@ vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:256], r6 @ CHECK: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6 @ encoding: [0x84,0xf9,0x26,0x03] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:16], r6 @ CHECK-ERRORS: ^ @ CHECK: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32], r6 @ encoding: [0x84,0xf9,0x36,0x03] -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 32 or omitted +@ CHECK-ERRORS: error: alignment must be 32 or omitted @ CHECK-ERRORS: vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -7794,10 +7794,10 @@ vst4.16 {d0, d1, d2, d3}, [r4:256] @ CHECK: vst4.16 {d0, d1, d2, d3}, [r4] @ encoding: [0x04,0xf9,0x4f,0x00] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst4.16 {d0, d1, d2, d3}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst4.16 {d0, d1, d2, d3}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vst4.16 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x04,0xf9,0x5f,0x00] @@ -7812,10 +7812,10 @@ vst4.16 {d0, d1, d2, d3}, [r4:256]! @ CHECK: vst4.16 {d0, d1, d2, d3}, [r4]! @ encoding: [0x04,0xf9,0x4d,0x00] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst4.16 {d0, d1, d2, d3}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst4.16 {d0, d1, d2, d3}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vst4.16 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x04,0xf9,0x5d,0x00] @@ -7830,10 +7830,10 @@ vst4.16 {d0, d1, d2, d3}, [r4:256], r6 @ CHECK: vst4.16 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x04,0xf9,0x46,0x00] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst4.16 {d0, d1, d2, d3}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst4.16 {d0, d1, d2, d3}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vst4.16 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x04,0xf9,0x56,0x00] @@ -7848,10 +7848,10 @@ vst4.16 {d0, d2, d4, d6}, [r4:256] @ CHECK: vst4.16 {d0, d2, d4, d6}, [r4] @ encoding: [0x04,0xf9,0x4f,0x01] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst4.16 {d0, d2, d4, d6}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst4.16 {d0, d2, d4, d6}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vst4.16 {d0, d2, d4, d6}, [r4:64] @ encoding: [0x04,0xf9,0x5f,0x01] @@ -7866,10 +7866,10 @@ vst4.16 {d0, d2, d4, d6}, [r4:256]! @ CHECK: vst4.16 {d0, d2, d4, d6}, [r4]! @ encoding: [0x04,0xf9,0x4d,0x01] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst4.16 {d0, d2, d4, d6}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst4.16 {d0, d2, d4, d6}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vst4.16 {d0, d2, d4, d6}, [r4:64]! @ encoding: [0x04,0xf9,0x5d,0x01] @@ -7884,10 +7884,10 @@ vst4.16 {d0, d2, d4, d6}, [r4:256], r6 @ CHECK: vst4.16 {d0, d2, d4, d6}, [r4], r6 @ encoding: [0x04,0xf9,0x46,0x01] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst4.16 {d0, d2, d4, d6}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst4.16 {d0, d2, d4, d6}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vst4.16 {d0, d2, d4, d6}, [r4:64], r6 @ encoding: [0x04,0xf9,0x56,0x01] @@ -7902,17 +7902,17 @@ vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:256] @ CHECK: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4] @ encoding: [0x84,0xf9,0x4f,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64] @ encoding: [0x84,0xf9,0x5f,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:256] @ CHECK-ERRORS: ^ @@ -7924,17 +7924,17 @@ vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]! @ CHECK: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4]! @ encoding: [0x84,0xf9,0x4d,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]! @ encoding: [0x84,0xf9,0x5d,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -7946,17 +7946,17 @@ vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:256], r6 @ CHECK: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6 @ encoding: [0x84,0xf9,0x46,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6 @ encoding: [0x84,0xf9,0x56,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -7968,17 +7968,17 @@ vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:256] @ CHECK: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4] @ encoding: [0x84,0xf9,0x6f,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64] @ encoding: [0x84,0xf9,0x7f,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:256] @ CHECK-ERRORS: ^ @@ -7990,17 +7990,17 @@ vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:256]! @ CHECK: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4]! @ encoding: [0x84,0xf9,0x6d,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]! @ encoding: [0x84,0xf9,0x7d,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -8012,17 +8012,17 @@ vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:256], r6 @ CHECK: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6 @ encoding: [0x84,0xf9,0x66,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6 @ encoding: [0x84,0xf9,0x76,0x07] -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:128], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64 or omitted +@ CHECK-ERRORS: error: alignment must be 64 or omitted @ CHECK-ERRORS: vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -8034,10 +8034,10 @@ vst4.32 {d0, d1, d2, d3}, [r4:256] @ CHECK: vst4.32 {d0, d1, d2, d3}, [r4] @ encoding: [0x04,0xf9,0x8f,0x00] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst4.32 {d0, d1, d2, d3}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst4.32 {d0, d1, d2, d3}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vst4.32 {d0, d1, d2, d3}, [r4:64] @ encoding: [0x04,0xf9,0x9f,0x00] @@ -8052,10 +8052,10 @@ vst4.32 {d0, d1, d2, d3}, [r4:256]! @ CHECK: vst4.32 {d0, d1, d2, d3}, [r4]! @ encoding: [0x04,0xf9,0x8d,0x00] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst4.32 {d0, d1, d2, d3}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst4.32 {d0, d1, d2, d3}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vst4.32 {d0, d1, d2, d3}, [r4:64]! @ encoding: [0x04,0xf9,0x9d,0x00] @@ -8070,10 +8070,10 @@ vst4.32 {d0, d1, d2, d3}, [r4:256], r6 @ CHECK: vst4.32 {d0, d1, d2, d3}, [r4], r6 @ encoding: [0x04,0xf9,0x86,0x00] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst4.32 {d0, d1, d2, d3}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst4.32 {d0, d1, d2, d3}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vst4.32 {d0, d1, d2, d3}, [r4:64], r6 @ encoding: [0x04,0xf9,0x96,0x00] @@ -8088,10 +8088,10 @@ vst4.32 {d0, d2, d4, d6}, [r4:256] @ CHECK: vst4.32 {d0, d2, d4, d6}, [r4] @ encoding: [0x04,0xf9,0x8f,0x01] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst4.32 {d0, d2, d4, d6}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst4.32 {d0, d2, d4, d6}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vst4.32 {d0, d2, d4, d6}, [r4:64] @ encoding: [0x04,0xf9,0x9f,0x01] @@ -8106,10 +8106,10 @@ vst4.32 {d0, d2, d4, d6}, [r4:256]! @ CHECK: vst4.32 {d0, d2, d4, d6}, [r4]! @ encoding: [0x04,0xf9,0x8d,0x01] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst4.32 {d0, d2, d4, d6}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst4.32 {d0, d2, d4, d6}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vst4.32 {d0, d2, d4, d6}, [r4:64]! @ encoding: [0x04,0xf9,0x9d,0x01] @@ -8124,10 +8124,10 @@ vst4.32 {d0, d2, d4, d6}, [r4:256], r6 @ CHECK: vst4.32 {d0, d2, d4, d6}, [r4], r6 @ encoding: [0x04,0xf9,0x86,0x01] -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst4.32 {d0, d2, d4, d6}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128, 256 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128, 256 or omitted @ CHECK-ERRORS: vst4.32 {d0, d2, d4, d6}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vst4.32 {d0, d2, d4, d6}, [r4:64], r6 @ encoding: [0x04,0xf9,0x96,0x01] @@ -8144,12 +8144,12 @@ @ CHECK: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4] @ encoding: [0x84,0xf9,0x8f,0x0b] @ CHECK-ERRORS: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64] @ encoding: [0x84,0xf9,0x9f,0x0b] @ CHECK: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128] @ encoding: [0x84,0xf9,0xaf,0x0b] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:256] @ CHECK-ERRORS: ^ @@ -8161,15 +8161,15 @@ vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]! @ CHECK: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4]! @ encoding: [0x84,0xf9,0x8d,0x0b] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]! @ encoding: [0x84,0xf9,0x9d,0x0b] @ CHECK: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]! @ encoding: [0x84,0xf9,0xad,0x0b] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -8181,15 +8181,15 @@ vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:256], r6 @ CHECK: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6 @ encoding: [0x84,0xf9,0x86,0x0b] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6 @ encoding: [0x84,0xf9,0x96,0x0b] @ CHECK: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6 @ encoding: [0x84,0xf9,0xa6,0x0b] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -8201,15 +8201,15 @@ vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256] @ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4] @ encoding: [0x84,0xf9,0xcf,0x0b] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64] @ encoding: [0x84,0xf9,0xdf,0x0b] @ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128] @ encoding: [0x84,0xf9,0xef,0x0b] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256] @ CHECK-ERRORS: ^ @@ -8221,15 +8221,15 @@ vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256]! @ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]! @ encoding: [0x84,0xf9,0xcd,0x0b] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]! @ encoding: [0x84,0xf9,0xdd,0x0b] @ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]! @ encoding: [0x84,0xf9,0xed,0x0b] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -8241,15 +8241,15 @@ vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256], r6 @ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6 @ encoding: [0x84,0xf9,0xc6,0x0b] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6 @ encoding: [0x84,0xf9,0xd6,0x0b] @ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128], r6 @ encoding: [0x84,0xf9,0xe6,0x0b] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -8261,15 +8261,15 @@ vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]! @ CHECK: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4]! @ encoding: [0x84,0xf9,0x8d,0x0b] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]! @ encoding: [0x84,0xf9,0x9d,0x0b] @ CHECK: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]! @ encoding: [0x84,0xf9,0xad,0x0b] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -8281,15 +8281,15 @@ vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:256], r6 @ CHECK: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6 @ encoding: [0x84,0xf9,0x86,0x0b] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6 @ encoding: [0x84,0xf9,0x96,0x0b] @ CHECK: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6 @ encoding: [0x84,0xf9,0xa6,0x0b] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:256], r6 @ CHECK-ERRORS: ^ @@ -8301,15 +8301,15 @@ vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256] @ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4] @ encoding: [0x84,0xf9,0xcf,0x0b] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:16] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:32] @ CHECK-ERRORS: ^ @ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64] @ encoding: [0x84,0xf9,0xdf,0x0b] @ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128] @ encoding: [0x84,0xf9,0xef,0x0b] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256] @ CHECK-ERRORS: ^ @@ -8321,15 +8321,15 @@ vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256]! @ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]! @ encoding: [0x84,0xf9,0xcd,0x0b] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:16]! @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:32]! @ CHECK-ERRORS: ^ @ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]! @ encoding: [0x84,0xf9,0xdd,0x0b] @ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]! @ encoding: [0x84,0xf9,0xed,0x0b] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256]! @ CHECK-ERRORS: ^ @@ -8341,14 +8341,14 @@ vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256], r6 @ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6 @ encoding: [0x84,0xf9,0xc6,0x0b] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:16], r6 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:32], r6 @ CHECK-ERRORS: ^ @ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6 @ encoding: [0x84,0xf9,0xd6,0x0b] @ CHECK: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128], r6 @ encoding: [0x84,0xf9,0xe6,0x0b] -@ CHECK-ERRORS: alignment must be 64, 128 or omitted +@ CHECK-ERRORS: error: alignment must be 64, 128 or omitted @ CHECK-ERRORS: vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:256], r6 @ CHECK-ERRORS: ^ Index: test/MC/ARM/not-armv4.s =================================================================== --- test/MC/ARM/not-armv4.s +++ test/MC/ARM/not-armv4.s @@ -1,10 +1,10 @@ @ RUN: not llvm-mc < %s -triple armv4-unknown-unknown -show-encoding 2>&1 | FileCheck %s @ PR18524 -@ CHECK: instruction requires: armv5t +@ CHECK: error: instruction requires: armv5t clz r4,r9 -@ CHECK: instruction requires: armv6t2 +@ CHECK: error: instruction requires: armv6t2 rbit r4,r9 @ CHECK: error: instruction requires: armv6t2 Index: test/MC/ARM/register-token-source-loc.s =================================================================== --- test/MC/ARM/register-token-source-loc.s +++ /dev/null @@ -1,12 +0,0 @@ -// RUN: not llvm-mc -triple armv6m--none-eabi < %s 2>&1 | FileCheck %s - -// Some of these CHECK lines need to uses regexes to that the amount of -// whitespace between the start of the line and the caret is significant. - - add sp, r0, #4 -// CHECK: error: invalid instruction, any one of the following would fix this: -// CHECK: note: instruction requires: thumb2 -// CHECK: note: invalid operand for instruction -// CHECK-NEXT: {{^ add sp, r0, #4}} -// CHECK-NEXT: {{^ \^}} -// CHECK: note: too many operands for instruction Index: test/MC/ARM/single-precision-fp.s =================================================================== --- test/MC/ARM/single-precision-fp.s +++ test/MC/ARM/single-precision-fp.s @@ -72,7 +72,7 @@ @ FIXME: overlapping aliases and a probable TableGen indeterminacy mean @ that the actual reason can vary by platform. vmov.f64 d11, d10 -@ CHECK-ERRORS: instruction requires: NEON +@ CHECK-ERRORS: error: instruction requires: @ CHECK-ERRORS-NEXT: vmov.f64 d11, d10 vcvt.f64.s32 d9, s8 Index: test/MC/ARM/t2-modified-immediate-fixup-error2.s =================================================================== --- test/MC/ARM/t2-modified-immediate-fixup-error2.s +++ test/MC/ARM/t2-modified-immediate-fixup-error2.s @@ -6,13 +6,7 @@ @ mov with :upper16: or :lower16: should not match mov with modified immediate mov r0, :upper16: sym0 -@ CHECK: error: invalid instruction, any one of the following would fix this: -@ CHECK: note: instruction requires: arm-mode -@ CHECK: note: invalid operand for instruction -@ CHECK: note: immediate operand must be in the range [256,65535] +@ CHECK: error: instruction requires: arm-mode mov r0, :lower16: sym0 -@ CHECK: error: invalid instruction, any one of the following would fix this: -@ CHECK: note: instruction requires: arm-mode -@ CHECK: note: invalid operand for instruction -@ CHECK: note: immediate operand must be in the range [256,65535] +@ CHECK: error: instruction requires: arm-mode .equ sym0, 0x01abcdef Index: test/MC/ARM/thumb-diagnostics.s =================================================================== --- test/MC/ARM/thumb-diagnostics.s +++ test/MC/ARM/thumb-diagnostics.s @@ -11,23 +11,16 @@ @ ADD instruction w/o 'S' suffix. add r1, r2, r3 -@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this: +@ CHECK-ERRORS: error: no flag-preserving variant of this instruction available @ CHECK-ERRORS: add r1, r2, r3 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: note: instruction requires: arm-mode -@ CHECK-ERRORS: note: instruction requires: thumb2 -@ CHECK-ERRORS: note: invalid operand for instruction -@ CHECK-ERRORS: note: immediate operand must be in the range [0,7] -@ CHECK-ERRORS: note: no flag-preserving variant of this instruction available @ Instructions which require v6+ for both registers to be low regs. add r2, r3 mov r2, r3 -@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this: +@ CHECK-ERRORS: error: instruction variant requires Thumb2 @ CHECK-ERRORS: add r2, r3 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: note: instruction variant requires Thumb2 -@ CHECK-ERRORS: note: invalid operand for instruction @ CHECK-ERRORS-V5: error: instruction variant requires ARMv6 or later @ CHECK-ERRORS-V5: mov r2, r3 @ CHECK-ERRORS-V5: ^ @@ -35,45 +28,32 @@ @ Out of range immediates for ASR instruction. asrs r2, r3, #33 -@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this: +@ CHECK-ERRORS: error: immediate operand must be in the range [0,32] @ CHECK-ERRORS: asrs r2, r3, #33 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: note: immediate operand must be in the range [1,32] -@ CHECK-ERRORS: note: too many operands for instruction @ Out of range immediates for BKPT instruction. bkpt #256 bkpt #-1 -@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this: -@ CHECK-ERRORS: bkpt #256 -@ CHECK-ERRORS: ^ -@ CHECK-ERRORS: note: instruction requires: arm-mode -@ CHECK-ERRORS: note: immediate operand must be in the range [0,255] -@ CHECK-ERRORS: note: too many operands for instruction - -@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this: -@ CHECK-ERRORS: bkpt #-1 -@ CHECK-ERRORS: ^ -@ CHECK-ERRORS: note: immediate operand must be in the range [0,255] -@ CHECK-ERRORS: note: too many operands for instruction +error: invalid operand for instruction + bkpt #256 + ^ +error: invalid operand for instruction + bkpt #-1 + ^ @ Out of range immediates for v8 HLT instruction. hlt #64 hlt #-1 -@CHECK-ERRORS: error: invalid instruction +@CHECK-ERRORS: error: instruction requires: armv8 arm-mode @CHECK-ERRORS: hlt #64 @CHECK-ERRORS: ^ -@CHECK-ERRORS-V8: error: invalid instruction, any one of the following would fix this: +@CHECK-ERRORS-V8: error: instruction requires: arm-mode @CHECK-ERRORS-V8: hlt #64 @CHECK-ERRORS-V8: ^ -@CHECK-ERRORS-V8: note: instruction requires: arm-mode -@CHECK-ERRORS-V8: immediate operand must be in the range [0,63] -@CHECK-ERRORS: error: invalid instruction -@CHECK-ERRORS: hlt #-1 -@CHECK-ERRORS: ^ -@CHECK-ERRORS-V8: error: immediate operand must be in the range [0,63] -@CHECK-ERRORS-V8: hlt #-1 -@CHECK-ERRORS-V8: ^ +@CHECK-ERRORS: error: immediate operand must be in the range [0,65535] +@CHECK-ERRORS: hlt #-1 +@CHECK-ERRORS: ^ @ Invalid writeback and register lists for LDM ldm r2!, {r5, r8} @@ -145,11 +125,9 @@ stmia r4!, {r0-r3, sp} stmdb r1, {r2, r3, sp} stmdb r1!, {r2, r3, sp} -@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this: +@ CHECK-ERRORS: error: instruction requires: thumb2 @ CHECK-ERRORS: stm r1, {r2, r6} @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: note: instruction requires: thumb2 -@ CHECK-ERRORS: note: instruction requires: arm-mode @ CHECK-ERRORS: error: registers must be in range r0-r7 @ CHECK-ERRORS: stm r1!, {r2, r9} @ CHECK-ERRORS: ^ @@ -175,16 +153,12 @@ @ Out of range immediates for LSL instruction. lsls r4, r5, #-1 lsls r4, r5, #32 -@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this: +@ CHECK-ERRORS: error: immediate operand must be in the range [0,31] @ CHECK-ERRORS: lsls r4, r5, #-1 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: note: immediate operand must be in the range [0,31] -@ CHECK-ERRORS: note: too many operands for instruction -@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this: +@ CHECK-ERRORS: error: immediate operand must be in the range [0,31] @ CHECK-ERRORS: lsls r4, r5, #32 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: note: immediate operand must be in the range [0,31] -@ CHECK-ERRORS: note: too many operands for instruction @ Mismatched source/destination operands for MUL instruction. muls r1, r2, r3 @@ -197,36 +171,25 @@ str r2, [r7, #-1] str r5, [r1, #3] str r3, [r7, #128] -@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this: +@ CHECK-ERRORS: error: instruction requires: thumb2 @ CHECK-ERRORS: str r2, [r7, #-1] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: note: instruction requires: thumb2 -@ CHECK-ERRORS: note: instruction requires: arm-mode -@ CHECK-ERRORS: note: invalid operand for instruction -@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this: +@ CHECK-ERRORS: error: instruction requires: thumb2 @ CHECK-ERRORS: str r5, [r1, #3] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: note: instruction requires: thumb2 -@ CHECK-ERRORS: note: instruction requires: arm-mode -@ CHECK-ERRORS: note: invalid operand for instruction -@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this: +@ CHECK-ERRORS: error: instruction requires: thumb2 @ CHECK-ERRORS: str r3, [r7, #128] @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: note: instruction requires: thumb2 -@ CHECK-ERRORS: note: instruction requires: arm-mode -@ CHECK-ERRORS: note: invalid operand for instruction @ Out of range immediate for SVC instruction. svc #-1 svc #256 -@ CHECK-ERRORS: error: immediate operand must be in the range [0,255] +@ CHECK-ERRORS: error: immediate operand must be in the range [0,0xffffff] @ CHECK-ERRORS: svc #-1 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this: +@ CHECK-ERRORS: error: instruction requires: arm-mode @ CHECK-ERRORS: svc #256 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: note: instruction requires: arm-mode -@ CHECK-ERRORS: note: immediate operand must be in the range [0,255] @ Out of range immediate for ADD SP instructions @@ -234,21 +197,15 @@ add sp, #3 add sp, sp, #512 add r2, sp, #1024 -@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this: +@ CHECK-ERRORS: error: instruction requires: thumb2 @ CHECK-ERRORS: add sp, #-1 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: note: invalid operand for instruction -@ CHECK-ERRORS: note: instruction requires: thumb2 -@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this: +@ CHECK-ERRORS: error: instruction requires: thumb2 @ CHECK-ERRORS: add sp, #3 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: note: invalid operand for instruction -@ CHECK-ERRORS: note: instruction requires: thumb2 -@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this: +@ CHECK-ERRORS: error: instruction requires: thumb2 @ CHECK-ERRORS: add sp, sp, #512 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: note: invalid operand for instruction -@ CHECK-ERRORS: note: instruction requires: thumb2 @ CHECK-ERRORS: error: instruction requires: thumb2 @ CHECK-ERRORS: add r2, sp, #1024 @ CHECK-ERRORS: ^ @@ -326,10 +283,7 @@ @------------------------------------------------------------------------------ ldr r4, [pc, #-12] -@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this: -@ CHECK-ERRORS: note: instruction requires: thumb2 -@ CHECK-ERRORS: note: instruction requires: arm-mode -@ CHECK-ERRORS: note: invalid operand for instruction +@ CHECK-ERRORS: error: instruction requires: thumb2 @------------------------------------------------------------------------------ @ STC2{L}/LDC2{L} - requires thumb2 @@ -338,7 +292,7 @@ stc2l p6, c2, [r7, #4] ldc2 p0, c8, [r1, #4] ldc2l p6, c2, [r7, #4] -@ CHECK-ERRORS: error: invalid instruction -@ CHECK-ERRORS: error: invalid instruction -@ CHECK-ERRORS: error: invalid instruction -@ CHECK-ERRORS: error: invalid instruction +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: invalid operand for instruction Index: test/MC/ARM/thumb-mov.s =================================================================== --- test/MC/ARM/thumb-mov.s +++ test/MC/ARM/thumb-mov.s @@ -17,7 +17,7 @@ // CHECK-NEXT: movs pc, r0 // CHECK: error: invalid operand for instruction // CHECK-NEXT: movs r0, pc -// CHECK: error: invalid instruction +// CHECK: error: invalid operand for instruction // CHECK-NEXT: movs pc, pc // mov.w selects t2MOVr @@ -28,7 +28,7 @@ // CHECK-NEXT: mov.w pc, r0 // CHECK: error: invalid operand for instruction // CHECK-NEXT: mov.w r0, pc -// CHECK: error: invalid instruction +// CHECK: error: invalid operand for instruction // CHECK-NEXT: mov.w pc, pc // movs.w selects t2MOVr @@ -39,7 +39,7 @@ // CHECK-NEXT: movs.w pc, r0 // CHECK: error: invalid operand for instruction // CHECK-NEXT: movs.w r0, pc -// CHECK: error: invalid instruction +// CHECK: error: invalid operand for instruction // CHECK-NEXT: movs.w pc, pc @@ -50,7 +50,7 @@ movs sp, sp // CHECK-V7: error: instruction variant requires ARMv8 or later // CHECK-V7-NEXT: movs sp, r0 -// CHECK-V7: instruction variant requires ARMv8 or later +// CHECK-V7: error: instruction variant requires ARMv8 or later // CHECK-V7-NEXT: movs r0, sp // CHECK-V7: error: instruction variant requires ARMv8 or later // CHECK-V7-NEXT: movs sp, sp @@ -68,7 +68,7 @@ movs.w sp, sp // CHECK-V7: error: instruction variant requires ARMv8 or later // CHECK-V7-NEXT: movs.w sp, r0 -// CHECK-V7: instruction variant requires ARMv8 or later +// CHECK-V7: error: instruction variant requires ARMv8 or later // CHECK-V7-NEXT: movs.w r0, sp // CHECK-V7: error: instruction variant requires ARMv8 or later // CHECK-V7-NEXT: movs.w sp, sp Index: test/MC/ARM/thumb-not-mclass.s =================================================================== --- test/MC/ARM/thumb-not-mclass.s +++ test/MC/ARM/thumb-not-mclass.s @@ -13,7 +13,7 @@ @------------------------------------------------------------------------------ blx _baz -@ CHECK: instruction requires: !armv*m +@ CHECK: error: instruction requires: !armv*m @------------------------------------------------------------------------------ @ SETEND @@ -22,5 +22,5 @@ setend be setend le -@ CHECK: error: invalid instruction -@ CHECK: error: invalid instruction +@ CHECK: error: immediate operand must be in the range [0,1] +@ CHECK: error: immediate operand must be in the range [0,1] Index: test/MC/ARM/thumb2-bxj-v8.s =================================================================== --- test/MC/ARM/thumb2-bxj-v8.s +++ test/MC/ARM/thumb2-bxj-v8.s @@ -8,4 +8,4 @@ @ CHECK: bxj sp @ encoding: [0xcd,0xf3,0x00,0x8f] @ UNDEF: error: r13 (SP) is an unpredictable operand to BXJ -@ ARM_MODE: error: instruction requires: !armv*m +@ ARM_MODE: error: instruction requires: arm-mode Index: test/MC/ARM/thumb2-bxj.s =================================================================== --- test/MC/ARM/thumb2-bxj.s +++ test/MC/ARM/thumb2-bxj.s @@ -7,4 +7,4 @@ bxj r2 @ CHECK: bxj r2 @ encoding: [0xc2,0xf3,0x00,0x8f] -@ UNDEF: error: instruction requires: !armv*m +@ UNDEF: error: instruction requires: arm-mode Index: test/MC/ARM/thumb2-diagnostics.s =================================================================== --- test/MC/ARM/thumb2-diagnostics.s +++ test/MC/ARM/thumb2-diagnostics.s @@ -39,15 +39,13 @@ mrc2 p14, #0, r1, c1, c2, #9 mrrc p7, #16, r5, r4, c1 mrrc2 p7, #17, r5, r4, c1 -@ CHECK-ERRORS: immediate operand must be in the range [0,7] -@ CHECK-ERRORS: immediate operand must be in the range [0,7] -@ CHECK-ERRORS-V7: immediate operand must be in the range [0,7] -@ CHECK-ERRORS-V7: immediate operand must be in the range [0,7] -@ CHECK-ERRORS-V8: invalid instruction -@ CHECK-ERRORS-V8: too many operands for instruction -@ CHECK-ERRORS: immediate operand must be in the range [0,15] -@ CHECK-ERRORS-V7: immediate operand must be in the range [0,15] -@ CHECK-ERRORS-V8: invalid instruction +@ CHECK-ERRORS: error: immediate operand must be in the range [0,7] +@ CHECK-ERRORS: error: immediate operand must be in the range [0,7] +@ CHECK-ERRORS: error: immediate operand must be in the range [0,7] +@ CHECK-ERRORS: error: immediate operand must be in the range [0,7] +@ CHECK-ERRORS: error: immediate operand must be in the range [0,15] +@ CHECK-ERRORS-V7: error: immediate operand must be in the range [0,15] +@ CHECK-ERRORS-V8: error: invalid operand for instruction isb #-1 isb #16 @@ -82,14 +80,13 @@ movt r0, foo2 @ CHECK-ERRORS: error: immediate expression for mov requires :lower16: or :upper16 @ CHECK-ERRORS: ^ -@ CHECK-ERRORS: immediate expression for mov requires :lower16: or :upper16 +@ CHECK-ERRORS: error: immediate expression for mov requires :lower16: or :upper16 @ CHECK-ERRORS: ^ and sp, r1, #80008000 and pc, r1, #80008000 -@ CHECK-ERRORS-V7: error: invalid instruction -@ CHECK-ERRORS-V8: error: invalid operand for instruction -@ CHECK-ERRORS: error: invalid instruction +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: invalid operand for instruction ssat r0, #1, r0, asr #32 usat r0, #1, r0, asr #32 @@ -99,12 +96,8 @@ @ PC is not valid as shifted-rGPR sbc.w r2, r7, pc, lsr #16 and.w r2, r7, pc, lsr #16 -@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this: -@ CHECK-ERRORS: note: invalid operand for instruction -@ CHECK-ERRORS: note: invalid operand for instruction -@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this: -@ CHECK-ERRORS: note: invalid operand for instruction -@ CHECK-ERRORS: note: invalid operand for instruction +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: invalid operand for instruction @ PC is not valid as base of load @@ -115,28 +108,16 @@ str r6, [pc, r7] strb r7 [pc, r8] strh r9, [pc, r10] -@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this: -@ CHECK-ERRORS: note: invalid operand for instruction -@ CHECK-ERRORS: note: instruction requires: arm-mode -@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this: -@ CHECK-ERRORS: note: invalid operand for instruction -@ CHECK-ERRORS: note: instruction requires: arm-mode -@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this: -@ CHECK-ERRORS: note: instruction requires: arm-mode -@ CHECK-ERRORS: note: invalid operand for instruction -@ CHECK-ERRORS: error: invalid instruction -@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this: -@ CHECK-ERRORS: note: invalid operand for instruction -@ CHECK-ERRORS: note: instruction requires: arm-mode +@ CHECK-ERRORS: error: instruction requires: arm-mode +@ CHECK-ERRORS: error: instruction requires: arm-mode +@ CHECK-ERRORS: error: instruction requires: arm-mode +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: error: instruction requires: arm-mode @ CHECK-ERRORS: error: immediate value expected for vector index -@ CHECK-ERRORS: error: invalid instruction, any one of the following would fix this: -@ CHECK-ERRORS: note: instruction requires: arm-mode -@ CHECK-ERRORS: note: invalid operand for instruction +@ CHECK-ERRORS: error: instruction requires: arm-mode @ SWP(B) is an ARM-only instruction swp r0, r1, [r2] swpb r3, r4, [r5] -@ CHECK-ERRORS-V7: error: instruction requires: arm-mode -@ CHECK-ERRORS-V7: error: instruction requires: arm-mode -@ CHECK-ERRORS-V8: error: invalid instruction -@ CHECK-ERRORS-V8: error: invalid instruction +@ CHECK-ERRORS: error: instruction requires: arm-mode +@ CHECK-ERRORS: error: instruction requires: arm-mode Index: test/MC/ARM/thumb2-dsp-diag.s =================================================================== --- test/MC/ARM/thumb2-dsp-diag.s +++ test/MC/ARM/thumb2-dsp-diag.s @@ -6,11 +6,11 @@ sxtab16 r0, r0, r0 sxtb16 r0, r0 sxtb16 r0, r0, ror #8 -@ CHECK-ERRORS: error: instruction requires: dsp -@ CHECK-ERRORS: error: instruction requires: dsp -@ CHECK-ERRORS: error: instruction requires: dsp -@ CHECK-ERRORS: error: instruction requires: dsp -@ CHECK-ERRORS: error: invalid instruction +@ CHECK-ERRORS: error: instruction requires: arm-mode +@ CHECK-ERRORS: error: instruction requires: arm-mode +@ CHECK-ERRORS: error: instruction requires: arm-mode +@ CHECK-ERRORS: error: instruction requires: arm-mode +@ CHECK-ERRORS: error: invalid operand for instruction @ CHECK-7EM: sxtab r0, r0, r0 @ encoding: [0x40,0xfa,0x80,0xf0] @ CHECK-7EM: sxtah r0, r0, r0 @ encoding: [0x00,0xfa,0x80,0xf0] @ CHECK-7EM: sxtab16 r0, r0, r0 @ encoding: [0x20,0xfa,0x80,0xf0] @@ -22,11 +22,11 @@ uxtab16 r0, r0, r0 uxtb16 r0, r0 uxtb16 r0, r0, ror #8 -@ CHECK-ERRORS: error: instruction requires: dsp -@ CHECK-ERRORS: error: instruction requires: dsp -@ CHECK-ERRORS: error: instruction requires: dsp -@ CHECK-ERRORS: error: instruction requires: dsp -@ CHECK-ERRORS: error: invalid instruction +@ CHECK-ERRORS: error: instruction requires: arm-mode +@ CHECK-ERRORS: error: instruction requires: arm-mode +@ CHECK-ERRORS: error: instruction requires: arm-mode +@ CHECK-ERRORS: error: instruction requires: arm-mode +@ CHECK-ERRORS: error: invalid operand for instruction @ CHECK-7EM: uxtab r0, r0, r0 @ encoding: [0x50,0xfa,0x80,0xf0] @ CHECK-7EM: uxtah r0, r0, r0 @ encoding: [0x10,0xfa,0x80,0xf0] @ CHECK-7EM: uxtab16 r0, r0, r0 @ encoding: [0x30,0xfa,0x80,0xf0] Index: test/MC/ARM/thumbv7m.s =================================================================== --- test/MC/ARM/thumbv7m.s +++ test/MC/ARM/thumbv7m.s @@ -30,16 +30,16 @@ @ CHECK: msr basepri_max, r0 @ encoding: [0x80,0xf3,0x12,0x88] @ CHECK: msr faultmask, r0 @ encoding: [0x80,0xf3,0x13,0x88] -@ CHECK-V6M: error: invalid instruction +@ CHECK-V6M: error: invalid operand for instruction @ CHECK-V6M-NEXT: mrs r0, basepri -@ CHECK-V6M: error: invalid instruction +@ CHECK-V6M: error: invalid operand for instruction @ CHECK-V6M-NEXT: mrs r0, basepri_max -@ CHECK-V6M: error: invalid instruction +@ CHECK-V6M: error: invalid operand for instruction @ CHECK-V6M-NEXT: mrs r0, faultmask -@ CHECK-V6M: error: invalid instruction +@ CHECK-V6M: error: invalid operand for instruction @ CHECK-V6M-NEXT: msr basepri, r0 -@ CHECK-V6M: error: invalid instruction +@ CHECK-V6M: error: invalid operand for instruction @ CHECK-V6M-NEXT: msr basepri_max, r0 -@ CHECK-V6M: error: invalid instruction +@ CHECK-V6M: error: invalid operand for instruction @ CHECK-V6M-NEXT: msr faultmask, r0 Index: test/MC/ARM/thumbv8m.s =================================================================== --- test/MC/ARM/thumbv8m.s +++ test/MC/ARM/thumbv8m.s @@ -19,12 +19,12 @@ .arm // And only +dsp has DSP and instructions -// UNDEF-BASELINE: error: instruction requires: dsp thumb2 -// UNDEF-MAINLINE: error: instruction requires: dsp +// UNDEF-BASELINE: error: instruction requires: arm-mode +// UNDEF-MAINLINE: error: instruction requires: arm-mode // UNDEF-MAINLINE_DSP-NOT: error: instruction requires: qadd16 r0, r0, r0 -// UNDEF-BASELINE: error: instruction requires: dsp thumb2 -// UNDEF-MAINLINE: error: instruction requires: dsp +// UNDEF-BASELINE: error: instruction requires: arm-mode +// UNDEF-MAINLINE: error: instruction requires: arm-mode // UNDEF-MAINLINE_DSP-NOT: error: instruction requires: uxtab16 r0, r1, r2 @@ -146,7 +146,7 @@ // CHECK: bxns r0 @ encoding: [0x04,0x47] bxns r0 -// UNDEF-BASELINE: error: invalid instruction +// UNDEF-BASELINE: error: invalid operand for instruction // UNDEF-BASELINE: error: conditional execution not supported in Thumb1 // CHECK-MAINLINE: it eq @ encoding: [0x08,0xbf] // CHECK-MAINLINE: bxnseq r1 @ encoding: [0x0c,0x47] @@ -159,7 +159,7 @@ // CHECK: blxns r0 @ encoding: [0x84,0x47] blxns r0 -// UNDEF-BASELINE: error: invalid instruction +// UNDEF-BASELINE: error: invalid operand for instruction // UNDEF-BASELINE: error: conditional execution not supported in Thumb1 // CHECK-MAINLINE: it eq @ encoding: [0x08,0xbf] // CHECK-MAINLINE: blxnseq r1 @ encoding: [0x8c,0x47] @@ -226,28 +226,28 @@ // UNDEF-BASELINE: error: invalid operand for instruction // Invalid operand tests -// UNDEF: error: too many operands for instruction +// UNDEF: error: invalid operand for instruction // UNDEF: sg #0 sg #0 -// UNDEF: error: too many operands for instruction +// UNDEF: error: invalid operand for instruction // UNDEF: sg r0 sg r0 -// UNDEF: error: too many operands for instruction +// UNDEF: error: invalid operand for instruction // UNDEF: bxns r0, r1 bxns r0, r1 -// UNDEF: error: too many operands for instruction +// UNDEF: error: invalid operand for instruction // UNDEF: blxns r0, #0 blxns r0, #0 // UNDEF: error: invalid operand for instruction // UNDEF: blxns label blxns label -// UNDEF: error: too many operands for instruction +// UNDEF: error: invalid operand for instruction // UNDEF: tt r0, r1, r2 tt r0, r1, r2 // UNDEF: error: invalid operand for instruction // UNDEF: tt r0, [r1] tt r0, [r1] -// UNDEF: error: too many operands for instruction +// UNDEF: error: invalid operand for instruction // UNDEF: tt r0, r1, #4 tt r0, r1, #4 // UNDEF: error: invalid operand for instruction @@ -268,12 +268,10 @@ // UNDEF: tt r0, pc tt r0, pc -// UNDEF-BASELINE: error: invalid instruction -// UNDEF-MAINLINE: error: invalid operand for instruction +// UNDEF: error: invalid operand for instruction // UNDEF: vlldm pc vlldm pc -// UNDEF-BASELINE: error: invalid instruction -// UNDEF-MAINLINE: error: invalid operand for instruction +// UNDEF: error: invalid operand for instruction // UNDEF: vlstm pc vlstm pc Index: test/MC/ARM/udf-thumb-2-diagnostics.s =================================================================== --- test/MC/ARM/udf-thumb-2-diagnostics.s +++ test/MC/ARM/udf-thumb-2-diagnostics.s @@ -13,9 +13,7 @@ udf #256 -@ CHECK: error: invalid instruction, any one of the following would fix this: -@ CHECK: note: instruction requires: arm-mode -@ CHECK: note: immediate operand must be in the range [0,255] +@ CHECK: error: instruction requires: arm-mode @ CHECK: udf #256 @ CHECK: ^ Index: test/MC/ARM/udf-thumb-diagnostics.s =================================================================== --- test/MC/ARM/udf-thumb-diagnostics.s +++ test/MC/ARM/udf-thumb-diagnostics.s @@ -13,7 +13,7 @@ udf #256 -@ CHECK: error: immediate operand must be in the range [0,255] +@ CHECK: error: instruction requires: arm-mode @ CHECK: udf #256 -@ CHECK: ^ +@ CHECK: ^ Index: test/MC/ARM/vfp4.s =================================================================== --- test/MC/ARM/vfp4.s +++ test/MC/ARM/vfp4.s @@ -6,7 +6,7 @@ @ ARM: vfma.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0xe2,0xee] @ THUMB: vfma.f64 d16, d18, d17 @ encoding: [0xe2,0xee,0xa1,0x0b] -@ THUMB_V7EM-ERRORS: error: invalid instruction +@ THUMB_V7EM-ERRORS: error: invalid operand for instruction @ THUMB_V7EM-ERRORS-NEXT: vfma.f64 d16, d18, d17 vfma.f64 d16, d18, d17 @@ -17,7 +17,7 @@ @ ARM: vfma.f32 d16, d18, d17 @ encoding: [0xb1,0x0c,0x42,0xf2] @ THUMB: vfma.f32 d16, d18, d17 @ encoding: [0x42,0xef,0xb1,0x0c] -@ THUMB_V7EM-ERRORS: error: invalid instruction +@ THUMB_V7EM-ERRORS: error: invalid operand for instruction @ THUMB_V7EM-ERRORS-NEXT: vfma.f32 d16, d18, d17 vfma.f32 d16, d18, d17 @@ -29,7 +29,7 @@ @ ARM: vfnma.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0xd2,0xee] @ THUMB: vfnma.f64 d16, d18, d17 @ encoding: [0xd2,0xee,0xe1,0x0b] -@ THUMB_V7EM-ERRORS: error: invalid instruction +@ THUMB_V7EM-ERRORS: error: invalid operand for instruction @ THUMB_V7EM-ERRORS-NEXT: vfnma.f64 d16, d18, d17 vfnma.f64 d16, d18, d17 @@ -40,7 +40,7 @@ @ ARM: vfms.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0xe2,0xee] @ THUMB: vfms.f64 d16, d18, d17 @ encoding: [0xe2,0xee,0xe1,0x0b] -@ THUMB_V7EM-ERRORS: error: invalid instruction +@ THUMB_V7EM-ERRORS: error: invalid operand for instruction @ THUMB_V7EM-ERRORS-NEXT: vfms.f64 d16, d18, d17 vfms.f64 d16, d18, d17 @@ -51,7 +51,7 @@ @ ARM: vfms.f32 d16, d18, d17 @ encoding: [0xb1,0x0c,0x62,0xf2] @ THUMB: vfms.f32 d16, d18, d17 @ encoding: [0x62,0xef,0xb1,0x0c] -@ THUMB_V7EM-ERRORS: error: invalid instruction +@ THUMB_V7EM-ERRORS: error: invalid operand for instruction @ THUMB_V7EM-ERRORS-NEXT: vfms.f32 d16, d18, d17 vfms.f32 d16, d18, d17 @@ -63,7 +63,7 @@ @ ARM: vfnms.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0xd2,0xee] @ THUMB: vfnms.f64 d16, d18, d17 @ encoding: [0xd2,0xee,0xa1,0x0b] -@ THUMB_V7EM-ERRORS: error: invalid instruction +@ THUMB_V7EM-ERRORS: error: invalid operand for instruction @ THUMB_V7EM-ERRORS-NEXT: vfnms.f64 d16, d18, d17 vfnms.f64 d16, d18, d17 Index: test/MC/ARM/vmrs_vmsr.s =================================================================== --- test/MC/ARM/vmrs_vmsr.s +++ test/MC/ARM/vmrs_vmsr.s @@ -112,8 +112,8 @@ // ERROR-NOVFP: instruction requires: VFP2 // ERROR-NOVFP: instruction requires: VFP2 // ERROR-NOVFP: instruction requires: FPARMv8 -// ERROR-NOVFP: invalid instruction -// ERROR-NOVFP: invalid instruction +// ERROR-NOVFP: instruction requires: VFP2 +// ERROR-NOVFP: invalid operand for instruction vmsr fpscr, APSR_nzcv vmsr fpscr, r0 @@ -171,10 +171,10 @@ // ERROR-V8M: invalid operand for instruction // ERROR-V8M: invalid operand for instruction -// ERROR-NOVFP: invalid instruction +// ERROR-NOVFP: invalid operand for instruction +// ERROR-NOVFP: instruction requires: VFP2 // ERROR-NOVFP: instruction requires: VFP2 // ERROR-NOVFP: instruction requires: VFP2 // ERROR-NOVFP: instruction requires: VFP2 // ERROR-NOVFP: instruction requires: VFP2 -// ERROR-NOVFP: invalid instruction -// ERROR-NOVFP: invalid instruction +// ERROR-NOVFP: invalid operand for instruction Index: test/MC/WebAssembly/init-fini-array.ll =================================================================== --- test/MC/WebAssembly/init-fini-array.ll +++ /dev/null @@ -1,101 +0,0 @@ -; RUN: llc -mtriple wasm32-unknown-unknown-wasm -filetype=obj %s -o - | obj2yaml | FileCheck %s - -@global1 = global i32 1025, align 8 - -declare void @func1() - -declare void @func2() - -@llvm.global_ctors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 65535, void ()* @func1, i8* null }] - -@llvm.global_dtors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 65535, void ()* @func2, i8* null }] - - -; CHECK: - Type: IMPORT -; CHECK-NEXT: Imports: -; CHECK-NEXT: - Module: env -; CHECK-NEXT: Field: func1 -; CHECK-NEXT: Kind: FUNCTION -; CHECK-NEXT: SigIndex: 0 -; CHECK-NEXT: - Module: env -; CHECK-NEXT: Field: func2 -; CHECK-NEXT: Kind: FUNCTION -; CHECK-NEXT: SigIndex: 0 -; CHECK-NEXT: - Type: TABLE -; CHECK-NEXT: Tables: -; CHECK-NEXT: - ElemType: ANYFUNC -; CHECK-NEXT: Limits: -; CHECK-NEXT: Initial: 0x00000002 -; CHECK-NEXT: - Type: MEMORY -; CHECK-NEXT: Memories: -; CHECK-NEXT: - Initial: 0x00000001 -; CHECK-NEXT: - Type: GLOBAL -; CHECK-NEXT: Globals: -; CHECK-NEXT: - Type: I32 -; CHECK-NEXT: Mutable: false -; CHECK-NEXT: InitExpr: -; CHECK-NEXT: Opcode: I32_CONST -; CHECK-NEXT: Value: 0 -; CHECK-NEXT: - Type: EXPORT -; CHECK-NEXT: Exports: -; CHECK-NEXT: - Name: global1 -; CHECK-NEXT: Kind: GLOBAL -; CHECK-NEXT: Index: 0 -; CHECK-NEXT: - Type: ELEM -; CHECK-NEXT: Segments: -; CHECK-NEXT: - Offset: -; CHECK-NEXT: Opcode: I32_CONST -; CHECK-NEXT: Value: 0 -; CHECK-NEXT: Functions: [ 0, 1 ] -; CHECK-NEXT: - Type: DATA -; CHECK-NEXT: Relocations: -; CHECK-NEXT: - Type: R_WEBASSEMBLY_TABLE_INDEX_I32 -; CHECK-NEXT: Index: 0 -; CHECK-NEXT: Offset: 0x0000000F -; CHECK-NEXT: - Type: R_WEBASSEMBLY_TABLE_INDEX_I32 -; CHECK-NEXT: Index: 1 -; CHECK-NEXT: Offset: 0x00000018 -; CHECK-NEXT: Segments: -; CHECK-NEXT: - SectionOffset: 6 -; CHECK-NEXT: MemoryIndex: 0 -; CHECK-NEXT: Offset: -; CHECK-NEXT: Opcode: I32_CONST -; CHECK-NEXT: Value: 0 -; CHECK-NEXT: Content: '01040000' -; CHECK-NEXT: - SectionOffset: 15 -; CHECK-NEXT: MemoryIndex: 0 -; CHECK-NEXT: Offset: -; CHECK-NEXT: Opcode: I32_CONST -; CHECK-NEXT: Value: 4 -; CHECK-NEXT: Content: '00000000' -; CHECK-NEXT: - SectionOffset: 24 -; CHECK-NEXT: MemoryIndex: 0 -; CHECK-NEXT: Offset: -; CHECK-NEXT: Opcode: I32_CONST -; CHECK-NEXT: Value: 8 -; CHECK-NEXT: Content: '01000000' -; CHECK-NEXT: - Type: CUSTOM -; CHECK-NEXT: Name: name -; CHECK-NEXT: FunctionNames: -; CHECK-NEXT: - Index: 0 -; CHECK-NEXT: Name: func1 -; CHECK-NEXT: - Index: 1 -; CHECK-NEXT: Name: func2 -; CHECK-NEXT: - Type: CUSTOM -; CHECK-NEXT: Name: linking -; CHECK-NEXT: DataSize: 12 -; CHECK-NEXT: SegmentInfo: -; CHECK-NEXT: - Index: 0 -; CHECK-NEXT: Name: .data.global1 -; CHECK-NEXT: Alignment: 8 -; CHECK-NEXT: Flags: 0 -; CHECK-NEXT: - Index: 1 -; CHECK-NEXT: Name: .init_array -; CHECK-NEXT: Alignment: 4 -; CHECK-NEXT: Flags: 0 -; CHECK-NEXT: - Index: 2 -; CHECK-NEXT: Name: .fini_array -; CHECK-NEXT: Alignment: 4 -; CHECK-NEXT: Flags: 0 -; CHECK-NEXT: ... - Index: test/Object/AMDGPU/elf-definitions.yaml =================================================================== --- test/Object/AMDGPU/elf-definitions.yaml +++ test/Object/AMDGPU/elf-definitions.yaml @@ -1,7 +1,7 @@ # RUN: yaml2obj %s > %t.o # RUN: llvm-readobj -s -file-headers %t.o | FileCheck %s -# CHECK: Format: ELF64-amdgpu +# CHECK: Format: ELF64-amdgpu-hsacobj # CHECK: Arch: amdgcn # CHECK: ElfHeader { # CHECK: Ident { Index: test/Object/AMDGPU/elf64-amdgcn-amdpal-definitions.yaml =================================================================== --- test/Object/AMDGPU/elf64-amdgcn-amdpal-definitions.yaml +++ /dev/null @@ -1,21 +0,0 @@ -# RUN: yaml2obj %s > %t.o -# RUN: llvm-readobj -s -file-headers %t.o | FileCheck %s - -# CHECK: Format: ELF64-amdgpu -# CHECK: Arch: amdgcn -# CHECK: ElfHeader { -# CHECK: Ident { -# CHECK: OS/ABI: AMDGPU_PAL (0x41) -# CHECK: ABIVersion: 0 -# CHECK: } -# CHECK: Machine: EM_AMDGPU (0xE0) -# CHECK: } - ---- !ELF -FileHeader: - Class: ELFCLASS64 - Data: ELFDATA2LSB - Type: ET_REL - Machine: EM_AMDGPU - OSABI: ELFOSABI_AMDGPU_PAL -... Index: test/Object/AMDGPU/elf64-amdgcn-mesa3d-definitions.yaml =================================================================== --- test/Object/AMDGPU/elf64-amdgcn-mesa3d-definitions.yaml +++ /dev/null @@ -1,21 +0,0 @@ -# RUN: yaml2obj %s > %t.o -# RUN: llvm-readobj -s -file-headers %t.o | FileCheck %s - -# CHECK: Format: ELF64-amdgpu -# CHECK: Arch: amdgcn -# CHECK: ElfHeader { -# CHECK: Ident { -# CHECK: OS/ABI: AMDGPU_MESA3D (0x42) -# CHECK: ABIVersion: 0 -# CHECK: } -# CHECK: Machine: EM_AMDGPU (0xE0) -# CHECK: } - ---- !ELF -FileHeader: - Class: ELFCLASS64 - Data: ELFDATA2LSB - Type: ET_REL - Machine: EM_AMDGPU - OSABI: ELFOSABI_AMDGPU_MESA3D -... Index: test/Object/AMDGPU/objdump.s =================================================================== --- test/Object/AMDGPU/objdump.s +++ test/Object/AMDGPU/objdump.s @@ -45,7 +45,7 @@ v_lshlrev_b32_e32 v7, 2, v7 s_endpgm -// CHECK: file format ELF64-amdgpu +// CHECK: file format ELF64-amdgpu-hsacobj // CHECK: Disassembly of section .text: // CHECK: hello_world: // CHECK: s_mov_b32 m0, 0x10000 // 000000000100: BEFC00FF 00010000 Index: test/Object/RISCV/elf-flags.yaml =================================================================== --- test/Object/RISCV/elf-flags.yaml +++ /dev/null @@ -1,24 +0,0 @@ -# RUN: yaml2obj %s > %t -# RUN: llvm-readobj -file-headers %t | FileCheck -check-prefix=OBJ %s -# RUN: obj2yaml %t | FileCheck -check-prefix=YAML %s - -# OBJ: Flags [ (0xD) -# OBJ-NEXT: EF_RISCV_FLOAT_ABI_DOUBLE (0x4) -# OBJ-NEXT: EF_RISCV_RVC (0x1) -# OBJ-NEXT: EF_RISCV_RVE (0x8) -# OBJ-NEXT: ] - -# YAML: FileHeader: -# YAML-NEXT: Class: ELFCLASS32 -# YAML-NEXT: Data: ELFDATA2LSB -# YAML-NEXT: Type: ET_EXEC -# YAML-NEXT: Machine: EM_RISCV -# YAML-NEXT: Flags: [ EF_RISCV_RVC, EF_RISCV_FLOAT_ABI_DOUBLE, EF_RISCV_RVE ] - ---- !ELF -FileHeader: - Class: ELFCLASS32 - Data: ELFDATA2LSB - Type: ET_EXEC - Machine: EM_RISCV - Flags: [ EF_RISCV_RVC, EF_RISCV_FLOAT_ABI_DOUBLE, EF_RISCV_RVE ] Index: test/Object/RISCV/lit.local.cfg =================================================================== --- test/Object/RISCV/lit.local.cfg +++ /dev/null @@ -1,2 +0,0 @@ -if not 'RISCV' in config.root.targets: - config.unsupported = True Index: test/ObjectYAML/ELF/shf-compressed.yaml =================================================================== --- test/ObjectYAML/ELF/shf-compressed.yaml +++ /dev/null @@ -1,28 +0,0 @@ -# RUN: yaml2obj %s -o %t -# RUN: llvm-readobj -sections %t | FileCheck -check-prefix=OBJ %s -# RUN: obj2yaml %t | FileCheck -check-prefix=YAML %s - ---- !ELF -FileHeader: - Class: ELFCLASS32 - Data: ELFDATA2LSB - Type: ET_REL - Machine: EM_386 -Sections: - - Name: .debug_line - Type: SHT_PROGBITS - Flags: [ SHF_COMPRESSED ] - -# OBJ: Sections [ -# OBJ: Section { -# OBJ: Index: 1 -# OBJ-NEXT: Name: .debug_line (1) -# OBJ-NEXT: Type: SHT_PROGBITS (0x1) -# OBJ-NEXT: Flags [ (0x800) -# OBJ-NEXT: SHF_COMPRESSED (0x800) -# OBJ-NEXT: ] - -# YAML: Sections: -# YAML-NEXT: - Name: .debug_line -# YAML-NEXT: Type: SHT_PROGBITS -# YAML-NEXT: Flags: [ SHF_COMPRESSED ] Index: test/Transforms/CodeGenPrepare/X86/sink-addrmode.ll =================================================================== --- test/Transforms/CodeGenPrepare/X86/sink-addrmode.ll +++ test/Transforms/CodeGenPrepare/X86/sink-addrmode.ll @@ -251,20 +251,3 @@ exit: ret void } - -; Make sure we can eliminate a select when both arguments perform equivalent -; address computation. -define void @test10(i1 %cond, i64* %base) { -; CHECK-LABEL: @test10 -; CHECK: getelementptr i8, {{.+}} 40 -; CHECK-NOT: select -entry: - %gep1 = getelementptr inbounds i64, i64* %base, i64 5 - %gep1.casted = bitcast i64* %gep1 to i32* - %base.casted = bitcast i64* %base to i32* - %gep2 = getelementptr inbounds i32, i32* %base.casted, i64 10 - %casted.merged = select i1 %cond, i32* %gep1.casted, i32* %gep2 - %v = load i32, i32* %casted.merged, align 4 - call void @foo(i32 %v) - ret void -} Index: test/Transforms/InstCombine/icmp-shr-lt-gt.ll =================================================================== --- test/Transforms/InstCombine/icmp-shr-lt-gt.ll +++ /dev/null @@ -1,1790 +0,0 @@ -; RUN: opt < %s -instcombine -S | FileCheck %s - -define i1 @lshrugt_01_00(i4 %x) { -; CHECK-LABEL: @lshrugt_01_00( -; CHECK-NEXT: [[C:%.*]] = icmp ugt i4 %x, 1 -; CHECK-NEXT: ret i1 [[C]] -; - %s = lshr i4 %x, 1 - %c = icmp ugt i4 %s, 0 - ret i1 %c -} - -define i1 @lshrugt_01_01(i4 %x) { -; CHECK-LABEL: @lshrugt_01_01( -; CHECK-NEXT: [[C:%.*]] = icmp ugt i4 %x, 3 -; CHECK-NEXT: ret i1 [[C]] -; - %s = lshr i4 %x, 1 - %c = icmp ugt i4 %s, 1 - ret i1 %c -} - -define i1 @lshrugt_01_02(i4 %x) { -; CHECK-LABEL: @lshrugt_01_02( -; CHECK-NEXT: [[C:%.*]] = icmp ugt i4 %x, 5 -; CHECK-NEXT: ret i1 [[C]] -; - %s = lshr i4 %x, 1 - %c = icmp ugt i4 %s, 2 - ret i1 %c -} - -define i1 @lshrugt_01_03(i4 %x) { -; CHECK-LABEL: @lshrugt_01_03( -; CHECK-NEXT: [[C:%.*]] = icmp slt i4 %x, 0 -; CHECK-NEXT: ret i1 [[C]] -; - %s = lshr i4 %x, 1 - %c = icmp ugt i4 %s, 3 - ret i1 %c -} - -define i1 @lshrugt_01_04(i4 %x) { -; CHECK-LABEL: @lshrugt_01_04( -; CHECK-NEXT: [[C:%.*]] = icmp ugt i4 %x, -7 -; CHECK-NEXT: ret i1 [[C]] -; - %s = lshr i4 %x, 1 - %c = icmp ugt i4 %s, 4 - ret i1 %c -} - -define i1 @lshrugt_01_05(i4 %x) { -; CHECK-LABEL: @lshrugt_01_05( -; CHECK-NEXT: [[C:%.*]] = icmp ugt i4 %x, -5 -; CHECK-NEXT: ret i1 [[C]] -; - %s = lshr i4 %x, 1 - %c = icmp ugt i4 %s, 5 - ret i1 %c -} - -define i1 @lshrugt_01_06(i4 %x) { -; CHECK-LABEL: @lshrugt_01_06( -; CHECK-NEXT: [[C:%.*]] = icmp ugt i4 %x, -3 -; CHECK-NEXT: ret i1 [[C]] -; - %s = lshr i4 %x, 1 - %c = icmp ugt i4 %s, 6 - ret i1 %c -} - -define i1 @lshrugt_01_07(i4 %x) { -; CHECK-LABEL: @lshrugt_01_07( -; CHECK-NEXT: ret i1 false -; - %s = lshr i4 %x, 1 - %c = icmp ugt i4 %s, 7 - ret i1 %c -} - -define i1 @lshrugt_01_08(i4 %x) { -; CHECK-LABEL: @lshrugt_01_08( -; CHECK-NEXT: ret i1 false -; - %s = lshr i4 %x, 1 - %c = icmp ugt i4 %s, 8 - ret i1 %c -} - -define i1 @lshrugt_01_09(i4 %x) { -; CHECK-LABEL: @lshrugt_01_09( -; CHECK-NEXT: ret i1 false -; - %s = lshr i4 %x, 1 - %c = icmp ugt i4 %s, 9 - ret i1 %c -} - -define i1 @lshrugt_01_10(i4 %x) { -; CHECK-LABEL: @lshrugt_01_10( -; CHECK-NEXT: ret i1 false -; - %s = lshr i4 %x, 1 - %c = icmp ugt i4 %s, 10 - ret i1 %c -} - -define i1 @lshrugt_01_11(i4 %x) { -; CHECK-LABEL: @lshrugt_01_11( -; CHECK-NEXT: ret i1 false -; - %s = lshr i4 %x, 1 - %c = icmp ugt i4 %s, 11 - ret i1 %c -} - -define i1 @lshrugt_01_12(i4 %x) { -; CHECK-LABEL: @lshrugt_01_12( -; CHECK-NEXT: ret i1 false -; - %s = lshr i4 %x, 1 - %c = icmp ugt i4 %s, 12 - ret i1 %c -} - -define i1 @lshrugt_01_13(i4 %x) { -; CHECK-LABEL: @lshrugt_01_13( -; CHECK-NEXT: ret i1 false -; - %s = lshr i4 %x, 1 - %c = icmp ugt i4 %s, 13 - ret i1 %c -} - -define i1 @lshrugt_01_14(i4 %x) { -; CHECK-LABEL: @lshrugt_01_14( -; CHECK-NEXT: ret i1 false -; - %s = lshr i4 %x, 1 - %c = icmp ugt i4 %s, 14 - ret i1 %c -} - -define i1 @lshrugt_01_15(i4 %x) { -; CHECK-LABEL: @lshrugt_01_15( -; CHECK-NEXT: ret i1 false -; - %s = lshr i4 %x, 1 - %c = icmp ugt i4 %s, 15 - ret i1 %c -} - -define i1 @lshrugt_02_00(i4 %x) { -; CHECK-LABEL: @lshrugt_02_00( -; CHECK-NEXT: [[C:%.*]] = icmp ugt i4 %x, 3 -; CHECK-NEXT: ret i1 [[C]] -; - %s = lshr i4 %x, 2 - %c = icmp ugt i4 %s, 0 - ret i1 %c -} - -define i1 @lshrugt_02_01(i4 %x) { -; CHECK-LABEL: @lshrugt_02_01( -; CHECK-NEXT: [[C:%.*]] = icmp slt i4 %x, 0 -; CHECK-NEXT: ret i1 [[C]] -; - %s = lshr i4 %x, 2 - %c = icmp ugt i4 %s, 1 - ret i1 %c -} - -define i1 @lshrugt_02_02(i4 %x) { -; CHECK-LABEL: @lshrugt_02_02( -; CHECK-NEXT: [[C:%.*]] = icmp ugt i4 %x, -5 -; CHECK-NEXT: ret i1 [[C]] -; - %s = lshr i4 %x, 2 - %c = icmp ugt i4 %s, 2 - ret i1 %c -} - -define i1 @lshrugt_02_03(i4 %x) { -; CHECK-LABEL: @lshrugt_02_03( -; CHECK-NEXT: ret i1 false -; - %s = lshr i4 %x, 2 - %c = icmp ugt i4 %s, 3 - ret i1 %c -} - -define i1 @lshrugt_02_04(i4 %x) { -; CHECK-LABEL: @lshrugt_02_04( -; CHECK-NEXT: ret i1 false -; - %s = lshr i4 %x, 2 - %c = icmp ugt i4 %s, 4 - ret i1 %c -} - -define i1 @lshrugt_02_05(i4 %x) { -; CHECK-LABEL: @lshrugt_02_05( -; CHECK-NEXT: ret i1 false -; - %s = lshr i4 %x, 2 - %c = icmp ugt i4 %s, 5 - ret i1 %c -} - -define i1 @lshrugt_02_06(i4 %x) { -; CHECK-LABEL: @lshrugt_02_06( -; CHECK-NEXT: ret i1 false -; - %s = lshr i4 %x, 2 - %c = icmp ugt i4 %s, 6 - ret i1 %c -} - -define i1 @lshrugt_02_07(i4 %x) { -; CHECK-LABEL: @lshrugt_02_07( -; CHECK-NEXT: ret i1 false -; - %s = lshr i4 %x, 2 - %c = icmp ugt i4 %s, 7 - ret i1 %c -} - -define i1 @lshrugt_02_08(i4 %x) { -; CHECK-LABEL: @lshrugt_02_08( -; CHECK-NEXT: ret i1 false -; - %s = lshr i4 %x, 2 - %c = icmp ugt i4 %s, 8 - ret i1 %c -} - -define i1 @lshrugt_02_09(i4 %x) { -; CHECK-LABEL: @lshrugt_02_09( -; CHECK-NEXT: ret i1 false -; - %s = lshr i4 %x, 2 - %c = icmp ugt i4 %s, 9 - ret i1 %c -} - -define i1 @lshrugt_02_10(i4 %x) { -; CHECK-LABEL: @lshrugt_02_10( -; CHECK-NEXT: ret i1 false -; - %s = lshr i4 %x, 2 - %c = icmp ugt i4 %s, 10 - ret i1 %c -} - -define i1 @lshrugt_02_11(i4 %x) { -; CHECK-LABEL: @lshrugt_02_11( -; CHECK-NEXT: ret i1 false -; - %s = lshr i4 %x, 2 - %c = icmp ugt i4 %s, 11 - ret i1 %c -} - -define i1 @lshrugt_02_12(i4 %x) { -; CHECK-LABEL: @lshrugt_02_12( -; CHECK-NEXT: ret i1 false -; - %s = lshr i4 %x, 2 - %c = icmp ugt i4 %s, 12 - ret i1 %c -} - -define i1 @lshrugt_02_13(i4 %x) { -; CHECK-LABEL: @lshrugt_02_13( -; CHECK-NEXT: ret i1 false -; - %s = lshr i4 %x, 2 - %c = icmp ugt i4 %s, 13 - ret i1 %c -} - -define i1 @lshrugt_02_14(i4 %x) { -; CHECK-LABEL: @lshrugt_02_14( -; CHECK-NEXT: ret i1 false -; - %s = lshr i4 %x, 2 - %c = icmp ugt i4 %s, 14 - ret i1 %c -} - -define i1 @lshrugt_02_15(i4 %x) { -; CHECK-LABEL: @lshrugt_02_15( -; CHECK-NEXT: ret i1 false -; - %s = lshr i4 %x, 2 - %c = icmp ugt i4 %s, 15 - ret i1 %c -} - -define i1 @lshrugt_03_00(i4 %x) { -; CHECK-LABEL: @lshrugt_03_00( -; CHECK-NEXT: [[C:%.*]] = icmp slt i4 %x, 0 -; CHECK-NEXT: ret i1 [[C]] -; - %s = lshr i4 %x, 3 - %c = icmp ugt i4 %s, 0 - ret i1 %c -} - -define i1 @lshrugt_03_01(i4 %x) { -; CHECK-LABEL: @lshrugt_03_01( -; CHECK-NEXT: ret i1 false -; - %s = lshr i4 %x, 3 - %c = icmp ugt i4 %s, 1 - ret i1 %c -} - -define i1 @lshrugt_03_02(i4 %x) { -; CHECK-LABEL: @lshrugt_03_02( -; CHECK-NEXT: ret i1 false -; - %s = lshr i4 %x, 3 - %c = icmp ugt i4 %s, 2 - ret i1 %c -} - -define i1 @lshrugt_03_03(i4 %x) { -; CHECK-LABEL: @lshrugt_03_03( -; CHECK-NEXT: ret i1 false -; - %s = lshr i4 %x, 3 - %c = icmp ugt i4 %s, 3 - ret i1 %c -} - -define i1 @lshrugt_03_04(i4 %x) { -; CHECK-LABEL: @lshrugt_03_04( -; CHECK-NEXT: ret i1 false -; - %s = lshr i4 %x, 3 - %c = icmp ugt i4 %s, 4 - ret i1 %c -} - -define i1 @lshrugt_03_05(i4 %x) { -; CHECK-LABEL: @lshrugt_03_05( -; CHECK-NEXT: ret i1 false -; - %s = lshr i4 %x, 3 - %c = icmp ugt i4 %s, 5 - ret i1 %c -} - -define i1 @lshrugt_03_06(i4 %x) { -; CHECK-LABEL: @lshrugt_03_06( -; CHECK-NEXT: ret i1 false -; - %s = lshr i4 %x, 3 - %c = icmp ugt i4 %s, 6 - ret i1 %c -} - -define i1 @lshrugt_03_07(i4 %x) { -; CHECK-LABEL: @lshrugt_03_07( -; CHECK-NEXT: ret i1 false -; - %s = lshr i4 %x, 3 - %c = icmp ugt i4 %s, 7 - ret i1 %c -} - -define i1 @lshrugt_03_08(i4 %x) { -; CHECK-LABEL: @lshrugt_03_08( -; CHECK-NEXT: ret i1 false -; - %s = lshr i4 %x, 3 - %c = icmp ugt i4 %s, 8 - ret i1 %c -} - -define i1 @lshrugt_03_09(i4 %x) { -; CHECK-LABEL: @lshrugt_03_09( -; CHECK-NEXT: ret i1 false -; - %s = lshr i4 %x, 3 - %c = icmp ugt i4 %s, 9 - ret i1 %c -} - -define i1 @lshrugt_03_10(i4 %x) { -; CHECK-LABEL: @lshrugt_03_10( -; CHECK-NEXT: ret i1 false -; - %s = lshr i4 %x, 3 - %c = icmp ugt i4 %s, 10 - ret i1 %c -} - -define i1 @lshrugt_03_11(i4 %x) { -; CHECK-LABEL: @lshrugt_03_11( -; CHECK-NEXT: ret i1 false -; - %s = lshr i4 %x, 3 - %c = icmp ugt i4 %s, 11 - ret i1 %c -} - -define i1 @lshrugt_03_12(i4 %x) { -; CHECK-LABEL: @lshrugt_03_12( -; CHECK-NEXT: ret i1 false -; - %s = lshr i4 %x, 3 - %c = icmp ugt i4 %s, 12 - ret i1 %c -} - -define i1 @lshrugt_03_13(i4 %x) { -; CHECK-LABEL: @lshrugt_03_13( -; CHECK-NEXT: ret i1 false -; - %s = lshr i4 %x, 3 - %c = icmp ugt i4 %s, 13 - ret i1 %c -} - -define i1 @lshrugt_03_14(i4 %x) { -; CHECK-LABEL: @lshrugt_03_14( -; CHECK-NEXT: ret i1 false -; - %s = lshr i4 %x, 3 - %c = icmp ugt i4 %s, 14 - ret i1 %c -} - -define i1 @lshrugt_03_15(i4 %x) { -; CHECK-LABEL: @lshrugt_03_15( -; CHECK-NEXT: ret i1 false -; - %s = lshr i4 %x, 3 - %c = icmp ugt i4 %s, 15 - ret i1 %c -} - -define i1 @lshrult_01_00(i4 %x) { -; CHECK-LABEL: @lshrult_01_00( -; CHECK-NEXT: ret i1 false -; - %s = lshr i4 %x, 1 - %c = icmp ult i4 %s, 0 - ret i1 %c -} - -define i1 @lshrult_01_01(i4 %x) { -; CHECK-LABEL: @lshrult_01_01( -; CHECK-NEXT: [[C:%.*]] = icmp ult i4 %x, 2 -; CHECK-NEXT: ret i1 [[C]] -; - %s = lshr i4 %x, 1 - %c = icmp ult i4 %s, 1 - ret i1 %c -} - -define i1 @lshrult_01_02(i4 %x) { -; CHECK-LABEL: @lshrult_01_02( -; CHECK-NEXT: [[C:%.*]] = icmp ult i4 %x, 4 -; CHECK-NEXT: ret i1 [[C]] -; - %s = lshr i4 %x, 1 - %c = icmp ult i4 %s, 2 - ret i1 %c -} - -define i1 @lshrult_01_03(i4 %x) { -; CHECK-LABEL: @lshrult_01_03( -; CHECK-NEXT: [[C:%.*]] = icmp ult i4 %x, 6 -; CHECK-NEXT: ret i1 [[C]] -; - %s = lshr i4 %x, 1 - %c = icmp ult i4 %s, 3 - ret i1 %c -} - -define i1 @lshrult_01_04(i4 %x) { -; CHECK-LABEL: @lshrult_01_04( -; CHECK-NEXT: [[C:%.*]] = icmp sgt i4 %x, -1 -; CHECK-NEXT: ret i1 [[C]] -; - %s = lshr i4 %x, 1 - %c = icmp ult i4 %s, 4 - ret i1 %c -} - -define i1 @lshrult_01_05(i4 %x) { -; CHECK-LABEL: @lshrult_01_05( -; CHECK-NEXT: [[C:%.*]] = icmp ult i4 %x, -6 -; CHECK-NEXT: ret i1 [[C]] -; - %s = lshr i4 %x, 1 - %c = icmp ult i4 %s, 5 - ret i1 %c -} - -define i1 @lshrult_01_06(i4 %x) { -; CHECK-LABEL: @lshrult_01_06( -; CHECK-NEXT: [[C:%.*]] = icmp ult i4 %x, -4 -; CHECK-NEXT: ret i1 [[C]] -; - %s = lshr i4 %x, 1 - %c = icmp ult i4 %s, 6 - ret i1 %c -} - -define i1 @lshrult_01_07(i4 %x) { -; CHECK-LABEL: @lshrult_01_07( -; CHECK-NEXT: [[C:%.*]] = icmp ult i4 %x, -2 -; CHECK-NEXT: ret i1 [[C]] -; - %s = lshr i4 %x, 1 - %c = icmp ult i4 %s, 7 - ret i1 %c -} - -define i1 @lshrult_01_08(i4 %x) { -; CHECK-LABEL: @lshrult_01_08( -; CHECK-NEXT: ret i1 true -; - %s = lshr i4 %x, 1 - %c = icmp ult i4 %s, 8 - ret i1 %c -} - -define i1 @lshrult_01_09(i4 %x) { -; CHECK-LABEL: @lshrult_01_09( -; CHECK-NEXT: ret i1 true -; - %s = lshr i4 %x, 1 - %c = icmp ult i4 %s, 9 - ret i1 %c -} - -define i1 @lshrult_01_10(i4 %x) { -; CHECK-LABEL: @lshrult_01_10( -; CHECK-NEXT: ret i1 true -; - %s = lshr i4 %x, 1 - %c = icmp ult i4 %s, 10 - ret i1 %c -} - -define i1 @lshrult_01_11(i4 %x) { -; CHECK-LABEL: @lshrult_01_11( -; CHECK-NEXT: ret i1 true -; - %s = lshr i4 %x, 1 - %c = icmp ult i4 %s, 11 - ret i1 %c -} - -define i1 @lshrult_01_12(i4 %x) { -; CHECK-LABEL: @lshrult_01_12( -; CHECK-NEXT: ret i1 true -; - %s = lshr i4 %x, 1 - %c = icmp ult i4 %s, 12 - ret i1 %c -} - -define i1 @lshrult_01_13(i4 %x) { -; CHECK-LABEL: @lshrult_01_13( -; CHECK-NEXT: ret i1 true -; - %s = lshr i4 %x, 1 - %c = icmp ult i4 %s, 13 - ret i1 %c -} - -define i1 @lshrult_01_14(i4 %x) { -; CHECK-LABEL: @lshrult_01_14( -; CHECK-NEXT: ret i1 true -; - %s = lshr i4 %x, 1 - %c = icmp ult i4 %s, 14 - ret i1 %c -} - -define i1 @lshrult_01_15(i4 %x) { -; CHECK-LABEL: @lshrult_01_15( -; CHECK-NEXT: ret i1 true -; - %s = lshr i4 %x, 1 - %c = icmp ult i4 %s, 15 - ret i1 %c -} - -define i1 @lshrult_02_00(i4 %x) { -; CHECK-LABEL: @lshrult_02_00( -; CHECK-NEXT: ret i1 false -; - %s = lshr i4 %x, 2 - %c = icmp ult i4 %s, 0 - ret i1 %c -} - -define i1 @lshrult_02_01(i4 %x) { -; CHECK-LABEL: @lshrult_02_01( -; CHECK-NEXT: [[C:%.*]] = icmp ult i4 %x, 4 -; CHECK-NEXT: ret i1 [[C]] -; - %s = lshr i4 %x, 2 - %c = icmp ult i4 %s, 1 - ret i1 %c -} - -define i1 @lshrult_02_02(i4 %x) { -; CHECK-LABEL: @lshrult_02_02( -; CHECK-NEXT: [[C:%.*]] = icmp sgt i4 %x, -1 -; CHECK-NEXT: ret i1 [[C]] -; - %s = lshr i4 %x, 2 - %c = icmp ult i4 %s, 2 - ret i1 %c -} - -define i1 @lshrult_02_03(i4 %x) { -; CHECK-LABEL: @lshrult_02_03( -; CHECK-NEXT: [[C:%.*]] = icmp ult i4 %x, -4 -; CHECK-NEXT: ret i1 [[C]] -; - %s = lshr i4 %x, 2 - %c = icmp ult i4 %s, 3 - ret i1 %c -} - -define i1 @lshrult_02_04(i4 %x) { -; CHECK-LABEL: @lshrult_02_04( -; CHECK-NEXT: ret i1 true -; - %s = lshr i4 %x, 2 - %c = icmp ult i4 %s, 4 - ret i1 %c -} - -define i1 @lshrult_02_05(i4 %x) { -; CHECK-LABEL: @lshrult_02_05( -; CHECK-NEXT: ret i1 true -; - %s = lshr i4 %x, 2 - %c = icmp ult i4 %s, 5 - ret i1 %c -} - -define i1 @lshrult_02_06(i4 %x) { -; CHECK-LABEL: @lshrult_02_06( -; CHECK-NEXT: ret i1 true -; - %s = lshr i4 %x, 2 - %c = icmp ult i4 %s, 6 - ret i1 %c -} - -define i1 @lshrult_02_07(i4 %x) { -; CHECK-LABEL: @lshrult_02_07( -; CHECK-NEXT: ret i1 true -; - %s = lshr i4 %x, 2 - %c = icmp ult i4 %s, 7 - ret i1 %c -} - -define i1 @lshrult_02_08(i4 %x) { -; CHECK-LABEL: @lshrult_02_08( -; CHECK-NEXT: ret i1 true -; - %s = lshr i4 %x, 2 - %c = icmp ult i4 %s, 8 - ret i1 %c -} - -define i1 @lshrult_02_09(i4 %x) { -; CHECK-LABEL: @lshrult_02_09( -; CHECK-NEXT: ret i1 true -; - %s = lshr i4 %x, 2 - %c = icmp ult i4 %s, 9 - ret i1 %c -} - -define i1 @lshrult_02_10(i4 %x) { -; CHECK-LABEL: @lshrult_02_10( -; CHECK-NEXT: ret i1 true -; - %s = lshr i4 %x, 2 - %c = icmp ult i4 %s, 10 - ret i1 %c -} - -define i1 @lshrult_02_11(i4 %x) { -; CHECK-LABEL: @lshrult_02_11( -; CHECK-NEXT: ret i1 true -; - %s = lshr i4 %x, 2 - %c = icmp ult i4 %s, 11 - ret i1 %c -} - -define i1 @lshrult_02_12(i4 %x) { -; CHECK-LABEL: @lshrult_02_12( -; CHECK-NEXT: ret i1 true -; - %s = lshr i4 %x, 2 - %c = icmp ult i4 %s, 12 - ret i1 %c -} - -define i1 @lshrult_02_13(i4 %x) { -; CHECK-LABEL: @lshrult_02_13( -; CHECK-NEXT: ret i1 true -; - %s = lshr i4 %x, 2 - %c = icmp ult i4 %s, 13 - ret i1 %c -} - -define i1 @lshrult_02_14(i4 %x) { -; CHECK-LABEL: @lshrult_02_14( -; CHECK-NEXT: ret i1 true -; - %s = lshr i4 %x, 2 - %c = icmp ult i4 %s, 14 - ret i1 %c -} - -define i1 @lshrult_02_15(i4 %x) { -; CHECK-LABEL: @lshrult_02_15( -; CHECK-NEXT: ret i1 true -; - %s = lshr i4 %x, 2 - %c = icmp ult i4 %s, 15 - ret i1 %c -} - -define i1 @lshrult_03_00(i4 %x) { -; CHECK-LABEL: @lshrult_03_00( -; CHECK-NEXT: ret i1 false -; - %s = lshr i4 %x, 3 - %c = icmp ult i4 %s, 0 - ret i1 %c -} - -define i1 @lshrult_03_01(i4 %x) { -; CHECK-LABEL: @lshrult_03_01( -; CHECK-NEXT: [[C:%.*]] = icmp sgt i4 %x, -1 -; CHECK-NEXT: ret i1 [[C]] -; - %s = lshr i4 %x, 3 - %c = icmp ult i4 %s, 1 - ret i1 %c -} - -define i1 @lshrult_03_02(i4 %x) { -; CHECK-LABEL: @lshrult_03_02( -; CHECK-NEXT: ret i1 true -; - %s = lshr i4 %x, 3 - %c = icmp ult i4 %s, 2 - ret i1 %c -} - -define i1 @lshrult_03_03(i4 %x) { -; CHECK-LABEL: @lshrult_03_03( -; CHECK-NEXT: ret i1 true -; - %s = lshr i4 %x, 3 - %c = icmp ult i4 %s, 3 - ret i1 %c -} - -define i1 @lshrult_03_04(i4 %x) { -; CHECK-LABEL: @lshrult_03_04( -; CHECK-NEXT: ret i1 true -; - %s = lshr i4 %x, 3 - %c = icmp ult i4 %s, 4 - ret i1 %c -} - -define i1 @lshrult_03_05(i4 %x) { -; CHECK-LABEL: @lshrult_03_05( -; CHECK-NEXT: ret i1 true -; - %s = lshr i4 %x, 3 - %c = icmp ult i4 %s, 5 - ret i1 %c -} - -define i1 @lshrult_03_06(i4 %x) { -; CHECK-LABEL: @lshrult_03_06( -; CHECK-NEXT: ret i1 true -; - %s = lshr i4 %x, 3 - %c = icmp ult i4 %s, 6 - ret i1 %c -} - -define i1 @lshrult_03_07(i4 %x) { -; CHECK-LABEL: @lshrult_03_07( -; CHECK-NEXT: ret i1 true -; - %s = lshr i4 %x, 3 - %c = icmp ult i4 %s, 7 - ret i1 %c -} - -define i1 @lshrult_03_08(i4 %x) { -; CHECK-LABEL: @lshrult_03_08( -; CHECK-NEXT: ret i1 true -; - %s = lshr i4 %x, 3 - %c = icmp ult i4 %s, 8 - ret i1 %c -} - -define i1 @lshrult_03_09(i4 %x) { -; CHECK-LABEL: @lshrult_03_09( -; CHECK-NEXT: ret i1 true -; - %s = lshr i4 %x, 3 - %c = icmp ult i4 %s, 9 - ret i1 %c -} - -define i1 @lshrult_03_10(i4 %x) { -; CHECK-LABEL: @lshrult_03_10( -; CHECK-NEXT: ret i1 true -; - %s = lshr i4 %x, 3 - %c = icmp ult i4 %s, 10 - ret i1 %c -} - -define i1 @lshrult_03_11(i4 %x) { -; CHECK-LABEL: @lshrult_03_11( -; CHECK-NEXT: ret i1 true -; - %s = lshr i4 %x, 3 - %c = icmp ult i4 %s, 11 - ret i1 %c -} - -define i1 @lshrult_03_12(i4 %x) { -; CHECK-LABEL: @lshrult_03_12( -; CHECK-NEXT: ret i1 true -; - %s = lshr i4 %x, 3 - %c = icmp ult i4 %s, 12 - ret i1 %c -} - -define i1 @lshrult_03_13(i4 %x) { -; CHECK-LABEL: @lshrult_03_13( -; CHECK-NEXT: ret i1 true -; - %s = lshr i4 %x, 3 - %c = icmp ult i4 %s, 13 - ret i1 %c -} - -define i1 @lshrult_03_14(i4 %x) { -; CHECK-LABEL: @lshrult_03_14( -; CHECK-NEXT: ret i1 true -; - %s = lshr i4 %x, 3 - %c = icmp ult i4 %s, 14 - ret i1 %c -} - -define i1 @lshrult_03_15(i4 %x) { -; CHECK-LABEL: @lshrult_03_15( -; CHECK-NEXT: ret i1 true -; - %s = lshr i4 %x, 3 - %c = icmp ult i4 %s, 15 - ret i1 %c -} - -define i1 @ashrsgt_01_00(i4 %x) { -; CHECK-LABEL: @ashrsgt_01_00( -; CHECK-NEXT: [[S:%.*]] = ashr i4 %x, 1 -; CHECK-NEXT: [[C:%.*]] = icmp sgt i4 [[S]], 0 -; CHECK-NEXT: ret i1 [[C]] -; - %s = ashr i4 %x, 1 - %c = icmp sgt i4 %s, 0 - ret i1 %c -} - -define i1 @ashrsgt_01_01(i4 %x) { -; CHECK-LABEL: @ashrsgt_01_01( -; CHECK-NEXT: [[S:%.*]] = ashr i4 %x, 1 -; CHECK-NEXT: [[C:%.*]] = icmp sgt i4 [[S]], 1 -; CHECK-NEXT: ret i1 [[C]] -; - %s = ashr i4 %x, 1 - %c = icmp sgt i4 %s, 1 - ret i1 %c -} - -define i1 @ashrsgt_01_02(i4 %x) { -; CHECK-LABEL: @ashrsgt_01_02( -; CHECK-NEXT: [[S:%.*]] = ashr i4 %x, 1 -; CHECK-NEXT: [[C:%.*]] = icmp sgt i4 [[S]], 2 -; CHECK-NEXT: ret i1 [[C]] -; - %s = ashr i4 %x, 1 - %c = icmp sgt i4 %s, 2 - ret i1 %c -} - -define i1 @ashrsgt_01_03(i4 %x) { -; CHECK-LABEL: @ashrsgt_01_03( -; CHECK-NEXT: ret i1 false -; - %s = ashr i4 %x, 1 - %c = icmp sgt i4 %s, 3 - ret i1 %c -} - -define i1 @ashrsgt_01_04(i4 %x) { -; CHECK-LABEL: @ashrsgt_01_04( -; CHECK-NEXT: ret i1 false -; - %s = ashr i4 %x, 1 - %c = icmp sgt i4 %s, 4 - ret i1 %c -} - -define i1 @ashrsgt_01_05(i4 %x) { -; CHECK-LABEL: @ashrsgt_01_05( -; CHECK-NEXT: ret i1 false -; - %s = ashr i4 %x, 1 - %c = icmp sgt i4 %s, 5 - ret i1 %c -} - -define i1 @ashrsgt_01_06(i4 %x) { -; CHECK-LABEL: @ashrsgt_01_06( -; CHECK-NEXT: ret i1 false -; - %s = ashr i4 %x, 1 - %c = icmp sgt i4 %s, 6 - ret i1 %c -} - -define i1 @ashrsgt_01_07(i4 %x) { -; CHECK-LABEL: @ashrsgt_01_07( -; CHECK-NEXT: ret i1 false -; - %s = ashr i4 %x, 1 - %c = icmp sgt i4 %s, 7 - ret i1 %c -} - -define i1 @ashrsgt_01_08(i4 %x) { -; CHECK-LABEL: @ashrsgt_01_08( -; CHECK-NEXT: ret i1 true -; - %s = ashr i4 %x, 1 - %c = icmp sgt i4 %s, 8 - ret i1 %c -} - -define i1 @ashrsgt_01_09(i4 %x) { -; CHECK-LABEL: @ashrsgt_01_09( -; CHECK-NEXT: ret i1 true -; - %s = ashr i4 %x, 1 - %c = icmp sgt i4 %s, 9 - ret i1 %c -} - -define i1 @ashrsgt_01_10(i4 %x) { -; CHECK-LABEL: @ashrsgt_01_10( -; CHECK-NEXT: ret i1 true -; - %s = ashr i4 %x, 1 - %c = icmp sgt i4 %s, 10 - ret i1 %c -} - -define i1 @ashrsgt_01_11(i4 %x) { -; CHECK-LABEL: @ashrsgt_01_11( -; CHECK-NEXT: ret i1 true -; - %s = ashr i4 %x, 1 - %c = icmp sgt i4 %s, 11 - ret i1 %c -} - -define i1 @ashrsgt_01_12(i4 %x) { -; CHECK-LABEL: @ashrsgt_01_12( -; CHECK-NEXT: [[S:%.*]] = ashr i4 %x, 1 -; CHECK-NEXT: [[C:%.*]] = icmp sgt i4 [[S]], -4 -; CHECK-NEXT: ret i1 [[C]] -; - %s = ashr i4 %x, 1 - %c = icmp sgt i4 %s, 12 - ret i1 %c -} - -define i1 @ashrsgt_01_13(i4 %x) { -; CHECK-LABEL: @ashrsgt_01_13( -; CHECK-NEXT: [[S:%.*]] = ashr i4 %x, 1 -; CHECK-NEXT: [[C:%.*]] = icmp sgt i4 [[S]], -3 -; CHECK-NEXT: ret i1 [[C]] -; - %s = ashr i4 %x, 1 - %c = icmp sgt i4 %s, 13 - ret i1 %c -} - -define i1 @ashrsgt_01_14(i4 %x) { -; CHECK-LABEL: @ashrsgt_01_14( -; CHECK-NEXT: [[S:%.*]] = ashr i4 %x, 1 -; CHECK-NEXT: [[C:%.*]] = icmp sgt i4 [[S]], -2 -; CHECK-NEXT: ret i1 [[C]] -; - %s = ashr i4 %x, 1 - %c = icmp sgt i4 %s, 14 - ret i1 %c -} - -define i1 @ashrsgt_01_15(i4 %x) { -; CHECK-LABEL: @ashrsgt_01_15( -; CHECK-NEXT: [[C:%.*]] = icmp sgt i4 %x, -1 -; CHECK-NEXT: ret i1 [[C]] -; - %s = ashr i4 %x, 1 - %c = icmp sgt i4 %s, 15 - ret i1 %c -} - -define i1 @ashrsgt_02_00(i4 %x) { -; CHECK-LABEL: @ashrsgt_02_00( -; CHECK-NEXT: [[S:%.*]] = ashr i4 %x, 2 -; CHECK-NEXT: [[C:%.*]] = icmp sgt i4 [[S]], 0 -; CHECK-NEXT: ret i1 [[C]] -; - %s = ashr i4 %x, 2 - %c = icmp sgt i4 %s, 0 - ret i1 %c -} - -define i1 @ashrsgt_02_01(i4 %x) { -; CHECK-LABEL: @ashrsgt_02_01( -; CHECK-NEXT: ret i1 false -; - %s = ashr i4 %x, 2 - %c = icmp sgt i4 %s, 1 - ret i1 %c -} - -define i1 @ashrsgt_02_02(i4 %x) { -; CHECK-LABEL: @ashrsgt_02_02( -; CHECK-NEXT: ret i1 false -; - %s = ashr i4 %x, 2 - %c = icmp sgt i4 %s, 2 - ret i1 %c -} - -define i1 @ashrsgt_02_03(i4 %x) { -; CHECK-LABEL: @ashrsgt_02_03( -; CHECK-NEXT: ret i1 false -; - %s = ashr i4 %x, 2 - %c = icmp sgt i4 %s, 3 - ret i1 %c -} - -define i1 @ashrsgt_02_04(i4 %x) { -; CHECK-LABEL: @ashrsgt_02_04( -; CHECK-NEXT: ret i1 false -; - %s = ashr i4 %x, 2 - %c = icmp sgt i4 %s, 4 - ret i1 %c -} - -define i1 @ashrsgt_02_05(i4 %x) { -; CHECK-LABEL: @ashrsgt_02_05( -; CHECK-NEXT: ret i1 false -; - %s = ashr i4 %x, 2 - %c = icmp sgt i4 %s, 5 - ret i1 %c -} - -define i1 @ashrsgt_02_06(i4 %x) { -; CHECK-LABEL: @ashrsgt_02_06( -; CHECK-NEXT: ret i1 false -; - %s = ashr i4 %x, 2 - %c = icmp sgt i4 %s, 6 - ret i1 %c -} - -define i1 @ashrsgt_02_07(i4 %x) { -; CHECK-LABEL: @ashrsgt_02_07( -; CHECK-NEXT: ret i1 false -; - %s = ashr i4 %x, 2 - %c = icmp sgt i4 %s, 7 - ret i1 %c -} - -define i1 @ashrsgt_02_08(i4 %x) { -; CHECK-LABEL: @ashrsgt_02_08( -; CHECK-NEXT: ret i1 true -; - %s = ashr i4 %x, 2 - %c = icmp sgt i4 %s, 8 - ret i1 %c -} - -define i1 @ashrsgt_02_09(i4 %x) { -; CHECK-LABEL: @ashrsgt_02_09( -; CHECK-NEXT: ret i1 true -; - %s = ashr i4 %x, 2 - %c = icmp sgt i4 %s, 9 - ret i1 %c -} - -define i1 @ashrsgt_02_10(i4 %x) { -; CHECK-LABEL: @ashrsgt_02_10( -; CHECK-NEXT: ret i1 true -; - %s = ashr i4 %x, 2 - %c = icmp sgt i4 %s, 10 - ret i1 %c -} - -define i1 @ashrsgt_02_11(i4 %x) { -; CHECK-LABEL: @ashrsgt_02_11( -; CHECK-NEXT: ret i1 true -; - %s = ashr i4 %x, 2 - %c = icmp sgt i4 %s, 11 - ret i1 %c -} - -define i1 @ashrsgt_02_12(i4 %x) { -; CHECK-LABEL: @ashrsgt_02_12( -; CHECK-NEXT: ret i1 true -; - %s = ashr i4 %x, 2 - %c = icmp sgt i4 %s, 12 - ret i1 %c -} - -define i1 @ashrsgt_02_13(i4 %x) { -; CHECK-LABEL: @ashrsgt_02_13( -; CHECK-NEXT: ret i1 true -; - %s = ashr i4 %x, 2 - %c = icmp sgt i4 %s, 13 - ret i1 %c -} - -define i1 @ashrsgt_02_14(i4 %x) { -; CHECK-LABEL: @ashrsgt_02_14( -; CHECK-NEXT: [[S:%.*]] = ashr i4 %x, 2 -; CHECK-NEXT: [[C:%.*]] = icmp sgt i4 [[S]], -2 -; CHECK-NEXT: ret i1 [[C]] -; - %s = ashr i4 %x, 2 - %c = icmp sgt i4 %s, 14 - ret i1 %c -} - -define i1 @ashrsgt_02_15(i4 %x) { -; CHECK-LABEL: @ashrsgt_02_15( -; CHECK-NEXT: [[C:%.*]] = icmp sgt i4 %x, -1 -; CHECK-NEXT: ret i1 [[C]] -; - %s = ashr i4 %x, 2 - %c = icmp sgt i4 %s, 15 - ret i1 %c -} - -define i1 @ashrsgt_03_00(i4 %x) { -; CHECK-LABEL: @ashrsgt_03_00( -; CHECK-NEXT: ret i1 false -; - %s = ashr i4 %x, 3 - %c = icmp sgt i4 %s, 0 - ret i1 %c -} - -define i1 @ashrsgt_03_01(i4 %x) { -; CHECK-LABEL: @ashrsgt_03_01( -; CHECK-NEXT: ret i1 false -; - %s = ashr i4 %x, 3 - %c = icmp sgt i4 %s, 1 - ret i1 %c -} - -define i1 @ashrsgt_03_02(i4 %x) { -; CHECK-LABEL: @ashrsgt_03_02( -; CHECK-NEXT: ret i1 false -; - %s = ashr i4 %x, 3 - %c = icmp sgt i4 %s, 2 - ret i1 %c -} - -define i1 @ashrsgt_03_03(i4 %x) { -; CHECK-LABEL: @ashrsgt_03_03( -; CHECK-NEXT: ret i1 false -; - %s = ashr i4 %x, 3 - %c = icmp sgt i4 %s, 3 - ret i1 %c -} - -define i1 @ashrsgt_03_04(i4 %x) { -; CHECK-LABEL: @ashrsgt_03_04( -; CHECK-NEXT: ret i1 false -; - %s = ashr i4 %x, 3 - %c = icmp sgt i4 %s, 4 - ret i1 %c -} - -define i1 @ashrsgt_03_05(i4 %x) { -; CHECK-LABEL: @ashrsgt_03_05( -; CHECK-NEXT: ret i1 false -; - %s = ashr i4 %x, 3 - %c = icmp sgt i4 %s, 5 - ret i1 %c -} - -define i1 @ashrsgt_03_06(i4 %x) { -; CHECK-LABEL: @ashrsgt_03_06( -; CHECK-NEXT: ret i1 false -; - %s = ashr i4 %x, 3 - %c = icmp sgt i4 %s, 6 - ret i1 %c -} - -define i1 @ashrsgt_03_07(i4 %x) { -; CHECK-LABEL: @ashrsgt_03_07( -; CHECK-NEXT: ret i1 false -; - %s = ashr i4 %x, 3 - %c = icmp sgt i4 %s, 7 - ret i1 %c -} - -define i1 @ashrsgt_03_08(i4 %x) { -; CHECK-LABEL: @ashrsgt_03_08( -; CHECK-NEXT: ret i1 true -; - %s = ashr i4 %x, 3 - %c = icmp sgt i4 %s, 8 - ret i1 %c -} - -define i1 @ashrsgt_03_09(i4 %x) { -; CHECK-LABEL: @ashrsgt_03_09( -; CHECK-NEXT: ret i1 true -; - %s = ashr i4 %x, 3 - %c = icmp sgt i4 %s, 9 - ret i1 %c -} - -define i1 @ashrsgt_03_10(i4 %x) { -; CHECK-LABEL: @ashrsgt_03_10( -; CHECK-NEXT: ret i1 true -; - %s = ashr i4 %x, 3 - %c = icmp sgt i4 %s, 10 - ret i1 %c -} - -define i1 @ashrsgt_03_11(i4 %x) { -; CHECK-LABEL: @ashrsgt_03_11( -; CHECK-NEXT: ret i1 true -; - %s = ashr i4 %x, 3 - %c = icmp sgt i4 %s, 11 - ret i1 %c -} - -define i1 @ashrsgt_03_12(i4 %x) { -; CHECK-LABEL: @ashrsgt_03_12( -; CHECK-NEXT: ret i1 true -; - %s = ashr i4 %x, 3 - %c = icmp sgt i4 %s, 12 - ret i1 %c -} - -define i1 @ashrsgt_03_13(i4 %x) { -; CHECK-LABEL: @ashrsgt_03_13( -; CHECK-NEXT: ret i1 true -; - %s = ashr i4 %x, 3 - %c = icmp sgt i4 %s, 13 - ret i1 %c -} - -define i1 @ashrsgt_03_14(i4 %x) { -; CHECK-LABEL: @ashrsgt_03_14( -; CHECK-NEXT: ret i1 true -; - %s = ashr i4 %x, 3 - %c = icmp sgt i4 %s, 14 - ret i1 %c -} - -define i1 @ashrsgt_03_15(i4 %x) { -; CHECK-LABEL: @ashrsgt_03_15( -; CHECK-NEXT: [[C:%.*]] = icmp sgt i4 %x, -1 -; CHECK-NEXT: ret i1 [[C]] -; - %s = ashr i4 %x, 3 - %c = icmp sgt i4 %s, 15 - ret i1 %c -} - -define i1 @ashrslt_01_00(i4 %x) { -; CHECK-LABEL: @ashrslt_01_00( -; CHECK-NEXT: [[C:%.*]] = icmp slt i4 %x, 0 -; CHECK-NEXT: ret i1 [[C]] -; - %s = ashr i4 %x, 1 - %c = icmp slt i4 %s, 0 - ret i1 %c -} - -define i1 @ashrslt_01_01(i4 %x) { -; CHECK-LABEL: @ashrslt_01_01( -; CHECK-NEXT: [[S:%.*]] = ashr i4 %x, 1 -; CHECK-NEXT: [[C:%.*]] = icmp slt i4 [[S]], 1 -; CHECK-NEXT: ret i1 [[C]] -; - %s = ashr i4 %x, 1 - %c = icmp slt i4 %s, 1 - ret i1 %c -} - -define i1 @ashrslt_01_02(i4 %x) { -; CHECK-LABEL: @ashrslt_01_02( -; CHECK-NEXT: [[S:%.*]] = ashr i4 %x, 1 -; CHECK-NEXT: [[C:%.*]] = icmp slt i4 [[S]], 2 -; CHECK-NEXT: ret i1 [[C]] -; - %s = ashr i4 %x, 1 - %c = icmp slt i4 %s, 2 - ret i1 %c -} - -define i1 @ashrslt_01_03(i4 %x) { -; CHECK-LABEL: @ashrslt_01_03( -; CHECK-NEXT: [[S:%.*]] = ashr i4 %x, 1 -; CHECK-NEXT: [[C:%.*]] = icmp slt i4 [[S]], 3 -; CHECK-NEXT: ret i1 [[C]] -; - %s = ashr i4 %x, 1 - %c = icmp slt i4 %s, 3 - ret i1 %c -} - -define i1 @ashrslt_01_04(i4 %x) { -; CHECK-LABEL: @ashrslt_01_04( -; CHECK-NEXT: ret i1 true -; - %s = ashr i4 %x, 1 - %c = icmp slt i4 %s, 4 - ret i1 %c -} - -define i1 @ashrslt_01_05(i4 %x) { -; CHECK-LABEL: @ashrslt_01_05( -; CHECK-NEXT: ret i1 true -; - %s = ashr i4 %x, 1 - %c = icmp slt i4 %s, 5 - ret i1 %c -} - -define i1 @ashrslt_01_06(i4 %x) { -; CHECK-LABEL: @ashrslt_01_06( -; CHECK-NEXT: ret i1 true -; - %s = ashr i4 %x, 1 - %c = icmp slt i4 %s, 6 - ret i1 %c -} - -define i1 @ashrslt_01_07(i4 %x) { -; CHECK-LABEL: @ashrslt_01_07( -; CHECK-NEXT: ret i1 true -; - %s = ashr i4 %x, 1 - %c = icmp slt i4 %s, 7 - ret i1 %c -} - -define i1 @ashrslt_01_08(i4 %x) { -; CHECK-LABEL: @ashrslt_01_08( -; CHECK-NEXT: ret i1 false -; - %s = ashr i4 %x, 1 - %c = icmp slt i4 %s, 8 - ret i1 %c -} - -define i1 @ashrslt_01_09(i4 %x) { -; CHECK-LABEL: @ashrslt_01_09( -; CHECK-NEXT: ret i1 false -; - %s = ashr i4 %x, 1 - %c = icmp slt i4 %s, 9 - ret i1 %c -} - -define i1 @ashrslt_01_10(i4 %x) { -; CHECK-LABEL: @ashrslt_01_10( -; CHECK-NEXT: ret i1 false -; - %s = ashr i4 %x, 1 - %c = icmp slt i4 %s, 10 - ret i1 %c -} - -define i1 @ashrslt_01_11(i4 %x) { -; CHECK-LABEL: @ashrslt_01_11( -; CHECK-NEXT: ret i1 false -; - %s = ashr i4 %x, 1 - %c = icmp slt i4 %s, 11 - ret i1 %c -} - -define i1 @ashrslt_01_12(i4 %x) { -; CHECK-LABEL: @ashrslt_01_12( -; CHECK-NEXT: ret i1 false -; - %s = ashr i4 %x, 1 - %c = icmp slt i4 %s, 12 - ret i1 %c -} - -define i1 @ashrslt_01_13(i4 %x) { -; CHECK-LABEL: @ashrslt_01_13( -; CHECK-NEXT: [[S:%.*]] = ashr i4 %x, 1 -; CHECK-NEXT: [[C:%.*]] = icmp slt i4 [[S]], -3 -; CHECK-NEXT: ret i1 [[C]] -; - %s = ashr i4 %x, 1 - %c = icmp slt i4 %s, 13 - ret i1 %c -} - -define i1 @ashrslt_01_14(i4 %x) { -; CHECK-LABEL: @ashrslt_01_14( -; CHECK-NEXT: [[S:%.*]] = ashr i4 %x, 1 -; CHECK-NEXT: [[C:%.*]] = icmp slt i4 [[S]], -2 -; CHECK-NEXT: ret i1 [[C]] -; - %s = ashr i4 %x, 1 - %c = icmp slt i4 %s, 14 - ret i1 %c -} - -define i1 @ashrslt_01_15(i4 %x) { -; CHECK-LABEL: @ashrslt_01_15( -; CHECK-NEXT: [[S:%.*]] = ashr i4 %x, 1 -; CHECK-NEXT: [[C:%.*]] = icmp slt i4 [[S]], -1 -; CHECK-NEXT: ret i1 [[C]] -; - %s = ashr i4 %x, 1 - %c = icmp slt i4 %s, 15 - ret i1 %c -} - -define i1 @ashrslt_02_00(i4 %x) { -; CHECK-LABEL: @ashrslt_02_00( -; CHECK-NEXT: [[C:%.*]] = icmp slt i4 %x, 0 -; CHECK-NEXT: ret i1 [[C]] -; - %s = ashr i4 %x, 2 - %c = icmp slt i4 %s, 0 - ret i1 %c -} - -define i1 @ashrslt_02_01(i4 %x) { -; CHECK-LABEL: @ashrslt_02_01( -; CHECK-NEXT: [[S:%.*]] = ashr i4 %x, 2 -; CHECK-NEXT: [[C:%.*]] = icmp slt i4 [[S]], 1 -; CHECK-NEXT: ret i1 [[C]] -; - %s = ashr i4 %x, 2 - %c = icmp slt i4 %s, 1 - ret i1 %c -} - -define i1 @ashrslt_02_02(i4 %x) { -; CHECK-LABEL: @ashrslt_02_02( -; CHECK-NEXT: ret i1 true -; - %s = ashr i4 %x, 2 - %c = icmp slt i4 %s, 2 - ret i1 %c -} - -define i1 @ashrslt_02_03(i4 %x) { -; CHECK-LABEL: @ashrslt_02_03( -; CHECK-NEXT: ret i1 true -; - %s = ashr i4 %x, 2 - %c = icmp slt i4 %s, 3 - ret i1 %c -} - -define i1 @ashrslt_02_04(i4 %x) { -; CHECK-LABEL: @ashrslt_02_04( -; CHECK-NEXT: ret i1 true -; - %s = ashr i4 %x, 2 - %c = icmp slt i4 %s, 4 - ret i1 %c -} - -define i1 @ashrslt_02_05(i4 %x) { -; CHECK-LABEL: @ashrslt_02_05( -; CHECK-NEXT: ret i1 true -; - %s = ashr i4 %x, 2 - %c = icmp slt i4 %s, 5 - ret i1 %c -} - -define i1 @ashrslt_02_06(i4 %x) { -; CHECK-LABEL: @ashrslt_02_06( -; CHECK-NEXT: ret i1 true -; - %s = ashr i4 %x, 2 - %c = icmp slt i4 %s, 6 - ret i1 %c -} - -define i1 @ashrslt_02_07(i4 %x) { -; CHECK-LABEL: @ashrslt_02_07( -; CHECK-NEXT: ret i1 true -; - %s = ashr i4 %x, 2 - %c = icmp slt i4 %s, 7 - ret i1 %c -} - -define i1 @ashrslt_02_08(i4 %x) { -; CHECK-LABEL: @ashrslt_02_08( -; CHECK-NEXT: ret i1 false -; - %s = ashr i4 %x, 2 - %c = icmp slt i4 %s, 8 - ret i1 %c -} - -define i1 @ashrslt_02_09(i4 %x) { -; CHECK-LABEL: @ashrslt_02_09( -; CHECK-NEXT: ret i1 false -; - %s = ashr i4 %x, 2 - %c = icmp slt i4 %s, 9 - ret i1 %c -} - -define i1 @ashrslt_02_10(i4 %x) { -; CHECK-LABEL: @ashrslt_02_10( -; CHECK-NEXT: ret i1 false -; - %s = ashr i4 %x, 2 - %c = icmp slt i4 %s, 10 - ret i1 %c -} - -define i1 @ashrslt_02_11(i4 %x) { -; CHECK-LABEL: @ashrslt_02_11( -; CHECK-NEXT: ret i1 false -; - %s = ashr i4 %x, 2 - %c = icmp slt i4 %s, 11 - ret i1 %c -} - -define i1 @ashrslt_02_12(i4 %x) { -; CHECK-LABEL: @ashrslt_02_12( -; CHECK-NEXT: ret i1 false -; - %s = ashr i4 %x, 2 - %c = icmp slt i4 %s, 12 - ret i1 %c -} - -define i1 @ashrslt_02_13(i4 %x) { -; CHECK-LABEL: @ashrslt_02_13( -; CHECK-NEXT: ret i1 false -; - %s = ashr i4 %x, 2 - %c = icmp slt i4 %s, 13 - ret i1 %c -} - -define i1 @ashrslt_02_14(i4 %x) { -; CHECK-LABEL: @ashrslt_02_14( -; CHECK-NEXT: ret i1 false -; - %s = ashr i4 %x, 2 - %c = icmp slt i4 %s, 14 - ret i1 %c -} - -define i1 @ashrslt_02_15(i4 %x) { -; CHECK-LABEL: @ashrslt_02_15( -; CHECK-NEXT: [[S:%.*]] = ashr i4 %x, 2 -; CHECK-NEXT: [[C:%.*]] = icmp slt i4 [[S]], -1 -; CHECK-NEXT: ret i1 [[C]] -; - %s = ashr i4 %x, 2 - %c = icmp slt i4 %s, 15 - ret i1 %c -} - -define i1 @ashrslt_03_00(i4 %x) { -; CHECK-LABEL: @ashrslt_03_00( -; CHECK-NEXT: [[C:%.*]] = icmp slt i4 %x, 0 -; CHECK-NEXT: ret i1 [[C]] -; - %s = ashr i4 %x, 3 - %c = icmp slt i4 %s, 0 - ret i1 %c -} - -define i1 @ashrslt_03_01(i4 %x) { -; CHECK-LABEL: @ashrslt_03_01( -; CHECK-NEXT: ret i1 true -; - %s = ashr i4 %x, 3 - %c = icmp slt i4 %s, 1 - ret i1 %c -} - -define i1 @ashrslt_03_02(i4 %x) { -; CHECK-LABEL: @ashrslt_03_02( -; CHECK-NEXT: ret i1 true -; - %s = ashr i4 %x, 3 - %c = icmp slt i4 %s, 2 - ret i1 %c -} - -define i1 @ashrslt_03_03(i4 %x) { -; CHECK-LABEL: @ashrslt_03_03( -; CHECK-NEXT: ret i1 true -; - %s = ashr i4 %x, 3 - %c = icmp slt i4 %s, 3 - ret i1 %c -} - -define i1 @ashrslt_03_04(i4 %x) { -; CHECK-LABEL: @ashrslt_03_04( -; CHECK-NEXT: ret i1 true -; - %s = ashr i4 %x, 3 - %c = icmp slt i4 %s, 4 - ret i1 %c -} - -define i1 @ashrslt_03_05(i4 %x) { -; CHECK-LABEL: @ashrslt_03_05( -; CHECK-NEXT: ret i1 true -; - %s = ashr i4 %x, 3 - %c = icmp slt i4 %s, 5 - ret i1 %c -} - -define i1 @ashrslt_03_06(i4 %x) { -; CHECK-LABEL: @ashrslt_03_06( -; CHECK-NEXT: ret i1 true -; - %s = ashr i4 %x, 3 - %c = icmp slt i4 %s, 6 - ret i1 %c -} - -define i1 @ashrslt_03_07(i4 %x) { -; CHECK-LABEL: @ashrslt_03_07( -; CHECK-NEXT: ret i1 true -; - %s = ashr i4 %x, 3 - %c = icmp slt i4 %s, 7 - ret i1 %c -} - -define i1 @ashrslt_03_08(i4 %x) { -; CHECK-LABEL: @ashrslt_03_08( -; CHECK-NEXT: ret i1 false -; - %s = ashr i4 %x, 3 - %c = icmp slt i4 %s, 8 - ret i1 %c -} - -define i1 @ashrslt_03_09(i4 %x) { -; CHECK-LABEL: @ashrslt_03_09( -; CHECK-NEXT: ret i1 false -; - %s = ashr i4 %x, 3 - %c = icmp slt i4 %s, 9 - ret i1 %c -} - -define i1 @ashrslt_03_10(i4 %x) { -; CHECK-LABEL: @ashrslt_03_10( -; CHECK-NEXT: ret i1 false -; - %s = ashr i4 %x, 3 - %c = icmp slt i4 %s, 10 - ret i1 %c -} - -define i1 @ashrslt_03_11(i4 %x) { -; CHECK-LABEL: @ashrslt_03_11( -; CHECK-NEXT: ret i1 false -; - %s = ashr i4 %x, 3 - %c = icmp slt i4 %s, 11 - ret i1 %c -} - -define i1 @ashrslt_03_12(i4 %x) { -; CHECK-LABEL: @ashrslt_03_12( -; CHECK-NEXT: ret i1 false -; - %s = ashr i4 %x, 3 - %c = icmp slt i4 %s, 12 - ret i1 %c -} - -define i1 @ashrslt_03_13(i4 %x) { -; CHECK-LABEL: @ashrslt_03_13( -; CHECK-NEXT: ret i1 false -; - %s = ashr i4 %x, 3 - %c = icmp slt i4 %s, 13 - ret i1 %c -} - -define i1 @ashrslt_03_14(i4 %x) { -; CHECK-LABEL: @ashrslt_03_14( -; CHECK-NEXT: ret i1 false -; - %s = ashr i4 %x, 3 - %c = icmp slt i4 %s, 14 - ret i1 %c -} - -define i1 @ashrslt_03_15(i4 %x) { -; CHECK-LABEL: @ashrslt_03_15( -; CHECK-NEXT: ret i1 false -; - %s = ashr i4 %x, 3 - %c = icmp slt i4 %s, 15 - ret i1 %c -} - Index: test/Transforms/InstSimplify/select.ll =================================================================== --- test/Transforms/InstSimplify/select.ll +++ test/Transforms/InstSimplify/select.ll @@ -17,14 +17,6 @@ ret <2 x i8> %s } -define <2 x i8> @vsel_mixedvec() { -; CHECK-LABEL: @vsel_mixedvec( -; CHECK-NEXT: ret <2 x i8> -; - %s = select <2 x i1>, <2 x i8> , <2 x i8> - ret <2 x i8> %s -} - define i32 @test1(i32 %x) { ; CHECK-LABEL: @test1( ; CHECK-NEXT: ret i32 %x Index: test/tools/llvm-cov/dir-with-filtering.test =================================================================== --- test/tools/llvm-cov/dir-with-filtering.test +++ test/tools/llvm-cov/dir-with-filtering.test @@ -32,14 +32,6 @@ RUN: FileCheck -input-file=%t.text_one_file/coverage/tmp/dir-with-filtering1.cpp.txt %s -check-prefix=TEXT-FILE1 -// Test TEXT index file with all functions in one file filtered out - -RUN: llvm-cov show %S/Inputs/dir-with-filtering.covmapping -o %t.text_one_func -instr-profile %t.profdata -path-equivalence=/tmp,%S/Inputs -name=main -RUN: FileCheck -input-file=%t.text_one_func/index.txt %s -check-prefix=TEXT-INDEX-ONE-FUNC - -TEXT-INDEX-ONE-FUNC-NOT: Files which contain no functions -TEXT-INDEX-ONE-FUNC-NOT: dir-with-filtering2.cpp - // Test HTML both files RUN: llvm-profdata merge %S/Inputs/dir-with-filtering.proftext -o %t.profdata @@ -75,11 +67,3 @@ HTML-INDEX-ONE-FILE-NOT: dir-with-filtering2.cpp RUN: FileCheck -input-file=%t.html_one_file/coverage/tmp/dir-with-filtering1.cpp.html %s -check-prefix=HTML-FILE1 - -// Test HTML index file with all functions in one file filtered out - -RUN: llvm-cov show %S/Inputs/dir-with-filtering.covmapping -format html -o %t.html_one_func -instr-profile %t.profdata -path-equivalence=/tmp,%S/Inputs -name=main -RUN: FileCheck -input-file=%t.html_one_func/index.html %s -check-prefix=HTML-INDEX-ONE-FUNC - -HTML-INDEX-ONE-FUNC-NOT: Files which contain no functions -HTML-INDEX-ONE-FUNC-NOT: dir-with-filtering2.cpp Index: test/tools/llvm-readobj/amdgpu-elf-definitions.test =================================================================== --- test/tools/llvm-readobj/amdgpu-elf-definitions.test +++ test/tools/llvm-readobj/amdgpu-elf-definitions.test @@ -1,6 +1,6 @@ RUN: llvm-readobj -file-headers -program-headers -sections -symbols %p/Inputs/trivial.obj.elf-amdhsa-gfx803 | FileCheck %s -CHECK: Format: ELF64-amdgpu +CHECK: Format: ELF64-amdgpu-hsacobj CHECK: Arch: amdgcn CHECK: ElfHeader { CHECK: Ident { Index: tools/llvm-cfi-verify/CMakeLists.txt =================================================================== --- tools/llvm-cfi-verify/CMakeLists.txt +++ tools/llvm-cfi-verify/CMakeLists.txt @@ -13,5 +13,6 @@ add_llvm_tool(llvm-cfi-verify llvm-cfi-verify.cpp - FileAnalysis.cpp + FileVerifier.cpp + GraphBuilder.cpp ) Index: tools/llvm-cfi-verify/FileVerifier.h =================================================================== --- tools/llvm-cfi-verify/FileVerifier.h +++ tools/llvm-cfi-verify/FileVerifier.h @@ -1,4 +1,4 @@ -//===- FileAnalysis.h -------------------------------------------*- C++ -*-===// +//===- FileVerifier.h -------------------------------------------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -7,8 +7,8 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_CFI_VERIFY_FILE_ANALYSIS_H -#define LLVM_CFI_VERIFY_FILE_ANALYSIS_H +#ifndef LLVM_CFI_VERIFY_FILE_VERIFIER_H +#define LLVM_CFI_VERIFY_FILE_VERIFIER_H #include "llvm/BinaryFormat/ELF.h" #include "llvm/MC/MCAsmInfo.h" @@ -42,28 +42,30 @@ namespace llvm { namespace cfi_verify { -// Disassembler and analysis tool for machine code files. Keeps track of non- -// sequential control flows, including indirect control flow instructions. -class FileAnalysis { +// This class is used to verify CFI instrumentation of a single file. +class FileVerifier { public: // A metadata struct for an instruction. struct Instr { uint64_t VMAddress; // Virtual memory address of this instruction. MCInst Instruction; // Instruction. uint64_t InstructionSize; // Size of this instruction. - bool Valid; // Is this a valid instruction? If false, Instr::Instruction is - // undefined. + std::string SectionName; // Section this instruction is found in. + bool Bad; // Is this instruction bad (in which case, Instr::Instruction is + // invalid). }; - // Construct a FileAnalysis from a file path. - static Expected Create(StringRef Filename); + // Construct a FileVerifier from a file path. + static Expected Create(StringRef Filename); // Construct and take ownership of the supplied object. Do not use this - // constructor, prefer to use FileAnalysis::Create instead. - FileAnalysis(object::OwningBinary Binary); - FileAnalysis() = delete; - FileAnalysis(const FileAnalysis &) = delete; - FileAnalysis(FileAnalysis &&Other) = default; + // constructor, prefer to use FileVerifier::Create instead. + FileVerifier(object::OwningBinary Binary); + FileVerifier() = delete; + FileVerifier(const FileVerifier &) = delete; + FileVerifier(FileVerifier &&Other) = default; + + Error printIndirectCFInstructions() const; // Returns the instruction at the provided address. Returns nullptr if there // is no instruction at the provided address. @@ -74,23 +76,24 @@ const Instr &getInstructionOrDie(uint64_t Address) const; // Returns a pointer to the previous/next instruction in sequence, - // respectively. Returns nullptr if the next/prev instruction doesn't exist, - // or if the provided instruction doesn't exist. + // respectively. Retusn nullptr if the next/prev instruction doesn't exist, or + // if the provided instruction doesn't exist. const Instr *getPrevInstructionSequential(const Instr &InstrMeta) const; const Instr *getNextInstructionSequential(const Instr &InstrMeta) const; - // Returns whether this instruction is used by CFI to trap the program. - bool isCFITrap(const Instr &InstrMeta) const; + // Returns whether this instruction is an undefined instruction (used in + // branch-to-undefined CFI protections). + bool isUndefinedInstruction(const Instr &InstrMeta) const; // Returns whether this function can fall through to the next instruction. // Undefined (and bad) instructions cannot fall through, and instruction that - // modify the control flow can only fall through if they are conditional + // modify the control flow can only flow through if they are conditional // branches or calls. bool canFallThrough(const Instr &InstrMeta) const; // Returns the definitive next instruction. This is different from the next - // instruction sequentially as it will follow unconditional branches (assuming - // they can be resolved at compile time, i.e. not indirect). This method + // instruction sequantially as it will follow unconditional branches (assuming + // they can be resolved at compile time, i.e. not indirect). This instruction // returns nullptr if the provided instruction does not transfer control flow // to exactly one instruction that is known deterministically at compile time. // Also returns nullptr if the deterministic target does not exist in this @@ -103,7 +106,6 @@ std::set getControlFlowXRefs(const Instr &InstrMeta) const; const std::set &getIndirectInstructions() const; - const MCRegisterInfo *getRegisterInfo() const; const MCInstrInfo *getMCInstrInfo() const; const MCInstrAnalysis *getMCInstrAnalysis() const; @@ -112,15 +114,16 @@ // Construct a blank object with the provided triple and features. Used in // testing, where a sub class will dependency inject protected methods to // allow analysis of raw binary, without requiring a fully valid ELF file. - FileAnalysis(const Triple &ObjectTriple, const SubtargetFeatures &Features); + FileVerifier(const Triple &ObjectTriple, const SubtargetFeatures &Features); // Add an instruction to this object. void addInstruction(const Instr &Instruction); // Disassemble and parse the provided bytes into this object. Instruction - // address calculation is done relative to the provided SectionAddress. + // address calculation is done relative to the provided SectionAddress, and + // instruction metadata is populated with the given section name. void parseSectionContents(ArrayRef SectionBytes, - uint64_t SectionAddress); + uint64_t SectionAddress, StringRef SectionName); // Constructs and initialises members required for disassembly. Error initialiseDisassemblyMembers(); @@ -173,4 +176,4 @@ } // namespace cfi_verify } // namespace llvm -#endif // LLVM_CFI_VERIFY_FILE_ANALYSIS_H +#endif // LLVM_CFI_VERIFY_FILE_VERIFIER_H Index: tools/llvm-cfi-verify/FileVerifier.cpp =================================================================== --- tools/llvm-cfi-verify/FileVerifier.cpp +++ tools/llvm-cfi-verify/FileVerifier.cpp @@ -1,4 +1,4 @@ -#include "FileAnalysis.h" +#include "FileVerifier.h" #include "llvm/BinaryFormat/ELF.h" #include "llvm/MC/MCAsmInfo.h" @@ -27,12 +27,12 @@ #include -using Instr = llvm::cfi_verify::FileAnalysis::Instr; +using Instr = llvm::cfi_verify::FileVerifier::Instr; namespace llvm { namespace cfi_verify { -Expected FileAnalysis::Create(StringRef Filename) { +Expected FileVerifier::Create(StringRef Filename) { // Open the filename provided. Expected> BinaryOrErr = object::createBinary(Filename); @@ -41,62 +41,80 @@ // Construct the object and allow it to take ownership of the binary. object::OwningBinary Binary = std::move(BinaryOrErr.get()); - FileAnalysis Analysis(std::move(Binary)); + FileVerifier Verifier(std::move(Binary)); - Analysis.Object = dyn_cast(Analysis.Binary.getBinary()); - if (!Analysis.Object) + Verifier.Object = dyn_cast(Verifier.Binary.getBinary()); + if (!Verifier.Object) return make_error(); - Analysis.ObjectTriple = Analysis.Object->makeTriple(); - Analysis.Features = Analysis.Object->getFeatures(); + Verifier.ObjectTriple = Verifier.Object->makeTriple(); + Verifier.Features = Verifier.Object->getFeatures(); // Init the rest of the object. - auto InitResponse = Analysis.initialiseDisassemblyMembers(); + auto InitResponse = Verifier.initialiseDisassemblyMembers(); if (InitResponse) return std::move(InitResponse); - auto SectionParseResponse = Analysis.parseCodeSections(); + auto SectionParseResponse = Verifier.parseCodeSections(); if (SectionParseResponse) return std::move(SectionParseResponse); - return std::move(Analysis); + return std::move(Verifier); } -FileAnalysis::FileAnalysis(object::OwningBinary Binary) +FileVerifier::FileVerifier(object::OwningBinary Binary) : Binary(std::move(Binary)) {} -FileAnalysis::FileAnalysis(const Triple &ObjectTriple, +FileVerifier::FileVerifier(const Triple &ObjectTriple, const SubtargetFeatures &Features) : ObjectTriple(ObjectTriple), Features(Features) {} +Error FileVerifier::printIndirectCFInstructions() const { + for (const auto &Address : IndirectInstructions) { + const auto &InstructionKV = Instructions.find(Address); + if (InstructionKV == Instructions.end()) + return make_error( + formatv("No instruction found at address {0:x}", Address), + inconvertibleErrorCode()); + + const auto &InstrMeta = InstructionKV->second; + outs() << format_hex(Address, 2) << " [" << InstrMeta.SectionName + << "] = " << MII->getName(InstrMeta.Instruction.getOpcode()) << " "; + InstrMeta.Instruction.print(outs()); + outs() << "\n"; + } + + return Error::success(); +} + const Instr * -FileAnalysis::getPrevInstructionSequential(const Instr &InstrMeta) const { +FileVerifier::getPrevInstructionSequential(const Instr &InstrMeta) const { std::map::const_iterator KV = Instructions.find(InstrMeta.VMAddress); if (KV == Instructions.end() || KV == Instructions.begin()) return nullptr; - if (!(--KV)->second.Valid) + if ((--KV)->second.Bad) return nullptr; return &KV->second; } const Instr * -FileAnalysis::getNextInstructionSequential(const Instr &InstrMeta) const { +FileVerifier::getNextInstructionSequential(const Instr &InstrMeta) const { std::map::const_iterator KV = Instructions.find(InstrMeta.VMAddress); - if (KV == Instructions.end() || ++KV == Instructions.end()) + if (KV++ == Instructions.end() || KV == Instructions.end()) return nullptr; - if (!KV->second.Valid) + if (KV->second.Bad) return nullptr; return &KV->second; } -const Instr *FileAnalysis::getInstruction(uint64_t Address) const { +const Instr *FileVerifier::getInstruction(uint64_t Address) const { const auto &InstrKV = Instructions.find(Address); if (InstrKV == Instructions.end()) return nullptr; @@ -104,21 +122,21 @@ return &InstrKV->second; } -const Instr &FileAnalysis::getInstructionOrDie(uint64_t Address) const { +const Instr &FileVerifier::getInstructionOrDie(uint64_t Address) const { const auto &InstrKV = Instructions.find(Address); assert(InstrKV != Instructions.end() && "Address doesn't exist."); return InstrKV->second; } -bool FileAnalysis::isCFITrap(const Instr &InstrMeta) const { +bool FileVerifier::isUndefinedInstruction(const Instr &InstrMeta) const { return MII->getName(InstrMeta.Instruction.getOpcode()) == "TRAP"; } -bool FileAnalysis::canFallThrough(const Instr &InstrMeta) const { - if (!InstrMeta.Valid) +bool FileVerifier::canFallThrough(const Instr &InstrMeta) const { + if (InstrMeta.Bad) return false; - if (isCFITrap(InstrMeta)) + if (isUndefinedInstruction(InstrMeta)) return false; const auto &InstrDesc = MII->get(InstrMeta.Instruction.getOpcode()); @@ -129,11 +147,11 @@ } const Instr * -FileAnalysis::getDefiniteNextInstruction(const Instr &InstrMeta) const { - if (!InstrMeta.Valid) +FileVerifier::getDefiniteNextInstruction(const Instr &InstrMeta) const { + if (InstrMeta.Bad) return nullptr; - if (isCFITrap(InstrMeta)) + if (isUndefinedInstruction(InstrMeta)) return nullptr; const auto &InstrDesc = MII->get(InstrMeta.Instruction.getOpcode()); @@ -150,9 +168,6 @@ if (NextKV == Instructions.end()) return nullptr; - if (!NextKV->second.Valid) - return nullptr; - return &NextKV->second; } @@ -161,14 +176,14 @@ if (NextKV == Instructions.end()) return nullptr; - if (!NextKV->second.Valid) + if (NextKV->second.Bad) return nullptr; return &NextKV->second; } std::set -FileAnalysis::getControlFlowXRefs(const Instr &InstrMeta) const { +FileVerifier::getControlFlowXRefs(const Instr &InstrMeta) const { std::set CFCrossReferences; const Instr *PrevInstruction = getPrevInstructionSequential(InstrMeta); @@ -195,21 +210,21 @@ return CFCrossReferences; } -const std::set &FileAnalysis::getIndirectInstructions() const { +const std::set &FileVerifier::getIndirectInstructions() const { return IndirectInstructions; } -const MCRegisterInfo *FileAnalysis::getRegisterInfo() const { +const MCRegisterInfo *FileVerifier::getRegisterInfo() const { return RegisterInfo.get(); } -const MCInstrInfo *FileAnalysis::getMCInstrInfo() const { return MII.get(); } +const MCInstrInfo *FileVerifier::getMCInstrInfo() const { return MII.get(); } -const MCInstrAnalysis *FileAnalysis::getMCInstrAnalysis() const { +const MCInstrAnalysis *FileVerifier::getMCInstrAnalysis() const { return MIA.get(); } -Error FileAnalysis::initialiseDisassemblyMembers() { +Error FileVerifier::initialiseDisassemblyMembers() { std::string TripleName = ObjectTriple.getTriple(); ArchName = ""; MCPU = ""; @@ -264,7 +279,7 @@ return Error::success(); } -Error FileAnalysis::parseCodeSections() { +Error FileVerifier::parseCodeSections() { for (const object::SectionRef &Section : Object->sections()) { // Ensure only executable sections get analysed. if (!(object::ELFSectionRef(Section).getFlags() & ELF::SHF_EXECINSTR)) @@ -275,24 +290,32 @@ return make_error("Failed to retrieve section contents", inconvertibleErrorCode()); + StringRef SectionName; + if (Section.getName(SectionName)) + SectionName = "UNKNOWN"; + ArrayRef SectionBytes((const uint8_t *)SectionContents.data(), Section.getSize()); - parseSectionContents(SectionBytes, Section.getAddress()); + parseSectionContents(SectionBytes, Section.getAddress(), SectionName); } return Error::success(); } -void FileAnalysis::parseSectionContents(ArrayRef SectionBytes, - uint64_t SectionAddress) { +void FileVerifier::parseSectionContents(ArrayRef SectionBytes, + uint64_t SectionAddress, + StringRef SectionName) { MCInst Instruction; Instr InstrMeta; uint64_t InstructionSize; for (uint64_t Byte = 0; Byte < SectionBytes.size();) { - bool ValidInstruction = - Disassembler->getInstruction(Instruction, InstructionSize, + bool BadInstruction = false; + + // Disassemble the instruction. + if (Disassembler->getInstruction(Instruction, InstructionSize, SectionBytes.drop_front(Byte), 0, nulls(), - outs()) == MCDisassembler::Success; + outs()) != MCDisassembler::Success) + BadInstruction = true; Byte += InstructionSize; @@ -300,11 +323,16 @@ InstrMeta.Instruction = Instruction; InstrMeta.VMAddress = VMAddress; InstrMeta.InstructionSize = InstructionSize; - InstrMeta.Valid = ValidInstruction; - addInstruction(InstrMeta); + InstrMeta.SectionName = SectionName; + InstrMeta.Bad = false; - if (!ValidInstruction) + if (BadInstruction) { + InstrMeta.Bad = true; + addInstruction(InstrMeta); continue; + } + + addInstruction(InstrMeta); // Skip additional parsing for instructions that do not affect the control // flow. @@ -333,7 +361,7 @@ } } -void FileAnalysis::addInstruction(const Instr &Instruction) { +void FileVerifier::addInstruction(const Instr &Instruction) { Instructions[Instruction.VMAddress] = Instruction; } Index: tools/llvm-cfi-verify/GraphBuilder.h =================================================================== --- /dev/null +++ tools/llvm-cfi-verify/GraphBuilder.h @@ -0,0 +1,114 @@ +//===- GraphBuilder.h -------------------------------------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CFI_VERIFY_GRAPH_BUILDER_H +#define LLVM_CFI_VERIFY_GRAPH_BUILDER_H + +#include "FileVerifier.h" + +#include "llvm/BinaryFormat/ELF.h" +#include "llvm/MC/MCAsmInfo.h" +#include "llvm/MC/MCContext.h" +#include "llvm/MC/MCDisassembler/MCDisassembler.h" +#include "llvm/MC/MCInst.h" +#include "llvm/MC/MCInstPrinter.h" +#include "llvm/MC/MCInstrAnalysis.h" +#include "llvm/MC/MCInstrDesc.h" +#include "llvm/MC/MCInstrInfo.h" +#include "llvm/MC/MCObjectFileInfo.h" +#include "llvm/MC/MCRegisterInfo.h" +#include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/Object/Binary.h" +#include "llvm/Object/COFF.h" +#include "llvm/Object/ELFObjectFile.h" +#include "llvm/Object/ObjectFile.h" +#include "llvm/Support/Casting.h" +#include "llvm/Support/CommandLine.h" +#include "llvm/Support/Error.h" +#include "llvm/Support/MemoryBuffer.h" +#include "llvm/Support/TargetRegistry.h" +#include "llvm/Support/TargetSelect.h" +#include "llvm/Support/raw_ostream.h" + +#include +#include +#include +#include + +using Instr = llvm::cfi_verify::FileVerifier::Instr; + +namespace llvm { +namespace cfi_verify { + +extern uint64_t SearchLengthForUndef; +extern uint64_t SearchLengthForConditionalBranch; + +struct ControlFlowNode { + ControlFlowNode *Next; + uint64_t InstructionAddress; + uint64_t FlowLength; +}; + +struct ConditionalBranchNode { + ControlFlowNode *Target; + ControlFlowNode *Fallthrough; + uint64_t InstructionAddress; + // Does this conditional branch successfully instrument CFI protections. + bool CFIProtection; +}; + +// Print the provided node to standard output. +void printConditionalBranchNode(const ConditionalBranchNode *Node); +void printControlFlowNode(const ControlFlowNode *Node, unsigned depth); +std::vector +flattenControlFlowNodeAddresses(const ControlFlowNode *Node); + +struct GraphResult { + ~GraphResult(); + + uint64_t BaseInstructionAddress; + std::vector BranchNodes; + std::vector OrphanedNodes; +}; + +class GraphBuilder { +public: + // Build the control flow graph for a provided control flow node. This method + // will enumerate all branch nodes that can lead to this node, and provide + // them, fully evaulated, in GraphResult::BranchNodes. It will also provide + // any orphaned (i.e. did not make it to a branch node) flows to the provided + // node in GraphResult::OrphanedNodes. + static GraphResult buildFlowGraph(const FileVerifier &Verifier, + uint64_t Address); + +protected: + // Utilised by buildFlowGraph to build the tree out from the provided + // conditional branch node to an undefined instruction. The provided + // conditional branch node must have exactly one of its subtrees set, and will + // update the node's CFIProtection field if a deterministic flow can be found + // to an undefined instruction. + static void buildFlowsToUndefined(const FileVerifier &Verifier, + ConditionalBranchNode *BranchNode); + + // Creates a control flow node with the information from the parent, and links + // it to the provided child. + static ControlFlowNode *createParentNode(const Instr &ParentMeta, + ControlFlowNode *ChildNode); + +private: + static void + buildFlowGraphImpl(const FileVerifier &Verifier, ControlFlowNode *Node, + std::vector *BranchNodes, + std::vector *OrphanedNodes); +}; + +} // end namespace cfi_verify +} // end namespace llvm + +#endif // LLVM_CFI_VERIFY_GRAPH_BUILDER_H Index: tools/llvm-cfi-verify/GraphBuilder.cpp =================================================================== --- /dev/null +++ tools/llvm-cfi-verify/GraphBuilder.cpp @@ -0,0 +1,365 @@ +#include "GraphBuilder.h" + +#include "llvm/BinaryFormat/ELF.h" +#include "llvm/MC/MCAsmInfo.h" +#include "llvm/MC/MCContext.h" +#include "llvm/MC/MCDisassembler/MCDisassembler.h" +#include "llvm/MC/MCInst.h" +#include "llvm/MC/MCInstPrinter.h" +#include "llvm/MC/MCInstrAnalysis.h" +#include "llvm/MC/MCInstrDesc.h" +#include "llvm/MC/MCInstrInfo.h" +#include "llvm/MC/MCObjectFileInfo.h" +#include "llvm/MC/MCRegisterInfo.h" +#include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/Object/Binary.h" +#include "llvm/Object/COFF.h" +#include "llvm/Object/ELFObjectFile.h" +#include "llvm/Object/ObjectFile.h" +#include "llvm/Support/Casting.h" +#include "llvm/Support/CommandLine.h" +#include "llvm/Support/Error.h" +#include "llvm/Support/FormatVariadic.h" +#include "llvm/Support/MemoryBuffer.h" +#include "llvm/Support/TargetRegistry.h" +#include "llvm/Support/TargetSelect.h" +#include "llvm/Support/raw_ostream.h" + +#include + +using Instr = llvm::cfi_verify::FileVerifier::Instr; + +namespace llvm { +namespace cfi_verify { + +uint64_t SearchLengthForUndef; +uint64_t SearchLengthForConditionalBranch; + +static cl::opt SearchLengthForUndefArg( + "search-length-undef", + cl::desc("Specify the maximum amount of instructions " + "to inspect when searching for an undefined " + "instruction from a conditional branch."), + cl::location(SearchLengthForUndef), cl::init(2)); + +static cl::opt SearchLengthForConditionalBranchArg( + "search-length-cb", + cl::desc("Specify the maximum amount of instructions " + "to inspect when searching for a conditional " + "branch from an indirect control flow."), + cl::location(SearchLengthForConditionalBranch), cl::init(20)); + +GraphResult::~GraphResult() { + std::set CFNs; + std::set CBNs; + for (const auto &BranchNode : BranchNodes) { + CBNs.insert(BranchNode); + for (ControlFlowNode *FlowNode = BranchNode->Target; FlowNode; + FlowNode = FlowNode->Next) + CFNs.insert(FlowNode); + + for (ControlFlowNode *FlowNode = BranchNode->Fallthrough; FlowNode; + FlowNode = FlowNode->Next) + CFNs.insert(FlowNode); + } + + for (const auto &FlowNode : OrphanedNodes) + CFNs.insert(FlowNode); + + for (const auto &Node : CFNs) + delete Node; + + for (const auto &Node : CBNs) + delete Node; +} + +void printControlFlowNode(const ControlFlowNode *Node, unsigned depth) { + assert(Node && "Null pointer provided to printControlFlowNode."); + for (unsigned i = 0; i < depth; ++i) + outs() << " "; + + outs() << "[" << Node->FlowLength << "] " + << format_hex(Node->InstructionAddress, 2) << "\n"; + if (Node->Next) + printControlFlowNode(Node->Next, depth + 1); +} + +void printConditionalBranchNode(const ConditionalBranchNode *Node) { + assert(Node && "Null pointer provided to printConditionalBranchNode."); + outs() << format_hex(Node->InstructionAddress, 2) << "\n"; + outs() << " Target:\n"; + if (Node->Target) + printControlFlowNode(Node->Target, 1); + else + outs() << " ???\n"; + + outs() << " Fallthrough:\n"; + if (Node->Fallthrough) + printControlFlowNode(Node->Fallthrough, 1); + else + outs() << " ???\n"; +} + +std::vector +flattenControlFlowNodeAddresses(const ControlFlowNode *Node) { + std::vector Addresses; + while (Node != nullptr) { + Addresses.push_back(Node->InstructionAddress); + Node = Node->Next; + } + return Addresses; +} + +GraphResult GraphBuilder::buildFlowGraph(const FileVerifier &Verifier, + uint64_t Address) { + GraphResult Result; + Result.BaseInstructionAddress = Address; + + const auto &IndirectInstructions = Verifier.getIndirectInstructions(); + + if (IndirectInstructions.find(Address) == IndirectInstructions.end()) + return Result; + + ControlFlowNode *Node = new ControlFlowNode(); + Node->Next = nullptr; + Node->InstructionAddress = Address; + Node->FlowLength = 0; + + buildFlowGraphImpl(Verifier, Node, &Result.BranchNodes, + &Result.OrphanedNodes); + return Result; +} + +void GraphBuilder::buildFlowsToUndefined(const FileVerifier &Verifier, + ConditionalBranchNode *BranchNode) { + assert(BranchNode && "Null pointer provided to buildFlowsToUndefined."); + assert(SearchLengthForUndef > 0 && + "Search length for undefined flow must be greater than zero."); + + // Resolve the metadata for the provided node. + const auto &BranchInstrMetaPtr = + Verifier.getInstruction(BranchNode->InstructionAddress); + if (!BranchInstrMetaPtr) { + errs() << "Failed to build flows from instruction with address" + << format_hex(BranchNode->InstructionAddress, 2) << ".\n"; + return; + } + const auto &BranchInstrMeta = *BranchInstrMetaPtr; + + // Start setting up the next node in the chain. + const Instr *NextMetaPtr; + ControlFlowNode *NextNode = new ControlFlowNode(); + NextNode->Next = nullptr; + NextNode->FlowLength = 1; + + // Find out the next instruction in the chain and add it to the new node. + if (BranchNode->Target && !BranchNode->Fallthrough) { + // We know the target of the branch, find the fallthrough. + NextMetaPtr = Verifier.getNextInstructionSequential(BranchInstrMeta); + if (!NextMetaPtr) { + errs() << "Failed to get next instruction from " + << format_hex(BranchNode->InstructionAddress, 2) << ".\n"; + delete NextNode; + return; + } + + NextNode->InstructionAddress = NextMetaPtr->VMAddress; + BranchNode->Fallthrough = NextNode; // Add the new node to the branch head. + } else if (BranchNode->Fallthrough && !BranchNode->Target) { + // We already know the fallthrough, evaluate the target. + uint64_t Target; + if (!Verifier.getMCInstrAnalysis()->evaluateBranch( + BranchInstrMeta.Instruction, BranchInstrMeta.VMAddress, + BranchInstrMeta.InstructionSize, Target)) { + errs() << "Failed to get branch target for conditional branch at address " + << format_hex(BranchInstrMeta.VMAddress, 2) << ".\n"; + delete NextNode; + return; + } + + // Resolve the meta pointer for the target of this branch. + NextMetaPtr = Verifier.getInstruction(Target); + if (!NextMetaPtr) { + errs() << "Failed to find instruction at address " + << format_hex(Target, 2) << ".\n"; + delete NextNode; + return; + } + + NextNode->InstructionAddress = Target; + BranchNode->Target = NextNode; // Add the new node to the branch head. + } else { + errs() << "ControlBranchNode supplied to buildFlowsToUndefined should " + "provide Target xor Fallthrough.\n"; + delete NextNode; + return; + } + + ControlFlowNode *CurrentNode = NextNode; + const Instr *CurrentMetaPtr = NextMetaPtr; + + // Now the branch head has been set properly, complete the rest of the chain. + for (uint64_t i = 1; i < SearchLengthForUndef; ++i) { + // Check to see whether the chain should die. + if (Verifier.isUndefinedInstruction(*CurrentMetaPtr)) { + BranchNode->CFIProtection = true; + return; + } + + // Find the metadata of the next instruction. + NextMetaPtr = Verifier.getDefiniteNextInstruction(*CurrentMetaPtr); + if (!NextMetaPtr) + return; + + // Setup the next node. + NextNode = new ControlFlowNode(); + NextNode->Next = nullptr; + NextNode->InstructionAddress = NextMetaPtr->VMAddress; + NextNode->FlowLength = CurrentNode->FlowLength + 1; + CurrentNode->Next = NextNode; + + // Finalise ready for the next loop. + CurrentMetaPtr = NextMetaPtr; + CurrentNode = NextNode; + } + + // Final check of the last thing we added to the chain. + if (Verifier.isUndefinedInstruction(*CurrentMetaPtr)) + BranchNode->CFIProtection = true; +} + +ControlFlowNode *GraphBuilder::createParentNode(const Instr &ParentMeta, + ControlFlowNode *ChildNode) { + assert(ChildNode && "Null pointer provided to createParentNode"); + ControlFlowNode *ParentNode = new ControlFlowNode(); + ParentNode->Next = ChildNode; + ParentNode->InstructionAddress = ParentMeta.VMAddress; + ParentNode->FlowLength = ChildNode->FlowLength + 1; + return ParentNode; +} + +void GraphBuilder::buildFlowGraphImpl( + const FileVerifier &Verifier, ControlFlowNode *ChildNode, + std::vector *BranchNodes, + std::vector *OrphanedNodes) { + assert(ChildNode && BranchNodes && OrphanedNodes && + "Null pointer provided to buildFlowGraphImpl."); + + // If we've exceeded the flow length, terminate. + if (ChildNode->FlowLength >= SearchLengthForConditionalBranch) { + OrphanedNodes->push_back(ChildNode); + return; + } + + // Get the metadata for the node instruction. + const auto &InstrMetaPtr = + Verifier.getInstruction(ChildNode->InstructionAddress); + if (!InstrMetaPtr) { + errs() << "Failed to build flow graph for instruction at address " + << format_hex(ChildNode->InstructionAddress, 2) << ".\n"; + OrphanedNodes->push_back(ChildNode); + return; + } + const auto &ChildMeta = *InstrMetaPtr; + + std::set CFCrossRefs = Verifier.getControlFlowXRefs(ChildMeta); + + bool HasValidCrossRef = false; + + for (const auto *ParentMetaPtr : CFCrossRefs) { + assert(ParentMetaPtr && "CFCrossRefs returned nullptr."); + const auto &ParentMeta = *ParentMetaPtr; + const auto &ParentDesc = + Verifier.getMCInstrInfo()->get(ParentMeta.Instruction.getOpcode()); + + if (!ParentDesc.mayAffectControlFlow(ParentMeta.Instruction, + *Verifier.getRegisterInfo())) { + // If this cross reference doesn't affect CF, continue the graph. + buildFlowGraphImpl(Verifier, createParentNode(ParentMeta, ChildNode), + BranchNodes, OrphanedNodes); + HasValidCrossRef = true; + continue; + } else { + // Evaluate the branch target to ascertain whether this XRef is the result + // of a fallthrough or the target of a branch. + uint64_t BranchTarget; + if (!Verifier.getMCInstrAnalysis()->evaluateBranch( + ParentMeta.Instruction, ParentMeta.VMAddress, + ParentMeta.InstructionSize, BranchTarget)) { + errs() << "Failed to evaluate branch target for instruction at address " + << format_hex(ParentMeta.VMAddress, 2) << ".\n"; + OrphanedNodes->push_back(createParentNode(ParentMeta, ChildNode)); + continue; + } + + // Allow unconditional branches to be part of the upwards traversal. + // Ensures that the unconditional branch is actually an XRef to the child. + if (ParentDesc.isUnconditionalBranch()) { + if (BranchTarget == ChildMeta.VMAddress) { + // Ensure the unconditional branch can't fall back on itself. Check + // the current tree. + bool IsUniqueInTree = true; + for (const auto &InstructionAddressInTree : + flattenControlFlowNodeAddresses(ChildNode)) { + if (InstructionAddressInTree == ParentMeta.VMAddress) { + IsUniqueInTree = false; + break; + } + } + + if (!IsUniqueInTree) { + OrphanedNodes->push_back(createParentNode(ParentMeta, ChildNode)); + continue; + } + + ControlFlowNode *NewNode = new ControlFlowNode(); + NewNode->Next = ChildNode; + NewNode->InstructionAddress = ParentMeta.VMAddress; + NewNode->FlowLength = ChildNode->FlowLength + 1; + + buildFlowGraphImpl(Verifier, NewNode, BranchNodes, OrphanedNodes); + HasValidCrossRef = true; + continue; + } else { + errs() << "Control flow to " << format_hex(ChildMeta.VMAddress, 2) + << ", but target resolution of " + << format_hex(ParentMeta.VMAddress, 2) + << " is not this address?\n"; + OrphanedNodes->push_back(createParentNode(ParentMeta, ChildNode)); + continue; + } + } + + // Ensure that any unknown CFs are caught. + if (!ParentDesc.isConditionalBranch()) { + errs() << "Unknown control flow encountered when building graph at " + << format_hex(ChildMeta.VMAddress, 2) << "\n."; + OrphanedNodes->push_back(createParentNode(ParentMeta, ChildNode)); + continue; + } + + // Only direct conditional branches should be present at this point. Setup + // a conditional branch node and build flows to the ud2. + ConditionalBranchNode *BranchNode = new ConditionalBranchNode(); + BranchNode->InstructionAddress = ParentMeta.VMAddress; + BranchNode->Target = nullptr; + BranchNode->Fallthrough = nullptr; + BranchNode->CFIProtection = false; + BranchNodes->push_back(BranchNode); + + if (BranchTarget == ChildMeta.VMAddress) + BranchNode->Target = ChildNode; + else + BranchNode->Fallthrough = ChildNode; + + HasValidCrossRef = true; + buildFlowsToUndefined(Verifier, BranchNode); + } + } + + if (!HasValidCrossRef) + OrphanedNodes->push_back(ChildNode); +} + +} // namespace cfi_verify +} // namespace llvm Index: tools/llvm-cfi-verify/llvm-cfi-verify.cpp =================================================================== --- tools/llvm-cfi-verify/llvm-cfi-verify.cpp +++ tools/llvm-cfi-verify/llvm-cfi-verify.cpp @@ -17,7 +17,7 @@ // //===----------------------------------------------------------------------===// -#include "FileAnalysis.h" +#include "FileVerifier.h" #include "llvm/BinaryFormat/ELF.h" #include "llvm/Support/CommandLine.h" @@ -34,18 +34,6 @@ ExitOnError ExitOnErr; -void printIndirectCFInstructions(const FileAnalysis &Verifier) { - for (uint64_t Address : Verifier.getIndirectInstructions()) { - const auto &InstrMeta = Verifier.getInstructionOrDie(Address); - outs() << format_hex(Address, 2) << " |" - << Verifier.getMCInstrInfo()->getName( - InstrMeta.Instruction.getOpcode()) - << " "; - InstrMeta.Instruction.print(outs()); - outs() << "\n"; - } -} - int main(int argc, char **argv) { cl::ParseCommandLineOptions(argc, argv); @@ -54,8 +42,8 @@ InitializeAllAsmParsers(); InitializeAllDisassemblers(); - FileAnalysis Verifier = ExitOnErr(FileAnalysis::Create(InputFilename)); - printIndirectCFInstructions(Verifier); + FileVerifier Verifier = ExitOnErr(FileVerifier::Create(InputFilename)); + ExitOnErr(Verifier.printIndirectCFInstructions()); return EXIT_SUCCESS; } Index: tools/llvm-cfi-verify/unittests/CMakeLists.txt =================================================================== --- tools/llvm-cfi-verify/unittests/CMakeLists.txt +++ tools/llvm-cfi-verify/unittests/CMakeLists.txt @@ -11,7 +11,8 @@ Support ) - - add_llvm_unittest(CFIVerifyTests - FileAnalysis.cpp ../FileAnalysis.cpp) + FileVerifier.cpp + GraphBuilder.cpp + ../GraphBuilder.cpp + ../FileVerifier.cpp) Index: tools/llvm-cfi-verify/unittests/FileVerifier.cpp =================================================================== --- tools/llvm-cfi-verify/unittests/FileVerifier.cpp +++ tools/llvm-cfi-verify/unittests/FileVerifier.cpp @@ -1,4 +1,4 @@ -//===- llvm/tools/llvm-cfi-verify/unittests/FileAnalysis.cpp --------------===// +//===- llvm/tools/llvm-cfi-verify/unittests/FileVerifier.cpp --------------===// // // The LLVM Compiler Infrastructure // @@ -7,7 +7,7 @@ // //===----------------------------------------------------------------------===// -#include "../FileAnalysis.h" +#include "../FileVerifier.h" #include "gmock/gmock.h" #include "gtest/gtest.h" @@ -37,30 +37,31 @@ #include -using Instr = ::llvm::cfi_verify::FileAnalysis::Instr; +using Instr = ::llvm::cfi_verify::FileVerifier::Instr; using ::testing::Eq; using ::testing::Field; namespace llvm { namespace cfi_verify { namespace { -class ELFx86TestFileAnalysis : public FileAnalysis { +class ELFx86TestFileVerifier : public FileVerifier { public: - ELFx86TestFileAnalysis() - : FileAnalysis(Triple("x86_64--"), SubtargetFeatures()) {} + ELFx86TestFileVerifier() + : FileVerifier(Triple("x86_64--"), SubtargetFeatures()) {} // Expose this method publicly for testing. void parseSectionContents(ArrayRef SectionBytes, - uint64_t SectionAddress) { - FileAnalysis::parseSectionContents(SectionBytes, SectionAddress); + uint64_t SectionAddress, StringRef SectionName) { + FileVerifier::parseSectionContents(SectionBytes, SectionAddress, + SectionName); } Error initialiseDisassemblyMembers() { - return FileAnalysis::initialiseDisassemblyMembers(); + return FileVerifier::initialiseDisassemblyMembers(); } }; -class BasicFileAnalysisTest : public ::testing::Test { +class BasicFileVerifierTest : public ::testing::Test { protected: virtual void SetUp() { if (Verifier.initialiseDisassemblyMembers()) { @@ -68,10 +69,10 @@ } } - ELFx86TestFileAnalysis Verifier; + ELFx86TestFileVerifier Verifier; }; -TEST_F(BasicFileAnalysisTest, BasicDisassemblyTraversalTest) { +TEST_F(BasicFileVerifierTest, BasicDisassemblyTraversalTest) { Verifier.parseSectionContents( { 0x90, // 0: nop @@ -84,7 +85,7 @@ 0x41, 0x0e, // 21: rex.B (bad) 0x62, 0x72, 0x65, 0x61, 0x6b, // 23: (bad) {%k1} }, - 0xDEADBEEF); + 0xDEADBEEF, "Test"); EXPECT_EQ(nullptr, Verifier.getInstruction(0x0)); EXPECT_EQ(nullptr, Verifier.getInstruction(0x1000)); @@ -94,7 +95,8 @@ EXPECT_NE(nullptr, InstrMeta); EXPECT_EQ(0xDEADBEEF, InstrMeta->VMAddress); EXPECT_EQ(1u, InstrMeta->InstructionSize); - EXPECT_TRUE(InstrMeta->Valid); + EXPECT_EQ("Test", InstrMeta->SectionName); + EXPECT_FALSE(InstrMeta->Bad); const auto *NextInstrMeta = Verifier.getNextInstructionSequential(*InstrMeta); EXPECT_EQ(nullptr, Verifier.getPrevInstructionSequential(*InstrMeta)); @@ -106,7 +108,8 @@ EXPECT_EQ(NextInstrMeta, InstrMeta); EXPECT_EQ(0xDEADBEEF + 1, InstrMeta->VMAddress); EXPECT_EQ(2u, InstrMeta->InstructionSize); - EXPECT_TRUE(InstrMeta->Valid); + EXPECT_EQ("Test", InstrMeta->SectionName); + EXPECT_FALSE(InstrMeta->Bad); NextInstrMeta = Verifier.getNextInstructionSequential(*InstrMeta); EXPECT_EQ(PrevInstrMeta, Verifier.getPrevInstructionSequential(*InstrMeta)); @@ -118,7 +121,8 @@ EXPECT_EQ(NextInstrMeta, InstrMeta); EXPECT_EQ(0xDEADBEEF + 3, InstrMeta->VMAddress); EXPECT_EQ(3u, InstrMeta->InstructionSize); - EXPECT_TRUE(InstrMeta->Valid); + EXPECT_EQ("Test", InstrMeta->SectionName); + EXPECT_FALSE(InstrMeta->Bad); NextInstrMeta = Verifier.getNextInstructionSequential(*InstrMeta); EXPECT_EQ(PrevInstrMeta, Verifier.getPrevInstructionSequential(*InstrMeta)); @@ -130,7 +134,8 @@ EXPECT_EQ(NextInstrMeta, InstrMeta); EXPECT_EQ(0xDEADBEEF + 6, InstrMeta->VMAddress); EXPECT_EQ(4u, InstrMeta->InstructionSize); - EXPECT_TRUE(InstrMeta->Valid); + EXPECT_EQ("Test", InstrMeta->SectionName); + EXPECT_FALSE(InstrMeta->Bad); NextInstrMeta = Verifier.getNextInstructionSequential(*InstrMeta); EXPECT_EQ(PrevInstrMeta, Verifier.getPrevInstructionSequential(*InstrMeta)); @@ -142,7 +147,8 @@ EXPECT_EQ(NextInstrMeta, InstrMeta); EXPECT_EQ(0xDEADBEEF + 10, InstrMeta->VMAddress); EXPECT_EQ(10u, InstrMeta->InstructionSize); - EXPECT_TRUE(InstrMeta->Valid); + EXPECT_EQ("Test", InstrMeta->SectionName); + EXPECT_FALSE(InstrMeta->Bad); EXPECT_EQ(nullptr, Verifier.getNextInstructionSequential(*InstrMeta)); EXPECT_EQ(PrevInstrMeta, Verifier.getPrevInstructionSequential(*InstrMeta)); @@ -153,7 +159,8 @@ EXPECT_NE(nullptr, InstrMeta); EXPECT_EQ(0xDEADBEEF + 20, InstrMeta->VMAddress); EXPECT_EQ(1u, InstrMeta->InstructionSize); - EXPECT_FALSE(InstrMeta->Valid); + EXPECT_EQ("Test", InstrMeta->SectionName); + EXPECT_TRUE(InstrMeta->Bad); EXPECT_EQ(nullptr, Verifier.getNextInstructionSequential(*InstrMeta)); EXPECT_EQ(PrevInstrMeta, Verifier.getPrevInstructionSequential(*InstrMeta)); @@ -163,7 +170,8 @@ EXPECT_NE(nullptr, InstrMeta); EXPECT_EQ(0xDEADBEEF + 21, InstrMeta->VMAddress); EXPECT_EQ(2u, InstrMeta->InstructionSize); - EXPECT_FALSE(InstrMeta->Valid); + EXPECT_EQ("Test", InstrMeta->SectionName); + EXPECT_TRUE(InstrMeta->Bad); EXPECT_EQ(nullptr, Verifier.getNextInstructionSequential(*InstrMeta)); EXPECT_EQ(nullptr, Verifier.getPrevInstructionSequential(*InstrMeta)); @@ -173,20 +181,21 @@ EXPECT_NE(nullptr, InstrMeta); EXPECT_EQ(0xDEADBEEF + 23, InstrMeta->VMAddress); EXPECT_EQ(5u, InstrMeta->InstructionSize); - EXPECT_FALSE(InstrMeta->Valid); + EXPECT_EQ("Test", InstrMeta->SectionName); + EXPECT_TRUE(InstrMeta->Bad); EXPECT_EQ(nullptr, Verifier.getNextInstructionSequential(*InstrMeta)); EXPECT_EQ(nullptr, Verifier.getPrevInstructionSequential(*InstrMeta)); } -TEST_F(BasicFileAnalysisTest, PrevAndNextFromBadInst) { +TEST_F(BasicFileVerifierTest, PrevAndNextFromBadInst) { Verifier.parseSectionContents( { 0x90, // 0: nop 0x2f, // 1: (bad) 0x90 // 2: nop }, - 0xDEADBEEF); + 0xDEADBEEF, "Test"); const auto &BadInstrMeta = Verifier.getInstructionOrDie(0xDEADBEEF + 1); const auto *GoodInstrMeta = Verifier.getPrevInstructionSequential(BadInstrMeta); @@ -200,7 +209,7 @@ EXPECT_EQ(1u, GoodInstrMeta->InstructionSize); } -TEST_F(BasicFileAnalysisTest, CFITrapTest) { +TEST_F(BasicFileVerifierTest, UndefinedInstructionTest) { Verifier.parseSectionContents( { 0x90, // 0: nop @@ -214,27 +223,27 @@ 0x62, 0x72, 0x65, 0x61, 0x6b, // 23: (bad) {%k1} 0x0f, 0x0b // 28: ud2 }, - 0xDEADBEEF); + 0xDEADBEEF, "Test"); - EXPECT_FALSE(Verifier.isCFITrap( + EXPECT_FALSE(Verifier.isUndefinedInstruction( Verifier.getInstructionOrDie(0xDEADBEEF))); - EXPECT_FALSE(Verifier.isCFITrap( + EXPECT_FALSE(Verifier.isUndefinedInstruction( Verifier.getInstructionOrDie(0xDEADBEEF + 3))); - EXPECT_FALSE(Verifier.isCFITrap( + EXPECT_FALSE(Verifier.isUndefinedInstruction( Verifier.getInstructionOrDie(0xDEADBEEF + 6))); - EXPECT_FALSE(Verifier.isCFITrap( + EXPECT_FALSE(Verifier.isUndefinedInstruction( Verifier.getInstructionOrDie(0xDEADBEEF + 10))); - EXPECT_FALSE(Verifier.isCFITrap( + EXPECT_FALSE(Verifier.isUndefinedInstruction( Verifier.getInstructionOrDie(0xDEADBEEF + 20))); - EXPECT_FALSE(Verifier.isCFITrap( + EXPECT_FALSE(Verifier.isUndefinedInstruction( Verifier.getInstructionOrDie(0xDEADBEEF + 21))); - EXPECT_FALSE(Verifier.isCFITrap( + EXPECT_FALSE(Verifier.isUndefinedInstruction( Verifier.getInstructionOrDie(0xDEADBEEF + 23))); - EXPECT_TRUE(Verifier.isCFITrap( + EXPECT_TRUE(Verifier.isUndefinedInstruction( Verifier.getInstructionOrDie(0xDEADBEEF + 28))); } -TEST_F(BasicFileAnalysisTest, FallThroughTest) { +TEST_F(BasicFileVerifierTest, FallThroughTest) { Verifier.parseSectionContents( { 0x90, // 0: nop @@ -248,7 +257,7 @@ 0x75, 0x00, // 17: jne +0 0xc3, // 19: retq }, - 0xDEADBEEF); + 0xDEADBEEF, "Test"); EXPECT_TRUE( Verifier.canFallThrough(Verifier.getInstructionOrDie(0xDEADBEEF))); @@ -272,7 +281,7 @@ Verifier.canFallThrough(Verifier.getInstructionOrDie(0xDEADBEEF + 19))); } -TEST_F(BasicFileAnalysisTest, DefiniteNextInstructionTest) { +TEST_F(BasicFileVerifierTest, DefiniteNextInstructionTest) { Verifier.parseSectionContents( { 0x90, // 0: nop @@ -293,7 +302,7 @@ 0xeb, 0xdd, // 36: jmp 3 [-35] 0xeb, 0xdc, // 38: jmp 4 [-36] }, - 0xDEADBEEF); + 0xDEADBEEF, "Test"); const auto *Current = Verifier.getInstruction(0xDEADBEEF); const auto *Next = Verifier.getDefiniteNextInstruction(*Current); @@ -352,7 +361,9 @@ EXPECT_EQ(0xDEADBEEF + 1, Next->VMAddress); Current = Verifier.getInstruction(0xDEADBEEF + 36); - EXPECT_EQ(nullptr, Verifier.getDefiniteNextInstruction(*Current)); + Next = Verifier.getDefiniteNextInstruction(*Current); + EXPECT_NE(nullptr, Next); + EXPECT_EQ(0xDEADBEEF + 3, Next->VMAddress); Current = Verifier.getInstruction(0xDEADBEEF + 38); Next = Verifier.getDefiniteNextInstruction(*Current); @@ -360,7 +371,7 @@ EXPECT_EQ(0xDEADBEEF + 4, Next->VMAddress); } -TEST_F(BasicFileAnalysisTest, ControlFlowXRefsTest) { +TEST_F(BasicFileVerifierTest, ControlFlowXRefsTest) { Verifier.parseSectionContents( { 0x90, // 0: nop @@ -381,7 +392,7 @@ 0xeb, 0xdd, // 36: jmp 3 [-35] 0xeb, 0xdc, // 38: jmp 4 [-36] }, - 0xDEADBEEF); + 0xDEADBEEF, "Test"); const auto *InstrMetaPtr = &Verifier.getInstructionOrDie(0xDEADBEEF); std::set XRefs = Verifier.getControlFlowXRefs(*InstrMetaPtr); EXPECT_TRUE(XRefs.empty()); @@ -462,7 +473,6 @@ EXPECT_TRUE(Verifier.getControlFlowXRefs(*InstrMetaPtr).empty()); } - } // anonymous namespace } // end namespace cfi_verify } // end namespace llvm Index: tools/llvm-cfi-verify/unittests/GraphBuilder.cpp =================================================================== --- /dev/null +++ tools/llvm-cfi-verify/unittests/GraphBuilder.cpp @@ -0,0 +1,505 @@ +//===- llvm/tools/llvm-cfi-verify/unittests/GraphBuilder.cpp --------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "../GraphBuilder.h" +#include "../FileVerifier.h" +#include "gmock/gmock.h" +#include "gtest/gtest.h" + +#include "llvm/BinaryFormat/ELF.h" +#include "llvm/MC/MCAsmInfo.h" +#include "llvm/MC/MCContext.h" +#include "llvm/MC/MCDisassembler/MCDisassembler.h" +#include "llvm/MC/MCInst.h" +#include "llvm/MC/MCInstPrinter.h" +#include "llvm/MC/MCInstrAnalysis.h" +#include "llvm/MC/MCInstrDesc.h" +#include "llvm/MC/MCInstrInfo.h" +#include "llvm/MC/MCObjectFileInfo.h" +#include "llvm/MC/MCRegisterInfo.h" +#include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/Object/Binary.h" +#include "llvm/Object/COFF.h" +#include "llvm/Object/ELFObjectFile.h" +#include "llvm/Object/ObjectFile.h" +#include "llvm/Support/Casting.h" +#include "llvm/Support/CommandLine.h" +#include "llvm/Support/Error.h" +#include "llvm/Support/MemoryBuffer.h" +#include "llvm/Support/TargetRegistry.h" +#include "llvm/Support/TargetSelect.h" +#include "llvm/Support/raw_ostream.h" + +#include + +using Instr = ::llvm::cfi_verify::FileVerifier::Instr; +using ::testing::Each; +using ::testing::ElementsAre; +using ::testing::Eq; +using ::testing::Field; +using ::testing::IsEmpty; +using ::testing::ResultOf; +using ::testing::SizeIs; + +namespace llvm { +namespace cfi_verify { +// Custom node printers for gtest. +void PrintControlFlowNode(ControlFlowNode *Node, unsigned depth, + ::std::ostream *os) { + for (unsigned i = 0; i < depth; ++i) + *os << " "; + + if (Node == nullptr) { + *os << "nullptr"; + return; + } + + *os << "[" << Node->FlowLength << "] 0x" << std::hex + << Node->InstructionAddress << std::dec; + if (Node->Next) { + *os << "\n"; + PrintControlFlowNode(Node->Next, depth + 1, os); + } +} + +void PrintTo(ControlFlowNode *Node, ::std::ostream *os) { + *os << "\nControl Flow Node:\n"; + PrintControlFlowNode(Node, 0, os); +} + +void PrintTo(ConditionalBranchNode *Node, ::std::ostream *os) { + *os << "\nConditional Branch Node:\n"; + if (Node == nullptr) { + *os << "nullptr"; + return; + } + + *os << "0x" << std::hex << Node->InstructionAddress << std::dec << "\n"; + *os << " Target:\n"; + if (Node->Target) { + PrintControlFlowNode(Node->Target, 1, os); + *os << "\n"; + } else { + *os << " ???\n"; + } + + *os << " Fallthrough:\n"; + if (Node->Fallthrough) { + PrintControlFlowNode(Node->Fallthrough, 1, os); + } else { + *os << " ???"; + } +} + +namespace { +class ELFx86TestFileVerifier : public FileVerifier { +public: + ELFx86TestFileVerifier() + : FileVerifier(Triple("x86_64--"), SubtargetFeatures()) {} + + // Expose this method publicly for testing. + void parseSectionContents(ArrayRef SectionBytes, + uint64_t SectionAddress, StringRef SectionName) { + FileVerifier::parseSectionContents(SectionBytes, SectionAddress, + SectionName); + } + + Error initialiseDisassemblyMembers() { + return FileVerifier::initialiseDisassemblyMembers(); + } +}; + +class BasicGraphBuilderTest : public ::testing::Test { +protected: + virtual void SetUp() { + if (Verifier.initialiseDisassemblyMembers()) { + exit(EXIT_FAILURE); + } + } + + ELFx86TestFileVerifier Verifier; +}; + +TEST_F(BasicGraphBuilderTest, BuildFlowGraphTestSinglePathFallthroughUd2) { + Verifier.parseSectionContents( + { + 0x75, 0x02, // 0: jne 4 [+2] + 0x0f, 0x0b, // 2: ud2 + 0xff, 0x10, // 4: callq *(%rax) + }, + 0xDEADBEEF, "Test"); + const auto Result = GraphBuilder::buildFlowGraph(Verifier, 0xDEADBEEF + 4); + + EXPECT_THAT(Result.OrphanedNodes, IsEmpty()); + EXPECT_THAT(Result.BranchNodes, SizeIs(1)); + EXPECT_THAT(Result.BranchNodes, + Each(Field(&ConditionalBranchNode::CFIProtection, Eq(true)))); + EXPECT_THAT(Result.BranchNodes, + Contains(AllOf(Field(&ConditionalBranchNode::InstructionAddress, + Eq(0xDEADBEEF)), + Field(&ConditionalBranchNode::Fallthrough, + ResultOf(flattenControlFlowNodeAddresses, + ElementsAre(0xDEADBEEF + 2))), + Field(&ConditionalBranchNode::Target, + ResultOf(flattenControlFlowNodeAddresses, + ElementsAre(0xDEADBEEF + 4)))))); +} + +TEST_F(BasicGraphBuilderTest, BuildFlowGraphTestSinglePathJumpUd2) { + Verifier.parseSectionContents( + { + 0x75, 0x02, // 0: jne 4 [+2] + 0xff, 0x10, // 2: callq *(%rax) + 0x0f, 0x0b, // 4: ud2 + }, + 0xDEADBEEF, "Test"); + const auto Result = GraphBuilder::buildFlowGraph(Verifier, 0xDEADBEEF + 2); + + EXPECT_THAT(Result.OrphanedNodes, IsEmpty()); + EXPECT_THAT(Result.BranchNodes, SizeIs(1)); + EXPECT_THAT(Result.BranchNodes, + Each(Field(&ConditionalBranchNode::CFIProtection, Eq(true)))); + EXPECT_THAT(Result.BranchNodes, + Contains(AllOf(Field(&ConditionalBranchNode::InstructionAddress, + Eq(0xDEADBEEF)), + Field(&ConditionalBranchNode::Fallthrough, + ResultOf(flattenControlFlowNodeAddresses, + ElementsAre(0xDEADBEEF + 2))), + Field(&ConditionalBranchNode::Target, + ResultOf(flattenControlFlowNodeAddresses, + ElementsAre(0xDEADBEEF + 4)))))); +} + +TEST_F(BasicGraphBuilderTest, BuildFlowGraphTestDualPathDualUd2) { + Verifier.parseSectionContents( + { + 0x75, 0x03, // 0: jne 5 [+3] + 0x90, // 2: nop + 0xff, 0x10, // 3: callq *(%rax) + 0x0f, 0x0b, // 5: ud2 + 0x75, 0xf9, // 7: jne 2 [-7] + 0x0f, 0x0b, // 9: ud2 + }, + 0xDEADBEEF, "Test"); + const auto Result = GraphBuilder::buildFlowGraph(Verifier, 0xDEADBEEF + 3); + + EXPECT_THAT(Result.OrphanedNodes, IsEmpty()); + EXPECT_THAT(Result.BranchNodes, SizeIs(2)); + EXPECT_THAT(Result.BranchNodes, + Each(Field(&ConditionalBranchNode::CFIProtection, Eq(true)))); + EXPECT_THAT( + Result.BranchNodes, + Contains(AllOf( + Field(&ConditionalBranchNode::InstructionAddress, Eq(0xDEADBEEF)), + Field(&ConditionalBranchNode::Fallthrough, + ResultOf(flattenControlFlowNodeAddresses, + ElementsAre(0xDEADBEEF + 2, 0xDEADBEEF + 3))), + Field(&ConditionalBranchNode::Target, + ResultOf(flattenControlFlowNodeAddresses, + ElementsAre(0xDEADBEEF + 5)))))); + EXPECT_THAT( + Result.BranchNodes, + Contains(AllOf( + Field(&ConditionalBranchNode::InstructionAddress, Eq(0xDEADBEEF + 7)), + Field(&ConditionalBranchNode::Fallthrough, + ResultOf(flattenControlFlowNodeAddresses, + ElementsAre(0xDEADBEEF + 9))), + Field(&ConditionalBranchNode::Target, + ResultOf(flattenControlFlowNodeAddresses, + ElementsAre(0xDEADBEEF + 2, 0xDEADBEEF + 3)))))); +} + +TEST_F(BasicGraphBuilderTest, BuildFlowGraphTestDualPathSingleUd2) { + Verifier.parseSectionContents( + { + 0x75, 0x05, // 0: jne 7 [+5] + 0x90, // 2: nop + 0xff, 0x10, // 3: callq *(%rax) + 0x75, 0xfb, // 5: jne 2 [-5] + 0x0f, 0x0b, // 7: ud2 + }, + 0xDEADBEEF, "Test"); + GraphResult Result = GraphBuilder::buildFlowGraph(Verifier, 0xDEADBEEF + 3); + + EXPECT_THAT(Result.OrphanedNodes, IsEmpty()); + EXPECT_THAT(Result.BranchNodes, SizeIs(2)); + EXPECT_THAT(Result.BranchNodes, + Each(Field(&ConditionalBranchNode::CFIProtection, Eq(true)))); + EXPECT_THAT( + Result.BranchNodes, + Contains(AllOf( + Field(&ConditionalBranchNode::InstructionAddress, Eq(0xDEADBEEF)), + Field(&ConditionalBranchNode::Fallthrough, + ResultOf(flattenControlFlowNodeAddresses, + ElementsAre(0xDEADBEEF + 2, 0xDEADBEEF + 3))), + Field(&ConditionalBranchNode::Target, + ResultOf(flattenControlFlowNodeAddresses, + ElementsAre(0xDEADBEEF + 7)))))); + EXPECT_THAT( + Result.BranchNodes, + Contains(AllOf( + Field(&ConditionalBranchNode::InstructionAddress, Eq(0xDEADBEEF + 5)), + Field(&ConditionalBranchNode::Fallthrough, + ResultOf(flattenControlFlowNodeAddresses, + ElementsAre(0xDEADBEEF + 7))), + Field(&ConditionalBranchNode::Target, + ResultOf(flattenControlFlowNodeAddresses, + ElementsAre(0xDEADBEEF + 2, 0xDEADBEEF + 3)))))); +} + +TEST_F(BasicGraphBuilderTest, BuildFlowGraphFailures) { + Verifier.parseSectionContents( + { + 0x90, // 0: nop + 0x75, 0xfe, // 1: jne 1 [-2] + }, + 0xDEADBEEF, "Test"); + GraphResult Result = GraphBuilder::buildFlowGraph(Verifier, 0xDEADBEEF); + EXPECT_THAT(Result.OrphanedNodes, IsEmpty()); + EXPECT_THAT(Result.BranchNodes, IsEmpty()); + + Result = GraphBuilder::buildFlowGraph(Verifier, 0xDEADBEEF + 1); + EXPECT_THAT(Result.OrphanedNodes, IsEmpty()); + EXPECT_THAT(Result.BranchNodes, IsEmpty()); + + Result = GraphBuilder::buildFlowGraph(Verifier, 0xDEADC0DE); + EXPECT_THAT(Result.OrphanedNodes, IsEmpty()); + EXPECT_THAT(Result.BranchNodes, IsEmpty()); +} + +TEST_F(BasicGraphBuilderTest, BuildFlowGraphNoXrefs) { + Verifier.parseSectionContents( + { + 0xeb, 0xfe, // 0: jmp 0 [-2] + 0xff, 0x10, // 2: callq *(%rax) + }, + 0xDEADBEEF, "Test"); + GraphResult Result = GraphBuilder::buildFlowGraph(Verifier, 0xDEADBEEF + 2); + EXPECT_THAT(Result.OrphanedNodes, SizeIs(1)); + EXPECT_THAT(Result.BranchNodes, IsEmpty()); + EXPECT_THAT(Result.OrphanedNodes, + Contains(AllOf(Field(&ControlFlowNode::InstructionAddress, + Eq(0xDEADBEEF + 2)), + Field(&ControlFlowNode::Next, Eq(nullptr))))); +} + +TEST_F(BasicGraphBuilderTest, BuildFlowGraphConditionalInfiniteLoop) { + Verifier.parseSectionContents( + { + 0x75, 0xfe, // 0: jne 0 [-2] + 0xff, 0x10, // 2: callq *(%rax) + }, + 0xDEADBEEF, "Test"); + GraphResult Result = GraphBuilder::buildFlowGraph(Verifier, 0xDEADBEEF + 2); + EXPECT_THAT(Result.OrphanedNodes, IsEmpty()); + EXPECT_THAT(Result.BranchNodes, SizeIs(1)); + EXPECT_THAT( + Result.BranchNodes, + Each(AllOf(Field(&ConditionalBranchNode::CFIProtection, Eq(false)), + Field(&ConditionalBranchNode::Target, + ResultOf(flattenControlFlowNodeAddresses, + ElementsAre(0xDEADBEEF))), + Field(&ConditionalBranchNode::Fallthrough, + ResultOf(flattenControlFlowNodeAddresses, + ElementsAre(0xDEADBEEF + 2)))))); +} + +TEST_F(BasicGraphBuilderTest, BuildFlowGraphUnconditionalInfiniteLoop) { + Verifier.parseSectionContents( + { + 0x75, 0x02, // 0: jne 4 [+2] + 0xeb, 0xfc, // 2: jmp 0 [-4] + 0xff, 0x10, // 4: callq *(%rax) + }, + 0xDEADBEEF, "Test"); + GraphResult Result = GraphBuilder::buildFlowGraph(Verifier, 0xDEADBEEF + 4); + EXPECT_THAT(Result.OrphanedNodes, IsEmpty()); + EXPECT_THAT(Result.BranchNodes, SizeIs(1)); + EXPECT_THAT( + Result.BranchNodes, + Contains(AllOf( + Field(&ConditionalBranchNode::InstructionAddress, Eq(0xDEADBEEF)), + Field(&ConditionalBranchNode::Fallthrough, + ResultOf(flattenControlFlowNodeAddresses, + ElementsAre(0xDEADBEEF + 2, 0xDEADBEEF))), + Field(&ConditionalBranchNode::Target, + ResultOf(flattenControlFlowNodeAddresses, + ElementsAre(0xDEADBEEF + 4)))))); +} + +TEST_F(BasicGraphBuilderTest, BuildFlowGraphNoFlowsToIndirection) { + Verifier.parseSectionContents( + { + 0x75, 0x00, // 0: jne 2 [+0] + 0xeb, 0xfc, // 2: jmp 0 [-4] + 0xff, 0x10, // 4: callq *(%rax) + }, + 0xDEADBEEF, "Test"); + GraphResult Result = GraphBuilder::buildFlowGraph(Verifier, 0xDEADBEEF + 4); + EXPECT_THAT(Result.OrphanedNodes, SizeIs(1)); + EXPECT_THAT(Result.OrphanedNodes, + Contains(AllOf(Field(&ControlFlowNode::InstructionAddress, + Eq(0xDEADBEEF + 4)), + Field(&ControlFlowNode::Next, Eq(nullptr))))); + EXPECT_THAT(Result.BranchNodes, IsEmpty()); +} + +TEST_F(BasicGraphBuilderTest, BuildFlowGraphLengthExceededUpwards) { + Verifier.parseSectionContents( + { + 0x75, 0x06, // 0: jne 8 [+6] + 0x90, // 2: nop + 0x90, // 3: nop + 0x90, // 4: nop + 0x90, // 5: nop + 0xff, 0x10, // 6: callq *(%rax) + 0x0f, 0x0b, // 8: ud2 + }, + 0xDEADBEEF, "Test"); + uint64_t PrevSearchLengthForConditionalBranch = + SearchLengthForConditionalBranch; + SearchLengthForConditionalBranch = 2; + + GraphResult Result = GraphBuilder::buildFlowGraph(Verifier, 0xDEADBEEF + 6); + EXPECT_THAT(Result.OrphanedNodes, SizeIs(1)); + EXPECT_THAT(Result.OrphanedNodes, + Each(ResultOf(flattenControlFlowNodeAddresses, + ElementsAre(0xDEADBEEF + 4, 0xDEADBEEF + 5, + 0xDEADBEEF + 6)))); + EXPECT_THAT(Result.BranchNodes, IsEmpty()); + + SearchLengthForConditionalBranch = PrevSearchLengthForConditionalBranch; +} + +TEST_F(BasicGraphBuilderTest, BuildFlowGraphLengthExceededDownwards) { + Verifier.parseSectionContents( + { + 0x75, 0x02, // 0: jne 4 [+2] + 0xff, 0x10, // 2: callq *(%rax) + 0x90, // 4: nop + 0x90, // 5: nop + 0x90, // 6: nop + 0x90, // 7: nop + 0x0f, 0x0b, // 8: ud2 + }, + 0xDEADBEEF, "Test"); + uint64_t PrevSearchLengthForUndef = SearchLengthForUndef; + SearchLengthForUndef = 2; + + GraphResult Result = GraphBuilder::buildFlowGraph(Verifier, 0xDEADBEEF + 2); + EXPECT_THAT(Result.OrphanedNodes, IsEmpty()); + EXPECT_THAT( + Result.BranchNodes, + Each(AllOf( + Field(&ConditionalBranchNode::CFIProtection, Eq(false)), + Field(&ConditionalBranchNode::InstructionAddress, Eq(0xDEADBEEF)), + Field(&ConditionalBranchNode::Target, + ResultOf(flattenControlFlowNodeAddresses, + ElementsAre(0xDEADBEEF + 4, 0xDEADBEEF + 5))), + Field(&ConditionalBranchNode::Fallthrough, + ResultOf(flattenControlFlowNodeAddresses, + ElementsAre(0xDEADBEEF + 2)))))); + + SearchLengthForUndef = PrevSearchLengthForUndef; +} + +TEST_F(BasicGraphBuilderTest, BuildFlowGraphComplexExample) { + // The following code has this graph (in DOT format): + // digraph G { + // "0" -> "20" + // "0" -> "2" + // "20" -> "21" + // "4" -> "22 (ud2)" + // "21" -> "22 (ud2)" + // "4" -> "6" + // "6" -> "7" + // "2" -> "7" + // "7" -> "8" + // "8" -> "9 (indirect)" + // "13" -> "15 (error)" + // "13" -> "9 (indirect)" + // "11" -> "9 (indirect)" + // } + // Or, in image format: https://i.imgur.com/aX5fCoi.png + + Verifier.parseSectionContents( + { + 0x75, 0x12, // 0: jne 20 [+18] + 0xeb, 0x03, // 2: jmp 7 [+3] + 0x75, 0x10, // 4: jne 22 [+16] + 0x90, // 6: nop + 0x90, // 7: nop + 0x90, // 8: nop + 0xff, 0x10, // 9: callq *(%rax) + 0xeb, 0xfc, // 11: jmp 9 [-4] + 0x75, 0xfa, // 13: jne 9 [-6] + 0xe8, 0x78, 0x56, 0x34, 0x12, // 15: callq OUTOFBOUNDS [+0x12345678] + 0x90, // 20: nop + 0x90, // 21: nop + 0x0f, 0x0b, // 22: ud2 + }, + 0x1000, "Test"); + uint64_t PrevSearchLengthForUndef = SearchLengthForUndef; + SearchLengthForUndef = 5; + + GraphResult Result = GraphBuilder::buildFlowGraph(Verifier, 0x1000 + 9); + + EXPECT_THAT(Result.OrphanedNodes, SizeIs(1)); + EXPECT_THAT(Result.BranchNodes, SizeIs(3)); + + EXPECT_THAT( + Result.OrphanedNodes, + Each(AllOf(Field(&ControlFlowNode::InstructionAddress, Eq(0x1000u + 11)), + ResultOf(flattenControlFlowNodeAddresses, + ElementsAre(0x1000 + 11, 0x1000 + 9))))); + + EXPECT_THAT( + Result.BranchNodes, + Contains(AllOf( + Field(&ConditionalBranchNode::CFIProtection, Eq(true)), + Field(&ConditionalBranchNode::InstructionAddress, Eq(0x1000u)), + Field(&ConditionalBranchNode::Target, + ResultOf(flattenControlFlowNodeAddresses, + ElementsAre(0x1000 + 20, 0x1000 + 21, 0x1000 + 22))), + Field(&ConditionalBranchNode::Fallthrough, + ResultOf(flattenControlFlowNodeAddresses, + ElementsAre(0x1000 + 2, 0x1000 + 7, 0x1000 + 8, + 0x1000 + 9)))))); + + EXPECT_THAT( + Result.BranchNodes, + Contains(AllOf( + Field(&ConditionalBranchNode::CFIProtection, Eq(true)), + Field(&ConditionalBranchNode::InstructionAddress, Eq(0x1000u + 4)), + Field(&ConditionalBranchNode::Target, + ResultOf(flattenControlFlowNodeAddresses, + ElementsAre(0x1000 + 22))), + Field(&ConditionalBranchNode::Fallthrough, + ResultOf(flattenControlFlowNodeAddresses, + ElementsAre(0x1000 + 6, 0x1000 + 7, 0x1000 + 8, + 0x1000 + 9)))))); + + EXPECT_THAT( + Result.BranchNodes, + Contains(AllOf( + Field(&ConditionalBranchNode::CFIProtection, Eq(false)), + Field(&ConditionalBranchNode::InstructionAddress, Eq(0x1000u + 13)), + Field(&ConditionalBranchNode::Target, + ResultOf(flattenControlFlowNodeAddresses, + ElementsAre(0x1000 + 9))), + Field(&ConditionalBranchNode::Fallthrough, + ResultOf(flattenControlFlowNodeAddresses, + ElementsAre(0x1000 + 15)))))); + + SearchLengthForUndef = PrevSearchLengthForUndef; +} + +} // anonymous namespace +} // end namespace cfi_verify +} // end namespace llvm Index: tools/llvm-cov/CoverageReport.h =================================================================== --- tools/llvm-cov/CoverageReport.h +++ tools/llvm-cov/CoverageReport.h @@ -50,7 +50,7 @@ /// Render file reports for the files specified in \p Files and the functions /// in \p Filters. void renderFileReports(raw_ostream &OS, ArrayRef Files, - const CoverageFiltersMatchAll &Filters) const; + const CoverageFilter &Filters) const; }; } // end namespace llvm Index: tools/llvm-cov/CoverageReport.cpp =================================================================== --- tools/llvm-cov/CoverageReport.cpp +++ tools/llvm-cov/CoverageReport.cpp @@ -367,9 +367,9 @@ renderFileReports(OS, UniqueSourceFiles, CoverageFiltersMatchAll()); } -void CoverageReport::renderFileReports( - raw_ostream &OS, ArrayRef Files, - const CoverageFiltersMatchAll &Filters) const { +void CoverageReport::renderFileReports(raw_ostream &OS, + ArrayRef Files, + const CoverageFilter &Filters) const { FileCoverageSummary Totals("TOTAL"); auto FileReports = prepareFileReports(Coverage, Totals, Files, Options, Filters); @@ -405,7 +405,7 @@ EmptyFiles = true; } - if (EmptyFiles && Filters.empty()) { + if (EmptyFiles) { OS << "\n" << "Files which contain no functions:\n"; Index: tools/llvm-cov/SourceCoverageView.h =================================================================== --- tools/llvm-cov/SourceCoverageView.h +++ tools/llvm-cov/SourceCoverageView.h @@ -22,7 +22,7 @@ namespace llvm { -class CoverageFiltersMatchAll; +class CoverageFilter; class SourceCoverageView; /// \brief A view that represents a macro or include expansion. @@ -113,7 +113,7 @@ /// \brief Create an index which lists reports for the given source files. virtual Error createIndexFile(ArrayRef SourceFiles, const coverage::CoverageMapping &Coverage, - const CoverageFiltersMatchAll &Filters) = 0; + const CoverageFilter &Filters) = 0; /// @} }; Index: tools/llvm-cov/SourceCoverageViewHTML.h =================================================================== --- tools/llvm-cov/SourceCoverageViewHTML.h +++ tools/llvm-cov/SourceCoverageViewHTML.h @@ -30,7 +30,7 @@ Error createIndexFile(ArrayRef SourceFiles, const coverage::CoverageMapping &Coverage, - const CoverageFiltersMatchAll &Filters) override; + const CoverageFilter &Filters) override; CoveragePrinterHTML(const CoverageViewOptions &Opts) : CoveragePrinter(Opts) {} Index: tools/llvm-cov/SourceCoverageViewHTML.cpp =================================================================== --- tools/llvm-cov/SourceCoverageViewHTML.cpp +++ tools/llvm-cov/SourceCoverageViewHTML.cpp @@ -366,8 +366,7 @@ Error CoveragePrinterHTML::createIndexFile( ArrayRef SourceFiles, - const coverage::CoverageMapping &Coverage, - const CoverageFiltersMatchAll &Filters) { + const coverage::CoverageMapping &Coverage, const CoverageFilter &Filters) { // Emit the default stylesheet. auto CSSOrErr = createOutputStream("style", "css", /*InToplevel=*/true); if (Error E = CSSOrErr.takeError()) @@ -420,7 +419,7 @@ // Emit links to files which don't contain any functions. These are normally // not very useful, but could be relevant for code which abuses the // preprocessor. - if (EmptyFiles && Filters.empty()) { + if (EmptyFiles) { OSRef << tag("p", "Files which contain no functions. (These " "files contain code pulled into other files " "by the preprocessor.)\n"); Index: tools/llvm-cov/SourceCoverageViewText.h =================================================================== --- tools/llvm-cov/SourceCoverageViewText.h +++ tools/llvm-cov/SourceCoverageViewText.h @@ -28,7 +28,7 @@ Error createIndexFile(ArrayRef SourceFiles, const coverage::CoverageMapping &Coverage, - const CoverageFiltersMatchAll &Filters) override; + const CoverageFilter &Filters) override; CoveragePrinterText(const CoverageViewOptions &Opts) : CoveragePrinter(Opts) {} Index: tools/llvm-cov/SourceCoverageViewText.cpp =================================================================== --- tools/llvm-cov/SourceCoverageViewText.cpp +++ tools/llvm-cov/SourceCoverageViewText.cpp @@ -30,8 +30,7 @@ Error CoveragePrinterText::createIndexFile( ArrayRef SourceFiles, - const coverage::CoverageMapping &Coverage, - const CoverageFiltersMatchAll &Filters) { + const coverage::CoverageMapping &Coverage, const CoverageFilter &Filters) { auto OSOrErr = createOutputStream("index", "txt", /*InToplevel=*/true); if (Error E = OSOrErr.takeError()) return E; Index: tools/llvm-pdbutil/MinimalSymbolDumper.cpp =================================================================== --- tools/llvm-pdbutil/MinimalSymbolDumper.cpp +++ tools/llvm-pdbutil/MinimalSymbolDumper.cpp @@ -287,11 +287,57 @@ static std::string formatRegisterId(RegisterId Id) { switch (Id) { -#define CV_REGISTER(name, val) RETURN_CASE(RegisterId, name, #name) -#include "llvm/DebugInfo/CodeView/CodeViewRegisters.def" -#undef CV_REGISTER + RETURN_CASE(RegisterId, VFrame, "vframe"); + RETURN_CASE(RegisterId, AL, "al"); + RETURN_CASE(RegisterId, CL, "cl"); + RETURN_CASE(RegisterId, DL, "dl"); + RETURN_CASE(RegisterId, BL, "bl"); + RETURN_CASE(RegisterId, AH, "ah"); + RETURN_CASE(RegisterId, CH, "ch"); + RETURN_CASE(RegisterId, DH, "dh"); + RETURN_CASE(RegisterId, BH, "bh"); + RETURN_CASE(RegisterId, AX, "ax"); + RETURN_CASE(RegisterId, CX, "cx"); + RETURN_CASE(RegisterId, DX, "dx"); + RETURN_CASE(RegisterId, BX, "bx"); + RETURN_CASE(RegisterId, SP, "sp"); + RETURN_CASE(RegisterId, BP, "bp"); + RETURN_CASE(RegisterId, SI, "si"); + RETURN_CASE(RegisterId, DI, "di"); + RETURN_CASE(RegisterId, EAX, "eax"); + RETURN_CASE(RegisterId, ECX, "ecx"); + RETURN_CASE(RegisterId, EDX, "edx"); + RETURN_CASE(RegisterId, EBX, "ebx"); + RETURN_CASE(RegisterId, ESP, "esp"); + RETURN_CASE(RegisterId, EBP, "ebp"); + RETURN_CASE(RegisterId, ESI, "esi"); + RETURN_CASE(RegisterId, EDI, "edi"); + RETURN_CASE(RegisterId, ES, "es"); + RETURN_CASE(RegisterId, CS, "cs"); + RETURN_CASE(RegisterId, SS, "ss"); + RETURN_CASE(RegisterId, DS, "ds"); + RETURN_CASE(RegisterId, FS, "fs"); + RETURN_CASE(RegisterId, GS, "gs"); + RETURN_CASE(RegisterId, IP, "ip"); + RETURN_CASE(RegisterId, RAX, "rax"); + RETURN_CASE(RegisterId, RBX, "rbx"); + RETURN_CASE(RegisterId, RCX, "rcx"); + RETURN_CASE(RegisterId, RDX, "rdx"); + RETURN_CASE(RegisterId, RSI, "rsi"); + RETURN_CASE(RegisterId, RDI, "rdi"); + RETURN_CASE(RegisterId, RBP, "rbp"); + RETURN_CASE(RegisterId, RSP, "rsp"); + RETURN_CASE(RegisterId, R8, "r8"); + RETURN_CASE(RegisterId, R9, "r9"); + RETURN_CASE(RegisterId, R10, "r10"); + RETURN_CASE(RegisterId, R11, "r11"); + RETURN_CASE(RegisterId, R12, "r12"); + RETURN_CASE(RegisterId, R13, "r13"); + RETURN_CASE(RegisterId, R14, "r14"); + RETURN_CASE(RegisterId, R15, "r15"); + default: + return formatUnknownEnum(Id); } - return formatUnknownEnum(Id); } static std::string formatRange(LocalVariableAddrRange Range) { Index: tools/llvm-profdata/llvm-profdata.cpp =================================================================== --- tools/llvm-profdata/llvm-profdata.cpp +++ tools/llvm-profdata/llvm-profdata.cpp @@ -211,8 +211,8 @@ // If NumThreads is not specified, auto-detect a good default. if (NumThreads == 0) - NumThreads = - std::min(hardware_concurrency(), unsigned((Inputs.size() + 1) / 2)); + NumThreads = std::max(1U, std::min(std::thread::hardware_concurrency(), + unsigned(Inputs.size() / 2))); // Initialize the writer contexts. SmallVector, 4> Contexts; Index: tools/llvm-readobj/ELFDumper.cpp =================================================================== --- tools/llvm-readobj/ELFDumper.cpp +++ tools/llvm-readobj/ELFDumper.cpp @@ -825,9 +825,7 @@ }; static const EnumEntry AMDGPUElfOSABI[] = { - {"AMDGPU_HSA", "AMDGPU - HSA", ELF::ELFOSABI_AMDGPU_HSA}, - {"AMDGPU_PAL", "AMDGPU - PAL", ELF::ELFOSABI_AMDGPU_PAL}, - {"AMDGPU_MESA3D", "AMDGPU - MESA3D", ELF::ELFOSABI_AMDGPU_MESA3D} + {"AMDGPU_HSA", "AMDGPU - HSA", ELF::ELFOSABI_AMDGPU_HSA} }; static const EnumEntry ARMElfOSABI[] = { @@ -1244,14 +1242,6 @@ LLVM_READOBJ_ENUM_ENT(ELF, EF_MIPS_ARCH_64R6) }; -static const EnumEntry ElfHeaderRISCVFlags[] = { - LLVM_READOBJ_ENUM_ENT(ELF, EF_RISCV_RVC), - LLVM_READOBJ_ENUM_ENT(ELF, EF_RISCV_FLOAT_ABI_SINGLE), - LLVM_READOBJ_ENUM_ENT(ELF, EF_RISCV_FLOAT_ABI_DOUBLE), - LLVM_READOBJ_ENUM_ENT(ELF, EF_RISCV_FLOAT_ABI_QUAD), - LLVM_READOBJ_ENUM_ENT(ELF, EF_RISCV_RVE) -}; - static const EnumEntry ElfSymOtherFlags[] = { LLVM_READOBJ_ENUM_ENT(ELF, STV_INTERNAL), LLVM_READOBJ_ENUM_ENT(ELF, STV_HIDDEN), @@ -3562,8 +3552,6 @@ W.printFlags("Flags", e->e_flags, makeArrayRef(ElfHeaderMipsFlags), unsigned(ELF::EF_MIPS_ARCH), unsigned(ELF::EF_MIPS_ABI), unsigned(ELF::EF_MIPS_MACH)); - else if (e->e_machine == EM_RISCV) - W.printFlags("Flags", e->e_flags, makeArrayRef(ElfHeaderRISCVFlags)); else W.printFlags("Flags", e->e_flags); W.printNumber("HeaderSize", e->e_ehsize); Index: utils/TableGen/AsmMatcherEmitter.cpp =================================================================== --- utils/TableGen/AsmMatcherEmitter.cpp +++ utils/TableGen/AsmMatcherEmitter.cpp @@ -205,9 +205,6 @@ /// For custom match classes: the diagnostic kind for when the predicate fails. std::string DiagnosticType; - /// For custom match classes: the diagnostic string for when the predicate fails. - std::string DiagnosticString; - /// Is this operand optional and not always required. bool IsOptional; @@ -1360,17 +1357,11 @@ if (StringInit *SI = dyn_cast(PRMName)) CI->ParserMethod = SI->getValue(); - // Get the diagnostic type and string or leave them as empty. + // Get the diagnostic type or leave it as empty. + // Get the parse method name or leave it as empty. Init *DiagnosticType = Rec->getValueInit("DiagnosticType"); if (StringInit *SI = dyn_cast(DiagnosticType)) CI->DiagnosticType = SI->getValue(); - Init *DiagnosticString = Rec->getValueInit("DiagnosticString"); - if (StringInit *SI = dyn_cast(DiagnosticString)) - CI->DiagnosticString = SI->getValue(); - // If we have a DiagnosticString, we need a DiagnosticType for use within - // the matcher. - if (!CI->DiagnosticString.empty() && CI->DiagnosticType.empty()) - CI->DiagnosticType = CI->ClassName; Init *IsOptional = Rec->getValueInit("IsOptional"); if (BitInit *BI = dyn_cast(IsOptional)) @@ -2197,38 +2188,6 @@ OS << "}\n\n"; } -/// emitMatchClassDiagStrings - Emit a function to get the diagnostic text to be -/// used when an assembly operand does not match the expected operand class. -static void emitOperandMatchErrorDiagStrings(AsmMatcherInfo &Info, raw_ostream &OS) { - // If the target does not use DiagnosticString for any operands, don't emit - // an unused function. - if (std::all_of( - Info.Classes.begin(), Info.Classes.end(), - [](const ClassInfo &CI) { return CI.DiagnosticString.empty(); })) - return; - - OS << "static const char *getMatchKindDiag(" << Info.Target.getName() - << "AsmParser::" << Info.Target.getName() - << "MatchResultTy MatchResult) {\n"; - OS << " switch (MatchResult) {\n"; - - for (const auto &CI: Info.Classes) { - if (!CI.DiagnosticString.empty()) { - assert(!CI.DiagnosticType.empty() && - "DiagnosticString set without DiagnosticType"); - OS << " case " << Info.Target.getName() - << "AsmParser::Match_" << CI.DiagnosticType << ":\n"; - OS << " return \"" << CI.DiagnosticString << "\";\n"; - } - } - - OS << " default:\n"; - OS << " return nullptr;\n"; - - OS << " }\n"; - OS << "}\n\n"; -} - /// emitValidateOperandClass - Emit the function to validate an operand class. static void emitValidateOperandClass(AsmMatcherInfo &Info, raw_ostream &OS) { @@ -2865,8 +2824,6 @@ bool HasMnemonicFirst = AsmParser->getValueAsBit("HasMnemonicFirst"); bool HasOptionalOperands = Info.hasOptionalOperands(); - bool ReportMultipleNearMisses = - AsmParser->getValueAsBit("ReportMultipleNearMisses"); // Write the output. @@ -2889,12 +2846,9 @@ OS << " void convertToMapAndConstraints(unsigned Kind,\n "; OS << " const OperandVector &Operands) override;\n"; OS << " unsigned MatchInstructionImpl(const OperandVector &Operands,\n" - << " MCInst &Inst,\n"; - if (ReportMultipleNearMisses) - OS << " SmallVectorImpl *NearMisses,\n"; - else - OS << " uint64_t &ErrorInfo,\n"; - OS << " bool matchingInlineAsm,\n" + << " MCInst &Inst,\n" + << " uint64_t &ErrorInfo," + << " bool matchingInlineAsm,\n" << " unsigned VariantID = 0);\n"; if (!Info.OperandMatchInfo.empty()) { @@ -2955,10 +2909,6 @@ // Emit the enumeration for classes which participate in matching. emitMatchClassEnumeration(Target, Info.Classes, OS); - // Emit a function to get the user-visible string to describe an operand - // match failure in diagnostics. - emitOperandMatchErrorDiagStrings(Info, OS); - // Emit the routine to match token strings to their match class. emitMatchTokenString(Target, Info.Classes, OS); @@ -3081,22 +3031,16 @@ // Finally, build the match function. OS << "unsigned " << Target.getName() << ClassName << "::\n" << "MatchInstructionImpl(const OperandVector &Operands,\n"; - OS << " MCInst &Inst,\n"; - if (ReportMultipleNearMisses) - OS << " SmallVectorImpl *NearMisses,\n"; - else - OS << " uint64_t &ErrorInfo,\n"; - OS << " bool matchingInlineAsm, unsigned VariantID) {\n"; - - if (!ReportMultipleNearMisses) { - OS << " // Eliminate obvious mismatches.\n"; - OS << " if (Operands.size() > " - << (MaxNumOperands + HasMnemonicFirst) << ") {\n"; - OS << " ErrorInfo = " - << (MaxNumOperands + HasMnemonicFirst) << ";\n"; - OS << " return Match_InvalidOperand;\n"; - OS << " }\n\n"; - } + OS << " MCInst &Inst, uint64_t &ErrorInfo,\n" + << " bool matchingInlineAsm, unsigned VariantID) {\n"; + + OS << " // Eliminate obvious mismatches.\n"; + OS << " if (Operands.size() > " + << (MaxNumOperands + HasMnemonicFirst) << ") {\n"; + OS << " ErrorInfo = " + << (MaxNumOperands + HasMnemonicFirst) << ";\n"; + OS << " return Match_InvalidOperand;\n"; + OS << " }\n\n"; // Emit code to get the available features. OS << " // Get the current feature set.\n"; @@ -3119,20 +3063,17 @@ } // Emit code to compute the class list for this operand vector. - if (!ReportMultipleNearMisses) { - OS << " // Some state to try to produce better error messages.\n"; - OS << " bool HadMatchOtherThanFeatures = false;\n"; - OS << " bool HadMatchOtherThanPredicate = false;\n"; - OS << " unsigned RetCode = Match_InvalidOperand;\n"; - OS << " uint64_t MissingFeatures = ~0ULL;\n"; - OS << " // Set ErrorInfo to the operand that mismatches if it is\n"; - OS << " // wrong for all instances of the instruction.\n"; - OS << " ErrorInfo = ~0ULL;\n"; - } - + OS << " // Some state to try to produce better error messages.\n"; + OS << " bool HadMatchOtherThanFeatures = false;\n"; + OS << " bool HadMatchOtherThanPredicate = false;\n"; + OS << " unsigned RetCode = Match_InvalidOperand;\n"; + OS << " uint64_t MissingFeatures = ~0ULL;\n"; if (HasOptionalOperands) { OS << " SmallBitVector OptionalOperandsMask(" << MaxNumOperands << ");\n"; } + OS << " // Set ErrorInfo to the operand that mismatches if it is\n"; + OS << " // wrong for all instances of the instruction.\n"; + OS << " ErrorInfo = ~0ULL;\n"; // Emit code to search the table. OS << " // Find the appropriate table for this asm variant.\n"; @@ -3167,23 +3108,13 @@ << "*ie = MnemonicRange.second;\n"; OS << " it != ie; ++it) {\n"; - if (ReportMultipleNearMisses) { - OS << " // Some state to record ways in which this instruction did not match.\n"; - OS << " NearMissInfo OperandNearMiss = NearMissInfo::getSuccess();\n"; - OS << " NearMissInfo FeaturesNearMiss = NearMissInfo::getSuccess();\n"; - OS << " NearMissInfo EarlyPredicateNearMiss = NearMissInfo::getSuccess();\n"; - OS << " NearMissInfo LatePredicateNearMiss = NearMissInfo::getSuccess();\n"; - OS << " bool MultipleInvalidOperands = false;\n"; - } - if (HasMnemonicFirst) { OS << " // equal_range guarantees that instruction mnemonic matches.\n"; OS << " assert(Mnemonic == it->getMnemonic());\n"; } // Emit check that the subclasses match. - if (!ReportMultipleNearMisses) - OS << " bool OperandsValid = true;\n"; + OS << " bool OperandsValid = true;\n"; if (HasOptionalOperands) { OS << " OptionalOperandsMask.reset(0, " << MaxNumOperands << ");\n"; } @@ -3193,30 +3124,14 @@ OS << " auto Formal = " << "static_cast(it->Classes[FormalIdx]);\n"; OS << " if (ActualIdx >= Operands.size()) {\n"; - if (ReportMultipleNearMisses) { - OS << " bool ThisOperandValid = (Formal == " <<"InvalidMatchClass) || " - "isSubclass(Formal, OptionalMatchClass);\n"; - OS << " if (!ThisOperandValid) {\n"; - OS << " if (!OperandNearMiss) {\n"; - OS << " // Record info about match failure for later use.\n"; - OS << " OperandNearMiss =\n"; - OS << " NearMissInfo::getTooFewOperands(Formal, it->Opcode);\n"; - OS << " } else {\n"; - OS << " // If more than one operand is invalid, give up on this match entry.\n"; - OS << " MultipleInvalidOperands = true;\n"; - OS << " break;\n"; - OS << " }\n"; - OS << " }\n"; - OS << " continue;\n"; - } else { - OS << " OperandsValid = (Formal == InvalidMatchClass) || isSubclass(Formal, OptionalMatchClass);\n"; - OS << " if (!OperandsValid) ErrorInfo = ActualIdx;\n"; - if (HasOptionalOperands) { - OS << " OptionalOperandsMask.set(FormalIdx, " << MaxNumOperands - << ");\n"; - } - OS << " break;\n"; + OS << " OperandsValid = (Formal == " <<"InvalidMatchClass) || " + "isSubclass(Formal, OptionalMatchClass);\n"; + OS << " if (!OperandsValid) ErrorInfo = ActualIdx;\n"; + if (HasOptionalOperands) { + OS << " OptionalOperandsMask.set(FormalIdx, " << MaxNumOperands + << ");\n"; } + OS << " break;\n"; OS << " }\n"; OS << " MCParsedAsmOperand &Actual = *Operands[ActualIdx];\n"; OS << " unsigned Diag = validateOperandClass(Actual, Formal);\n"; @@ -3242,58 +3157,34 @@ } OS << " continue;\n"; OS << " }\n"; + OS << " // If this operand is broken for all of the instances of this\n"; + OS << " // mnemonic, keep track of it so we can report loc info.\n"; + OS << " // If we already had a match that only failed due to a\n"; + OS << " // target predicate, that diagnostic is preferred.\n"; + OS << " if (!HadMatchOtherThanPredicate &&\n"; + OS << " (it == MnemonicRange.first || ErrorInfo <= ActualIdx)) {\n"; + OS << " ErrorInfo = ActualIdx;\n"; + OS << " // InvalidOperand is the default. Prefer specificity.\n"; + OS << " if (Diag != Match_InvalidOperand)\n"; + OS << " RetCode = Diag;\n"; + OS << " }\n"; + OS << " // Otherwise, just reject this instance of the mnemonic.\n"; + OS << " OperandsValid = false;\n"; + OS << " break;\n"; + OS << " }\n\n"; - if (ReportMultipleNearMisses) { - OS << " if (!OperandNearMiss) {\n"; - OS << " // If this is the first invalid operand we have seen, record some\n"; - OS << " // information about it.\n"; - OS << " OperandNearMiss =\n"; - OS << " NearMissInfo::getMissedOperand(Diag, Formal, it->Opcode, ActualIdx);\n"; - OS << " ++ActualIdx;\n"; - OS << " } else {\n"; - OS << " // If more than one operand is invalid, give up on this match entry.\n"; - OS << " MultipleInvalidOperands = true;\n"; - OS << " break;\n"; - OS << " }\n"; - OS << " }\n\n"; - } else { - OS << " // If this operand is broken for all of the instances of this\n"; - OS << " // mnemonic, keep track of it so we can report loc info.\n"; - OS << " // If we already had a match that only failed due to a\n"; - OS << " // target predicate, that diagnostic is preferred.\n"; - OS << " if (!HadMatchOtherThanPredicate &&\n"; - OS << " (it == MnemonicRange.first || ErrorInfo <= ActualIdx)) {\n"; - OS << " ErrorInfo = ActualIdx;\n"; - OS << " // InvalidOperand is the default. Prefer specificity.\n"; - OS << " if (Diag != Match_InvalidOperand)\n"; - OS << " RetCode = Diag;\n"; - OS << " }\n"; - OS << " // Otherwise, just reject this instance of the mnemonic.\n"; - OS << " OperandsValid = false;\n"; - OS << " break;\n"; - OS << " }\n\n"; - } - - if (ReportMultipleNearMisses) - OS << " if (MultipleInvalidOperands) continue;\n\n"; - else - OS << " if (!OperandsValid) continue;\n\n"; + OS << " if (!OperandsValid) continue;\n"; // Emit check that the required features are available. OS << " if ((AvailableFeatures & it->RequiredFeatures) " << "!= it->RequiredFeatures) {\n"; - if (!ReportMultipleNearMisses) - OS << " HadMatchOtherThanFeatures = true;\n"; + OS << " HadMatchOtherThanFeatures = true;\n"; OS << " uint64_t NewMissingFeatures = it->RequiredFeatures & " "~AvailableFeatures;\n"; - if (ReportMultipleNearMisses) { - OS << " FeaturesNearMiss = NearMissInfo::getMissedFeature(NewMissingFeatures);\n"; - } else { - OS << " if (countPopulation(NewMissingFeatures) <=\n" - " countPopulation(MissingFeatures))\n"; - OS << " MissingFeatures = NewMissingFeatures;\n"; - OS << " continue;\n"; - } + OS << " if (countPopulation(NewMissingFeatures) <=\n" + " countPopulation(MissingFeatures))\n"; + OS << " MissingFeatures = NewMissingFeatures;\n"; + OS << " continue;\n"; OS << " }\n"; OS << "\n"; OS << " Inst.clear();\n\n"; @@ -3309,28 +3200,11 @@ << " unsigned MatchResult;\n" << " if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, " "Operands)) != Match_Success) {\n" - << " Inst.clear();\n"; - if (ReportMultipleNearMisses) { - OS << " EarlyPredicateNearMiss = NearMissInfo::getMissedPredicate(MatchResult);\n"; - } else { - OS << " RetCode = MatchResult;\n" - << " HadMatchOtherThanPredicate = true;\n" - << " continue;\n"; - } - OS << " }\n\n"; - - if (ReportMultipleNearMisses) { - OS << " // If we did not successfully match the operands, then we can't convert to\n"; - OS << " // an MCInst, so bail out on this instruction variant now.\n"; - OS << " if (OperandNearMiss) {\n"; - OS << " // If the operand mismatch was the only problem, reprrt it as a near-miss.\n"; - OS << " if (NearMisses && !FeaturesNearMiss && !EarlyPredicateNearMiss) {\n"; - OS << " NearMisses->push_back(OperandNearMiss);\n"; - OS << " }\n"; - OS << " continue;\n"; - OS << " }\n\n"; - } - + << " Inst.clear();\n" + << " RetCode = MatchResult;\n" + << " HadMatchOtherThanPredicate = true;\n" + << " continue;\n" + << " }\n\n"; OS << " if (matchingInlineAsm) {\n"; OS << " convertToMapAndConstraints(it->ConvertFn, Operands);\n"; OS << " return Match_Success;\n"; @@ -3350,37 +3224,11 @@ << " // handle any context sensitive constraints.\n" << " if ((MatchResult = checkTargetMatchPredicate(Inst)) !=" << " Match_Success) {\n" - << " Inst.clear();\n"; - if (ReportMultipleNearMisses) { - OS << " LatePredicateNearMiss = NearMissInfo::getMissedPredicate(MatchResult);\n"; - } else { - OS << " RetCode = MatchResult;\n" - << " HadMatchOtherThanPredicate = true;\n" - << " continue;\n"; - } - OS << " }\n\n"; - - if (ReportMultipleNearMisses) { - OS << " int NumNearMisses = ((int)(bool)OperandNearMiss +\n"; - OS << " (int)(bool)FeaturesNearMiss +\n"; - OS << " (int)(bool)EarlyPredicateNearMiss +\n"; - OS << " (int)(bool)LatePredicateNearMiss);\n"; - OS << " if (NumNearMisses == 1) {\n"; - OS << " // We had exactly one type of near-miss, so add that to the list.\n"; - OS << " assert(!OperandNearMiss && \"OperandNearMiss was handled earlier\");\n"; - OS << " if (NearMisses && FeaturesNearMiss)\n"; - OS << " NearMisses->push_back(FeaturesNearMiss);\n"; - OS << " else if (NearMisses && EarlyPredicateNearMiss)\n"; - OS << " NearMisses->push_back(EarlyPredicateNearMiss);\n"; - OS << " else if (NearMisses && LatePredicateNearMiss)\n"; - OS << " NearMisses->push_back(LatePredicateNearMiss);\n"; - OS << "\n"; - OS << " continue;\n"; - OS << " } else if (NumNearMisses > 1) {\n"; - OS << " // This instruction missed in more than one way, so ignore it.\n"; - OS << " continue;\n"; - OS << " }\n"; - } + << " Inst.clear();\n" + << " RetCode = MatchResult;\n" + << " HadMatchOtherThanPredicate = true;\n" + << " continue;\n" + << " }\n\n"; // Call the post-processing function, if used. StringRef InsnCleanupFn = AsmParser->getValueAsString("AsmParserInstCleanup"); @@ -3401,17 +3249,12 @@ OS << " return Match_Success;\n"; OS << " }\n\n"; - if (ReportMultipleNearMisses) { - OS << " // No instruction variants matched exactly.\n"; - OS << " return Match_NearMisses;\n"; - } else { - OS << " // Okay, we had no match. Try to return a useful error code.\n"; - OS << " if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)\n"; - OS << " return RetCode;\n\n"; - OS << " // Missing feature matches return which features were missing\n"; - OS << " ErrorInfo = MissingFeatures;\n"; - OS << " return Match_MissingFeature;\n"; - } + OS << " // Okay, we had no match. Try to return a useful error code.\n"; + OS << " if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)\n"; + OS << " return RetCode;\n\n"; + OS << " // Missing feature matches return which features were missing\n"; + OS << " ErrorInfo = MissingFeatures;\n"; + OS << " return Match_MissingFeature;\n"; OS << "}\n\n"; if (!Info.OperandMatchInfo.empty())