Index: lib/Target/PowerPC/CMakeLists.txt =================================================================== --- lib/Target/PowerPC/CMakeLists.txt +++ lib/Target/PowerPC/CMakeLists.txt @@ -27,6 +27,7 @@ PPCFastISel.cpp PPCFrameLowering.cpp PPCLoopPreIncPrep.cpp + PPCColdCC.cpp PPCMCInstLower.cpp PPCMachineFunctionInfo.cpp PPCMIPeephole.cpp Index: lib/Target/PowerPC/PPC.h =================================================================== --- lib/Target/PowerPC/PPC.h +++ lib/Target/PowerPC/PPC.h @@ -26,6 +26,7 @@ class PassRegistry; class FunctionPass; class MachineInstr; + class ModulePass; class AsmPrinter; class MCInst; @@ -47,12 +48,14 @@ FunctionPass *createPPCTLSDynamicCallPass(); FunctionPass *createPPCBoolRetToIntPass(); FunctionPass *createPPCExpandISELPass(); + ModulePass *createPPCColdCCPass(); void LowerPPCMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, AsmPrinter &AP, bool isDarwin); void initializePPCVSXFMAMutatePass(PassRegistry&); void initializePPCBoolRetToIntPass(PassRegistry&); void initializePPCExpandISELPass(PassRegistry &); + void initializePPCColdCCPass(PassRegistry &); void initializePPCTLSDynamicCallPass(PassRegistry &); extern char &PPCVSXFMAMutateID; Index: lib/Target/PowerPC/PPCCallingConv.td =================================================================== --- lib/Target/PowerPC/PPCCallingConv.td +++ lib/Target/PowerPC/PPCCallingConv.td @@ -45,6 +45,29 @@ CCCustom<"CC_PPC_AnyReg_Error"> ]>; +// Return-value convention for PowerPC coldcc +def RetCC_PPC_Cold : CallingConv<[ + // Use the same return registers as RetCC_PPC, but limited to only + // one return value. The remaining return values will be saved to + // the stack. + CCIfType<[i32, i1], CCIfSubtarget<"isPPC64()", CCPromoteToType>>, + CCIfType<[i1], CCIfNotSubtarget<"isPPC64()", CCPromoteToType>>, + + CCIfType<[i32], CCAssignToReg<[R3]>>, + CCIfType<[i64], CCAssignToReg<[X3]>>, + CCIfType<[i128], CCAssignToReg<[X3]>>, + + CCIfType<[f32], CCAssignToReg<[F1]>>, + CCIfType<[f64], CCAssignToReg<[F1]>>, + + CCIfType<[v4f64, v4f32, v4i1], + CCIfSubtarget<"hasQPX()", CCAssignToReg<[QF1]>>>, + + CCIfType<[v16i8, v8i16, v4i32, v2i64, v1i128, v4f32, v2f64], + CCIfSubtarget<"hasAltivec()", + CCAssignToReg<[V2]>>> +]>; + // Return-value convention for PowerPC def RetCC_PPC : CallingConv<[ CCIfCC<"CallingConv::AnyReg", CCDelegateTo>, @@ -271,6 +294,33 @@ def CSR_NoRegs : CalleeSavedRegs<(add)>; +// coldcc calling convection marks most registers as non-volatile +// Do not include r0,r11,r13 as they are optional in functional linkage +// and value may be altered by inter-library calls. +// Do not include r12 as it is used as a scratch register. +// Do not include return registers r3, f1, v2. +def CSR_SVR32_ColdCC : CalleeSavedRegs<(add (sequence "R%u", 4, 10), + (sequence "R%u", 14, 31), + F0, (sequence "F%u", 2, 31), + (sequence "CR%u", 0, 7))>; + +def CSR_SVR32_ColdCC_Altivec : CalleeSavedRegs<(add CSR_SVR32_ColdCC, + (sequence "V%u", 0, 1), + (sequence "V%u", 3, 31))>; + +def CSR_SVR64_ColdCC : CalleeSavedRegs<(add (sequence "X%u", 4, 10), + (sequence "X%u", 14, 31), + F0, (sequence "F%u", 2, 31), + (sequence "CR%u", 0, 7))>; + +def CSR_SVR64_ColdCC_R2: CalleeSavedRegs<(add CSR_SVR64_ColdCC, X2)>; + +def CSR_SVR64_ColdCC_Altivec : CalleeSavedRegs<(add CSR_SVR64_ColdCC, + (sequence "V%u", 0, 1), + (sequence "V%u", 3, 31))>; + +def CSR_SVR64_ColdCC_R2_Altivec : CalleeSavedRegs<(add CSR_SVR64_ColdCC_Altivec, X2)>; + def CSR_64_AllRegs: CalleeSavedRegs<(add X0, (sequence "X%u", 3, 10), (sequence "X%u", 14, 31), (sequence "F%u", 0, 31), Index: lib/Target/PowerPC/PPCColdCC.cpp =================================================================== --- /dev/null +++ lib/Target/PowerPC/PPCColdCC.cpp @@ -0,0 +1,144 @@ +//===-------- PPCColdCC.cpp - Expand memory instinsics -------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +/// +/// +//===----------------------------------------------------------------------===// + +#include "PPC.h" +#include "PPCTargetMachine.h" +#include "llvm/ADT/Statistic.h" +#include "llvm/Analysis/BlockFrequencyInfo.h" +#include "llvm/CodeGen/TargetPassConfig.h" +#include "llvm/IR/CallSite.h" +#include "llvm/IR/Constants.h" +#include "llvm/IR/Instructions.h" +#include "llvm/IR/Module.h" +#include "llvm/Pass.h" +#include "llvm/Support/CommandLine.h" + +using namespace llvm; + +#define DEBUG_TYPE "coldcc" + +STATISTIC(NumInternalFunc, "Number of internal functions"); +STATISTIC(NumColdCC, "Number of functions marked coldcc"); + +static cl::opt EnableColdCCStressTest( + "ppc-enable-coldcc-stress-test", + cl::desc("Enable stress test of PPC coldcc."), + cl::init(false), cl::Hidden); + + +static cl::opt EnableColdCC( + "ppc-enable-coldcc", + cl::desc("Enable the PPC pass to use coldcc on internal functions."), + cl::init(false), cl::Hidden); + +namespace { +class PPCColdCC : public ModulePass { +public: + static char ID; + PPCColdCC() : ModulePass(ID) {} + + void getAnalysisUsage(AnalysisUsage &AU) const override { + AU.addRequired(); + } + + bool runOnModule(Module &M) override; + + bool hasColdCallSite(Function &F); + bool isColdCallSite(CallSite CS, BlockFrequencyInfo *CallerBFI); + bool markCallSitesColdCC(Function &F); + StringRef getPassName() const override { + return "PPC add coldcc"; + } + const PPCSubtarget *ST; +}; +} // namespace + +bool PPCColdCC::hasColdCallSite(Function &F) { + unsigned NumCallSites, NumColdCallSites; + NumCallSites = 0; NumColdCallSites = 0; + for (User *U : F.users()) { + if (isa(U)) + continue; + CallSite CS(cast(U)); + NumCallSites++; + Function *CallerFunc = CS.getInstruction()->getParent()->getParent(); + BlockFrequencyInfo *CallerBFI = + &getAnalysis(*CallerFunc).getBFI(); + if (isColdCallSite(CS, CallerBFI)) { + NumColdCallSites++; + } + } + + if (NumCallSites == NumColdCallSites) + return true; + else + return false; +} + +bool PPCColdCC::isColdCallSite(CallSite CS, + BlockFrequencyInfo *CallerBFI) { + + const BranchProbability ColdProb(10, 100); + auto CallSiteBB = CS.getInstruction()->getParent(); + auto CallSiteFreq = CallerBFI->getBlockFreq(CallSiteBB); + auto CallerEntryFreq = + CallerBFI->getBlockFreq(&(CS.getCaller()->getEntryBlock())); + + return CallSiteFreq < CallerEntryFreq * ColdProb; +} + +bool PPCColdCC::markCallSitesColdCC(Function &F) { + for (User *U : F.users()) { + if (isa(U)) + continue; + CallSite CS(cast(U)); + CS.setCallingConv(CallingConv::Cold); + } + + return true; +} + +bool PPCColdCC::runOnModule(Module &M) { + bool Changed = false; + auto *TPC = getAnalysisIfAvailable(); + if (!TPC) + return false; + + auto &TM = TPC->getTM(); + if (EnableColdCC) { + for (Function &F : M) { + ST = TM.getSubtargetImpl(F); + if (!ST->isSVR4ABI()) + return false; + if (F.hasLocalLinkage() && !F.isVarArg() && !F.hasAddressTaken()) { + NumInternalFunc++; + if (hasColdCallSite(F) || EnableColdCCStressTest) { + F.setCallingConv(CallingConv::Cold); + Changed = markCallSitesColdCC(F); + NumColdCC++; + } + } + } + } + return Changed; +} + +ModulePass *llvm::createPPCColdCCPass() { return new PPCColdCC(); } + +char PPCColdCC::ID = 0; +INITIALIZE_PASS_BEGIN(PPCColdCC, "PPCColdCC", + "Add coldcc", false, false) + +INITIALIZE_PASS_DEPENDENCY(BlockFrequencyInfoWrapperPass) + +INITIALIZE_PASS_END(PPCColdCC, "PPCColdCC", + "Add coldcc", false, false) Index: lib/Target/PowerPC/PPCFastISel.cpp =================================================================== --- lib/Target/PowerPC/PPCFastISel.cpp +++ lib/Target/PowerPC/PPCFastISel.cpp @@ -206,6 +206,8 @@ return CC_PPC32_SVR4_ByVal; else if (Flag == 3) return CC_PPC32_SVR4_VarArg; + else if (Flag == 4) + return RetCC_PPC_Cold; else return RetCC_PPC; } Index: lib/Target/PowerPC/PPCFrameLowering.cpp =================================================================== --- lib/Target/PowerPC/PPCFrameLowering.cpp +++ lib/Target/PowerPC/PPCFrameLowering.cpp @@ -1952,7 +1952,11 @@ bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4; // Add the callee-saved register as live-in; it's killed at the spill. - MBB.addLiveIn(Reg); + const MachineRegisterInfo &MRI = MF->getRegInfo(); + bool isLiveIn = MRI.isLiveIn(Reg); + if (!isLiveIn) { + MBB.addLiveIn(Reg); + } if (CRSpilled && IsCRField) { CRMIB.addReg(Reg, RegState::ImplicitKill); @@ -1982,7 +1986,7 @@ } } else { const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); - TII.storeRegToStackSlot(MBB, MI, Reg, true, + TII.storeRegToStackSlot(MBB, MI, Reg, !isLiveIn, CSI[i].getFrameIdx(), RC, TRI); } } Index: lib/Target/PowerPC/PPCISelLowering.cpp =================================================================== --- lib/Target/PowerPC/PPCISelLowering.cpp +++ lib/Target/PowerPC/PPCISelLowering.cpp @@ -4890,7 +4890,11 @@ SmallVector RVLocs; CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, *DAG.getContext()); - CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC); + + if (CallConv == CallingConv::Cold) + CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC_Cold); + else + CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC); // Copy all of the result registers out of their specified physreg. for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { @@ -5110,6 +5114,7 @@ // of the 32-bit SVR4 ABI stack frame layout. assert((CallConv == CallingConv::C || + CallConv == CallingConv::Cold || CallConv == CallingConv::Fast) && "Unknown calling convention!"); unsigned PtrByteSize = 4; @@ -6371,7 +6376,10 @@ LLVMContext &Context) const { SmallVector RVLocs; CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context); - return CCInfo.CheckReturn(Outs, RetCC_PPC); + if (CallConv == CallingConv::Cold) + return CCInfo.CheckReturn(Outs, RetCC_PPC_Cold); + else + return CCInfo.CheckReturn(Outs, RetCC_PPC); } SDValue @@ -6383,7 +6391,10 @@ SmallVector RVLocs; CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, *DAG.getContext()); - CCInfo.AnalyzeReturn(Outs, RetCC_PPC); + if (CallConv == CallingConv::Cold) + CCInfo.AnalyzeReturn(Outs, RetCC_PPC_Cold); + else + CCInfo.AnalyzeReturn(Outs, RetCC_PPC); SDValue Flag; SmallVector RetOps(1, Chain); Index: lib/Target/PowerPC/PPCRegisterInfo.cpp =================================================================== --- lib/Target/PowerPC/PPCRegisterInfo.cpp +++ lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -113,6 +113,10 @@ const MCPhysReg* PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { const PPCSubtarget &Subtarget = MF->getSubtarget(); + + // On PPC64, we might need to save r2 (but only if it is not reserved). + bool SaveR2 = MF->getRegInfo().isAllocatable(PPC::X2); + if (MF->getFunction()->getCallingConv() == CallingConv::AnyReg) { if (Subtarget.hasVSX()) return CSR_64_AllRegs_VSX_SaveList; @@ -131,8 +135,16 @@ if (TM.isPPC64() && MF->getInfo()->isSplitCSR()) return CSR_SRV464_TLS_PE_SaveList; - // On PPC64, we might need to save r2 (but only if it is not reserved). - bool SaveR2 = MF->getRegInfo().isAllocatable(PPC::X2); + if (MF->getFunction()->getCallingConv() == CallingConv::Cold) { + return TM.isPPC64() + ? (Subtarget.hasAltivec() + ? (SaveR2 ? CSR_SVR64_ColdCC_R2_Altivec_SaveList + : CSR_SVR64_ColdCC_Altivec_SaveList) + : (SaveR2 ? CSR_SVR64_ColdCC_R2_SaveList + : CSR_SVR64_ColdCC_SaveList)) + : (Subtarget.hasAltivec() ? CSR_SVR32_ColdCC_Altivec_SaveList + : CSR_SVR32_ColdCC_SaveList); + } return TM.isPPC64() ? (Subtarget.hasAltivec() @@ -186,6 +198,13 @@ : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_RegMask : CSR_Darwin32_RegMask); + if (CC == CallingConv::Cold) { + return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR64_ColdCC_Altivec_RegMask + : CSR_SVR64_ColdCC_RegMask) + : (Subtarget.hasAltivec() ? CSR_SVR32_ColdCC_Altivec_RegMask + : CSR_SVR32_ColdCC_RegMask); + } + return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR464_Altivec_RegMask : CSR_SVR464_RegMask) : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_RegMask Index: lib/Target/PowerPC/PPCTargetMachine.cpp =================================================================== --- lib/Target/PowerPC/PPCTargetMachine.cpp +++ lib/Target/PowerPC/PPCTargetMachine.cpp @@ -97,6 +97,7 @@ PassRegistry &PR = *PassRegistry::getPassRegistry(); initializePPCBoolRetToIntPass(PR); initializePPCExpandISELPass(PR); + initializePPCColdCCPass(PR); initializePPCTLSDynamicCallPass(PR); } @@ -346,6 +347,9 @@ addPass(createLICMPass()); } + if (TM->getOptLevel() != CodeGenOpt::None) + addPass(createPPCColdCCPass()); + TargetPassConfig::addIRPasses(); } Index: test/CodeGen/PowerPC/coldcc.ll =================================================================== --- /dev/null +++ test/CodeGen/PowerPC/coldcc.ll @@ -0,0 +1,44 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -ppc-enable-coldcc -ppc-enable-coldcc-stress-test < %s | FileCheck %s -check-prefix=COLDCC + +define signext i32 @caller(i32 signext %a, i32 signext %b, i32 signext %cold) { +entry: + %0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"(i32 %a, i32 %b) + %mul = mul nsw i32 %0, %cold + %tobool = icmp eq i32 %cold, 0 + br i1 %tobool, label %if.end, label %if.then + +if.then: ; preds = %entry + %mul1 = mul nsw i32 %mul, %cold + %mul2 = mul nsw i32 %b, %a + %call = tail call fastcc signext i32 @callee(i32 signext %a, i32 signext %b) + %add = add i32 %mul2, %a + %add3 = add i32 %add, %mul + %add4 = add i32 %add3, %mul1 + %add5 = add i32 %add4, %call + br label %if.end + +if.end: ; preds = %entry, %if.then + %f.0 = phi i32 [ %add5, %if.then ], [ %0, %entry ] + ret i32 %f.0 +} + +define internal fastcc signext i32 @callee(i32 signext %a, i32 signext %b) { +entry: +; COLDCC: @callee +; COLDCC: std 6, -8(1) +; COLDCC: std 7, -16(1) +; COLDCC: std 8, -24(1) +; COLDCC: std 9, -32(1) +; COLDCC: std 10, -40(1) +; COLDCC: ld 9, -32(1) +; COLDCC: ld 8, -24(1) +; COLDCC: ld 7, -16(1) +; COLDCC: ld 10, -40(1) +; COLDCC: ld 6, -8(1) + %0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{r6},~{r7},~{r8},~{r9},~{r10}"(i32 %a, i32 %b) + %mul = mul nsw i32 %a, 3 + %1 = mul i32 %b, -5 + %add = add i32 %1, %mul + %sub = add i32 %add, %0 + ret i32 %sub +} Index: test/CodeGen/PowerPC/coldcc2.ll =================================================================== --- /dev/null +++ test/CodeGen/PowerPC/coldcc2.ll @@ -0,0 +1,42 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -ppc-enable-coldcc -ppc-enable-coldcc-stress-test < %s | FileCheck %s -check-prefix=COLDCC + +%struct.MyStruct = type { i32, i32, i32, i32 } + +@caller.s = internal unnamed_addr global %struct.MyStruct zeroinitializer, align 8 + +define signext i32 @caller(i32 signext %a, i32 signext %b, i32 signext %cold) { +entry: +; COLDCC: bl callee +; COLDCC: ld 4, 40(1) +; COLDCC: ld 5, 32(1) + %call = tail call fastcc { i64, i64 } @callee(i32 signext %a, i32 signext %b) + %0 = extractvalue { i64, i64 } %call, 0 + %1 = extractvalue { i64, i64 } %call, 1 + store i64 %0, i64* bitcast (%struct.MyStruct* @caller.s to i64*), align 8 + store i64 %1, i64* bitcast (i32* getelementptr inbounds (%struct.MyStruct, %struct.MyStruct* @caller.s, i64 0, i32 2) to i64*), align 8 + %2 = lshr i64 %1, 32 + %3 = trunc i64 %2 to i32 + %sub = sub nsw i32 0, %3 + ret i32 %sub +} + +define internal fastcc { i64, i64 } @callee(i32 signext %a, i32 signext %b) { +entry: +; COLDCC: std 0, 0(3) +; COLDCC: std 11, 8(3) + %0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{r6},~{r7},~{r8},~{r9},~{r10}"(i32 %a, i32 %b) + %mul = mul nsw i32 %a, 3 + %1 = mul i32 %b, -5 + %add = add i32 %1, %mul + %sub = add i32 %add, %0 + %mul5 = mul nsw i32 %b, %a + %add6 = add nsw i32 %sub, %mul5 + %retval.sroa.0.0.insert.ext = zext i32 %0 to i64 + %retval.sroa.3.8.insert.ext = zext i32 %sub to i64 + %retval.sroa.3.12.insert.ext = zext i32 %add6 to i64 + %retval.sroa.3.12.insert.shift = shl nuw i64 %retval.sroa.3.12.insert.ext, 32 + %retval.sroa.3.12.insert.insert = or i64 %retval.sroa.3.12.insert.shift, %retval.sroa.3.8.insert.ext + %.fca.0.insert = insertvalue { i64, i64 } undef, i64 %retval.sroa.0.0.insert.ext, 0 + %.fca.1.insert = insertvalue { i64, i64 } %.fca.0.insert, i64 %retval.sroa.3.12.insert.insert, 1 + ret { i64, i64 } %.fca.1.insert +} Index: test/CodeGen/PowerPC/coldcc3.ll =================================================================== --- /dev/null +++ test/CodeGen/PowerPC/coldcc3.ll @@ -0,0 +1,87 @@ +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -ppc-enable-coldcc < %s | FileCheck %s -check-prefix=COLDCC + +define signext i32 @caller(i32 signext %a, i32 signext %b, i32 signext %lim, i32 signext %i) local_unnamed_addr #0 !prof !30 { +entry: + %add = add nsw i32 %b, %a + %sub = add nsw i32 %lim, -1 + %cmp = icmp eq i32 %sub, %i + br i1 %cmp, label %if.then, label %if.end, !prof !31 + +if.then: ; preds = %entry + %call = tail call fastcc signext i32 @callee(i32 signext %a, i32 signext %b) + br label %if.end + +if.end: ; preds = %if.then, %entry + %f.0 = phi i32 [ %call, %if.then ], [ %add, %entry ] + ret i32 %f.0 +} + +define internal fastcc signext i32 @callee(i32 signext %a, i32 signext %b) unnamed_addr #0 { +; COLDCC: @callee +; COLDCC: std 6, -8(1) +; COLDCC: std 7, -16(1) +; COLDCC: std 8, -24(1) +; COLDCC: std 9, -32(1) +; COLDCC: ld 9, -32(1) +; COLDCC: ld 8, -24(1) +; COLDCC: ld 7, -16(1) +; COLDCC: ld 6, -8(1) + +entry: + %0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{r6},~{r7},~{r8},~{r9}"(i32 %a, i32 %b) #1, !srcloc !32 + %mul = mul nsw i32 %a, 3 + %mul1 = shl i32 %0, 1 + %add = add nsw i32 %mul1, %mul + ret i32 %add +} + +define signext i32 @main() local_unnamed_addr #0 !prof !33 { +entry: + br label %for.body + +for.cond.cleanup: ; preds = %for.body + %add.lcssa = phi i32 [ %add, %for.body ] + ret i32 %add.lcssa + +for.body: ; preds = %for.body, %entry + %i.011 = phi i32 [ 0, %entry ], [ %inc, %for.body ] + %ret.010 = phi i32 [ 0, %entry ], [ %add, %for.body ] + %call = tail call signext i32 @caller(i32 signext 4, i32 signext 5, i32 signext 10000000, i32 signext %i.011) + %add = add nsw i32 %call, %ret.010 + %inc = add nuw nsw i32 %i.011, 1 + %exitcond = icmp eq i32 %inc, 10000000 + br i1 %exitcond, label %for.cond.cleanup, label %for.body, !prof !34 +} + +!0 = !{i32 1, !"ProfileSummary", !1} +!1 = !{!2, !3, !4, !5, !6, !7, !8, !9} +!2 = !{!"ProfileFormat", !"InstrProf"} +!3 = !{!"TotalCount", i64 20000003} +!4 = !{!"MaxCount", i64 10000000} +!5 = !{!"MaxInternalCount", i64 10000000} +!6 = !{!"MaxFunctionCount", i64 10000000} +!7 = !{!"NumCounts", i64 5} +!8 = !{!"NumFunctions", i64 3} +!9 = !{!"DetailedSummary", !10} +!10 = !{!11, !12, !13, !14, !15, !16, !16, !17, !17, !18, !19, !20, !21, !22, !23, !24, !25, !26} +!11 = !{i32 10000, i64 10000000, i32 2} +!12 = !{i32 100000, i64 10000000, i32 2} +!13 = !{i32 200000, i64 10000000, i32 2} +!14 = !{i32 300000, i64 10000000, i32 2} +!15 = !{i32 400000, i64 10000000, i32 2} +!16 = !{i32 500000, i64 10000000, i32 2} +!17 = !{i32 600000, i64 10000000, i32 2} +!18 = !{i32 700000, i64 10000000, i32 2} +!19 = !{i32 800000, i64 10000000, i32 2} +!20 = !{i32 900000, i64 10000000, i32 2} +!21 = !{i32 950000, i64 10000000, i32 2} +!22 = !{i32 990000, i64 10000000, i32 2} +!23 = !{i32 999000, i64 10000000, i32 2} +!24 = !{i32 999900, i64 10000000, i32 2} +!25 = !{i32 999990, i64 10000000, i32 2} +!26 = !{i32 999999, i64 10000000, i32 2} +!30 = !{!"function_entry_count", i64 10000000} +!31 = !{!"branch_weights", i32 2, i32 10000000} +!32 = !{i32 59} +!33 = !{!"function_entry_count", i64 1} +!34 = !{!"branch_weights", i32 2, i32 10000001}