Index: lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- lib/Target/X86/X86ISelLowering.cpp
+++ lib/Target/X86/X86ISelLowering.cpp
@@ -6602,6 +6602,40 @@
   return false;
 }
 
+// check if the current node of build vector is a zero extended vedtor.
+// if so, return the value extended.
+static SDValue isSplatZeroExtended(const BuildVectorSDNode *Op, unsigned &NumElt,
+                                    MVT &EltType) {
+  SDValue ExtValue = Op->getOperand(0);
+  unsigned Delta = Op->getNumOperands();
+
+  for (unsigned i = 1; i < Op->getNumOperands(); i++) {
+    if (Op->getOperand(i) == ExtValue) {
+      Delta = i;
+      break;
+    }
+    if (!(Op->getOperand(i).isUndef() || isNullConstant(Op->getOperand(i))))
+      return SDValue();
+  }
+  if (!isPowerOf2_32(Delta) || Delta == 1)
+    return SDValue();
+
+  for (unsigned i = Delta; i < Op->getNumOperands(); i++) {
+    if (i % Delta == 0) {
+      if (Op->getOperand(i) != ExtValue)
+        return SDValue();
+    } else if (!(isNullConstant(Op->getOperand(i)) ||
+               Op->getOperand(i).isUndef()))
+      return SDValue();
+  }
+  unsigned EltSize =
+      Op->getSimpleValueType(0).getVectorElementType().getSizeInBits();
+  unsigned ExtVTSize = EltSize * Delta;
+  EltType = MVT::getIntegerVT(ExtVTSize);
+  NumElt = Op->getNumOperands() / Delta;
+  return ExtValue;
+}
+
 /// Attempt to use the vbroadcast instruction to generate a splat value
 /// from a splat BUILD_VECTOR which uses:
 ///  a. A single scalar load, or a constant.
@@ -6624,6 +6658,30 @@
   assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
          "Unsupported vector type for broadcast.");
 
+  // Attempt to use VBROADCASTM
+  // from this paterrn:
+  //  a. t0 = (zext_i64 (bitcast_i8 v2i1 X))
+  //  b. t1 = (build_vector t0 t0)
+  //
+  // create (VBROADCASTM v2i1 X)
+  if (Subtarget.hasCDI() && (VT.getSizeInBits() == 512 || Subtarget.hasVLX())) {
+    MVT EltType;
+    unsigned NumElts = 1;
+    SDValue ZeroExtended = isSplatZeroExtended(BVOp, NumElts, EltType);
+    if (ZeroExtended && ZeroExtended.getOpcode() == ISD::BITCAST) {
+      SDValue BOperand = ZeroExtended.getOperand(0);
+      if (BOperand.getSimpleValueType().getVectorElementType() == MVT::i1) {
+        if ((EltType == MVT::i64 && VT.getVectorElementType() == MVT::i8) ||  //for broadcastmb2q
+            (EltType == MVT::i32 && VT.getVectorElementType() == MVT::i16)) { //for broadcastmw2d
+          SDValue Brdcst =
+              DAG.getNode(X86ISD::VBROADCASTM, dl,
+                          MVT::getVectorVT(EltType, NumElts), BOperand);
+          return DAG.getBitcast(VT, Brdcst);
+        }
+      }
+    }
+  }
+
   BitVector UndefElements;
   SDValue Ld = BVOp->getSplatValue(&UndefElements);
 
Index: test/CodeGen/X86/broadcastm-lowering.ll
===================================================================
--- /dev/null
+++ test/CodeGen/X86/broadcastm-lowering.ll
@@ -0,0 +1,215 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512cd | FileCheck %s --check-prefix=ALL --check-prefix=AVX5CD
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown  -mattr=+avx512vl,avx512cd,+avx512bw| FileCheck %s --check-prefix=ALL --check-prefix=AVX512VLCDBW
+; RUN: llc < %s -mtriple=i686-unknown-unknown  -mattr=+avx512vl,avx512cd,+avx512bw| FileCheck %s --check-prefix=ALL --check-prefix=I686
+
+define <2 x i64> @test_mm_epi64(<8 x i16> %a, <8 x i16> %b) {
+; AVX5CD-LABEL: test_mm_epi64:
+; AVX5CD:       # BB#0: # %entry
+; AVX5CD-NEXT:    vpcmpeqw %xmm1, %xmm0, %xmm0
+; AVX5CD-NEXT:    vpmovsxwq %xmm0, %zmm0
+; AVX5CD-NEXT:    vpsllq $63, %zmm0, %zmm0
+; AVX5CD-NEXT:    vptestmq %zmm0, %zmm0, %k0
+; AVX5CD-NEXT:    kmovw %k0, %eax
+; AVX5CD-NEXT:    vpxor %xmm0, %xmm0, %xmm0
+; AVX5CD-NEXT:    vpinsrb $0, %eax, %xmm0, %xmm0
+; AVX5CD-NEXT:    vpinsrb $8, %eax, %xmm0, %xmm0
+; AVX5CD-NEXT:    vzeroupper
+; AVX5CD-NEXT:    retq
+;
+; AVX512VLCDBW-LABEL: test_mm_epi64:
+; AVX512VLCDBW:       # BB#0: # %entry
+; AVX512VLCDBW-NEXT:    vpcmpeqw %xmm1, %xmm0, %k0
+; AVX512VLCDBW-NEXT:    vpbroadcastmb2q %k0, %xmm0
+; AVX512VLCDBW-NEXT:    retq
+;
+; I686-LABEL: test_mm_epi64:
+; I686:       # BB#0: # %entry
+; I686-NEXT:    vpcmpeqw %xmm1, %xmm0, %k0
+; I686-NEXT:    kmovd %k0, %eax
+; I686-NEXT:    movzbl %al, %eax
+; I686-NEXT:    vmovd %eax, %xmm0
+; I686-NEXT:    vpbroadcastq %xmm0, %xmm0
+; I686-NEXT:    retl
+entry:
+  %0 = icmp eq <8 x i16> %a, %b
+  %1 = bitcast <8 x i1> %0 to i8
+  %conv.i = zext i8 %1 to i64
+  %vecinit.i.i = insertelement <2 x i64> undef, i64 %conv.i, i32 0
+  %vecinit1.i.i = shufflevector <2 x i64> %vecinit.i.i, <2 x i64> undef, <2 x i32> zeroinitializer
+  ret <2 x i64> %vecinit1.i.i
+}
+
+define <4 x i32> @test_mm_epi32(<16 x i8> %a, <16 x i8> %b) {
+; AVX5CD-LABEL: test_mm_epi32:
+; AVX5CD:       # BB#0: # %entry
+; AVX5CD-NEXT:    vpcmpeqb %xmm1, %xmm0, %xmm0
+; AVX5CD-NEXT:    vpmovsxbd %xmm0, %zmm0
+; AVX5CD-NEXT:    vpslld $31, %zmm0, %zmm0
+; AVX5CD-NEXT:    vptestmd %zmm0, %zmm0, %k0
+; AVX5CD-NEXT:    kmovw %k0, %eax
+; AVX5CD-NEXT:    vpxor %xmm0, %xmm0, %xmm0
+; AVX5CD-NEXT:    vpinsrw $0, %eax, %xmm0, %xmm0
+; AVX5CD-NEXT:    vpinsrw $2, %eax, %xmm0, %xmm0
+; AVX5CD-NEXT:    vpinsrw $4, %eax, %xmm0, %xmm0
+; AVX5CD-NEXT:    vpinsrw $6, %eax, %xmm0, %xmm0
+; AVX5CD-NEXT:    vzeroupper
+; AVX5CD-NEXT:    retq
+;
+; AVX512VLCDBW-LABEL: test_mm_epi32:
+; AVX512VLCDBW:       # BB#0: # %entry
+; AVX512VLCDBW-NEXT:    vpcmpeqb %xmm1, %xmm0, %k0
+; AVX512VLCDBW-NEXT:    vpbroadcastmw2d %k0, %xmm0
+; AVX512VLCDBW-NEXT:    retq
+;
+; I686-LABEL: test_mm_epi32:
+; I686:       # BB#0: # %entry
+; I686-NEXT:    vpcmpeqb %xmm1, %xmm0, %k0
+; I686-NEXT:    vpbroadcastmw2d %k0, %xmm0
+; I686-NEXT:    retl
+entry:
+  %0 = icmp eq <16 x i8> %a, %b
+  %1 = bitcast <16 x i1> %0 to i16
+  %conv.i = zext i16 %1 to i32
+  %vecinit.i.i = insertelement <4 x i32> undef, i32 %conv.i, i32 0
+  %vecinit3.i.i = shufflevector <4 x i32> %vecinit.i.i, <4 x i32> undef, <4 x i32> zeroinitializer
+  ret <4 x i32> %vecinit3.i.i
+}
+
+define <16 x i32> @test_mm512_epi32(<16 x i32> %a, <16 x i32> %b) {
+; AVX5CD-LABEL: test_mm512_epi32:
+; AVX5CD:       # BB#0: # %entry
+; AVX5CD-NEXT:    vpcmpeqd %zmm1, %zmm0, %k0
+; AVX5CD-NEXT:    kmovw %k0, %eax
+; AVX5CD-NEXT:    vpbroadcastd %eax, %zmm0
+; AVX5CD-NEXT:    retq
+;
+; AVX512VLCDBW-LABEL: test_mm512_epi32:
+; AVX512VLCDBW:       # BB#0: # %entry
+; AVX512VLCDBW-NEXT:    vpcmpeqd %zmm1, %zmm0, %k0
+; AVX512VLCDBW-NEXT:    vpbroadcastmw2d %k0, %zmm0
+; AVX512VLCDBW-NEXT:    retq
+;
+; I686-LABEL: test_mm512_epi32:
+; I686:       # BB#0: # %entry
+; I686-NEXT:    vpcmpeqd %zmm1, %zmm0, %k0
+; I686-NEXT:    vpbroadcastmw2d %k0, %zmm0
+; I686-NEXT:    retl
+entry:
+  %0 = icmp eq <16 x i32> %a, %b
+  %1 = bitcast <16 x i1> %0 to i16
+  %conv.i = zext i16 %1 to i32
+  %vecinit.i.i = insertelement <16 x i32> undef, i32 %conv.i, i32 0
+  %vecinit15.i.i = shufflevector <16 x i32> %vecinit.i.i, <16 x i32> undef, <16 x i32> zeroinitializer
+  ret <16 x i32> %vecinit15.i.i
+}
+
+define <8 x i64> @test_mm512_epi64(<8 x i32> %a, <8 x i32> %b) {
+; AVX5CD-LABEL: test_mm512_epi64:
+; AVX5CD:       # BB#0: # %entry
+; AVX5CD-NEXT:    # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
+; AVX5CD-NEXT:    # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; AVX5CD-NEXT:    vpcmpeqd %zmm1, %zmm0, %k0
+; AVX5CD-NEXT:    kmovw %k0, %eax
+; AVX5CD-NEXT:    movzbl %al, %eax
+; AVX5CD-NEXT:    vpbroadcastq %rax, %zmm0
+; AVX5CD-NEXT:    retq
+;
+; AVX512VLCDBW-LABEL: test_mm512_epi64:
+; AVX512VLCDBW:       # BB#0: # %entry
+; AVX512VLCDBW-NEXT:    vpcmpeqd %ymm1, %ymm0, %k0
+; AVX512VLCDBW-NEXT:    vpbroadcastmb2q %k0, %zmm0
+; AVX512VLCDBW-NEXT:    retq
+;
+; I686-LABEL: test_mm512_epi64:
+; I686:       # BB#0: # %entry
+; I686-NEXT:    vpcmpeqd %ymm1, %ymm0, %k0
+; I686-NEXT:    kmovd %k0, %eax
+; I686-NEXT:    movzbl %al, %eax
+; I686-NEXT:    vmovd %eax, %xmm0
+; I686-NEXT:    vpbroadcastq %xmm0, %xmm0
+; I686-NEXT:    vinserti128 $1, %xmm0, %ymm0, %ymm0
+; I686-NEXT:    vinserti64x4 $1, %ymm0, %zmm0, %zmm0
+; I686-NEXT:    retl
+entry:
+  %0 = icmp eq <8 x i32> %a, %b
+  %1 = bitcast <8 x i1> %0 to i8
+  %conv.i = zext i8 %1 to i64
+  %vecinit.i.i = insertelement <8 x i64> undef, i64 %conv.i, i32 0
+  %vecinit7.i.i = shufflevector <8 x i64> %vecinit.i.i, <8 x i64> undef, <8 x i32> zeroinitializer
+  ret <8 x i64> %vecinit7.i.i
+}
+
+define <4 x i64> @test_mm256_epi64(<8 x i32> %a, <8 x i32> %b) {
+; AVX5CD-LABEL: test_mm256_epi64:
+; AVX5CD:       # BB#0: # %entry
+; AVX5CD-NEXT:    # kill: %YMM1<def> %YMM1<kill> %ZMM1<def>
+; AVX5CD-NEXT:    # kill: %YMM0<def> %YMM0<kill> %ZMM0<def>
+; AVX5CD-NEXT:    vpcmpeqd %zmm1, %zmm0, %k0
+; AVX5CD-NEXT:    kmovw %k0, %eax
+; AVX5CD-NEXT:    vpxor %xmm0, %xmm0, %xmm0
+; AVX5CD-NEXT:    vpinsrb $0, %eax, %xmm0, %xmm0
+; AVX5CD-NEXT:    vpinsrb $8, %eax, %xmm0, %xmm0
+; AVX5CD-NEXT:    vinserti128 $1, %xmm0, %ymm0, %ymm0
+; AVX5CD-NEXT:    retq
+;
+; AVX512VLCDBW-LABEL: test_mm256_epi64:
+; AVX512VLCDBW:       # BB#0: # %entry
+; AVX512VLCDBW-NEXT:    vpcmpeqd %ymm1, %ymm0, %k0
+; AVX512VLCDBW-NEXT:    vpbroadcastmb2q %k0, %ymm0
+; AVX512VLCDBW-NEXT:    retq
+;
+; I686-LABEL: test_mm256_epi64:
+; I686:       # BB#0: # %entry
+; I686-NEXT:    vpcmpeqd %ymm1, %ymm0, %k0
+; I686-NEXT:    kmovd %k0, %eax
+; I686-NEXT:    movzbl %al, %eax
+; I686-NEXT:    vmovd %eax, %xmm0
+; I686-NEXT:    vpbroadcastq %xmm0, %xmm0
+; I686-NEXT:    vinserti128 $1, %xmm0, %ymm0, %ymm0
+; I686-NEXT:    retl
+entry:
+  %0 = icmp eq <8 x i32> %a, %b
+  %1 = bitcast <8 x i1> %0 to i8
+  %conv.i = zext i8 %1 to i64
+  %vecinit.i.i = insertelement <4 x i64> undef, i64 %conv.i, i32 0
+  %vecinit3.i.i = shufflevector <4 x i64> %vecinit.i.i, <4 x i64> undef, <4 x i32> zeroinitializer
+  ret <4 x i64> %vecinit3.i.i
+}
+
+define <8 x i32> @test_mm256_epi32(<16 x i16> %a, <16 x i16> %b) {
+; AVX5CD-LABEL: test_mm256_epi32:
+; AVX5CD:       # BB#0: # %entry
+; AVX5CD-NEXT:    vpcmpeqw %ymm1, %ymm0, %ymm0
+; AVX5CD-NEXT:    vpmovsxwd %ymm0, %zmm0
+; AVX5CD-NEXT:    vpslld $31, %zmm0, %zmm0
+; AVX5CD-NEXT:    vptestmd %zmm0, %zmm0, %k0
+; AVX5CD-NEXT:    kmovw %k0, %eax
+; AVX5CD-NEXT:    vpxor %xmm0, %xmm0, %xmm0
+; AVX5CD-NEXT:    vpinsrw $0, %eax, %xmm0, %xmm0
+; AVX5CD-NEXT:    vpinsrw $2, %eax, %xmm0, %xmm0
+; AVX5CD-NEXT:    vpinsrw $4, %eax, %xmm0, %xmm0
+; AVX5CD-NEXT:    vpinsrw $6, %eax, %xmm0, %xmm0
+; AVX5CD-NEXT:    vinserti128 $1, %xmm0, %ymm0, %ymm0
+; AVX5CD-NEXT:    retq
+;
+; AVX512VLCDBW-LABEL: test_mm256_epi32:
+; AVX512VLCDBW:       # BB#0: # %entry
+; AVX512VLCDBW-NEXT:    vpcmpeqw %ymm1, %ymm0, %k0
+; AVX512VLCDBW-NEXT:    vpbroadcastmw2d %k0, %ymm0
+; AVX512VLCDBW-NEXT:    retq
+;
+; I686-LABEL: test_mm256_epi32:
+; I686:       # BB#0: # %entry
+; I686-NEXT:    vpcmpeqw %ymm1, %ymm0, %k0
+; I686-NEXT:    vpbroadcastmw2d %k0, %ymm0
+; I686-NEXT:    retl
+entry:
+  %0 = icmp eq <16 x i16> %a, %b
+  %1 = bitcast <16 x i1> %0 to i16
+  %conv.i = zext i16 %1 to i32
+  %vecinit.i.i = insertelement <8 x i32> undef, i32 %conv.i, i32 0
+  %vecinit7.i.i = shufflevector <8 x i32> %vecinit.i.i, <8 x i32> undef, <8 x i32> zeroinitializer
+  ret <8 x i32> %vecinit7.i.i
+}
+