Index: lib/CodeGen/MachineScheduler.cpp
===================================================================
--- lib/CodeGen/MachineScheduler.cpp
+++ lib/CodeGen/MachineScheduler.cpp
@@ -2441,7 +2441,9 @@
   // acyclic latency during PostRA, and highly out-of-order processors will
   // skip PostRA scheduling.
   if (!OtherResLimited) {
-    if (IsPostRA || (RemLatency + CurrZone.getCurrCycle() > Rem.CriticalPath)) {
+    unsigned Issued = CurrZone.isTop() ? CurrZone.getCurrCycle() :
+                                         CurrZone.getScheduledLatency();
+    if (IsPostRA || (RemLatency + Issued > Rem.CriticalPath)) {
       Policy.ReduceLatency |= true;
       DEBUG(dbgs() << "  " << CurrZone.Available.getName()
             << " RemainingLatency " << RemLatency << " + "
Index: test/CodeGen/AArch64/machine-combiner.ll
===================================================================
--- test/CodeGen/AArch64/machine-combiner.ll
+++ test/CodeGen/AArch64/machine-combiner.ll
@@ -63,9 +63,9 @@
 ; CHECK-LABEL:   reassociate_adds5:
 ; CHECK:         fadd  s0, s0, s1
 ; CHECK-NEXT:    fadd  s1, s2, s3
+; CHECK-NEXT:    fadd  s2, s4, s5
 ; CHECK-NEXT:    fadd  s0, s0, s1
-; CHECK-NEXT:    fadd  s1, s4, s5
-; CHECK-NEXT:    fadd  s1, s1, s6
+; CHECK-NEXT:    fadd  s1, s2, s6
 ; CHECK-NEXT:    fadd  s0, s0, s1
 ; CHECK-NEXT:    fadd  s0, s0, s7
 ; CHECK-NEXT:    ret
Index: test/CodeGen/AArch64/misched-sdiv.ll
===================================================================
--- /dev/null
+++ test/CodeGen/AArch64/misched-sdiv.ll
@@ -0,0 +1,28 @@
+; RUN: llc < %s -mtriple=aarch64-unknown-linux -mcpu=cortex-a57 -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=A57_SCHED
+; RUN: llc < %s -mtriple=aarch64-unknown-linux -mcpu=generic -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefix=CHECK --check-prefix=GENERIC
+
+; Check the latency for instructions for both generic and cortex-a57.
+; SDIV should be scheduled at the block's begin (20 cyc of independent M unit).
+;
+; CHECK:       ********** MI Scheduling **********
+; CHECK:      foo:BB#0 entry
+
+; CHECK:      ** Final schedule for BB#0 ***
+; GENERIC:    LDRWui
+; GENERIC:    SDIV
+; A57_SCHED:  SDIV
+; A57_SCHED:  LDRWui
+; CHECK:      ********** INTERVALS **********
+
+
+; Function Attrs: norecurse nounwind readnone
+define hidden i32 @foo(i32 %a, i32 %b, i32 %c, i32* %d) local_unnamed_addr #0 {
+entry:
+  %xor = xor i32 %c, %b
+  %ld = load i32, i32* %d
+  %add = add nsw i32 %xor, %ld
+  %div = sdiv i32 %a, %b
+  ;%div1 = sdiv i32 %add, %b
+  %sub = sub i32 %div, %add
+  ret i32 %sub
+}