Index: llvm/trunk/lib/CodeGen/UnreachableBlockElim.cpp =================================================================== --- llvm/trunk/lib/CodeGen/UnreachableBlockElim.cpp +++ llvm/trunk/lib/CodeGen/UnreachableBlockElim.cpp @@ -207,11 +207,12 @@ MachineRegisterInfo &MRI = F.getRegInfo(); unsigned InputSub = Input.getSubReg(); if (InputSub == 0 && - MRI.constrainRegClass(InputReg, MRI.getRegClass(OutputReg))) { + MRI.constrainRegClass(InputReg, MRI.getRegClass(OutputReg)) && + !Input.isUndef()) { MRI.replaceRegWith(OutputReg, InputReg); } else { // The input register to the PHI has a subregister or it can't be - // constrained to the proper register class: + // constrained to the proper register class or it is undef: // insert a COPY instead of simply replacing the output // with the input. const TargetInstrInfo *TII = F.getSubtarget().getInstrInfo(); Index: llvm/trunk/test/CodeGen/MIR/X86/unreachable-mbb-undef-phi.mir =================================================================== --- llvm/trunk/test/CodeGen/MIR/X86/unreachable-mbb-undef-phi.mir +++ llvm/trunk/test/CodeGen/MIR/X86/unreachable-mbb-undef-phi.mir @@ -0,0 +1,38 @@ +# RUN: llc %s -o - -run-pass=processimpdefs -run-pass=unreachable-mbb-elimination | FileCheck %s +--- +name: f +tracksRegLiveness: true +registers: + - { id: 0, class: gr32, preferred-register: '' } + - { id: 1, class: gr32, preferred-register: '' } + - { id: 2, class: gr32, preferred-register: '' } +body: | + bb.0: + %0 = IMPLICIT_DEF + JMP_1 %bb.1 + + bb.1: + %1 = PHI %0, %bb.0, %2, %bb.2 + %2 = ADD32ri8 killed %1, 1, implicit-def %eflags + JMP_1 %bb.3 + + bb.2: + JMP_1 %bb.1 + + bb.3: +... + +# bb2 above is dead and should be removed and the PHI should be replaced with a +# COPY from an undef value since the bb0 value in the PHI is undef. + +# CHECK: bb.0: +# CHECK: successors: %bb.1 +# CHECK: JMP_1 %bb.1 + +# CHECK: bb.1: +# CHECK: successors: %bb.2 +# CHECK: [[TMP1:%[0-9]+]] = COPY undef %{{[0-9]+}} +# CHECK: %{{[0-9]+}} = ADD32ri8 killed [[TMP1]], 1 +# CHECK: JMP_1 %bb.2 + +# CHECK: bb.2: