Index: include/llvm/Analysis/TargetTransformInfo.h
===================================================================
--- include/llvm/Analysis/TargetTransformInfo.h
+++ include/llvm/Analysis/TargetTransformInfo.h
@@ -548,7 +548,7 @@
   bool enableAggressiveInterleaving(bool LoopHasReductions) const;
 
   /// \brief Enable inline expansion of memcmp
-  bool expandMemCmp(Instruction *I, unsigned &MaxLoadSize) const;
+  bool enableMemCmpExpansion(unsigned &MaxLoadSize) const;
 
   /// \brief Enable matching of interleaved access groups.
   bool enableInterleavedAccessVectorization() const;
@@ -985,7 +985,7 @@
                                                     unsigned VF) = 0;
   virtual bool supportsEfficientVectorElementLoadStore() = 0;
   virtual bool enableAggressiveInterleaving(bool LoopHasReductions) = 0;
-  virtual bool expandMemCmp(Instruction *I, unsigned &MaxLoadSize) = 0;
+  virtual bool enableMemCmpExpansion(unsigned &MaxLoadSize) = 0;
   virtual bool enableInterleavedAccessVectorization() = 0;
   virtual bool isFPVectorizationPotentiallyUnsafe() = 0;
   virtual bool allowsMisalignedMemoryAccesses(LLVMContext &Context,
@@ -1235,8 +1235,8 @@
   bool enableAggressiveInterleaving(bool LoopHasReductions) override {
     return Impl.enableAggressiveInterleaving(LoopHasReductions);
   }
-  bool expandMemCmp(Instruction *I, unsigned &MaxLoadSize) override {
-    return Impl.expandMemCmp(I, MaxLoadSize);
+  bool enableMemCmpExpansion(unsigned &MaxLoadSize) override {
+    return Impl.enableMemCmpExpansion(MaxLoadSize);
   }
   bool enableInterleavedAccessVectorization() override {
     return Impl.enableInterleavedAccessVectorization();
Index: include/llvm/Analysis/TargetTransformInfoImpl.h
===================================================================
--- include/llvm/Analysis/TargetTransformInfoImpl.h
+++ include/llvm/Analysis/TargetTransformInfoImpl.h
@@ -290,7 +290,7 @@
 
   bool enableAggressiveInterleaving(bool LoopHasReductions) { return false; }
 
-  bool expandMemCmp(Instruction *I, unsigned &MaxLoadSize) { return false; }
+  bool enableMemCmpExpansion(unsigned &MaxLoadSize) { return false; }
 
   bool enableInterleavedAccessVectorization() { return false; }
 
Index: lib/Analysis/TargetTransformInfo.cpp
===================================================================
--- lib/Analysis/TargetTransformInfo.cpp
+++ lib/Analysis/TargetTransformInfo.cpp
@@ -245,8 +245,8 @@
   return TTIImpl->enableAggressiveInterleaving(LoopHasReductions);
 }
 
-bool TargetTransformInfo::expandMemCmp(Instruction *I, unsigned &MaxLoadSize) const {
-  return TTIImpl->expandMemCmp(I, MaxLoadSize);
+bool TargetTransformInfo::enableMemCmpExpansion(unsigned &MaxLoadSize) const {
+  return TTIImpl->enableMemCmpExpansion(MaxLoadSize);
 }
 
 bool TargetTransformInfo::enableInterleavedAccessVectorization() const {
Index: lib/CodeGen/CodeGenPrepare.cpp
===================================================================
--- lib/CodeGen/CodeGenPrepare.cpp
+++ lib/CodeGen/CodeGenPrepare.cpp
@@ -2315,7 +2315,7 @@
   // TTI call to check if target would like to expand memcmp. Also, get the
   // MaxLoadSize.
   unsigned MaxLoadSize;
-  if (!TTI->expandMemCmp(CI, MaxLoadSize))
+  if (!TTI->enableMemCmpExpansion(MaxLoadSize))
     return false;
 
   // Early exit from expansion if -Oz.
Index: lib/Target/PowerPC/PPCTargetTransformInfo.h
===================================================================
--- lib/Target/PowerPC/PPCTargetTransformInfo.h
+++ lib/Target/PowerPC/PPCTargetTransformInfo.h
@@ -61,7 +61,7 @@
   /// @{
 
   bool enableAggressiveInterleaving(bool LoopHasReductions);
-  bool expandMemCmp(Instruction *I, unsigned &MaxLoadSize);
+  bool enableMemCmpExpansion(unsigned &MaxLoadSize);
   bool enableInterleavedAccessVectorization();
   unsigned getNumberOfRegisters(bool Vector);
   unsigned getRegisterBitWidth(bool Vector) const;
Index: lib/Target/PowerPC/PPCTargetTransformInfo.cpp
===================================================================
--- lib/Target/PowerPC/PPCTargetTransformInfo.cpp
+++ lib/Target/PowerPC/PPCTargetTransformInfo.cpp
@@ -215,7 +215,7 @@
   return LoopHasReductions;
 }
 
-bool PPCTTIImpl::expandMemCmp(Instruction *I, unsigned &MaxLoadSize) {
+bool PPCTTIImpl::enableMemCmpExpansion(unsigned &MaxLoadSize) {
   MaxLoadSize = 8;
   return true;
 }
Index: lib/Target/X86/X86TargetTransformInfo.h
===================================================================
--- lib/Target/X86/X86TargetTransformInfo.h
+++ lib/Target/X86/X86TargetTransformInfo.h
@@ -127,7 +127,7 @@
   bool hasDivRemOp(Type *DataType, bool IsSigned);
   bool areInlineCompatible(const Function *Caller,
                            const Function *Callee) const;
-  bool expandMemCmp(Instruction *I, unsigned &MaxLoadSize);
+  bool enableMemCmpExpansion(unsigned &MaxLoadSize);
   bool enableInterleavedAccessVectorization();
 private:
   int getGSScalarCost(unsigned Opcode, Type *DataTy, bool VariableMask,
Index: lib/Target/X86/X86TargetTransformInfo.cpp
===================================================================
--- lib/Target/X86/X86TargetTransformInfo.cpp
+++ lib/Target/X86/X86TargetTransformInfo.cpp
@@ -2536,7 +2536,7 @@
   return (CallerBits & CalleeBits) == CalleeBits;
 }
 
-bool X86TTIImpl::expandMemCmp(Instruction *I, unsigned &MaxLoadSize) {
+bool X86TTIImpl::enableMemCmpExpansion(unsigned &MaxLoadSize) {
   // TODO: We can increase these based on available vector ops.
   MaxLoadSize = ST->is64Bit() ? 8 : 4;
   return true;