Index: lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp =================================================================== --- lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp +++ lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp @@ -380,7 +380,7 @@ return X86::reloc_riprel_4byte_movq_load; case X86::CALL64m: case X86::JMP64m: - case X86::TEST64rm: + case X86::TEST64mr: case X86::ADC64rm: case X86::ADD64rm: case X86::AND64rm: Index: lib/Target/X86/X86InstrArithmetic.td =================================================================== --- lib/Target/X86/X86InstrArithmetic.td +++ lib/Target/X86/X86InstrArithmetic.td @@ -652,9 +652,8 @@ // BinOpRR - Instructions like "add reg, reg, reg". class BinOpRR opcode, string mnemonic, X86TypeInfo typeinfo, - dag outlist, list pattern, InstrItinClass itin, - Format f = MRMDestReg> - : ITy pattern, InstrItinClass itin> + : ITy, Sched<[WriteALU]>; @@ -662,11 +661,11 @@ // BinOpRR_F - Instructions like "cmp reg, Reg", where the pattern has // just a EFLAGS as a result. class BinOpRR_F opcode, string mnemonic, X86TypeInfo typeinfo, - SDPatternOperator opnode, Format f = MRMDestReg> + SDPatternOperator opnode> : BinOpRR; + IIC_BIN_NONMEM>; // BinOpRR_RF - Instructions like "add reg, reg, reg", where the pattern has // both a regclass and EFLAGS as a result. @@ -727,7 +726,7 @@ // BinOpRM_F - Instructions like "cmp reg, [mem]". class BinOpRM_F opcode, string mnemonic, X86TypeInfo typeinfo, - SDPatternOperator opnode> + SDNode opnode> : BinOpRM; @@ -837,7 +836,7 @@ // BinOpMR_F - Instructions like "cmp [mem], reg". class BinOpMR_F opcode, string mnemonic, X86TypeInfo typeinfo, - SDNode opnode> + SDPatternOperator opnode> : BinOpMR; @@ -1224,10 +1223,10 @@ def TEST64rr : BinOpRR_F<0x84, "test", Xi64, X86testpat>; } // isCommutable - def TEST8rm : BinOpRM_F<0x84, "test", Xi8 , X86testpat>; - def TEST16rm : BinOpRM_F<0x84, "test", Xi16, X86testpat>; - def TEST32rm : BinOpRM_F<0x84, "test", Xi32, X86testpat>; - def TEST64rm : BinOpRM_F<0x84, "test", Xi64, X86testpat>; + def TEST8mr : BinOpMR_F<0x84, "test", Xi8 , X86testpat>; + def TEST16mr : BinOpMR_F<0x84, "test", Xi16, X86testpat>; + def TEST32mr : BinOpMR_F<0x84, "test", Xi32, X86testpat>; + def TEST64mr : BinOpMR_F<0x84, "test", Xi64, X86testpat>; def TEST8ri : BinOpRI_F<0xF6, "test", Xi8 , X86testpat, MRM0r>; def TEST16ri : BinOpRI_F<0xF6, "test", Xi16, X86testpat, MRM0r>; Index: lib/Target/X86/X86InstrInfo.cpp =================================================================== --- lib/Target/X86/X86InstrInfo.cpp +++ lib/Target/X86/X86InstrInfo.cpp @@ -375,9 +375,13 @@ { X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD }, { X86::TAILJMPr64_REX, X86::TAILJMPm64_REX, TB_FOLDED_LOAD }, { X86::TEST16ri, X86::TEST16mi, TB_FOLDED_LOAD }, + { X86::TEST16rr, X86::TEST16mr, TB_FOLDED_LOAD }, { X86::TEST32ri, X86::TEST32mi, TB_FOLDED_LOAD }, + { X86::TEST32rr, X86::TEST32mr, TB_FOLDED_LOAD }, { X86::TEST64ri32, X86::TEST64mi32, TB_FOLDED_LOAD }, + { X86::TEST64rr, X86::TEST64mr, TB_FOLDED_LOAD }, { X86::TEST8ri, X86::TEST8mi, TB_FOLDED_LOAD }, + { X86::TEST8rr, X86::TEST8mr, TB_FOLDED_LOAD }, // AVX 128-bit versions of foldable instructions { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr, TB_FOLDED_STORE }, @@ -608,10 +612,6 @@ { X86::SQRTSDr_Int, X86::SQRTSDm_Int, TB_NO_REVERSE }, { X86::SQRTSSr, X86::SQRTSSm, 0 }, { X86::SQRTSSr_Int, X86::SQRTSSm_Int, TB_NO_REVERSE }, - { X86::TEST16rr, X86::TEST16rm, 0 }, - { X86::TEST32rr, X86::TEST32rm, 0 }, - { X86::TEST64rr, X86::TEST64rm, 0 }, - { X86::TEST8rr, X86::TEST8rm, 0 }, // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0 { X86::UCOMISDrr, X86::UCOMISDrm, 0 }, { X86::UCOMISSrr, X86::UCOMISSrm, 0 }, Index: lib/Target/X86/X86InstrInfo.td =================================================================== --- lib/Target/X86/X86InstrInfo.td +++ lib/Target/X86/X86InstrInfo.td @@ -3234,14 +3234,14 @@ FIXME */ // test: We accept "testX , " and "testX , " as synonyms. -def : InstAlias<"test{b}\t{$val, $mem|$mem, $val}", - (TEST8rm GR8 :$val, i8mem :$mem), 0>; -def : InstAlias<"test{w}\t{$val, $mem|$mem, $val}", - (TEST16rm GR16:$val, i16mem:$mem), 0>; -def : InstAlias<"test{l}\t{$val, $mem|$mem, $val}", - (TEST32rm GR32:$val, i32mem:$mem), 0>; -def : InstAlias<"test{q}\t{$val, $mem|$mem, $val}", - (TEST64rm GR64:$val, i64mem:$mem), 0>; +def : InstAlias<"test{b}\t{$mem, $val|$val, $mem}", + (TEST8mr i8mem :$mem, GR8 :$val), 0>; +def : InstAlias<"test{w}\t{$mem, $val|$val, $mem}", + (TEST16mr i16mem:$mem, GR16:$val), 0>; +def : InstAlias<"test{l}\t{$mem, $val|$val, $mem}", + (TEST32mr i32mem:$mem, GR32:$val), 0>; +def : InstAlias<"test{q}\t{$mem, $val|$val, $mem}", + (TEST64mr i64mem:$mem, GR64:$val), 0>; // xchg: We accept "xchgX , " and "xchgX , " as synonyms. def : InstAlias<"xchg{b}\t{$mem, $val|$val, $mem}", Index: lib/Target/X86/X86MacroFusion.cpp =================================================================== --- lib/Target/X86/X86MacroFusion.cpp +++ lib/Target/X86/X86MacroFusion.cpp @@ -82,10 +82,10 @@ case X86::TEST32i32: case X86::TEST64i32: case X86::TEST64ri32: - case X86::TEST8rm: - case X86::TEST16rm: - case X86::TEST32rm: - case X86::TEST64rm: + case X86::TEST8mr: + case X86::TEST16mr: + case X86::TEST32mr: + case X86::TEST64mr: case X86::TEST8ri_NOREX: case X86::AND16i16: case X86::AND16ri: Index: lib/Target/X86/X86SchedHaswell.td =================================================================== --- lib/Target/X86/X86SchedHaswell.td +++ lib/Target/X86/X86SchedHaswell.td @@ -2099,9 +2099,9 @@ def: InstRW<[HWWriteResGroup18], (instregex "POP(16|32|64)r(mr?)")>; def: InstRW<[HWWriteResGroup18], (instregex "SUB(16|32|64)rm")>; def: InstRW<[HWWriteResGroup18], (instregex "SUB8rm")>; -def: InstRW<[HWWriteResGroup18], (instregex "TEST(16|32|64)rm")>; +def: InstRW<[HWWriteResGroup18], (instregex "TEST(16|32|64)mr")>; def: InstRW<[HWWriteResGroup18], (instregex "TEST8mi")>; -def: InstRW<[HWWriteResGroup18], (instregex "TEST8rm")>; +def: InstRW<[HWWriteResGroup18], (instregex "TEST8mr")>; def: InstRW<[HWWriteResGroup18], (instregex "XOR(16|32|64)rm")>; def: InstRW<[HWWriteResGroup18], (instregex "XOR8rm")>; Index: lib/Target/X86/X86SchedSandyBridge.td =================================================================== --- lib/Target/X86/X86SchedSandyBridge.td +++ lib/Target/X86/X86SchedSandyBridge.td @@ -2010,9 +2010,9 @@ def: InstRW<[SBWriteResGroup70], (instregex "SUB(16|32|64)mr")>; def: InstRW<[SBWriteResGroup70], (instregex "SUB8mi")>; def: InstRW<[SBWriteResGroup70], (instregex "SUB8mr")>; -def: InstRW<[SBWriteResGroup70], (instregex "TEST(16|32|64)rm")>; +def: InstRW<[SBWriteResGroup70], (instregex "TEST(16|32|64)mr")>; def: InstRW<[SBWriteResGroup70], (instregex "TEST8mi")>; -def: InstRW<[SBWriteResGroup70], (instregex "TEST8rm")>; +def: InstRW<[SBWriteResGroup70], (instregex "TEST8mr")>; def: InstRW<[SBWriteResGroup70], (instregex "XOR(16|32|64)mi8")>; def: InstRW<[SBWriteResGroup70], (instregex "XOR(16|32|64)mr")>; def: InstRW<[SBWriteResGroup70], (instregex "XOR8mi")>; Index: lib/Target/X86/X86SchedSkylakeClient.td =================================================================== --- lib/Target/X86/X86SchedSkylakeClient.td +++ lib/Target/X86/X86SchedSkylakeClient.td @@ -1634,9 +1634,9 @@ def: InstRW<[SKLWriteResGroup21], (instregex "POP(16|32|64)r(mr?)")>; def: InstRW<[SKLWriteResGroup21], (instregex "SUB(16|32|64)rm")>; def: InstRW<[SKLWriteResGroup21], (instregex "SUB8rm")>; -def: InstRW<[SKLWriteResGroup21], (instregex "TEST(16|32|64)rm")>; +def: InstRW<[SKLWriteResGroup21], (instregex "TEST(16|32|64)mr")>; def: InstRW<[SKLWriteResGroup21], (instregex "TEST8mi")>; -def: InstRW<[SKLWriteResGroup21], (instregex "TEST8rm")>; +def: InstRW<[SKLWriteResGroup21], (instregex "TEST8mr")>; def: InstRW<[SKLWriteResGroup21], (instregex "XOR(16|32|64)rm")>; def: InstRW<[SKLWriteResGroup21], (instregex "XOR8rm")>; Index: test/CodeGen/X86/absolute-bit-mask.ll =================================================================== --- test/CodeGen/X86/absolute-bit-mask.ll +++ test/CodeGen/X86/absolute-bit-mask.ll @@ -43,7 +43,7 @@ define void @foo64(i64* %ptr) { %load = load i64, i64* %ptr ; CHECK: movabsq $bit_mask64, %rax - ; CHECK: testq (%rdi), %rax + ; CHECK: testq %rax, (%rdi) %and = and i64 %load, ptrtoint (i8* @bit_mask64 to i64) %icmp = icmp eq i64 %and, 0 br i1 %icmp, label %t, label %f Index: test/CodeGen/X86/post-ra-sched-with-debug.mir =================================================================== --- test/CodeGen/X86/post-ra-sched-with-debug.mir +++ test/CodeGen/X86/post-ra-sched-with-debug.mir @@ -292,7 +292,7 @@ %rcx = CMOVNE64rr killed %rcx, killed %rdx, implicit killed %eflags %rcx = OR64rr killed %rcx, killed %rsi, implicit-def dead %eflags %rdx = MOVSX64rm32 %rbx, 1, _, 0, _ :: (load 4, align 8) - TEST32rm killed %eax, killed %rcx, 4, killed %rdx, 0, _, implicit-def %eflags :: (load 4) + TEST32mr killed %rcx, 4, killed %rdx, 0, _, killed %eax, implicit-def %eflags :: (load 4) JNE_1 %bb.2, implicit %eflags JMP_1 %bb.3 Index: test/CodeGen/X86/testl-commute.ll =================================================================== --- test/CodeGen/X86/testl-commute.ll +++ test/CodeGen/X86/testl-commute.ll @@ -9,7 +9,7 @@ define i32 @test(i32* %P, i32* %G) nounwind { ; CHECK-LABEL: test: ; CHECK-NOT: ret -; CHECK: testl (%{{.*}}), %{{.*}} +; CHECK: testl %{{.*}}, (%{{.*}}) ; CHECK: ret entry: @@ -30,7 +30,7 @@ define i32 @test2(i32* %P, i32* %G) nounwind { ; CHECK-LABEL: test2: ; CHECK-NOT: ret -; CHECK: testl (%{{.*}}), %{{.*}} +; CHECK: testl %{{.*}}, (%{{.*}}) ; CHECK: ret entry: @@ -51,7 +51,7 @@ define i32 @test3(i32* %P, i32* %G) nounwind { ; CHECK-LABEL: test3: ; CHECK-NOT: ret -; CHECK: testl (%{{.*}}), %{{.*}} +; CHECK: testl %{{.*}}, (%{{.*}}) ; CHECK: ret entry: Index: test/MC/Disassembler/X86/x86-16.txt =================================================================== --- test/MC/Disassembler/X86/x86-16.txt +++ test/MC/Disassembler/X86/x86-16.txt @@ -318,10 +318,10 @@ # CHECK: sysretl 0x0f 0x07 -# CHECK: testl -24(%ebp), %ecx +# CHECK: testl %ecx, -24(%ebp) 0x67 0x66 0x85 0x4d 0xe8 -# CHECK: testl -24(%ebp), %ecx +# CHECK: testl %ecx, -24(%ebp) 0x67 0x66 0x85 0x4d 0xe8 # CHECK: pushw %cs Index: test/MC/X86/intel-syntax.s =================================================================== --- test/MC/X86/intel-syntax.s +++ test/MC/X86/intel-syntax.s @@ -532,14 +532,14 @@ xchg AX, [ECX] xchg [ECX], AX -// CHECK: testq (%ecx), %rax -// CHECK: testq (%ecx), %rax -// CHECK: testl (%ecx), %eax -// CHECK: testl (%ecx), %eax -// CHECK: testw (%ecx), %ax -// CHECK: testw (%ecx), %ax -// CHECK: testb (%ecx), %al -// CHECK: testb (%ecx), %al +// CHECK: testq %rax, (%ecx) +// CHECK: testq %rax, (%ecx) +// CHECK: testl %eax, (%ecx) +// CHECK: testl %eax, (%ecx) +// CHECK: testw %ax, (%ecx) +// CHECK: testw %ax, (%ecx) +// CHECK: testb %al, (%ecx) +// CHECK: testb %al, (%ecx) test RAX, [ECX] test [ECX], RAX test EAX, [ECX] Index: test/MC/X86/x86-16.s =================================================================== --- test/MC/X86/x86-16.s +++ test/MC/X86/x86-16.s @@ -406,9 +406,9 @@ // CHECK: encoding: [0x0f,0x07] testl %ecx, -24(%ebp) -// CHECK: testl -24(%ebp), %ecx +// CHECK: testl %ecx, -24(%ebp) testl -24(%ebp), %ecx -// CHECK: testl -24(%ebp), %ecx +// CHECK: testl %ecx, -24(%ebp) push %cs Index: test/MC/X86/x86-32.s =================================================================== --- test/MC/X86/x86-32.s +++ test/MC/X86/x86-32.s @@ -528,9 +528,9 @@ // rdar://8018260 testl %ecx, -24(%ebp) -// CHECK: testl -24(%ebp), %ecx +// CHECK: testl %ecx, -24(%ebp) testl -24(%ebp), %ecx -// CHECK: testl -24(%ebp), %ecx +// CHECK: testl %ecx, -24(%ebp) // rdar://8407242