Index: lib/Target/Hexagon/HexagonIntrinsics.td =================================================================== --- lib/Target/Hexagon/HexagonIntrinsics.td +++ lib/Target/Hexagon/HexagonIntrinsics.td @@ -390,6 +390,28 @@ let Inst{12-8} = Rtt; } +class T_XTYPE_Vect_acc < string opc, bits<3> MajOp, bits<3> MinOp, bit isConj, + Intrinsic IntID > + : MInst <(outs DoubleRegs:$Rdd), + (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt), + "$Rdd += "#opc#"($Rss, $Rtt"#!if(isConj,"*)",")"), + [(set DoubleRegs:$Rdd, + (IntID DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt))], + "$dst2 = $Rdd",M_tc_3x_SLOT23 > { + bits<5> Rdd; + bits<5> Rss; + bits<5> Rtt; + + let IClass = 0b1110; + + let Inst{27-24} = 0b1010; + let Inst{23-21} = MajOp; + let Inst{7-5} = MinOp; + let Inst{4-0} = Rdd; + let Inst{20-16} = Rss; + let Inst{12-8} = Rtt; + } + class T_XTYPE_Vect_diff < bits<3> MajOp, string opc, Intrinsic IntID > : MInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rtt, DoubleRegs:$Rss), "$Rdd = "#opc#"($Rtt, $Rss)", @@ -412,10 +434,14 @@ // Vector reduce add unsigned bytes: Rdd32=vrmpybu(Rss32,Rtt32) def HEXAGON_A2_vraddub : T_XTYPE_Vect < "vraddub", 0b010, 0b001, 0, int_hexagon_A2_vraddub>; +def HEXAGON_A2_vraddub_acc : T_XTYPE_Vect_acc + < "vraddub", 0b010, 0b001, 0, int_hexagon_A2_vraddub_acc>; // Vector sum of absolute differences unsigned bytes: Rdd=vrsadub(Rss,Rtt) def HEXAGON_A2_vrsadub : T_XTYPE_Vect < "vrsadub", 0b010, 0b010, 0, int_hexagon_A2_vrsadub>; +def HEXAGON_A2_vrsadub_acc : T_XTYPE_Vect_acc + < "vrsadub", 0b010, 0b010, 0, int_hexagon_A2_vrsadub_acc>; // Vector absolute difference: Rdd=vabsdiffh(Rtt,Rss) def HEXAGON_M2_vabsdiffh : @@ -426,19 +452,146 @@ T_XTYPE_Vect_diff < 0b001, "vabsdiffw", int_hexagon_M2_vabsdiffw>; // Vector reduce complex multiply real or imaginary: -// Rdd=vrcmpy[ir](Rss,Rtt[*]) +// Rdd[+]=vrcmpy[ir](Rss,Rtt[*]) def HEXAGON_M2_vrcmpyi_s0 : T_XTYPE_Vect < "vrcmpyi", 0b000, 0b000, 0, int_hexagon_M2_vrcmpyi_s0>; def HEXAGON_M2_vrcmpyi_s0c : T_XTYPE_Vect < "vrcmpyi", 0b010, 0b000, 1, int_hexagon_M2_vrcmpyi_s0c>; +def HEXAGON_M2_vrcmaci_s0 : T_XTYPE_Vect_acc + < "vrcmpyi", 0b000, 0b000, 0, int_hexagon_M2_vrcmaci_s0>; +def HEXAGON_M2_vrcmaci_s0c : T_XTYPE_Vect_acc + < "vrcmpyi", 0b010, 0b000, 1, int_hexagon_M2_vrcmaci_s0c>; + def HEXAGON_M2_vrcmpyr_s0 : T_XTYPE_Vect < "vrcmpyr", 0b000, 0b001, 0, int_hexagon_M2_vrcmpyr_s0>; def HEXAGON_M2_vrcmpyr_s0c : T_XTYPE_Vect < "vrcmpyr", 0b011, 0b001, 1, int_hexagon_M2_vrcmpyr_s0c>; +def HEXAGON_M2_vrcmacr_s0 : T_XTYPE_Vect_acc + < "vrcmpyr", 0b000, 0b001, 0, int_hexagon_M2_vrcmacr_s0>; +def HEXAGON_M2_vrcmacr_s0c : T_XTYPE_Vect_acc + < "vrcmpyr", 0b011, 0b001, 1, int_hexagon_M2_vrcmacr_s0c>; // Vector reduce multiply halfwords: Rdd=vrmpyh(Rss,Rtt) +// Rdd[+]=vrmpyh(Rss,Rtt) def HEXAGON_M2_vrmpy_s0 : T_XTYPE_Vect < "vrmpyh", 0b000, 0b010, 0, int_hexagon_M2_vrmpy_s0>; +def HEXAGON_M2_vrmac_s0 : T_XTYPE_Vect_acc + < "vrmpyh", 0b000, 0b010, 0, int_hexagon_M2_vrmac_s0>; + +//===----------------------------------------------------------------------===// +// Template Class -- Vector Multipy with accumulation. +// Used for complex multiply real or imaginary, dual multiply and even halfwords +//===----------------------------------------------------------------------===// +let Defs = [USR] in +class T_M2_vmpy_acc_sat < string opc, bits<3> MajOp, bits<3> MinOp, + bit hasShift, bit isRnd, Intrinsic IntID > + : MInst <(outs DoubleRegs:$Rxx), + (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt), + "$Rxx += "#opc#"($Rss, $Rtt)"#!if(hasShift,":<<1","") + #!if(isRnd,":rnd","")#":sat", +// #!if(isSat,":sat",""), + [(set DoubleRegs:$Rxx, + (IntID DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt))], + "$dst2 = $Rxx",M_tc_3x_SLOT23 > { + bits<5> Rxx; + bits<5> Rss; + bits<5> Rtt; + + let IClass = 0b1110; + + let Inst{27-24} = 0b1010; + let Inst{23-21} = MajOp; + let Inst{7-5} = MinOp; + let Inst{4-0} = Rxx; + let Inst{20-16} = Rss; + let Inst{12-8} = Rtt; + } + +class T_M2_vmpy_acc < string opc, bits<3> MajOp, bits<3> MinOp, bit hasShift, + bit isRnd, Intrinsic IntID > + : MInst <(outs DoubleRegs:$Rxx), + (ins DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt), + "$Rxx += "#opc#"($Rss, $Rtt)"#!if(hasShift,":<<1","") + #!if(isRnd,":rnd",""), + [(set DoubleRegs:$Rxx, + (IntID DoubleRegs:$dst2, DoubleRegs:$Rss, DoubleRegs:$Rtt))], + "$dst2 = $Rxx",M_tc_3x_SLOT23 > { + bits<5> Rxx; + bits<5> Rss; + bits<5> Rtt; + + let IClass = 0b1110; + + let Inst{27-24} = 0b1010; + let Inst{23-21} = MajOp; + let Inst{7-5} = MinOp; + let Inst{4-0} = Rxx; + let Inst{20-16} = Rss; + let Inst{12-8} = Rtt; + } + +// Vector multiply word by signed half with accumulation +// Rxx+=vmpyw[eo]h(Rss,Rtt)[:<<1][:rnd]:sat +def HEXAGON_M2_mmacls_s1 : T_M2_vmpy_acc_sat + < "vmpyweh", 0b100, 0b101, 1, 0, int_hexagon_M2_mmacls_s1>; +def HEXAGON_M2_mmacls_s0 : T_M2_vmpy_acc_sat + < "vmpyweh", 0b000, 0b101, 0, 0, int_hexagon_M2_mmacls_s0>; +def HEXAGON_M2_mmacls_rs1 : T_M2_vmpy_acc_sat + < "vmpyweh", 0b101, 0b101, 1, 1, int_hexagon_M2_mmacls_rs1>; +def HEXAGON_M2_mmacls_rs0 : T_M2_vmpy_acc_sat + < "vmpyweh", 0b001, 0b101, 0, 1, int_hexagon_M2_mmacls_rs0>; + +def HEXAGON_M2_mmachs_s1 : T_M2_vmpy_acc_sat + < "vmpywoh", 0b100, 0b111, 1, 0, int_hexagon_M2_mmachs_s1>; +def HEXAGON_M2_mmachs_s0 : T_M2_vmpy_acc_sat + < "vmpywoh", 0b000, 0b111, 0, 0, int_hexagon_M2_mmachs_s0>; +def HEXAGON_M2_mmachs_rs1 : T_M2_vmpy_acc_sat + < "vmpywoh", 0b101, 0b111, 1, 1, int_hexagon_M2_mmachs_rs1>; +def HEXAGON_M2_mmachs_rs0 : T_M2_vmpy_acc_sat + < "vmpywoh", 0b001, 0b111, 0, 1, int_hexagon_M2_mmachs_rs0>; + +// Vector multiply word by unsigned half with accumulation +// Rxx+=vmpyw[eo]uh(Rss,Rtt)[:<<1][:rnd]:sat +def HEXAGON_M2_mmaculs_s1 : T_M2_vmpy_acc_sat + < "vmpyweuh", 0b110, 0b101, 1, 0, int_hexagon_M2_mmaculs_s1>; +def HEXAGON_M2_mmaculs_s0 : T_M2_vmpy_acc_sat + < "vmpyweuh", 0b010, 0b101, 0, 0, int_hexagon_M2_mmaculs_s0>; +def HEXAGON_M2_mmaculs_rs1 : T_M2_vmpy_acc_sat + < "vmpyweuh", 0b111, 0b101, 1, 1, int_hexagon_M2_mmaculs_rs1>; +def HEXAGON_M2_mmaculs_rs0 : T_M2_vmpy_acc_sat + < "vmpyweuh", 0b011, 0b101, 0, 1, int_hexagon_M2_mmaculs_rs0>; + +def HEXAGON_M2_mmacuhs_s1 : T_M2_vmpy_acc_sat + < "vmpywouh", 0b110, 0b111, 1, 0, int_hexagon_M2_mmacuhs_s1>; +def HEXAGON_M2_mmacuhs_s0 : T_M2_vmpy_acc_sat + < "vmpywouh", 0b010, 0b111, 0, 0, int_hexagon_M2_mmacuhs_s0>; +def HEXAGON_M2_mmacuhs_rs1 : T_M2_vmpy_acc_sat + < "vmpywouh", 0b111, 0b111, 1, 1, int_hexagon_M2_mmacuhs_rs1>; +def HEXAGON_M2_mmacuhs_rs0 : T_M2_vmpy_acc_sat + < "vmpywouh", 0b011, 0b111, 0, 1, int_hexagon_M2_mmacuhs_rs0>; + +// Vector multiply even halfwords with accumulation +// Rxx+=vmpyeh(Rss,Rtt)[:<<1][:sat] +def HEXAGON_M2_vmac2es : T_M2_vmpy_acc + < "vmpyeh", 0b001, 0b010, 0, 0, int_hexagon_M2_vmac2es>; +def HEXAGON_M2_vmac2es_s1 : T_M2_vmpy_acc_sat + < "vmpyeh", 0b100, 0b110, 1, 0, int_hexagon_M2_vmac2es_s1>; +def HEXAGON_M2_vmac2es_s0 : T_M2_vmpy_acc_sat + < "vmpyeh", 0b000, 0b110, 0, 0, int_hexagon_M2_vmac2es_s0>; + +// Vector dual multiply with accumulation +// Rxx+=vdmpy(Rss,Rtt)[:sat] +def HEXAGON_M2_vdmacs_s1 : T_M2_vmpy_acc_sat + < "vdmpy", 0b100, 0b100, 1, 0, int_hexagon_M2_vdmacs_s1>; +def HEXAGON_M2_vdmacs_s0 : T_M2_vmpy_acc_sat + < "vdmpy", 0b000, 0b100, 0, 0, int_hexagon_M2_vdmacs_s0>; + +// Vector complex multiply real or imaginary with accumulation +// Rxx+=vcmpy[ir](Rss,Rtt):sat +def HEXAGON_M2_vcmac_s0_sat_r : T_M2_vmpy_acc_sat + < "vcmpyr", 0b001, 0b100, 0, 0, int_hexagon_M2_vcmac_s0_sat_r>; +def HEXAGON_M2_vcmac_s0_sat_i : T_M2_vmpy_acc_sat + < "vcmpyi", 0b010, 0b100, 0, 0, int_hexagon_M2_vcmac_s0_sat_i>; // // ALU 32 types. @@ -1499,67 +1652,6 @@ DoubleRegs:$src2))], "$dst2 = $dst">; -class di_MInst_dididi_acc_rnd_sat - : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1, - DoubleRegs:$src2), - !strconcat("$dst += ", - !strconcat(opc , "($src1, $src2):rnd:sat")), - [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, - DoubleRegs:$src1, - DoubleRegs:$src2))], - "$dst2 = $dst">; - -class di_MInst_dididi_acc_s1 - : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, - DoubleRegs:$src1, - DoubleRegs:$src2), - !strconcat("$dst += ", - !strconcat(opc , "($src1, $src2):<<1")), - [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, - DoubleRegs:$src1, - DoubleRegs:$src2))], - "$dst2 = $dst">; - - -class di_MInst_dididi_acc_s1_sat - : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, - DoubleRegs:$src1, - DoubleRegs:$src2), - !strconcat("$dst += ", - !strconcat(opc , "($src1, $src2):<<1:sat")), - [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, - DoubleRegs:$src1, - DoubleRegs:$src2))], - "$dst2 = $dst">; - -class di_MInst_dididi_acc_s1_rnd_sat - : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1, - DoubleRegs:$src2), - !strconcat("$dst += ", - !strconcat(opc , "($src1, $src2):<<1:rnd:sat")), - [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, - DoubleRegs:$src1, - DoubleRegs:$src2))], - "$dst2 = $dst">; - -class di_MInst_dididi_acc - : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1, - DoubleRegs:$src2), - !strconcat("$dst += ", !strconcat(opc , "($src1, $src2)")), - [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, - DoubleRegs:$src1, - DoubleRegs:$src2))], - "$dst2 = $dst">; - -class di_MInst_dididi_acc_conj - : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1, - DoubleRegs:$src2), - !strconcat("$dst += ", !strconcat(opc , "($src1, $src2*)")), - [(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, - DoubleRegs:$src1, - DoubleRegs:$src2))], - "$dst2 = $dst">; - class di_MInst_disisi_acc_hh : MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, IntRegs:$src1, IntRegs:$src2), @@ -2279,24 +2371,6 @@ def HEXAGON_M2_cmpyrsc_s1: si_MInst_sisi_s1_rnd_sat_conj <"cmpy", int_hexagon_M2_cmpyrsc_s1>; -//MTYPE / COMPLEX / Vector complex multiply real or imaginary. - -def HEXAGON_M2_vcmac_s0_sat_i: - di_MInst_dididi_acc_sat <"vcmpyi", int_hexagon_M2_vcmac_s0_sat_i>; -def HEXAGON_M2_vcmac_s0_sat_r: - di_MInst_dididi_acc_sat <"vcmpyr", int_hexagon_M2_vcmac_s0_sat_r>; - -def HEXAGON_M2_vrcmaci_s0: - di_MInst_dididi_acc <"vrcmpyi", int_hexagon_M2_vrcmaci_s0>; -def HEXAGON_M2_vrcmacr_s0: - di_MInst_dididi_acc <"vrcmpyr", int_hexagon_M2_vrcmacr_s0>; - -def HEXAGON_M2_vrcmaci_s0c: - di_MInst_dididi_acc_conj <"vrcmpyi", int_hexagon_M2_vrcmaci_s0c>; -def HEXAGON_M2_vrcmacr_s0c: - di_MInst_dididi_acc_conj <"vrcmpyr", int_hexagon_M2_vrcmacr_s0c>; - - /******************************************************************** * MTYPE/MPYH * *********************************************************************/ @@ -2320,46 +2394,6 @@ def HEXAGON_M2_macsin: si_MInst_sisiu8_nac <"mpyi", int_hexagon_M2_macsin>; -// MTYPE / MPYH / Multiply word by half (32x16). -//Rdd[+]=vmpywoh(Rss,Rtt)[:<<1][:rnd][:sat] -//Rdd[+]=vmpyweh(Rss,Rtt)[:<<1][:rnd][:sat] -def HEXAGON_M2_mmacls_rs1: - di_MInst_dididi_acc_s1_rnd_sat <"vmpyweh", int_hexagon_M2_mmacls_rs1>; -def HEXAGON_M2_mmacls_s1: - di_MInst_dididi_acc_s1_sat <"vmpyweh", int_hexagon_M2_mmacls_s1>; -def HEXAGON_M2_mmacls_rs0: - di_MInst_dididi_acc_rnd_sat <"vmpyweh", int_hexagon_M2_mmacls_rs0>; -def HEXAGON_M2_mmacls_s0: - di_MInst_dididi_acc_sat <"vmpyweh", int_hexagon_M2_mmacls_s0>; -def HEXAGON_M2_mmachs_rs1: - di_MInst_dididi_acc_s1_rnd_sat <"vmpywoh", int_hexagon_M2_mmachs_rs1>; -def HEXAGON_M2_mmachs_s1: - di_MInst_dididi_acc_s1_sat <"vmpywoh", int_hexagon_M2_mmachs_s1>; -def HEXAGON_M2_mmachs_rs0: - di_MInst_dididi_acc_rnd_sat <"vmpywoh", int_hexagon_M2_mmachs_rs0>; -def HEXAGON_M2_mmachs_s0: - di_MInst_dididi_acc_sat <"vmpywoh", int_hexagon_M2_mmachs_s0>; - -// MTYPE / MPYH / Multiply word by unsigned half (32x16). -//Rdd[+]=vmpywouh(Rss,Rtt)[:<<1][:rnd][:sat] -//Rdd[+]=vmpyweuh(Rss,Rtt)[:<<1][:rnd][:sat] -def HEXAGON_M2_mmaculs_rs1: - di_MInst_dididi_acc_s1_rnd_sat <"vmpyweuh", int_hexagon_M2_mmaculs_rs1>; -def HEXAGON_M2_mmaculs_s1: - di_MInst_dididi_acc_s1_sat <"vmpyweuh", int_hexagon_M2_mmaculs_s1>; -def HEXAGON_M2_mmaculs_rs0: - di_MInst_dididi_acc_rnd_sat <"vmpyweuh", int_hexagon_M2_mmaculs_rs0>; -def HEXAGON_M2_mmaculs_s0: - di_MInst_dididi_acc_sat <"vmpyweuh", int_hexagon_M2_mmaculs_s0>; -def HEXAGON_M2_mmacuhs_rs1: - di_MInst_dididi_acc_s1_rnd_sat <"vmpywouh", int_hexagon_M2_mmacuhs_rs1>; -def HEXAGON_M2_mmacuhs_s1: - di_MInst_dididi_acc_s1_sat <"vmpywouh", int_hexagon_M2_mmacuhs_s1>; -def HEXAGON_M2_mmacuhs_rs0: - di_MInst_dididi_acc_rnd_sat <"vmpywouh", int_hexagon_M2_mmacuhs_rs0>; -def HEXAGON_M2_mmacuhs_s0: - di_MInst_dididi_acc_sat <"vmpywouh", int_hexagon_M2_mmacuhs_s0>; - // MTYPE / MPYH / Multiply and use upper result. def HEXAGON_M2_hmmpyh_rs1: si_MInst_sisi_h_s1_rnd_sat <"mpy", int_hexagon_M2_hmmpyh_rs1>; @@ -2530,24 +2564,10 @@ /******************************************************************** -* MTYPE/VB * -*********************************************************************/ - -def HEXAGON_A2_vraddub_acc: - di_MInst_dididi_acc <"vraddub", int_hexagon_A2_vraddub_acc>; - -def HEXAGON_A2_vrsadub_acc: - di_MInst_dididi_acc <"vrsadub", int_hexagon_A2_vrsadub_acc>; - -/******************************************************************** * MTYPE/VH * *********************************************************************/ // MTYPE / VH / Vector dual multiply. -def HEXAGON_M2_vdmacs_s1: - di_MInst_dididi_acc_s1_sat <"vdmpy", int_hexagon_M2_vdmacs_s1>; -def HEXAGON_M2_vdmacs_s0: - di_MInst_dididi_acc_sat <"vdmpy", int_hexagon_M2_vdmacs_s0>; // MTYPE / VH / Vector dual multiply with round and pack. def HEXAGON_M2_vdmpyrs_s0: @@ -2556,13 +2576,6 @@ si_MInst_didi_s1_rnd_sat <"vdmpy", int_hexagon_M2_vdmpyrs_s1>; // MTYPE / VH / Vector multiply even halfwords. -def HEXAGON_M2_vmac2es: - di_MInst_dididi_acc <"vmpyeh", int_hexagon_M2_vmac2es>; -def HEXAGON_M2_vmac2es_s1: - di_MInst_dididi_acc_s1_sat <"vmpyeh", int_hexagon_M2_vmac2es_s1>; -def HEXAGON_M2_vmac2es_s0: - di_MInst_dididi_acc_sat <"vmpyeh", int_hexagon_M2_vmac2es_s0>; - // MTYPE / VH / Vector multiply halfwords. def HEXAGON_M2_vmpy2s_s0: di_MInst_sisi_sat <"vmpyh", int_hexagon_M2_vmpy2s_s0>; @@ -2581,11 +2594,6 @@ def HEXAGON_M2_vmpy2s_s1pack: si_MInst_sisi_s1_rnd_sat <"vmpyh", int_hexagon_M2_vmpy2s_s1pack>; -// MTYPE / VH / Vector reduce multiply halfwords. -def HEXAGON_M2_vrmac_s0: - di_MInst_dididi_acc <"vrmpyh", int_hexagon_M2_vrmac_s0>; - - /******************************************************************** * STYPE/ALU * *********************************************************************/ Index: lib/Target/Hexagon/HexagonIntrinsicsV4.td =================================================================== --- lib/Target/Hexagon/HexagonIntrinsicsV4.td +++ lib/Target/Hexagon/HexagonIntrinsicsV4.td @@ -25,6 +25,18 @@ T_M2_vmpy < "vrmpywoh", 0b001, 0b010, 0, 0, 0, int_hexagon_M4_vrmpyoh_s0>; def HEXAGON_M4_vrmpyoh_s1 : T_M2_vmpy < "vrmpywoh", 0b101, 0b010, 1, 0, 0, int_hexagon_M4_vrmpyoh_s1>; + +//Rdd+=vrmpyweh(Rss,Rtt)[:<<1] +def HEXAGON_M4_vrmpyeh_acc_s0 : T_M2_vmpy_acc + < "vrmpyweh", 0b001, 0b110, 0, 0, int_hexagon_M4_vrmpyeh_acc_s0>; +def HEXAGON_M4_vrmpyeh_acc_s1 : T_M2_vmpy_acc + < "vrmpyweh", 0b101, 0b110, 1, 0, int_hexagon_M4_vrmpyeh_acc_s1>; + +//Rdd=vrmpywoh(Rss,Rtt)[:<<1] +def HEXAGON_M4_vrmpyoh_acc_s0 : T_M2_vmpy_acc + < "vrmpywoh", 0b011, 0b110, 0, 0, int_hexagon_M4_vrmpyoh_acc_s0>; +def HEXAGON_M4_vrmpyoh_acc_s1 : T_M2_vmpy_acc + < "vrmpywoh", 0b111, 0b110, 1, 0, int_hexagon_M4_vrmpyoh_acc_s1>; } // Index: lib/Target/Hexagon/HexagonIntrinsicsV5.td =================================================================== --- lib/Target/Hexagon/HexagonIntrinsicsV5.td +++ lib/Target/Hexagon/HexagonIntrinsicsV5.td @@ -8,18 +8,20 @@ //===----------------------------------------------------------------------===// //Rdd[+]=vrmpybsu(Rss,Rtt) -let Predicates = [HasV5T], validSubTargets = HasV5SubT in +let Predicates = [HasV5T], validSubTargets = HasV5SubT in { def HEXAGON_M5_vrmpybsu : T_XTYPE_Vect < "vrmpybsu", 0b110, 0b001, 0, int_hexagon_M5_vrmpybsu>; def HEXAGON_M5_vrmacbsu : T_XTYPE_Vect_acc < "vrmpybsu", 0b110, 0b001, 0, int_hexagon_M5_vrmacbsu>; +} //Rdd[+]=vrmpybu(Rss,Rtt) -let Predicates = [HasV5T], validSubTargets = HasV5SubT in +let Predicates = [HasV5T], validSubTargets = HasV5SubT in { def HEXAGON_M5_vrmpybuu : T_XTYPE_Vect < "vrmpybu", 0b100, 0b001, 0, int_hexagon_M5_vrmpybuu>; def HEXAGON_M5_vrmacbuu : T_XTYPE_Vect_acc < "vrmpybu", 0b100, 0b001, 0, int_hexagon_M5_vrmacbuu>; +} class sf_SInst_sf : SInst<(outs IntRegs:$dst), (ins IntRegs:$src1), @@ -250,10 +252,6 @@ qi_SInst_qiqi <"fastcorner9", int_hexagon_C4_fastcorner9>; def HEXAGON_C4_fastcorner9_not: qi_SInst_qiqi <"!fastcorner9", int_hexagon_C4_fastcorner9_not>; -def HEXAGON_M5_vrmacbuu: - di_MInst_dididi_acc <"vrmpybu", int_hexagon_M5_vrmacbuu>; -def HEXAGON_M5_vrmacbsu: - di_MInst_dididi_acc <"vrmpybsu", int_hexagon_M5_vrmacbsu>; def HEXAGON_M5_vmpybuu: di_MInst_sisi <"vmpybu", int_hexagon_M5_vmpybuu>; def HEXAGON_M5_vmpybsu: Index: test/CodeGen/Hexagon/intrinsics-vmpy-acc.ll =================================================================== --- /dev/null +++ test/CodeGen/Hexagon/intrinsics-vmpy-acc.ll @@ -0,0 +1,448 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s + +; Check that these intrinsics are lowered to the right instructions. + +@c = external global i64 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}vraddub(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}) + +define void @test1(i64 %a1, i64 %b1) #0 { +entry: + %0 = load i64* @c, align 8, !tbaa !1 + %1 = tail call i64 @llvm.hexagon.A2.vraddub.acc(i64 %0, i64 %a1, i64 %b1) + store i64 %1, i64* @c, align 8, !tbaa !1 + ret void +} + +declare i64 @llvm.hexagon.A2.vraddub.acc(i64, i64, i64) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}vrsadub(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}) + +define void @test2(i64 %a2, i64 %b2) #0 { +entry: + %0 = load i64* @c, align 8, !tbaa !1 + %1 = tail call i64 @llvm.hexagon.A2.vrsadub.acc(i64 %0, i64 %a2, i64 %b2) + store i64 %1, i64* @c, align 8, !tbaa !1 + ret void +} + +declare i64 @llvm.hexagon.A2.vrsadub.acc(i64, i64, i64) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}vrcmpyi(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}) + +define void @test3(i64 %a3, i64 %b3) #0 { +entry: + %0 = load i64* @c, align 8, !tbaa !1 + %1 = tail call i64 @llvm.hexagon.M2.vrcmaci.s0(i64 %0, i64 %a3, i64 %b3) + store i64 %1, i64* @c, align 8, !tbaa !1 + ret void +} + +declare i64 @llvm.hexagon.M2.vrcmaci.s0(i64, i64, i64) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}vrcmpyi(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}*) + +define void @test4(i64 %a4, i64 %b4) #0 { +entry: + %0 = load i64* @c, align 8, !tbaa !1 + %1 = tail call i64 @llvm.hexagon.M2.vrcmaci.s0c(i64 %0, i64 %a4, i64 %b4) + store i64 %1, i64* @c, align 8, !tbaa !1 + ret void +} + +declare i64 @llvm.hexagon.M2.vrcmaci.s0c(i64, i64, i64) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}vrcmpyr(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}) + +define void @test5(i64 %a5, i64 %b5) #0 { +entry: + %0 = load i64* @c, align 8, !tbaa !1 + %1 = tail call i64 @llvm.hexagon.M2.vrcmacr.s0(i64 %0, i64 %a5, i64 %b5) + store i64 %1, i64* @c, align 8, !tbaa !1 + ret void +} + +declare i64 @llvm.hexagon.M2.vrcmacr.s0(i64, i64, i64) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}vrcmpyr(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}*) + +define void @test6(i64 %a6, i64 %b6) #0 { +entry: + %0 = load i64* @c, align 8, !tbaa !1 + %1 = tail call i64 @llvm.hexagon.M2.vrcmacr.s0c(i64 %0, i64 %a6, i64 %b6) + store i64 %1, i64* @c, align 8, !tbaa !1 + ret void +} + +declare i64 @llvm.hexagon.M2.vrcmacr.s0c(i64, i64, i64) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}vrmpyh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}) + +define void @test7(i64 %a7, i64 %b7) #0 { +entry: + %0 = load i64* @c, align 8, !tbaa !1 + %1 = tail call i64 @llvm.hexagon.M2.vrmac.s0(i64 %0, i64 %a7, i64 %b7) + store i64 %1, i64* @c, align 8, !tbaa !1 + ret void +} + +declare i64 @llvm.hexagon.M2.vrmac.s0(i64, i64, i64) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}vmpyweh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):<<1:sat + +define void @test8(i64 %a8, i64 %b8) #0 { +entry: + %0 = load i64* @c, align 8, !tbaa !1 + %1 = tail call i64 @llvm.hexagon.M2.mmacls.s1(i64 %0, i64 %a8, i64 %b8) + store i64 %1, i64* @c, align 8, !tbaa !1 + ret void +} + +declare i64 @llvm.hexagon.M2.mmacls.s1(i64, i64, i64) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}vmpyweh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):sat + +define void @test9(i64 %a9, i64 %b9) #0 { +entry: + %0 = load i64* @c, align 8, !tbaa !1 + %1 = tail call i64 @llvm.hexagon.M2.mmacls.s0(i64 %0, i64 %a9, i64 %b9) + store i64 %1, i64* @c, align 8, !tbaa !1 + ret void +} + +declare i64 @llvm.hexagon.M2.mmacls.s0(i64, i64, i64) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}vmpyweh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):<<1:rnd:sat + +define void @test10(i64 %a10, i64 %b10) #0 { +entry: + %0 = load i64* @c, align 8, !tbaa !1 + %1 = tail call i64 @llvm.hexagon.M2.mmacls.rs1(i64 %0, i64 %a10, i64 %b10) + store i64 %1, i64* @c, align 8, !tbaa !1 + ret void +} + +declare i64 @llvm.hexagon.M2.mmacls.rs1(i64, i64, i64) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}vmpyweh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):rnd:sat + +define void @test11(i64 %a11, i64 %b11) #0 { +entry: + %0 = load i64* @c, align 8, !tbaa !1 + %1 = tail call i64 @llvm.hexagon.M2.mmacls.rs0(i64 %0, i64 %a11, i64 %b11) + store i64 %1, i64* @c, align 8, !tbaa !1 + ret void +} + +declare i64 @llvm.hexagon.M2.mmacls.rs0(i64, i64, i64) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}vmpywoh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):<<1:sat + +define void @test12(i64 %a12, i64 %b12) #0 { +entry: + %0 = load i64* @c, align 8, !tbaa !1 + %1 = tail call i64 @llvm.hexagon.M2.mmachs.s1(i64 %0, i64 %a12, i64 %b12) + store i64 %1, i64* @c, align 8, !tbaa !1 + ret void +} + +declare i64 @llvm.hexagon.M2.mmachs.s1(i64, i64, i64) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}vmpywoh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):sat + +define void @test13(i64 %a13, i64 %b13) #0 { +entry: + %0 = load i64* @c, align 8, !tbaa !1 + %1 = tail call i64 @llvm.hexagon.M2.mmachs.s0(i64 %0, i64 %a13, i64 %b13) + store i64 %1, i64* @c, align 8, !tbaa !1 + ret void +} + +declare i64 @llvm.hexagon.M2.mmachs.s0(i64, i64, i64) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}vmpywoh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):<<1:rnd:sat + +define void @test14(i64 %a14, i64 %b14) #0 { +entry: + %0 = load i64* @c, align 8, !tbaa !1 + %1 = tail call i64 @llvm.hexagon.M2.mmachs.rs1(i64 %0, i64 %a14, i64 %b14) + store i64 %1, i64* @c, align 8, !tbaa !1 + ret void +} + +declare i64 @llvm.hexagon.M2.mmachs.rs1(i64, i64, i64) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}vmpywoh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):rnd:sat + +define void @test15(i64 %a15, i64 %b15) #0 { +entry: + %0 = load i64* @c, align 8, !tbaa !1 + %1 = tail call i64 @llvm.hexagon.M2.mmachs.rs0(i64 %0, i64 %a15, i64 %b15) + store i64 %1, i64* @c, align 8, !tbaa !1 + ret void +} + +declare i64 @llvm.hexagon.M2.mmachs.rs0(i64, i64, i64) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}vmpyweuh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):<<1:sat + +define void @test16(i64 %a16, i64 %b16) #0 { +entry: + %0 = load i64* @c, align 8, !tbaa !1 + %1 = tail call i64 @llvm.hexagon.M2.mmaculs.s1(i64 %0, i64 %a16, i64 %b16) + store i64 %1, i64* @c, align 8, !tbaa !1 + ret void +} + +declare i64 @llvm.hexagon.M2.mmaculs.s1(i64, i64, i64) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}vmpyweuh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):sat + +define void @test17(i64 %a17, i64 %b17) #0 { +entry: + %0 = load i64* @c, align 8, !tbaa !1 + %1 = tail call i64 @llvm.hexagon.M2.mmaculs.s0(i64 %0, i64 %a17, i64 %b17) + store i64 %1, i64* @c, align 8, !tbaa !1 + ret void +} + +declare i64 @llvm.hexagon.M2.mmaculs.s0(i64, i64, i64) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}vmpyweuh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):<<1:rnd:sat + +define void @test18(i64 %a18, i64 %b18) #0 { +entry: + %0 = load i64* @c, align 8, !tbaa !1 + %1 = tail call i64 @llvm.hexagon.M2.mmaculs.rs1(i64 %0, i64 %a18, i64 %b18) + store i64 %1, i64* @c, align 8, !tbaa !1 + ret void +} + +declare i64 @llvm.hexagon.M2.mmaculs.rs1(i64, i64, i64) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}vmpyweuh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):rnd:sat + +define void @test19(i64 %a19, i64 %b19) #0 { +entry: + %0 = load i64* @c, align 8, !tbaa !1 + %1 = tail call i64 @llvm.hexagon.M2.mmaculs.rs0(i64 %0, i64 %a19, i64 %b19) + store i64 %1, i64* @c, align 8, !tbaa !1 + ret void +} + +declare i64 @llvm.hexagon.M2.mmaculs.rs0(i64, i64, i64) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}vmpywouh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):<<1:sat + +define void @test20(i64 %a20, i64 %b20) #0 { +entry: + %0 = load i64* @c, align 8, !tbaa !1 + %1 = tail call i64 @llvm.hexagon.M2.mmacuhs.s1(i64 %0, i64 %a20, i64 %b20) + store i64 %1, i64* @c, align 8, !tbaa !1 + ret void +} + +declare i64 @llvm.hexagon.M2.mmacuhs.s1(i64, i64, i64) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}vmpywouh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):sat + +define void @test21(i64 %a21, i64 %b21) #0 { +entry: + %0 = load i64* @c, align 8, !tbaa !1 + %1 = tail call i64 @llvm.hexagon.M2.mmacuhs.s0(i64 %0, i64 %a21, i64 %b21) + store i64 %1, i64* @c, align 8, !tbaa !1 + ret void +} + +declare i64 @llvm.hexagon.M2.mmacuhs.s0(i64, i64, i64) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}vmpywouh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):<<1:rnd:sat + +define void @test22(i64 %a22, i64 %b22) #0 { +entry: + %0 = load i64* @c, align 8, !tbaa !1 + %1 = tail call i64 @llvm.hexagon.M2.mmacuhs.rs1(i64 %0, i64 %a22, i64 %b22) + store i64 %1, i64* @c, align 8, !tbaa !1 + ret void +} + +declare i64 @llvm.hexagon.M2.mmacuhs.rs1(i64, i64, i64) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}vmpywouh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):rnd:sat + +define void @test23(i64 %a23, i64 %b23) #0 { +entry: + %0 = load i64* @c, align 8, !tbaa !1 + %1 = tail call i64 @llvm.hexagon.M2.mmacuhs.rs0(i64 %0, i64 %a23, i64 %b23) + store i64 %1, i64* @c, align 8, !tbaa !1 + ret void +} + +declare i64 @llvm.hexagon.M2.mmacuhs.rs0(i64, i64, i64) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}vmpyeh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}) + +define void @test24(i64 %a24, i64 %b24) #0 { +entry: + %0 = load i64* @c, align 8, !tbaa !1 + %1 = tail call i64 @llvm.hexagon.M2.vmac2es(i64 %0, i64 %a24, i64 %b24) + store i64 %1, i64* @c, align 8, !tbaa !1 + ret void +} + +declare i64 @llvm.hexagon.M2.vmac2es(i64, i64, i64) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}vmpyeh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):<<1:sat + +define void @test25(i64 %a25, i64 %b25) #0 { +entry: + %0 = load i64* @c, align 8, !tbaa !1 + %1 = tail call i64 @llvm.hexagon.M2.vmac2es.s1(i64 %0, i64 %a25, i64 %b25) + store i64 %1, i64* @c, align 8, !tbaa !1 + ret void +} + +declare i64 @llvm.hexagon.M2.vmac2es.s1(i64, i64, i64) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}vmpyeh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):sat + +define void @test26(i64 %a26, i64 %b26) #0 { +entry: + %0 = load i64* @c, align 8, !tbaa !1 + %1 = tail call i64 @llvm.hexagon.M2.vmac2es.s0(i64 %0, i64 %a26, i64 %b26) + store i64 %1, i64* @c, align 8, !tbaa !1 + ret void +} + +declare i64 @llvm.hexagon.M2.vmac2es.s0(i64, i64, i64) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}vdmpy(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):<<1:sat + +define void @test27(i64 %a27, i64 %b27) #0 { +entry: + %0 = load i64* @c, align 8, !tbaa !1 + %1 = tail call i64 @llvm.hexagon.M2.vdmacs.s1(i64 %0, i64 %a27, i64 %b27) + store i64 %1, i64* @c, align 8, !tbaa !1 + ret void +} + +declare i64 @llvm.hexagon.M2.vdmacs.s1(i64, i64, i64) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}vdmpy(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):sat + +define void @test28(i64 %a28, i64 %b28) #0 { +entry: + %0 = load i64* @c, align 8, !tbaa !1 + %1 = tail call i64 @llvm.hexagon.M2.vdmacs.s0(i64 %0, i64 %a28, i64 %b28) + store i64 %1, i64* @c, align 8, !tbaa !1 + ret void +} + +declare i64 @llvm.hexagon.M2.vdmacs.s0(i64, i64, i64) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}vcmpyr(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):sat + +define void @test29(i64 %a29, i64 %b29) #0 { +entry: + %0 = load i64* @c, align 8, !tbaa !1 + %1 = tail call i64 @llvm.hexagon.M2.vcmac.s0.sat.r(i64 %0, i64 %a29, i64 %b29) + store i64 %1, i64* @c, align 8, !tbaa !1 + ret void +} + +declare i64 @llvm.hexagon.M2.vcmac.s0.sat.r(i64, i64, i64) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}vcmpyi(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):sat + +define void @test30(i64 %a30, i64 %b30) #0 { +entry: + %0 = load i64* @c, align 8, !tbaa !1 + %1 = tail call i64 @llvm.hexagon.M2.vcmac.s0.sat.i(i64 %0, i64 %a30, i64 %b30) + store i64 %1, i64* @c, align 8, !tbaa !1 + ret void +} + +declare i64 @llvm.hexagon.M2.vcmac.s0.sat.i(i64, i64, i64) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}vrmpyweh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}) + +define void @test31(i64 %a31, i64 %b31) #0 { +entry: + %0 = load i64* @c, align 8, !tbaa !1 + %1 = tail call i64 @llvm.hexagon.M4.vrmpyeh.acc.s0(i64 %0, i64 %a31, i64 %b31) + store i64 %1, i64* @c, align 8, !tbaa !1 + ret void +} + +declare i64 @llvm.hexagon.M4.vrmpyeh.acc.s0(i64, i64, i64) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}vrmpyweh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):<<1 + +define void @test32(i64 %a32, i64 %b32) #0 { +entry: + %0 = load i64* @c, align 8, !tbaa !1 + %1 = tail call i64 @llvm.hexagon.M4.vrmpyeh.acc.s1(i64 %0, i64 %a32, i64 %b32) + store i64 %1, i64* @c, align 8, !tbaa !1 + ret void +} + +declare i64 @llvm.hexagon.M4.vrmpyeh.acc.s1(i64, i64, i64) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}vrmpywoh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}) + +define void @test33(i64 %a33, i64 %b33) #0 { +entry: + %0 = load i64* @c, align 8, !tbaa !1 + %1 = tail call i64 @llvm.hexagon.M4.vrmpyoh.acc.s0(i64 %0, i64 %a33, i64 %b33) + store i64 %1, i64* @c, align 8, !tbaa !1 + ret void +} + +declare i64 @llvm.hexagon.M4.vrmpyoh.acc.s0(i64, i64, i64) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}vrmpywoh(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}):<<1 + +define void @test34(i64 %a34, i64 %b34) #0 { +entry: + %0 = load i64* @c, align 8, !tbaa !1 + %1 = tail call i64 @llvm.hexagon.M4.vrmpyoh.acc.s1(i64 %0, i64 %a34, i64 %b34) + store i64 %1, i64* @c, align 8, !tbaa !1 + ret void +} + +declare i64 @llvm.hexagon.M4.vrmpyoh.acc.s1(i64, i64, i64) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}vrmpybsu(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}) + +define void @test35(i64 %a35, i64 %b35) #0 { +entry: + %0 = load i64* @c, align 8, !tbaa !1 + %1 = tail call i64 @llvm.hexagon.M5.vrmacbsu(i64 %0, i64 %a35, i64 %b35) + store i64 %1, i64* @c, align 8, !tbaa !1 + ret void +} + +declare i64 @llvm.hexagon.M5.vrmacbsu(i64, i64, i64) #1 + +; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}vrmpybu(r{{[0-9]+}}:{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}}:{{[0-9]+}}) + +define void @test36(i64 %a36, i64 %b36) #0 { +entry: + %0 = load i64* @c, align 8, !tbaa !1 + %1 = tail call i64 @llvm.hexagon.M5.vrmacbuu(i64 %0, i64 %a36, i64 %b36) + store i64 %1, i64* @c, align 8, !tbaa !1 + ret void +} + +declare i64 @llvm.hexagon.M5.vrmacbuu(i64, i64, i64) #1 + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind readnone } + +!llvm.ident = !{!0} + +!0 = metadata !{metadata !"QuIC LLVM Hexagon Clang version 7.1-internal"} +!1 = metadata !{metadata !2, metadata !2, i64 0} +!2 = metadata !{metadata !"long long", metadata !3, i64 0} +!3 = metadata !{metadata !"omnipotent char", metadata !4, i64 0} +!4 = metadata !{metadata !"Simple C/C++ TBAA"} Index: test/MC/Hexagon/vector-acc.s =================================================================== --- /dev/null +++ test/MC/Hexagon/vector-acc.s @@ -0,0 +1,112 @@ +#REQUIRES: object-emission +#This test will be enabled when assembler support has been added. + +#RUN: llvm-mc -filetype=obj %s | llvm-objdump -d - | FileCheck %s + +lr:fp+=vmpywoh(r19:18,r17:16):<<1:rnd:sat +#CHECK: eab2d0fe { r31:30 += vmpywoh(r19:18, r17:16):<<1:rnd:sat } + +r15:14+=vmpywoh(r19:18,r11:10):<<1:sat +#CHECK: ea92caee { r15:14 += vmpywoh(r19:18, r11:10):<<1:sat } + +r11:10+=vrsadub(r15:14,r15:14) +#CHECK: ea4ece4a { r11:10 += vrsadub(r15:14, r15:14) } + +r21:20+=vrmpyh(r17:16,r31:30) +#CHECK: ea10de54 { r21:20 += vrmpyh(r17:16, r31:30) } + +r15:14+=vrmpybu(r17:16,r7:6) +#CHECK: ea90c62e { r15:14 += vrmpybu(r17:16, r7:6) } + +r27:26+=vrmpybsu(r11:10,r29:28) +#CHECK: eacadc3a { r27:26 += vrmpybsu(r11:10, r29:28) } + +r31:30+=vrcmpyr(r19:18,r29:28*) +#CHECK: ea72dc3e { r31:30 += vrcmpyr(r19:18, r29:28*) } + +r9:8+=vrcmpyr(r1:0,r29:28) +#CHECK: ea00dc28 { r9:8 += vrcmpyr(r1:0, r29:28) } + +r31:30+=vrcmpyi(r19:18,r3:2*) +#CHECK: ea52c21e { r31:30 += vrcmpyi(r19:18, r3:2*) } + +r19:18+=vrcmpyi(r3:2,r5:4) +#CHECK: ea02c412 { r19:18 += vrcmpyi(r3:2, r5:4) } + +r17:16+=vraddub(lr:fp,r1:0) +#CHECK: ea5ec030 { r17:16 += vraddub(r31:30, r1:0) } + +r3:2+=vmpyweuh(r31:30,r25:24):sat +#CHECK: ea5ed8a2 { r3:2 += vmpyweuh(r31:30, r25:24):sat } + +r21:20+=vmpywouh(r29:28,r19:18):<<1:rnd:sat +#CHECK: eafcd2f4 { r21:20 += vmpywouh(r29:28, r19:18):<<1:rnd:sat } + +r13:12+=vmpywouh(r9:8,r5:4):<<1:sat +#CHECK: eac8c4ec { r13:12 += vmpywouh(r9:8, r5:4):<<1:sat } + +r27:26+=vmpyweuh(r19:18,r15:14):<<1:rnd:sat +#CHECK: eaf2ceba { r27:26 += vmpyweuh(r19:18, r15:14):<<1:rnd:sat } + +lr:fp+=vmpywouh(r9:8,r29:28):sat +#CHECK: ea48dcfe { r31:30 += vmpywouh(r9:8, r29:28):sat } + +r9:8+=vmpyweh(r23:22,r23:22):rnd:sat +#CHECK: ea36d6a8 { r9:8 += vmpyweh(r23:22, r23:22):rnd:sat } + +r9:8+=vrmpyweh(r7:6,r29:28):<<1 +#CHECK: eaa6dcc8 { r9:8 += vrmpyweh(r7:6, r29:28):<<1 } + +r31:30+=vrmpyweh(r9:8,r15:14) +#CHECK: ea28cede { r31:30 += vrmpyweh(r9:8, r15:14) } + +r11:10+=vrmpywoh(r9:8,r25:24):<<1 +#CHECK: eae8d8ca { r11:10 += vrmpywoh(r9:8, r25:24):<<1 } + +r13:12+=vmpyweuh(r1:0,r25:24):<<1:sat +#CHECK: eac0d8ac { r13:12 += vmpyweuh(r1:0, r25:24):<<1:sat } + +lr:fp+=vdmpy(r1:0,r23:22):<<1:sat +#CHECK: ea80d69e { r31:30 += vdmpy(r1:0, r23:22):<<1:sat } + +r7:6+=vcmpyr(r5:4,r9:8):sat +#CHECK: ea24c886 { r7:6 += vcmpyr(r5:4, r9:8):sat } + +r19:18+=vcmpyi(r15:14,r13:12):sat +#CHECK: ea4ecc92 { r19:18 += vcmpyi(r15:14, r13:12):sat } + +r25:24+=vmpyeh(r5:4,r19:18):sat +#CHECK: ea04d2d8 { r25:24 += vmpyeh(r5:4, r19:18):sat } + +r5:4+=vmpyeh(r17:16,r29:28):<<1:sat +#CHECK: ea90dcc4 { r5:4 += vmpyeh(r17:16, r29:28):<<1:sat } + +r19:18+=vmpyeh(r3:2,r15:14) +#CHECK: ea22ce52 { r19:18 += vmpyeh(r3:2, r15:14) } + +r15:14+=vdmpy(r13:12,r13:12):sat +#CHECK: ea0ccc8e { r15:14 += vdmpy(r13:12, r13:12):sat } + +r11:10+=vmpyweh(r23:22,r21:20):<<1:sat +#CHECK: ea96d4aa { r11:10 += vmpyweh(r23:22, r21:20):<<1:sat } + +r9:8+=vmpyweh(r19:18,r11:10):<<1:rnd:sat +#CHECK: eab2caa8 { r9:8 += vmpyweh(r19:18, r11:10):<<1:rnd:sat } + +r5:4+=vmpywouh(r27:26,r7:6):rnd:sat +#CHECK: ea7ac6e4 { r5:4 += vmpywouh(r27:26, r7:6):rnd:sat } + +r21:20+=vmpywoh(r19:18,r9:8):rnd:sat +#CHECK: ea32c8f4 { r21:20 += vmpywoh(r19:18, r9:8):rnd:sat } + +r21:20+=vmpywoh(r19:18,r1:0):sat +#CHECK: ea12c0f4 { r21:20 += vmpywoh(r19:18, r1:0):sat } + +r21:20+=vmpyweuh(r25:24,r23:22):rnd:sat +#CHECK: ea78d6b4 { r21:20 += vmpyweuh(r25:24, r23:22):rnd:sat } + +r5:4+=vmpyweh(r31:30,r11:10):sat +#CHECK: ea1ecaa4 { r5:4 += vmpyweh(r31:30, r11:10):sat } + +r13:12+=vrmpywoh(r9:8,r9:8) +#CHECK: ea68c8cc { r13:12 += vrmpywoh(r9:8, r9:8) }