Index: llvm/trunk/lib/Target/Mips/MicroMipsDSPInstrInfo.td
===================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsDSPInstrInfo.td
+++ llvm/trunk/lib/Target/Mips/MicroMipsDSPInstrInfo.td
@@ -415,6 +415,13 @@
 class BPOSGE32_MM_DESC : BPOSGE32_DESC_BASE<"bposge32", brtarget_mm,
                                             NoItinerary>;
 
+let DecoderNamespace = "MicroMipsDSP", Arch = "mmdsp",
+    AdditionalPredicates = [HasDSP, InMicroMips] in {
+    def LWDSP_MM : Load<"lw", DSPROpnd, null_frag, II_LW>, DspMMRel,
+                   LW_FM_MM<0x3f>;
+    def SWDSP_MM : Store<"sw", DSPROpnd, null_frag, II_SW>, DspMMRel,
+                   LW_FM_MM<0x3e>;
+}
 // Instruction defs.
 // microMIPS DSP Rev 1
 def ADDQ_PH_MM : DspMMRel, ADDQ_PH_MM_ENC, ADDQ_PH_DESC;
Index: llvm/trunk/lib/Target/Mips/MipsDSPInstrInfo.td
===================================================================
--- llvm/trunk/lib/Target/Mips/MipsDSPInstrInfo.td
+++ llvm/trunk/lib/Target/Mips/MipsDSPInstrInfo.td
@@ -1284,6 +1284,12 @@
   def STORE_CCOND_DSP : Store<"store_ccond_dsp", DSPCC>;
 }
 
+let DecoderNamespace = "MipsDSP", Arch = "dsp",
+    AdditionalPredicates = [HasDSP] in {
+  def LWDSP : Load<"lw", DSPROpnd, null_frag, II_LW>, DspMMRel, LW_FM<0x23>;
+  def SWDSP : Store<"sw", DSPROpnd, null_frag, II_SW>, DspMMRel, LW_FM<0x2b>;
+}
+
 // Pseudo CMP and PICK instructions.
 class PseudoCMP<Instruction RealInst> :
   PseudoDSP<(outs DSPCC:$cmp), (ins DSPROpnd:$rs, DSPROpnd:$rt), []>,
Index: llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cpp
===================================================================
--- llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cpp
+++ llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cpp
@@ -226,6 +226,8 @@
     Opc = Mips::SW;
   else if (Mips::HI64RegClass.hasSubClassEq(RC))
     Opc = Mips::SD;
+  else if (Mips::DSPRRegClass.hasSubClassEq(RC))
+    Opc = Mips::SWDSP;
 
   // Hi, Lo are normally caller save but they are callee save
   // for interrupt handling.
@@ -302,6 +304,8 @@
     Opc = Mips::LW;
   else if (Mips::LO64RegClass.hasSubClassEq(RC))
     Opc = Mips::LD;
+  else if (Mips::DSPRRegClass.hasSubClassEq(RC))
+    Opc = Mips::LWDSP;
 
   assert(Opc && "Register class not handled!");
 
Index: llvm/trunk/test/CodeGen/Mips/dsp-spill-reload.ll
===================================================================
--- llvm/trunk/test/CodeGen/Mips/dsp-spill-reload.ll
+++ llvm/trunk/test/CodeGen/Mips/dsp-spill-reload.ll
@@ -0,0 +1,52 @@
+; RUN: llc -march=mips -mattr=+dsp < %s -asm-show-inst -O0 | FileCheck %s \
+; RUN:   --check-prefixes=ASM,ALL
+; RUN: llc -march=mips -mattr=+dsp,+micromips < %s -O0 -filetype=obj | \
+; RUN:   llvm-objdump -d - | FileCheck %s --check-prefixes=MM-OBJ,ALL
+
+; Test that spill and reloads use the dsp "variant" instructions. We use -O0
+; to use the simple register allocator.
+
+; To test the micromips output, we have to take a round trip through the
+; object file encoder/decoder as the instruction mapping tables are used to
+; support micromips.
+
+; FIXME: We should be able to get rid of those instructions with the variable
+;        value registers.
+
+; ALL-LABEL: spill_reload:
+
+define <4 x i8>  @spill_reload(<4 x i8> %a, <4 x i8> %b, i32 %g) {
+entry:
+  %c = tail call <4 x i8> @llvm.mips.addu.qb(<4 x i8> %a, <4 x i8> %b)
+  %cond = icmp eq i32 %g, 0
+  br i1 %cond, label %true, label %end
+
+; ASM: SWDSP
+; ASM: SWDSP
+; ASM: SWDSP
+
+; MM-OBJ:   sw  ${{[0-9]+}}, {{[0-9]+}}($sp)
+; MM-OBJ:   sw  ${{[0-9]+}}, {{[0-9]+}}($sp)
+; MM-OBJ:   sw  ${{[0-9]+}}, {{[0-9]+}}($sp)
+; MM-OBJ:   sw  ${{[0-9]+}}, {{[0-9]+}}($sp)
+
+true:
+  ret <4 x i8> %c
+
+; ASM: LWDSP
+
+; MM-OBJ: lw ${{[0-9]+}}, {{[0-9]+}}($sp)
+
+end:
+  %d = tail call <4 x i8> @llvm.mips.addu.qb(<4 x i8> %c, <4 x i8> %a)
+  ret <4 x i8> %d
+
+; ASM: LWDSP
+; ASM: LWDSP
+
+; MM-OBJ: lw ${{[0-9]+}}, {{[0-9]+}}($sp)
+; MM-OBJ: lw ${{[0-9]+}}, {{[0-9]+}}($sp)
+
+}
+
+declare <4 x i8> @llvm.mips.addu.qb(<4 x i8>, <4 x i8>) nounwind