Index: lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- lib/Target/X86/X86ISelLowering.cpp
+++ lib/Target/X86/X86ISelLowering.cpp
@@ -36800,12 +36800,14 @@
     if (Size == 1) Size = 8;
     unsigned DestReg = getX86SubSuperRegisterOrZero(Res.first, Size);
     if (DestReg > 0) {
-      Res.first = DestReg;
-      Res.second = Size == 8 ? &X86::GR8RegClass
-                 : Size == 16 ? &X86::GR16RegClass
-                 : Size == 32 ? &X86::GR32RegClass
-                 : &X86::GR64RegClass;
-      assert(Res.second->contains(Res.first) && "Register in register class");
+      bool is64Bit = Subtarget.is64Bit();
+      const TargetRegisterClass *RC =
+          Size == 8 ? (is64Bit ? &X86::GR8RegClass : &X86::GR8_NOREXRegClass)
+        : Size == 16 ? (is64Bit ? &X86::GR16RegClass : &X86::GR16_NOREXRegClass)
+        : Size == 32 ? (is64Bit ? &X86::GR32RegClass : &X86::GR32_NOREXRegClass)
+        : &X86::GR64RegClass;
+      if (RC->contains(DestReg))
+        Res = std::make_pair(DestReg, RC);
     } else {
       // No register found/type mismatch.
       Res.first = 0;
Index: test/CodeGen/X86/pr29061.ll
===================================================================
--- test/CodeGen/X86/pr29061.ll
+++ test/CodeGen/X86/pr29061.ll
@@ -0,0 +1,19 @@
+; RUN: llc -mtriple i386 < %s | FileCheck %s
+
+; Previously, a reference to SIL/DIL was being emitted
+; but those aren't available unless on a 64bit mode
+
+; CHECK:  movzbl  8(%esp), %edi
+define void @t1(i8 signext %c) {
+entry:
+  tail call void asm sideeffect "", "{di},~{dirflag},~{fpsr},~{flags}"(i8 %c)
+  ret void
+}
+
+; CHECK:  movzbl  8(%esp), %esi
+define void @t2(i8 signext %c) {
+entry:
+  tail call void asm sideeffect "", "{si},~{dirflag},~{fpsr},~{flags}"(i8 %c)
+  ret void
+}
+