Index: include/llvm/Target/TargetRegisterInfo.h
===================================================================
--- include/llvm/Target/TargetRegisterInfo.h
+++ include/llvm/Target/TargetRegisterInfo.h
@@ -752,6 +752,9 @@
   virtual const RegClassWeight &getRegClassWeight(
     const TargetRegisterClass *RC) const = 0;
 
+  /// Returns size in bits of a phys/virtual/generic register.
+  unsigned getRegSizeInBits(unsigned Reg, const MachineRegisterInfo &MRI) const;
+
   /// Get the weight in units of pressure for this register unit.
   virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0;
 
Index: lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
===================================================================
--- lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
+++ lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
@@ -442,24 +442,7 @@
 unsigned RegisterBankInfo::getSizeInBits(unsigned Reg,
                                          const MachineRegisterInfo &MRI,
                                          const TargetRegisterInfo &TRI) {
-  const TargetRegisterClass *RC = nullptr;
-  if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
-    // The size is not directly available for physical registers.
-    // Instead, we need to access a register class that contains Reg and
-    // get the size of that register class.
-    RC = TRI.getMinimalPhysRegClass(Reg);
-  } else {
-    LLT Ty = MRI.getType(Reg);
-    unsigned RegSize = Ty.isValid() ? Ty.getSizeInBits() : 0;
-    // If Reg is not a generic register, query the register class to
-    // get its size.
-    if (RegSize)
-      return RegSize;
-    // Since Reg is not a generic register, it must have a register class.
-    RC = MRI.getRegClass(Reg);
-  }
-  assert(RC && "Unable to deduce the register class");
-  return TRI.getRegSizeInBits(*RC);
+  return TRI.getRegSizeInBits(Reg, MRI);
 }
 
 //------------------------------------------------------------------------------
Index: lib/CodeGen/MachineVerifier.cpp
===================================================================
--- lib/CodeGen/MachineVerifier.cpp
+++ lib/CodeGen/MachineVerifier.cpp
@@ -972,6 +972,26 @@
              MI);
     break;
   }
+  case TargetOpcode::COPY: {
+    const MachineOperand &DstOp = MI->getOperand(0);
+    const MachineOperand &SrcOp = MI->getOperand(1);
+    LLT DstTy = MRI->getType(DstOp.getReg());
+    LLT SrcTy = MRI->getType(SrcOp.getReg());
+    if (SrcTy.isValid() || DstTy.isValid()) {
+      unsigned SrcSize = TRI->getRegSizeInBits(SrcOp.getReg(), *MRI);
+      unsigned DstSize = TRI->getRegSizeInBits(DstOp.getReg(), *MRI);
+      assert(SrcSize && "Expecting size here");
+      assert(DstSize && "Expecting size here");
+      if (SrcSize != DstSize)
+        // Catch only obvious cases not involving subregs for now.
+        if (!DstOp.getSubReg() && !SrcOp.getSubReg()) {
+          report("Copy Instruction is illegal with mismatching sizes", MI);
+          errs() << "Def Size = " << DstSize << ", Src Size = " << SrcSize
+                 << "\n";
+        }
+    }
+    break;
+  }
   case TargetOpcode::STATEPOINT:
     if (!MI->getOperand(StatepointOpers::IDPos).isImm() ||
         !MI->getOperand(StatepointOpers::NBytesPos).isImm() ||
Index: lib/CodeGen/TargetRegisterInfo.cpp
===================================================================
--- lib/CodeGen/TargetRegisterInfo.cpp
+++ lib/CodeGen/TargetRegisterInfo.cpp
@@ -424,6 +424,21 @@
   return true;
 }
 
+unsigned
+TargetRegisterInfo::getRegSizeInBits(unsigned Reg,
+                                     const MachineRegisterInfo &MRI) const {
+  const TargetRegisterClass *RC = nullptr;
+  if (isPhysicalRegister(Reg))
+    RC = getMinimalPhysRegClass(Reg);
+  else
+    RC = MRI.getRegClassOrNull(Reg);
+  if (!RC) {
+    LLT Ty = MRI.getType(Reg);
+    assert(Ty.isValid() && "Expecting valid type here");
+    return Ty.getSizeInBits();
+  }
+  return getRegSizeInBits(*RC);
+}
 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
 LLVM_DUMP_METHOD
 void TargetRegisterInfo::dumpReg(unsigned Reg, unsigned SubRegIndex,
Index: test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
===================================================================
--- test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
+++ test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
@@ -90,11 +90,13 @@
 
       ; A narrow insert gets surrounded by a G_ANYEXT/G_TRUNC pair.
     ; CHECK-LABEL: name: test_inserts_4
-    ; CHECK: [[VALEXT:%[0-9]+]](s32) = G_ANYEXT %1(s8)
-    ; CHECK: [[VAL:%[0-9]+]](s32) = G_INSERT [[VALEXT]], %0(s1), 0
-    ; CHECK: %3(s8) = G_TRUNC [[VAL]](s32)
-    %0:_(s1) = COPY %w0
-    %1:_(s8) = COPY %w1
+    ; CHECK: [[VALEXT:%[0-9]+]](s32) = COPY %2(s32)
+    ; CHECK: [[VAL:%[0-9]+]](s32) = G_INSERT [[VALEXT]], %1(s1), 0
+    ; CHECK: %5(s8) = G_TRUNC [[VAL]](s32)
+    %4:_(s32) = COPY %w0
+    %0:_(s1) = G_TRUNC %4
+    %5:_(s32) = COPY %w1
+    %1:_(s8) = G_TRUNC %5
     %2:_(p0) = COPY %x2
     %3:_(s8) = G_INSERT %1(s8), %0(s1), 0
     G_STORE %3(s8), %2(p0) :: (store 1)
Index: test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
===================================================================
--- test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
+++ test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
@@ -128,20 +128,22 @@
   bb.1:
    ; CHECK-LABEL: name: legalize_phi_ptr
    ; CHECK-LABEL: bb.0:
-   ; CHECK: %0(p0) = COPY %x0
-   ; CHECK: %1(p0) = COPY %x1
-   ; CHECK: %2(s1) = COPY %w2
+   ; CHECK: [[A:%[0-9]+]](p0) = COPY %x0
+   ; CHECK: [[B:%[0-9]+]](p0) = COPY %x1
+   ; CHECK: [[CE:%[0-9]+]](s32) = COPY %w2
+   ; CHECK: [[C:%[0-9]+]](s1) = G_TRUNC [[CE]]
 
    ; CHECK-LABEL: bb.1:
    ; CHECK-LABEL: bb.2:
-   ; CHECK: %3(p0) = G_PHI %0(p0), %bb.0, %1(p0), %bb.1
+   ; CHECK: %3(p0) = G_PHI [[A]](p0), %bb.0, [[B]](p0), %bb.1
    ; CHECK: %x0 = COPY %3(p0)
     successors: %bb.2, %bb.3
     liveins: %w2, %x0, %x1
 
     %0(p0) = COPY %x0
     %1(p0) = COPY %x1
-    %2(s1) = COPY %w2
+    %4(s32) = COPY %w2
+    %2(s1) = G_TRUNC %4(s32)
     G_BRCOND %2(s1), %bb.2
     G_BR %bb.3
 
Index: test/CodeGen/AArch64/GlobalISel/localizer-in-O0-pipeline.mir
===================================================================
--- test/CodeGen/AArch64/GlobalISel/localizer-in-O0-pipeline.mir
+++ test/CodeGen/AArch64/GlobalISel/localizer-in-O0-pipeline.mir
@@ -41,15 +41,17 @@
 # CHECK-NEXT: - { id: 3, class: fpr, preferred-register: '' }
 # CHECK-NEXT: - { id: 4, class: fpr, preferred-register: '' }
 # CHECK-NEXT: - { id: 5, class: fpr, preferred-register: '' }
+# CHECK-NEXT: - { id: 6, class: gpr, preferred-register: '' }
 # The localizer will create two new values to materialize the constants.
-# OPTNONE-NEXT:  - { id: 6, class: fpr, preferred-register: '' }
 # OPTNONE-NEXT:  - { id: 7, class: fpr, preferred-register: '' }
+# OPTNONE-NEXT:  - { id: 8, class: fpr, preferred-register: '' }
   - { id: 0, class: fpr }
   - { id: 1, class: gpr }
   - { id: 2, class: fpr }
   - { id: 3, class: fpr }
   - { id: 4, class: fpr }
   - { id: 5, class: fpr }
+  - { id: 6, class: gpr }
 
 # First block remains untouched
 # CHECK: body
@@ -76,7 +78,8 @@
     liveins: %s0, %w0
 
     %0(s32) = COPY %s0
-    %1(s1) = COPY %w0
+    %6(s32) = COPY %w0
+    %1(s1) = G_TRUNC %6
     %4(s32) = G_FCONSTANT float 1.000000e+00
     %5(s32) = G_FCONSTANT float 2.000000e+00
     G_BRCOND %1(s1), %bb.1.true
Index: test/CodeGen/AArch64/GlobalISel/reg-bank-128bit.mir
===================================================================
--- test/CodeGen/AArch64/GlobalISel/reg-bank-128bit.mir
+++ test/CodeGen/AArch64/GlobalISel/reg-bank-128bit.mir
@@ -17,5 +17,6 @@
     %1:_(s64) = COPY %x1
     %2:_(p0) = COPY %x2
     %3:_(s128) = G_MERGE_VALUES %0, %1
-    %d0 = COPY %3
+    %4:_(s64) = G_TRUNC %3
+    %d0 = COPY %4
 ...
Index: test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
===================================================================
--- test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
+++ test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
@@ -898,6 +898,7 @@
   - { id: 3, class: _, preferred-register: '' }
   - { id: 4, class: _, preferred-register: '' }
   - { id: 5, class: _, preferred-register: '' }
+  - { id: 6, class: _, preferred-register: '' }
 body:             |
   bb.0:
     successors: %bb.1, %bb.2
@@ -905,7 +906,8 @@
 
     %0(p0) = COPY %x0
     %1(p0) = COPY %x1
-    %2(s1) = COPY %w2
+    %6(s32) = COPY %w2
+    %2(s1) = G_TRUNC %6
     G_BRCOND %2(s1), %bb.1
     G_BR %bb.2
 
Index: test/CodeGen/AArch64/GlobalISel/select-br.mir
===================================================================
--- test/CodeGen/AArch64/GlobalISel/select-br.mir
+++ test/CodeGen/AArch64/GlobalISel/select-br.mir
@@ -33,6 +33,7 @@
 
 registers:
   - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
 
 # CHECK:  body:
 # CHECK:   bb.0:
@@ -41,7 +42,8 @@
 body:             |
   bb.0:
     successors: %bb.0, %bb.1
-    %0(s1) = COPY %w0
+    %1(s32) = COPY %w0
+    %0(s1) = G_TRUNC %1
     G_BRCOND %0(s1), %bb.1
     G_BR %bb.0
 
Index: test/CodeGen/AArch64/GlobalISel/select-fma.mir
===================================================================
--- test/CodeGen/AArch64/GlobalISel/select-fma.mir
+++ test/CodeGen/AArch64/GlobalISel/select-fma.mir
@@ -36,6 +36,6 @@
     %1(s32) = COPY %w1
     %2(s32) = COPY %w2
     %3(s32) = G_FMA %0, %1, %2
-    %x0 = COPY %3
+    %w0 = COPY %3
 ...
 
Index: test/CodeGen/AArch64/GlobalISel/select-imm.mir
===================================================================
--- test/CodeGen/AArch64/GlobalISel/select-imm.mir
+++ test/CodeGen/AArch64/GlobalISel/select-imm.mir
@@ -49,5 +49,5 @@
     liveins: %w0, %w1
 
     %0(s64) = G_CONSTANT i64 1234
-    %w0 = COPY %0(s64)
+    %x0 = COPY %0(s64)
 ...
Index: test/CodeGen/AArch64/GlobalISel/select-int-ext.mir
===================================================================
--- test/CodeGen/AArch64/GlobalISel/select-int-ext.mir
+++ test/CodeGen/AArch64/GlobalISel/select-int-ext.mir
@@ -51,20 +51,21 @@
 regBankSelected: true
 
 # CHECK:      registers:
-# CHECK-NEXT:  - { id: 0, class: gpr32all, preferred-register: '' }
+# CHECK-NEXT:  - { id: 0, class: gpr32, preferred-register: '' }
 # CHECK-NEXT:  - { id: 1, class: gpr32all, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
 # CHECK:  body:
-# CHECK:    %0 = COPY %w0
+# CHECK:    %2 = COPY %w0
 # CHECK:    %1 = COPY %0
 body:             |
   bb.0:
     liveins: %w0
 
-    %0(s8) = COPY %w0
+    %2:gpr(s32) = COPY %w0
+    %0(s8) = G_TRUNC %2
     %1(s32) = G_ANYEXT %0
     %w0 = COPY %1(s32)
 ...
@@ -110,13 +111,14 @@
   - { id: 1, class: gpr }
 
 # CHECK:  body:
-# CHECK:    %0 = COPY %w0
+# CHECK:    %2 = COPY %w0
 # CHECK:    %1 = UBFMWri %0, 0, 15
 body:             |
   bb.0:
     liveins: %w0
 
-    %0(s16) = COPY %w0
+    %2:gpr(s32) = COPY %w0
+    %0(s16) = G_TRUNC %2
     %1(s32) = G_ZEXT %0
     %w0 = COPY %1
 ...
@@ -135,13 +137,14 @@
   - { id: 1, class: gpr }
 
 # CHECK:  body:
-# CHECK:    %0 = COPY %w0
+# CHECK:    %2 = COPY %w0
 # CHECK:    %1 = UBFMWri %0, 0, 7
 body:             |
   bb.0:
     liveins: %w0
 
-    %0(s8) = COPY %w0
+    %2:gpr(s32) = COPY %w0
+    %0(s8) = G_TRUNC %2
     %1(s32) = G_ZEXT %0
     %w0 = COPY %1(s32)
 ...
@@ -160,15 +163,17 @@
   - { id: 1, class: gpr }
 
 # CHECK:  body:
-# CHECK:    %0 = COPY %w0
+# CHECK:    %2 = COPY %w0
 # CHECK:    %1 = UBFMWri %0, 0, 7
 body:             |
   bb.0:
     liveins: %w0
 
-    %0(s8) = COPY %w0
+    %2:gpr(s32) = COPY %w0
+    %0(s8) = G_TRUNC %2
     %1(s16) = G_ZEXT %0
-    %w0 = COPY %1(s16)
+    %3:gpr(s32) = G_ANYEXT %1
+    %w0 = COPY %3(s32)
 ...
 
 ---
@@ -212,13 +217,14 @@
   - { id: 1, class: gpr }
 
 # CHECK:  body:
-# CHECK:    %0 = COPY %w0
+# CHECK:    %2 = COPY %w0
 # CHECK:    %1 = SBFMWri %0, 0, 15
 body:             |
   bb.0:
     liveins: %w0
 
-    %0(s16) = COPY %w0
+    %2:gpr(s32) = COPY %w0
+    %0(s16) = G_TRUNC %2
     %1(s32) = G_SEXT %0
     %w0 = COPY %1
 ...
@@ -237,13 +243,14 @@
   - { id: 1, class: gpr }
 
 # CHECK:  body:
-# CHECK:    %0 = COPY %w0
+# CHECK:    %2 = COPY %w0
 # CHECK:    %1 = SBFMWri %0, 0, 7
 body:             |
   bb.0:
     liveins: %w0
 
-    %0(s8) = COPY %w0
+    %2:gpr(s32) = COPY %w0
+    %0(s8) = G_TRUNC %2
     %1(s32) = G_SEXT %0
     %w0 = COPY %1(s32)
 ...
@@ -262,13 +269,15 @@
   - { id: 1, class: gpr }
 
 # CHECK:  body:
-# CHECK:    %0 = COPY %w0
+# CHECK:    %2 = COPY %w0
 # CHECK:    %1 = SBFMWri %0, 0, 7
 body:             |
   bb.0:
     liveins: %w0
 
-    %0(s8) = COPY %w0
+    %2:gpr(s32) = COPY %w0
+    %0(s8) = G_TRUNC %2
     %1(s16) = G_SEXT %0
-    %w0 = COPY %1(s16)
+    %3:gpr(s32) = G_ANYEXT %1
+    %w0 = COPY %3(s32)
 ...
Index: test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir
===================================================================
--- test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir
+++ test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir
@@ -100,7 +100,8 @@
     liveins: %x0
     %0(p0) = COPY %x0
     %1(s16) = G_PTRTOINT %0
-    %w0 = COPY %1(s16)
+    %2:gpr(s32) = G_ANYEXT %1
+    %w0 = COPY %2(s32)
 ...
 
 ---
@@ -123,7 +124,8 @@
     liveins: %x0
     %0(p0) = COPY %x0
     %1(s8) = G_PTRTOINT %0
-    %w0 = COPY %1(s8)
+    %2:gpr(s32) = G_ANYEXT %1
+    %w0 = COPY %2(s32)
 ...
 
 ---
@@ -146,5 +148,6 @@
     liveins: %x0
     %0(p0) = COPY %x0
     %1(s1) = G_PTRTOINT %0
-    %w0 = COPY %1(s1)
+    %2:gpr(s32) = G_ANYEXT %1
+    %w0 = COPY %2(s32)
 ...
Index: test/CodeGen/AArch64/GlobalISel/select-load.mir
===================================================================
--- test/CodeGen/AArch64/GlobalISel/select-load.mir
+++ test/CodeGen/AArch64/GlobalISel/select-load.mir
@@ -102,7 +102,8 @@
 
     %0(p0) = COPY %x0
     %1(s16) = G_LOAD  %0 :: (load 2 from %ir.addr)
-    %w0 = COPY %1(s16)
+    %2:gpr(s32) = G_ANYEXT %1
+    %w0 = COPY %2(s32)
 ...
 
 ---
@@ -127,7 +128,8 @@
 
     %0(p0) = COPY %x0
     %1(s8) = G_LOAD  %0 :: (load 1 from %ir.addr)
-    %w0 = COPY %1(s8)
+    %2:gpr(s32) = G_ANYEXT %1
+    %w0 = COPY %2(s32)
 ...
 
 ---
@@ -242,7 +244,7 @@
 # CHECK:  body:
 # CHECK: %0 = COPY %x0
 # CHECK: %3 = LDRHHui %0, 32 :: (load 2 from %ir.addr)
-# CHECK: %w0 = COPY %3
+# CHECK: %w0 = COPY %4
 body:             |
   bb.0:
     liveins: %x0
@@ -251,7 +253,8 @@
     %1(s64) = G_CONSTANT i64 64
     %2(p0) = G_GEP %0, %1
     %3(s16) = G_LOAD %2 :: (load 2 from %ir.addr)
-    %w0 = COPY %3
+    %4:gpr(s32) = G_ANYEXT %3
+    %w0 = COPY %4(s32)
 ...
 
 ---
@@ -274,7 +277,7 @@
 # CHECK:  body:
 # CHECK: %0 = COPY %x0
 # CHECK: %3 = LDRBBui %0, 1 :: (load 1 from %ir.addr)
-# CHECK: %w0 = COPY %3
+# CHECK: %w0 = COPY %4
 body:             |
   bb.0:
     liveins: %x0
@@ -283,7 +286,8 @@
     %1(s64) = G_CONSTANT i64 1
     %2(p0) = G_GEP %0, %1
     %3(s8) = G_LOAD %2 :: (load 1 from %ir.addr)
-    %w0 = COPY %3
+    %4:gpr(s32) = G_ANYEXT %3
+    %w0 = COPY %4(s32)
 ...
 
 ---
Index: test/CodeGen/AArch64/GlobalISel/select-phi.mir
===================================================================
--- test/CodeGen/AArch64/GlobalISel/select-phi.mir
+++ test/CodeGen/AArch64/GlobalISel/select-phi.mir
@@ -106,7 +106,8 @@
 
     %0(p0) = COPY %x0
     %1(p0) = COPY %x1
-    %2(s1) = COPY %w2
+    %6:gpr(s32) = COPY %w2
+    %2(s1) = G_TRUNC %6
     G_BRCOND %2(s1), %bb.1
     G_BR %bb.2
 
Index: test/CodeGen/AArch64/GlobalISel/select-store.mir
===================================================================
--- test/CodeGen/AArch64/GlobalISel/select-store.mir
+++ test/CodeGen/AArch64/GlobalISel/select-store.mir
@@ -97,14 +97,15 @@
 
 # CHECK:  body:
 # CHECK: %0 = COPY %x0
-# CHECK: %1 = COPY %w1
+# CHECK: %2 = COPY %w1
 # CHECK: STRHHui %1, %0, 0 :: (store 2 into %ir.addr)
 body:             |
   bb.0:
     liveins: %x0, %w1
 
     %0(p0) = COPY %x0
-    %1(s16) = COPY %w1
+    %2:gpr(s32) = COPY %w1
+    %1(s16) = G_TRUNC %2
     G_STORE  %1, %0 :: (store 2 into %ir.addr)
 
 ...
@@ -124,14 +125,15 @@
 
 # CHECK:  body:
 # CHECK: %0 = COPY %x0
-# CHECK: %1 = COPY %w1
+# CHECK: %2 = COPY %w1
 # CHECK: STRBBui %1, %0, 0 :: (store 1 into %ir.addr)
 body:             |
   bb.0:
     liveins: %x0, %w1
 
     %0(p0) = COPY %x0
-    %1(s8) = COPY %w1
+    %2:gpr(s32) = COPY %w1
+    %1(s8) = G_TRUNC %2
     G_STORE  %1, %0 :: (store 1 into %ir.addr)
 
 ...
@@ -299,14 +301,15 @@
 
 # CHECK:  body:
 # CHECK: %0 = COPY %x0
-# CHECK: %1 = COPY %w1
+# CHECK: %4 = COPY %w1
 # CHECK: STRHHui %1, %0, 32 :: (store 2 into %ir.addr)
 body:             |
   bb.0:
     liveins: %x0, %w1
 
     %0(p0) = COPY %x0
-    %1(s16) = COPY %w1
+    %4:gpr(s32) = COPY %w1
+    %1(s16) = G_TRUNC %4
     %2(s64) = G_CONSTANT i64 64
     %3(p0) = G_GEP %0, %2
     G_STORE %1, %3 :: (store 2 into %ir.addr)
@@ -331,14 +334,15 @@
 
 # CHECK:  body:
 # CHECK: %0 = COPY %x0
-# CHECK: %1 = COPY %w1
+# CHECK: %4 = COPY %w1
 # CHECK: STRBBui %1, %0, 1 :: (store 1 into %ir.addr)
 body:             |
   bb.0:
     liveins: %x0, %w1
 
     %0(p0) = COPY %x0
-    %1(s8) = COPY %w1
+    %4:gpr(s32) = COPY %w1
+    %1(s8) = G_TRUNC %4
     %2(s64) = G_CONSTANT i64 1
     %3(p0) = G_GEP %0, %2
     G_STORE %1, %3 :: (store 1 into %ir.addr)
Index: test/CodeGen/AArch64/GlobalISel/select-trunc.mir
===================================================================
--- test/CodeGen/AArch64/GlobalISel/select-trunc.mir
+++ test/CodeGen/AArch64/GlobalISel/select-trunc.mir
@@ -53,7 +53,8 @@
 
     %0(s64) = COPY %x0
     %1(s8) = G_TRUNC %0
-    %w0 = COPY %1(s8)
+    %2:gpr(s32) = G_ANYEXT %1
+    %w0 = COPY %2(s32)
 ...
 
 ---
@@ -77,5 +78,6 @@
 
     %0(s32) = COPY %w0
     %1(s1) = G_TRUNC %0
-    %w0 = COPY %1(s1)
+    %2:gpr(s32) = G_ANYEXT %1
+    %w0 = COPY %2(s32)
 ...
Index: test/CodeGen/AArch64/GlobalISel/select.mir
===================================================================
--- test/CodeGen/AArch64/GlobalISel/select.mir
+++ test/CodeGen/AArch64/GlobalISel/select.mir
@@ -148,6 +148,9 @@
   - { id: 6, class: gpr }
   - { id: 7, class: gpr }
   - { id: 8, class: gpr }
+  - { id: 9, class: gpr }
+  - { id: 10, class: gpr }
+  - { id: 11, class: gpr }
 
 # CHECK:  body:
 # CHECK:    %wzr = SUBSWrr %0, %0, implicit-def %nzcv
@@ -166,17 +169,20 @@
     %0(s32) = COPY %w0
     %1(s32) = G_ICMP intpred(eq), %0, %0
     %6(s1) = G_TRUNC %1(s32)
-    %w0 = COPY %6(s1)
+    %9(s32) = G_ANYEXT %6
+    %w0 = COPY %9(s32)
 
     %2(s64) = COPY %x0
     %3(s32) = G_ICMP intpred(uge), %2, %2
     %7(s1) = G_TRUNC %3(s32)
-    %w0 = COPY %7(s1)
+    %10(s32) = G_ANYEXT %7
+    %w0 = COPY %10(s32)
 
     %4(p0) = COPY %x0
     %5(s32) = G_ICMP intpred(ne), %4, %4
     %8(s1) = G_TRUNC %5(s32)
-    %w0 = COPY %8(s1)
+    %11(s32) = G_ANYEXT %8
+    %w0 = COPY %11(s32)
 ...
 
 ---
@@ -199,6 +205,8 @@
   - { id: 3, class: gpr }
   - { id: 4, class: gpr }
   - { id: 5, class: gpr }
+  - { id: 6, class: gpr }
+  - { id: 7, class: gpr }
 
 # CHECK:  body:
 # CHECK:    FCMPSrr %0, %0, implicit-def %nzcv
@@ -216,12 +224,14 @@
     %0(s32) = COPY %s0
     %1(s32) = G_FCMP floatpred(one), %0, %0
     %4(s1) = G_TRUNC %1(s32)
-    %w0 = COPY %4(s1)
+    %6(s32) = G_ANYEXT %4
+    %w0 = COPY %6(s32)
 
     %2(s64) = COPY %d0
     %3(s32) = G_FCMP floatpred(uge), %2, %2
     %5(s1) = G_TRUNC %3(s32)
-    %w0 = COPY %5(s1)
+    %7(s32) = G_ANYEXT %5
+    %w0 = COPY %7(s32)
 
 ...
 
@@ -250,7 +260,8 @@
     liveins: %s0, %w0
     successors: %bb.1
     %0(s32) = COPY %s0
-    %1(s1) = COPY %w0
+    %3:gpr(s32) = COPY %w0
+    %1(s1) = G_TRUNC %3
 
   bb.1:
     successors: %bb.1, %bb.2
@@ -302,7 +313,8 @@
 body:             |
   bb.0:
     liveins: %w0, %w1, %w2
-    %0(s1) = COPY %w0
+    %10:gpr(s32) = COPY %w0
+    %0(s1) = G_TRUNC %10
 
     %1(s32) = COPY %w1
     %2(s32) = COPY %w2
Index: test/Verifier/test_copy.mir
===================================================================
--- /dev/null
+++ test/Verifier/test_copy.mir
@@ -0,0 +1,30 @@
+#RUN: not llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# REQUIRES: global-isel, aarch64-registered-target
+--- |
+  ; ModuleID = 'test.ll'
+  source_filename = "test.ll"
+  target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+  target triple = "aarch64-unknown-unknown"
+  
+  define i32 @test_copy(i32 %argc) {
+    ret i32 0
+  }
+
+...
+---
+name:            test_copy
+legalized:       true
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:       
+  - { id: 0, class: _, preferred-register: '' }
+liveins:         
+body:             |
+  bb.0:
+    liveins: %w0
+    ; This test is used to catch verifier errors with copys having mismatching sizes
+    ; CHECK: Bad machine code: Copy Instruction is illegal with mismatching sizes
+  
+    %0(s8) = COPY %w0
+...