Index: llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp
===================================================================
--- llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp
+++ llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp
@@ -70,6 +70,8 @@
                    MachineFunction &MF) const;
   bool selectZext(MachineInstr &I, MachineRegisterInfo &MRI,
                   MachineFunction &MF) const;
+  bool selectAnyext(MachineInstr &I, MachineRegisterInfo &MRI,
+                    MachineFunction &MF) const;
   bool selectCmp(MachineInstr &I, MachineRegisterInfo &MRI,
                  MachineFunction &MF) const;
   bool selectUadde(MachineInstr &I, MachineRegisterInfo &MRI,
@@ -318,6 +320,8 @@
     return true;
   if (selectZext(I, MRI, MF))
     return true;
+  if (selectAnyext(I, MRI, MF))
+    return true;
   if (selectCmp(I, MRI, MF))
     return true;
   if (selectUadde(I, MRI, MF))
@@ -720,6 +724,57 @@
   return true;
 }
 
+bool X86InstructionSelector::selectAnyext(MachineInstr &I,
+                                          MachineRegisterInfo &MRI,
+                                          MachineFunction &MF) const {
+
+  if (I.getOpcode() != TargetOpcode::G_ANYEXT)
+    return false;
+
+  const unsigned DstReg = I.getOperand(0).getReg();
+  const unsigned SrcReg = I.getOperand(1).getReg();
+
+  const LLT DstTy = MRI.getType(DstReg);
+  const LLT SrcTy = MRI.getType(SrcReg);
+
+  const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI);
+  const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI);
+
+  assert (DstRB.getID() == SrcRB.getID() &&
+      "G_ANYEXT input/output on different banks\n");
+
+  assert (DstTy.getSizeInBits() > SrcTy.getSizeInBits() &&
+      "G_ANYEXT incorrect operand size");
+
+  if (DstRB.getID() != X86::GPRRegBankID)
+    return false;
+
+  const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB);
+  const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB);
+
+  if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI) ||
+      !RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
+    DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
+                 << " operand\n");
+    return false;
+  }
+
+  if (SrcRC == DstRC) {
+    I.setDesc(TII.get(X86::COPY));
+    return true;
+  }
+
+  BuildMI(*I.getParent(), I, I.getDebugLoc(),
+          TII.get(TargetOpcode::SUBREG_TO_REG))
+      .addDef(DstReg)
+      .addImm(0)
+      .addReg(SrcReg)
+      .addImm(getSubRegIndex(SrcRC));
+
+  I.eraseFromParent();
+  return true;
+}
+
 bool X86InstructionSelector::selectCmp(MachineInstr &I,
                                        MachineRegisterInfo &MRI,
                                        MachineFunction &MF) const {
Index: llvm/trunk/lib/Target/X86/X86LegalizerInfo.cpp
===================================================================
--- llvm/trunk/lib/Target/X86/X86LegalizerInfo.cpp
+++ llvm/trunk/lib/Target/X86/X86LegalizerInfo.cpp
@@ -99,11 +99,13 @@
   for (auto Ty : {s8, s16, s32}) {
     setAction({G_ZEXT, Ty}, Legal);
     setAction({G_SEXT, Ty}, Legal);
+    setAction({G_ANYEXT, Ty}, Legal);
   }
 
   for (auto Ty : {s1, s8, s16}) {
     setAction({G_ZEXT, 1, Ty}, Legal);
     setAction({G_SEXT, 1, Ty}, Legal);
+    setAction({G_ANYEXT, 1, Ty}, Legal);
   }
 
   // Comparison
@@ -128,9 +130,8 @@
   for (unsigned BinOp : {G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR})
     setAction({BinOp, s64}, Legal);
 
-  for (unsigned MemOp : {G_LOAD, G_STORE}) {
+  for (unsigned MemOp : {G_LOAD, G_STORE})
     setAction({MemOp, s64}, Legal);
-  }
 
   // Pointer-handling
   setAction({G_GEP, 1, s64}, Legal);
@@ -139,11 +140,10 @@
   setAction({TargetOpcode::G_CONSTANT, s64}, Legal);
 
   // Extensions
-  setAction({G_ZEXT, s64}, Legal);
-  setAction({G_SEXT, s64}, Legal);
-
-  setAction({G_ZEXT, 1, s32}, Legal);
-  setAction({G_SEXT, 1, s32}, Legal);
+  for (unsigned extOp : {G_ZEXT, G_SEXT, G_ANYEXT}) {
+    setAction({extOp, s64}, Legal);
+    setAction({extOp, 1, s32}, Legal);
+  }
 
   // Comparison
   setAction({G_ICMP, 1, s64}, Legal);
Index: llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir
===================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir
@@ -42,6 +42,23 @@
     %r = zext i32 %val to i64
     ret i64 %r
   }
+  
+  define void @test_anyext_i1(i8 %a) {
+    ret void
+  }
+
+  define void @test_anyext_i8(i8 %val) {
+    ret void
+  }
+
+  define void @test_anyext_i16(i16 %val) {
+    ret void
+  }
+
+  define void @test_anyext_i32(i32 %val) {
+    ret void
+  }
+  
 
 ...
 ---
@@ -234,3 +251,99 @@
     RET 0, implicit %rax
 
 ...
+---
+name:            test_anyext_i1
+# CHECK-LABEL: name:  test_anyext_i1
+alignment:       4
+legalized:       false
+regBankSelected: false
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+# CHECK:          %0(s8) = COPY %edi
+# CHECK-NEXT:     %1(s1) = G_TRUNC %0(s8)
+# CHECK-NEXT:     %2(s64) = G_ANYEXT %1(s1)
+# CHECK-NEXT:     %rax = COPY %2(s64)
+# CHECK-NEXT:     RET 0, implicit %rax
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %edi
+
+    %0(s8) = COPY %edi
+    %1(s1) = G_TRUNC %0(s8)
+    %2(s64) = G_ANYEXT %1(s1)
+    %rax = COPY %2(s64)
+    RET 0, implicit %rax
+
+...
+---
+name:            test_anyext_i8
+# CHECK-LABEL: name:  test_anyext_i8
+alignment:       4
+legalized:       false
+regBankSelected: false
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+# CHECK:          %0(s8) = COPY %edi
+# CHECK-NEXT:     %1(s64) = G_ANYEXT %0(s8)
+# CHECK-NEXT:     %rax = COPY %1(s64)
+# CHECK-NEXT:     RET 0, implicit %rax
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %edi
+
+    %0(s8) = COPY %edi
+    %1(s64) = G_ANYEXT %0(s8)
+    %rax = COPY %1(s64)
+    RET 0, implicit %rax
+
+...
+---
+name:            test_anyext_i16
+# CHECK-LABEL: name:  test_anyext_i16
+alignment:       4
+legalized:       false
+regBankSelected: false
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+# CHECK:          %0(s16) = COPY %edi
+# CHECK-NEXT:     %1(s64) = G_ANYEXT %0(s16)
+# CHECK-NEXT:     %rax = COPY %1(s64)
+# CHECK-NEXT:     RET 0, implicit %rax
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %edi
+
+    %0(s16) = COPY %edi
+    %1(s64) = G_ANYEXT %0(s16)
+    %rax = COPY %1(s64)
+    RET 0, implicit %rax
+
+...
+---
+name:            test_anyext_i32
+# CHECK-LABEL: name:  test_anyext_i32
+alignment:       4
+legalized:       false
+regBankSelected: false
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+# CHECK:          %0(s32) = COPY %edi
+# CHECK-NEXT:     %1(s64) = G_ANYEXT %0(s32)
+# CHECK-NEXT:     %rax = COPY %1(s64)
+# CHECK-NEXT:     RET 0, implicit %rax
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %edi
+
+    %0(s32) = COPY %edi
+    %1(s64) = G_ANYEXT %0(s32)
+    %rax = COPY %1(s64)
+    RET 0, implicit %rax
+
+...
+
Index: llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-ext.mir
===================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-ext.mir
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/legalize-ext.mir
@@ -64,6 +64,30 @@
     ret i32 %r
   }
 
+  define void @test_anyext_i1toi8(i1 %a) {
+    ret void
+  }
+
+  define void @test_anyext_i1toi16(i1 %a) {
+    ret void
+  }
+
+  define void @test_anyext_i1(i8 %a) {
+    ret void
+  }
+
+  define void @test_anyext_i8toi16(i8 %val) {
+    ret void
+  }
+
+  define void @test_anyext_i8(i8 %val) {
+    ret void
+  }
+
+  define void @test_anyext_i16(i16 %val) {
+    ret void
+  }
+
 ...
 ---
 name:            test_zext_i1toi8
@@ -347,3 +371,144 @@
     RET 0, implicit %eax
 
 ...
+---
+name:            test_anyext_i1toi8
+# ALL-LABEL: name:  test_anyext_i1toi8
+alignment:       4
+legalized:       false
+regBankSelected: false
+registers:
+  - { id: 0, class: _, preferred-register: '' }
+  - { id: 1, class: _, preferred-register: '' }
+# ALL:          %0(s1) = COPY %edi
+# ALL-NEXT:     %1(s8) = G_ANYEXT %0(s1)
+# ALL-NEXT:     %al = COPY %1(s8)
+# ALL-NEXT:     RET 0, implicit %al
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %edi
+
+    %0(s1) = COPY %edi
+    %1(s8) = G_ANYEXT %0(s1)
+    %al = COPY %1(s8)
+    RET 0, implicit %al
+
+...
+---
+name:            test_anyext_i1toi16
+# ALL-LABEL: name:  test_anyext_i1toi16
+alignment:       4
+legalized:       false
+regBankSelected: false
+registers:
+  - { id: 0, class: _, preferred-register: '' }
+  - { id: 1, class: _, preferred-register: '' }
+# ALL:          %0(s1) = COPY %edi
+# ALL-NEXT:     %1(s16) = G_ANYEXT %0(s1)
+# ALL-NEXT:     %ax = COPY %1(s16)
+# ALL-NEXT:     RET 0, implicit %ax
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %edi
+
+    %0(s1) = COPY %edi
+    %1(s16) = G_ANYEXT %0(s1)
+    %ax = COPY %1(s16)
+    RET 0, implicit %ax
+
+...
+---
+name:            test_anyext_i1
+# ALL-LABEL: name:  test_anyext_i1
+alignment:       4
+legalized:       false
+regBankSelected: false
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+# ALL:          %0(s8) = COPY %edi
+# ALL-NEXT:     %1(s1) = G_TRUNC %0(s8)
+# ALL-NEXT:     %2(s32) = G_ANYEXT %1(s1)
+# ALL-NEXT:     %eax = COPY %2(s32)
+# ALL-NEXT:     RET 0, implicit %eax
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %edi
+
+    %0(s8) = COPY %edi
+    %1(s1) = G_TRUNC %0(s8)
+    %2(s32) = G_ANYEXT %1(s1)
+    %eax = COPY %2(s32)
+    RET 0, implicit %eax
+
+...
+---
+name:            test_anyext_i8toi16
+# ALL-LABEL: name:  test_anyext_i8toi16
+alignment:       4
+legalized:       false
+regBankSelected: false
+registers:
+  - { id: 0, class: _, preferred-register: '' }
+  - { id: 1, class: _, preferred-register: '' }
+# ALL:          %0(s8) = COPY %edi
+# ALL-NEXT:     %1(s16) = G_ANYEXT %0(s8)
+# ALL-NEXT:     %ax = COPY %1(s16)
+# ALL-NEXT:     RET 0, implicit %ax
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %edi
+
+    %0(s8) = COPY %edi
+    %1(s16) = G_ANYEXT %0(s8)
+    %ax = COPY %1(s16)
+    RET 0, implicit %ax
+
+...
+---
+name:            test_anyext_i8
+# ALL-LABEL: name:  test_anyext_i8
+alignment:       4
+legalized:       false
+regBankSelected: false
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+# ALL:          %0(s8) = COPY %edi
+# ALL-NEXT:     %1(s32) = G_ANYEXT %0(s8)
+# ALL-NEXT:     %eax = COPY %1(s32)
+# ALL-NEXT:     RET 0, implicit %eax
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %edi
+
+    %0(s8) = COPY %edi
+    %1(s32) = G_ANYEXT %0(s8)
+    %eax = COPY %1(s32)
+    RET 0, implicit %eax
+
+...
+---
+name:            test_anyext_i16
+# ALL-LABEL: name:  test_anyext_i16
+alignment:       4
+legalized:       false
+regBankSelected: false
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+# ALL:          %0(s16) = COPY %edi
+# ALL-NEXT:     %1(s32) = G_ANYEXT %0(s16)
+# ALL-NEXT:     %eax = COPY %1(s32)
+# ALL-NEXT:     RET 0, implicit %eax
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %edi
+
+    %0(s16) = COPY %edi
+    %1(s32) = G_ANYEXT %0(s16)
+    %eax = COPY %1(s32)
+    RET 0, implicit %eax
+
+...
Index: llvm/trunk/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir
===================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir
@@ -17,6 +17,10 @@
     ret i64 %r
   }
 
+  define void @anyext_s64_from_s1() { ret void }
+  define void @anyext_s64_from_s8() { ret void }
+  define void @anyext_s64_from_s16() { ret void }
+  define void @anyext_s64_from_s32() { ret void }
 ...
 ---
 name:            test_zext_i1
@@ -102,3 +106,119 @@
     RET 0, implicit %rax
 
 ...
+---
+name:            anyext_s64_from_s1
+# ALL-LABEL: name:  anyext_s64_from_s1
+alignment:       4
+legalized:       true
+regBankSelected: true
+# ALL:      registers:
+# ALL-NEXT:   - { id: 0, class: gr64_with_sub_8bit, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: gr8, preferred-register: '' }
+# ALL-NEXT:   - { id: 2, class: gr64, preferred-register: '' }
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+# ALL:          %0 = COPY %rdi
+# ALL-NEXT:     %1 = COPY %0.sub_8bit
+# ALL-NEXT:     %2 = SUBREG_TO_REG 0, %1, 1
+# ALL-NEXT:     %rax = COPY %2
+# ALL-NEXT:     RET 0, implicit %rax
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %edi
+
+    %0(s64) = COPY %rdi
+    %1(s1) = G_TRUNC %0(s64)
+    %2(s64) = G_ANYEXT %1(s1)
+    %rax = COPY %2(s64)
+    RET 0, implicit %rax
+...
+---
+name:            anyext_s64_from_s8
+# ALL-LABEL: name:  anyext_s64_from_s8
+alignment:       4
+legalized:       true
+regBankSelected: true
+# ALL:      registers:
+# ALL-NEXT:   - { id: 0, class: gr64_with_sub_8bit, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: gr8, preferred-register: '' }
+# ALL-NEXT:   - { id: 2, class: gr64, preferred-register: '' }
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+# ALL:          %0 = COPY %rdi
+# ALL-NEXT:     %1 = COPY %0.sub_8bit
+# ALL-NEXT:     %2 = SUBREG_TO_REG 0, %1, 1
+# ALL-NEXT:     %rax = COPY %2
+# ALL-NEXT:     RET 0, implicit %rax
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %edi
+
+    %0(s64) = COPY %rdi
+    %1(s8) = G_TRUNC %0(s64)
+    %2(s64) = G_ANYEXT %1(s8)
+    %rax = COPY %2(s64)
+    RET 0, implicit %rax
+...
+---
+name:            anyext_s64_from_s16
+# ALL-LABEL: name:  anyext_s64_from_s16
+alignment:       4
+legalized:       true
+regBankSelected: true
+# ALL:      registers:
+# ALL-NEXT:   - { id: 0, class: gr64, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: gr16, preferred-register: '' }
+# ALL-NEXT:   - { id: 2, class: gr64, preferred-register: '' }
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+# ALL:          %0 = COPY %rdi
+# ALL-NEXT:     %1 = COPY %0.sub_16bit
+# ALL-NEXT:     %2 = SUBREG_TO_REG 0, %1, 3
+# ALL-NEXT:     %rax = COPY %2
+# ALL-NEXT:     RET 0, implicit %rax
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %edi
+
+    %0(s64) = COPY %rdi
+    %1(s16) = G_TRUNC %0(s64)
+    %2(s64) = G_ANYEXT %1(s16)
+    %rax = COPY %2(s64)
+    RET 0, implicit %rax
+...
+---
+name:            anyext_s64_from_s32
+# ALL-LABEL: name:  anyext_s64_from_s32
+alignment:       4
+legalized:       true
+regBankSelected: true
+# ALL:      registers:
+# ALL-NEXT:   - { id: 0, class: gr64, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
+# ALL-NEXT:   - { id: 2, class: gr64, preferred-register: '' }
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+# ALL:          %0 = COPY %rdi
+# ALL-NEXT:     %1 = COPY %0.sub_32bit
+# ALL-NEXT:     %2 = SUBREG_TO_REG 0, %1, 4
+# ALL-NEXT:     %rax = COPY %2
+# ALL-NEXT:     RET 0, implicit %rax
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %edi
+
+    %0(s64) = COPY %rdi
+    %1(s32) = G_TRUNC %0(s64)
+    %2(s64) = G_ANYEXT %1(s32)
+    %rax = COPY %2(s64)
+    RET 0, implicit %rax
+...
Index: llvm/trunk/test/CodeGen/X86/GlobalISel/select-ext.mir
===================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-ext.mir
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-ext.mir
@@ -37,6 +37,13 @@
     ret i32 %r
   }
 
+  define void @test_anyext_i1toi8() { ret void }
+  define void @test_anyext_i1toi16() { ret void }
+  define void @test_anyext_i1toi32() { ret void }
+  define void @test_anyext_i8toi16() { ret void }
+  define void @test_anyext_i8toi32() { ret void }
+  define void @test_anyext_i16toi32() { ret void }
+
 ...
 ---
 name:            test_zext_i1toi8
@@ -224,3 +231,202 @@
     RET 0, implicit %eax
 
 ...
+---
+name:            test_anyext_i1toi8
+# ALL-LABEL: name:  test_anyext_i1toi8
+alignment:       4
+legalized:       true
+regBankSelected: true
+# X32:      registers:
+# X32-NEXT:   - { id: 0, class: gr32_abcd, preferred-register: '' }
+# X32-NEXT:   - { id: 1, class: gr8, preferred-register: '' }
+# X32-NEXT:   - { id: 2, class: gr8, preferred-register: '' }
+#
+# X64:      registers:
+# X64-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
+# X64-NEXT:   - { id: 1, class: gr8, preferred-register: '' }
+# X64-NEXT:   - { id: 2, class: gr8, preferred-register: '' }
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+# ALL:          %0 = COPY %edi
+# ALL-NEXT:     %1 = COPY %0.sub_8bit
+# ALL-NEXT:     %2 = COPY %1
+# ALL-NEXT:     %al = COPY %2
+# ALL-NEXT:     RET 0, implicit %al
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %edi
+
+    %0(s32) = COPY %edi
+    %1(s1) = G_TRUNC %0(s32)
+    %2(s8) = G_ANYEXT %1(s1)
+    %al = COPY %2(s8)
+    RET 0, implicit %al
+...
+---
+name:            test_anyext_i1toi16
+# ALL-LABEL: name:  test_anyext_i1toi16
+alignment:       4
+legalized:       true
+regBankSelected: true
+# X32:      registers:
+# X32-NEXT:   - { id: 0, class: gr32_abcd, preferred-register: '' }
+# X32-NEXT:   - { id: 1, class: gr8, preferred-register: '' }
+# X32-NEXT:   - { id: 2, class: gr16, preferred-register: '' }
+#
+# X64:      registers:
+# X64-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
+# X64-NEXT:   - { id: 1, class: gr8, preferred-register: '' }
+# X64-NEXT:   - { id: 2, class: gr16, preferred-register: '' }
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+# ALL:          %0 = COPY %edi
+# ALL-NEXT:     %1 = COPY %0.sub_8bit
+# ALL-NEXT:     %2 = SUBREG_TO_REG 0, %1, 1
+# ALL-NEXT:     %ax = COPY %2
+# ALL-NEXT:     RET 0, implicit %ax
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %edi
+
+    %0(s32) = COPY %edi
+    %1(s1) = G_TRUNC %0(s32)
+    %2(s16) = G_ANYEXT %1(s1)
+    %ax = COPY %2(s16)
+    RET 0, implicit %ax
+...
+---
+name:            test_anyext_i1toi32
+# ALL-LABEL: name:  test_anyext_i1toi32
+alignment:       4
+legalized:       true
+regBankSelected: true
+# X32:      registers:
+# X32-NEXT:   - { id: 0, class: gr32_abcd, preferred-register: '' }
+# X32-NEXT:   - { id: 1, class: gr8, preferred-register: '' }
+# X32-NEXT:   - { id: 2, class: gr32, preferred-register: '' }
+#
+# X64:      registers:
+# X64-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
+# X64-NEXT:   - { id: 1, class: gr8, preferred-register: '' }
+# X64-NEXT:   - { id: 2, class: gr32, preferred-register: '' }
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+# ALL:          %0 = COPY %edi
+# ALL-NEXT:     %1 = COPY %0.sub_8bit
+# ALL-NEXT:     %2 = SUBREG_TO_REG 0, %1, 1
+# ALL-NEXT:     %eax = COPY %2
+# ALL-NEXT:     RET 0, implicit %eax
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %edi
+
+    %0(s32) = COPY %edi
+    %1(s1) = G_TRUNC %0(s32)
+    %2(s32) = G_ANYEXT %1(s1)
+    %eax = COPY %2(s32)
+    RET 0, implicit %eax
+...
+---
+name:            test_anyext_i8toi16
+# ALL-LABEL: name:  test_anyext_i8toi16
+alignment:       4
+legalized:       true
+regBankSelected: true
+# X32:      registers:
+# X32-NEXT:   - { id: 0, class: gr32_abcd, preferred-register: '' }
+# X32-NEXT:   - { id: 1, class: gr8, preferred-register: '' }
+# X32-NEXT:   - { id: 2, class: gr16, preferred-register: '' }
+#
+# X64:      registers:
+# X64-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
+# X64-NEXT:   - { id: 1, class: gr8, preferred-register: '' }
+# X64-NEXT:   - { id: 2, class: gr16, preferred-register: '' }
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+# ALL:          %0 = COPY %edi
+# ALL-NEXT:     %1 = COPY %0.sub_8bit
+# ALL-NEXT:     %2 = SUBREG_TO_REG 0, %1, 1
+# ALL-NEXT:     %ax = COPY %2
+# ALL-NEXT:     RET 0, implicit %ax
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %edi
+
+    %0(s32) = COPY %edi
+    %1(s8) = G_TRUNC %0(s32)
+    %2(s16) = G_ANYEXT %1(s8)
+    %ax = COPY %2(s16)
+    RET 0, implicit %ax
+...
+---
+name:            test_anyext_i8toi32
+# ALL-LABEL: name:  test_anyext_i8toi32
+alignment:       4
+legalized:       true
+regBankSelected: true
+# X32:      registers:
+# X32-NEXT:   - { id: 0, class: gr32_abcd, preferred-register: '' }
+# X32-NEXT:   - { id: 1, class: gr8, preferred-register: '' }
+# X32-NEXT:   - { id: 2, class: gr32, preferred-register: '' }
+#
+# X64:      registers:
+# X64-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
+# X64-NEXT:   - { id: 1, class: gr8, preferred-register: '' }
+# X64-NEXT:   - { id: 2, class: gr32, preferred-register: '' }
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+# ALL:          %0 = COPY %edi
+# ALL-NEXT:     %1 = COPY %0.sub_8bit
+# ALL-NEXT:     %2 = MOVZX32rr8 %1
+# ALL-NEXT:     %eax = COPY %2
+# ALL-NEXT:     RET 0, implicit %eax
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %edi
+
+    %0(s32) = COPY %edi
+    %1(s8) = G_TRUNC %0(s32)
+    %2(s32) = G_ANYEXT %1(s8)
+    %eax = COPY %2(s32)
+    RET 0, implicit %eax
+...
+---
+name:            test_anyext_i16toi32
+# ALL-LABEL: name:  test_anyext_i16toi32
+alignment:       4
+legalized:       true
+regBankSelected: true
+# ALL:      registers:
+# ALL-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
+# ALL-NEXT:   - { id: 1, class: gr16, preferred-register: '' }
+# ALL-NEXT:   - { id: 2, class: gr32, preferred-register: '' }
+registers:
+  - { id: 0, class: gpr }
+  - { id: 1, class: gpr }
+  - { id: 2, class: gpr }
+# ALL:          %0 = COPY %edi
+# ALL-NEXT:     %1 = COPY %0.sub_16bit
+# ALL-NEXT:     %2 = SUBREG_TO_REG 0, %1, 3
+# ALL-NEXT:     %eax = COPY %2
+# ALL-NEXT:     RET 0, implicit %eax
+body:             |
+  bb.1 (%ir-block.0):
+    liveins: %edi
+
+    %0(s32) = COPY %edi
+    %1(s16) = G_TRUNC %0(s32)
+    %2(s32) = G_ANYEXT %1(s16)
+    %eax = COPY %2(s32)
+    RET 0, implicit %eax
+...