Index: include/llvm/CodeGen/MachineBasicBlock.h =================================================================== --- include/llvm/CodeGen/MachineBasicBlock.h +++ include/llvm/CodeGen/MachineBasicBlock.h @@ -294,6 +294,9 @@ LiveIns.push_back(RegMaskPair); } + /// Remove kills and deads for registers that need to be live. + void removeDeadAndKillFlagsForLiveRegs(); + /// Sorts and uniques the LiveIns vector. It can be significantly faster to do /// this than repeatedly calling isLiveIn before calling addLiveIn for every /// LiveIn insertion. Index: lib/CodeGen/IfConversion.cpp =================================================================== --- lib/CodeGen/IfConversion.cpp +++ lib/CodeGen/IfConversion.cpp @@ -179,7 +179,6 @@ MachineRegisterInfo *MRI; LivePhysRegs Redefs; - LivePhysRegs DontKill; bool PreRegAlloc; bool MadeChange; @@ -461,6 +460,9 @@ } } + if (RetVal && MRI->tracksLiveness()) + BBI.BB->removeDeadAndKillFlagsForLiveRegs(); + Change |= RetVal; NumIfCvts = NumSimple + NumSimpleFalse + NumTriangle + NumTriangleRev + @@ -1380,13 +1382,6 @@ MIB.addReg(Reg, RegState::Implicit | RegState::Define); continue; } - assert(Op.isReg() && "Register operand required"); - if (Op.isDead()) { - // If we found a dead def, but it needs to be live, then remove the dead - // flag. - if (Redefs.contains(Op.getReg())) - Op.setIsDead(false); - } if (LiveBeforeMI.count(Reg)) MIB.addReg(Reg, RegState::Implicit); else { @@ -1403,26 +1398,6 @@ } } -/// Remove kill flags from operands with a registers in the \p DontKill set. -static void RemoveKills(MachineInstr &MI, const LivePhysRegs &DontKill) { - for (MIBundleOperands O(MI); O.isValid(); ++O) { - if (!O->isReg() || !O->isKill()) - continue; - if (DontKill.contains(O->getReg())) - O->setIsKill(false); - } -} - -/// Walks a range of machine instructions and removes kill flags for registers -/// in the \p DontKill set. -static void RemoveKills(MachineBasicBlock::iterator I, - MachineBasicBlock::iterator E, - const LivePhysRegs &DontKill, - const MCRegisterInfo &MCRI) { - for (MachineInstr &MI : make_range(I, E)) - RemoveKills(MI, DontKill); -} - /// If convert a simple (split, no rejoin) sub-CFG. bool IfConverter::IfConvertSimple(BBInfo &BBI, IfcvtKind Kind) { BBInfo &TrueBBI = BBAnalysis[BBI.TrueBB->getNumber()]; @@ -1453,16 +1428,12 @@ llvm_unreachable("Unable to reverse branch condition!"); Redefs.init(*TRI); - DontKill.init(*TRI); if (MRI->tracksLiveness()) { // Initialize liveins to the first BB. These are potentiall redefined by // predicated instructions. Redefs.addLiveIns(CvtMBB); Redefs.addLiveIns(NextMBB); - // Compute a set of registers which must not be killed by instructions in - // BB1: This is everything live-in to BB2. - DontKill.addLiveIns(NextMBB); } // Remove the branches from the entry so we can add the contents of the true @@ -1478,7 +1449,6 @@ BBI.BB->removeSuccessor(&CvtMBB, true); } else { // Predicate the instructions in the true block. - RemoveKills(CvtMBB.begin(), CvtMBB.end(), DontKill, *TRI); PredicateBlock(*CvtBBI, CvtMBB.end(), Cond); // Merge converted block into entry block. The BB to Cvt edge is removed @@ -1567,8 +1537,6 @@ Redefs.addLiveIns(NextMBB); } - DontKill.clear(); - bool HasEarlyExit = CvtBBI->FalseBB != nullptr; BranchProbability CvtNext, CvtFalse, BBNext, BBCvt; @@ -1751,25 +1719,12 @@ --NumDups1; } - // Compute a set of registers which must not be killed by instructions in BB1: - // This is everything used+live in BB2 after the duplicated instructions. We - // can compute this set by simulating liveness backwards from the end of BB2. - DontKill.init(*TRI); if (MRI->tracksLiveness()) { - for (const MachineInstr &MI : make_range(MBB2.rbegin(), ++DI2.getReverse())) - DontKill.stepBackward(MI); - for (const MachineInstr &MI : make_range(MBB1.begin(), DI1)) { SmallVector, 4> Dummy; Redefs.stepForward(MI, Dummy); } } - // Kill flags in the true block for registers living into the false block - // must be removed. This should be done before extracting the common - // instructions from the beginning of the MBB1, since these instructions - // can actually differ between MBB1 and MBB2 in terms of flags. - RemoveKills(MBB1.begin(), MBB1.end(), DontKill, *TRI); - BBI.BB->splice(BBI.BB->end(), &MBB1, MBB1.begin(), DI1); MBB2.erase(MBB2.begin(), DI2); @@ -2085,10 +2040,6 @@ // If the predicated instruction now redefines a register as the result of // if-conversion, add an implicit kill. UpdatePredRedefs(*MI, Redefs); - - // Some kill flags may not be correct anymore. - if (!DontKill.empty()) - RemoveKills(*MI, DontKill); } if (!IgnoreBr) { Index: lib/CodeGen/MachineBasicBlock.cpp =================================================================== --- lib/CodeGen/MachineBasicBlock.cpp +++ lib/CodeGen/MachineBasicBlock.cpp @@ -15,6 +15,7 @@ #include "llvm/ADT/SmallPtrSet.h" #include "llvm/CodeGen/LiveIntervalAnalysis.h" #include "llvm/CodeGen/LiveVariables.h" +#include "llvm/CodeGen/LivePhysRegs.h" #include "llvm/CodeGen/MachineDominators.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" @@ -421,6 +422,45 @@ return VirtReg; } +void MachineBasicBlock::removeDeadAndKillFlagsForLiveRegs() { + const TargetRegisterInfo *TRI = + getParent()->getSubtarget().getRegisterInfo(); + + // We walk through the block backwards and start with the registers that + // successor BBs say are live. + LivePhysRegs LiveRegs; + LiveRegs.init(*TRI); + for (auto Succ : successors()) + LiveRegs.addLiveIns(*Succ); + + for (MachineInstr &MI : make_range(rbegin(), rend())) { + if (MI.isDebugValue()) + continue; + for (MIBundleOperands MO(MI); MO.isValid(); ++MO) { + if (!MO->isReg()) + continue; + + unsigned Reg = MO->getReg(); + if (Reg == 0) + continue; + + bool IsLive = false; + for (unsigned LiveReg : LiveRegs) + IsLive = IsLive || TRI->regsOverlap(Reg, LiveReg); + + if (!IsLive) + continue; + + if (MO->isKill()) + MO->setIsKill(false); + if (MO->isDead()) + MO->setIsDead(false); + } + LiveRegs.stepBackward(MI); + } +} + + void MachineBasicBlock::moveBefore(MachineBasicBlock *NewAfter) { getParent()->splice(NewAfter->getIterator(), getIterator()); } Index: test/CodeGen/Hexagon/ifcvt-live-subreg.mir =================================================================== --- test/CodeGen/Hexagon/ifcvt-live-subreg.mir +++ test/CodeGen/Hexagon/ifcvt-live-subreg.mir @@ -9,7 +9,7 @@ # CHECK: liveins: %r0, %r1, %p0, %d8 # CHECK: %d8 = A2_combinew killed %r0, killed %r1 # CHECK: %d8 = L2_ploadrdf_io %p0, %r29, 0, implicit %d8 -# CHECK: J2_jumprf %p0, killed %r31, implicit-def %pc, implicit-def %pc, implicit killed %d8 +# CHECK: J2_jumprf %p0, killed %r31, implicit-def %pc, implicit-def dead %pc, implicit %d8 --- | define void @foo() { @@ -35,7 +35,7 @@ J2_jumpf killed %p0, %bb.2, implicit-def %pc bb.1: - liveins: %d0, %r17 + liveins: %r17 %r0 = A2_tfrsi 0 %r1 = A2_tfrsi 0 A2_nop ; non-predicable