Index: llvm/trunk/test/CodeGen/X86/psubus.ll =================================================================== --- llvm/trunk/test/CodeGen/X86/psubus.ll +++ llvm/trunk/test/CodeGen/X86/psubus.ll @@ -1,18 +1,18 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=x86_64-apple-macosx10.8.0 -mattr=+sse2 | FileCheck %s --check-prefix=SSE --check-prefix=SSE2 -; RUN: llc < %s -mtriple=x86_64-apple-macosx10.8.0 -mattr=+ssse3 | FileCheck %s --check-prefix=SSE --check-prefix=SSSE3 -; RUN: llc < %s -mtriple=x86_64-apple-macosx10.8.0 -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE --check-prefix=SSE41 -; RUN: llc < %s -mtriple=x86_64-apple-macosx10.8.0 -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1 -; RUN: llc < %s -mtriple=x86_64-apple-macosx10.8.0 -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE --check-prefix=SSE2 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+ssse3 | FileCheck %s --check-prefix=SSE --check-prefix=SSSE3 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE --check-prefix=SSE41 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2 define <8 x i16> @test1(<8 x i16> %x) nounwind { ; SSE-LABEL: test1: -; SSE: ## BB#0: ## %vector.ph +; SSE: # BB#0: # %vector.ph ; SSE-NEXT: psubusw {{.*}}(%rip), %xmm0 ; SSE-NEXT: retq ; ; AVX-LABEL: test1: -; AVX: ## BB#0: ## %vector.ph +; AVX: # BB#0: # %vector.ph ; AVX-NEXT: vpsubusw {{.*}}(%rip), %xmm0, %xmm0 ; AVX-NEXT: retq vector.ph: @@ -24,12 +24,12 @@ define <8 x i16> @test2(<8 x i16> %x) nounwind { ; SSE-LABEL: test2: -; SSE: ## BB#0: ## %vector.ph +; SSE: # BB#0: # %vector.ph ; SSE-NEXT: psubusw {{.*}}(%rip), %xmm0 ; SSE-NEXT: retq ; ; AVX-LABEL: test2: -; AVX: ## BB#0: ## %vector.ph +; AVX: # BB#0: # %vector.ph ; AVX-NEXT: vpsubusw {{.*}}(%rip), %xmm0, %xmm0 ; AVX-NEXT: retq vector.ph: @@ -41,7 +41,7 @@ define <8 x i16> @test3(<8 x i16> %x, i16 zeroext %w) nounwind { ; SSE-LABEL: test3: -; SSE: ## BB#0: ## %vector.ph +; SSE: # BB#0: # %vector.ph ; SSE-NEXT: movd %edi, %xmm1 ; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,0,0,0,4,5,6,7] ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,1,1] @@ -49,7 +49,7 @@ ; SSE-NEXT: retq ; ; AVX1-LABEL: test3: -; AVX1: ## BB#0: ## %vector.ph +; AVX1: # BB#0: # %vector.ph ; AVX1-NEXT: vmovd %edi, %xmm1 ; AVX1-NEXT: vpshuflw {{.*#+}} xmm1 = xmm1[0,0,0,0,4,5,6,7] ; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,0,1,1] @@ -57,7 +57,7 @@ ; AVX1-NEXT: retq ; ; AVX2-LABEL: test3: -; AVX2: ## BB#0: ## %vector.ph +; AVX2: # BB#0: # %vector.ph ; AVX2-NEXT: vmovd %edi, %xmm1 ; AVX2-NEXT: vpbroadcastw %xmm1, %xmm1 ; AVX2-NEXT: vpsubusw %xmm1, %xmm0, %xmm0 @@ -73,12 +73,12 @@ define <16 x i8> @test4(<16 x i8> %x) nounwind { ; SSE-LABEL: test4: -; SSE: ## BB#0: ## %vector.ph +; SSE: # BB#0: # %vector.ph ; SSE-NEXT: psubusb {{.*}}(%rip), %xmm0 ; SSE-NEXT: retq ; ; AVX-LABEL: test4: -; AVX: ## BB#0: ## %vector.ph +; AVX: # BB#0: # %vector.ph ; AVX-NEXT: vpsubusb {{.*}}(%rip), %xmm0, %xmm0 ; AVX-NEXT: retq vector.ph: @@ -90,12 +90,12 @@ define <16 x i8> @test5(<16 x i8> %x) nounwind { ; SSE-LABEL: test5: -; SSE: ## BB#0: ## %vector.ph +; SSE: # BB#0: # %vector.ph ; SSE-NEXT: psubusb {{.*}}(%rip), %xmm0 ; SSE-NEXT: retq ; ; AVX-LABEL: test5: -; AVX: ## BB#0: ## %vector.ph +; AVX: # BB#0: # %vector.ph ; AVX-NEXT: vpsubusb {{.*}}(%rip), %xmm0, %xmm0 ; AVX-NEXT: retq vector.ph: @@ -107,7 +107,7 @@ define <16 x i8> @test6(<16 x i8> %x, i8 zeroext %w) nounwind { ; SSE2-LABEL: test6: -; SSE2: ## BB#0: ## %vector.ph +; SSE2: # BB#0: # %vector.ph ; SSE2-NEXT: movd %edi, %xmm1 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,0,0,0,4,5,6,7] @@ -116,7 +116,7 @@ ; SSE2-NEXT: retq ; ; SSSE3-LABEL: test6: -; SSSE3: ## BB#0: ## %vector.ph +; SSSE3: # BB#0: # %vector.ph ; SSSE3-NEXT: movd %edi, %xmm1 ; SSSE3-NEXT: pxor %xmm2, %xmm2 ; SSSE3-NEXT: pshufb %xmm2, %xmm1 @@ -124,7 +124,7 @@ ; SSSE3-NEXT: retq ; ; SSE41-LABEL: test6: -; SSE41: ## BB#0: ## %vector.ph +; SSE41: # BB#0: # %vector.ph ; SSE41-NEXT: movd %edi, %xmm1 ; SSE41-NEXT: pxor %xmm2, %xmm2 ; SSE41-NEXT: pshufb %xmm2, %xmm1 @@ -132,7 +132,7 @@ ; SSE41-NEXT: retq ; ; AVX1-LABEL: test6: -; AVX1: ## BB#0: ## %vector.ph +; AVX1: # BB#0: # %vector.ph ; AVX1-NEXT: vmovd %edi, %xmm1 ; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1 @@ -140,7 +140,7 @@ ; AVX1-NEXT: retq ; ; AVX2-LABEL: test6: -; AVX2: ## BB#0: ## %vector.ph +; AVX2: # BB#0: # %vector.ph ; AVX2-NEXT: vmovd %edi, %xmm1 ; AVX2-NEXT: vpbroadcastb %xmm1, %xmm1 ; AVX2-NEXT: vpsubusb %xmm1, %xmm0, %xmm0 @@ -156,14 +156,14 @@ define <16 x i16> @test7(<16 x i16> %x) nounwind { ; SSE-LABEL: test7: -; SSE: ## BB#0: ## %vector.ph +; SSE: # BB#0: # %vector.ph ; SSE-NEXT: movdqa {{.*#+}} xmm2 = [32768,32768,32768,32768,32768,32768,32768,32768] ; SSE-NEXT: psubusw %xmm2, %xmm0 ; SSE-NEXT: psubusw %xmm2, %xmm1 ; SSE-NEXT: retq ; ; AVX1-LABEL: test7: -; AVX1: ## BB#0: ## %vector.ph +; AVX1: # BB#0: # %vector.ph ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; AVX1-NEXT: vpcmpgtw %xmm1, %xmm2, %xmm1 @@ -174,7 +174,7 @@ ; AVX1-NEXT: retq ; ; AVX2-LABEL: test7: -; AVX2: ## BB#0: ## %vector.ph +; AVX2: # BB#0: # %vector.ph ; AVX2-NEXT: vpsubusw {{.*}}(%rip), %ymm0, %ymm0 ; AVX2-NEXT: retq vector.ph: @@ -186,14 +186,14 @@ define <16 x i16> @test8(<16 x i16> %x) nounwind { ; SSE-LABEL: test8: -; SSE: ## BB#0: ## %vector.ph +; SSE: # BB#0: # %vector.ph ; SSE-NEXT: movdqa {{.*#+}} xmm2 = [32767,32767,32767,32767,32767,32767,32767,32767] ; SSE-NEXT: psubusw %xmm2, %xmm0 ; SSE-NEXT: psubusw %xmm2, %xmm1 ; SSE-NEXT: retq ; ; AVX1-LABEL: test8: -; AVX1: ## BB#0: ## %vector.ph +; AVX1: # BB#0: # %vector.ph ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [32768,32768,32768,32768,32768,32768,32768,32768] ; AVX1-NEXT: vpxor %xmm2, %xmm1, %xmm3 @@ -210,7 +210,7 @@ ; AVX1-NEXT: retq ; ; AVX2-LABEL: test8: -; AVX2: ## BB#0: ## %vector.ph +; AVX2: # BB#0: # %vector.ph ; AVX2-NEXT: vpsubusw {{.*}}(%rip), %ymm0, %ymm0 ; AVX2-NEXT: retq vector.ph: @@ -222,7 +222,7 @@ define <16 x i16> @test9(<16 x i16> %x, i16 zeroext %w) nounwind { ; SSE-LABEL: test9: -; SSE: ## BB#0: ## %vector.ph +; SSE: # BB#0: # %vector.ph ; SSE-NEXT: movd %edi, %xmm2 ; SSE-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,0,0,0,4,5,6,7] ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,0,1,1] @@ -231,7 +231,7 @@ ; SSE-NEXT: retq ; ; AVX1-LABEL: test9: -; AVX1: ## BB#0: ## %vector.ph +; AVX1: # BB#0: # %vector.ph ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vmovd %edi, %xmm2 ; AVX1-NEXT: vpshuflw {{.*#+}} xmm2 = xmm2[0,0,0,0,4,5,6,7] @@ -248,7 +248,7 @@ ; AVX1-NEXT: retq ; ; AVX2-LABEL: test9: -; AVX2: ## BB#0: ## %vector.ph +; AVX2: # BB#0: # %vector.ph ; AVX2-NEXT: vmovd %edi, %xmm1 ; AVX2-NEXT: vpbroadcastw %xmm1, %ymm1 ; AVX2-NEXT: vpsubusw %ymm1, %ymm0, %ymm0 @@ -264,14 +264,14 @@ define <32 x i8> @test10(<32 x i8> %x) nounwind { ; SSE-LABEL: test10: -; SSE: ## BB#0: ## %vector.ph +; SSE: # BB#0: # %vector.ph ; SSE-NEXT: movdqa {{.*#+}} xmm2 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128] ; SSE-NEXT: psubusb %xmm2, %xmm0 ; SSE-NEXT: psubusb %xmm2, %xmm1 ; SSE-NEXT: retq ; ; AVX1-LABEL: test10: -; AVX1: ## BB#0: ## %vector.ph +; AVX1: # BB#0: # %vector.ph ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; AVX1-NEXT: vpcmpgtb %xmm1, %xmm2, %xmm1 @@ -282,7 +282,7 @@ ; AVX1-NEXT: retq ; ; AVX2-LABEL: test10: -; AVX2: ## BB#0: ## %vector.ph +; AVX2: # BB#0: # %vector.ph ; AVX2-NEXT: vpsubusb {{.*}}(%rip), %ymm0, %ymm0 ; AVX2-NEXT: retq vector.ph: @@ -294,14 +294,14 @@ define <32 x i8> @test11(<32 x i8> %x) nounwind { ; SSE-LABEL: test11: -; SSE: ## BB#0: ## %vector.ph +; SSE: # BB#0: # %vector.ph ; SSE-NEXT: movdqa {{.*#+}} xmm2 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127] ; SSE-NEXT: psubusb %xmm2, %xmm0 ; SSE-NEXT: psubusb %xmm2, %xmm1 ; SSE-NEXT: retq ; ; AVX1-LABEL: test11: -; AVX1: ## BB#0: ## %vector.ph +; AVX1: # BB#0: # %vector.ph ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128] ; AVX1-NEXT: vpxor %xmm2, %xmm1, %xmm3 @@ -318,7 +318,7 @@ ; AVX1-NEXT: retq ; ; AVX2-LABEL: test11: -; AVX2: ## BB#0: ## %vector.ph +; AVX2: # BB#0: # %vector.ph ; AVX2-NEXT: vpsubusb {{.*}}(%rip), %ymm0, %ymm0 ; AVX2-NEXT: retq vector.ph: @@ -330,7 +330,7 @@ define <32 x i8> @test12(<32 x i8> %x, i8 zeroext %w) nounwind { ; SSE2-LABEL: test12: -; SSE2: ## BB#0: ## %vector.ph +; SSE2: # BB#0: # %vector.ph ; SSE2-NEXT: movd %edi, %xmm2 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] ; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,0,0,0,4,5,6,7] @@ -340,7 +340,7 @@ ; SSE2-NEXT: retq ; ; SSSE3-LABEL: test12: -; SSSE3: ## BB#0: ## %vector.ph +; SSSE3: # BB#0: # %vector.ph ; SSSE3-NEXT: movd %edi, %xmm2 ; SSSE3-NEXT: pxor %xmm3, %xmm3 ; SSSE3-NEXT: pshufb %xmm3, %xmm2 @@ -349,7 +349,7 @@ ; SSSE3-NEXT: retq ; ; SSE41-LABEL: test12: -; SSE41: ## BB#0: ## %vector.ph +; SSE41: # BB#0: # %vector.ph ; SSE41-NEXT: movd %edi, %xmm2 ; SSE41-NEXT: pxor %xmm3, %xmm3 ; SSE41-NEXT: pshufb %xmm3, %xmm2 @@ -358,7 +358,7 @@ ; SSE41-NEXT: retq ; ; AVX1-LABEL: test12: -; AVX1: ## BB#0: ## %vector.ph +; AVX1: # BB#0: # %vector.ph ; AVX1-NEXT: vmovd %edi, %xmm1 ; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1 @@ -375,7 +375,7 @@ ; AVX1-NEXT: retq ; ; AVX2-LABEL: test12: -; AVX2: ## BB#0: ## %vector.ph +; AVX2: # BB#0: # %vector.ph ; AVX2-NEXT: vmovd %edi, %xmm1 ; AVX2-NEXT: vpbroadcastb %xmm1, %ymm1 ; AVX2-NEXT: vpsubusb %ymm1, %ymm0, %ymm0 @@ -391,7 +391,7 @@ define <8 x i16> @test13(<8 x i16> %x, <8 x i32> %y) nounwind { ; SSE2-LABEL: test13: -; SSE2: ## BB#0: ## %vector.ph +; SSE2: # BB#0: # %vector.ph ; SSE2-NEXT: pxor %xmm4, %xmm4 ; SSE2-NEXT: movdqa %xmm0, %xmm3 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1],xmm3[2],xmm4[2],xmm3[3],xmm4[3] @@ -424,7 +424,7 @@ ; SSE2-NEXT: retq ; ; SSSE3-LABEL: test13: -; SSSE3: ## BB#0: ## %vector.ph +; SSSE3: # BB#0: # %vector.ph ; SSSE3-NEXT: pxor %xmm4, %xmm4 ; SSSE3-NEXT: movdqa %xmm0, %xmm3 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1],xmm3[2],xmm4[2],xmm3[3],xmm4[3] @@ -453,7 +453,7 @@ ; SSSE3-NEXT: retq ; ; SSE41-LABEL: test13: -; SSE41: ## BB#0: ## %vector.ph +; SSE41: # BB#0: # %vector.ph ; SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,3,0,1] ; SSE41-NEXT: pmovzxwd {{.*#+}} xmm4 = xmm3[0],zero,xmm3[1],zero,xmm3[2],zero,xmm3[3],zero ; SSE41-NEXT: pmovzxwd {{.*#+}} xmm3 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero @@ -480,7 +480,7 @@ ; SSE41-NEXT: retq ; ; AVX1-LABEL: test13: -; AVX1: ## BB#0: ## %vector.ph +; AVX1: # BB#0: # %vector.ph ; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[2,3,0,1] ; AVX1-NEXT: vpmovzxwd {{.*#+}} xmm2 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero ; AVX1-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero @@ -504,9 +504,9 @@ ; AVX1-NEXT: retq ; ; AVX2-LABEL: test13: -; AVX2: ## BB#0: ## %vector.ph +; AVX2: # BB#0: # %vector.ph ; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero -; AVX2-NEXT: vpbroadcastd {{.*}}(%rip), %ymm2 +; AVX2-NEXT: vpbroadcastd {{.*#+}} ymm2 = [2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648] ; AVX2-NEXT: vpxor %ymm2, %ymm1, %ymm3 ; AVX2-NEXT: vpxor %ymm2, %ymm0, %ymm2 ; AVX2-NEXT: vpcmpgtd %ymm2, %ymm3, %ymm2 @@ -529,7 +529,7 @@ define <16 x i8> @test14(<16 x i8> %x, <16 x i32> %y) nounwind { ; SSE2-LABEL: test14: -; SSE2: ## BB#0: ## %vector.ph +; SSE2: # BB#0: # %vector.ph ; SSE2-NEXT: movdqa %xmm0, %xmm5 ; SSE2-NEXT: pxor %xmm0, %xmm0 ; SSE2-NEXT: movdqa %xmm5, %xmm6 @@ -581,7 +581,7 @@ ; SSE2-NEXT: retq ; ; SSSE3-LABEL: test14: -; SSSE3: ## BB#0: ## %vector.ph +; SSSE3: # BB#0: # %vector.ph ; SSSE3-NEXT: pxor %xmm7, %xmm7 ; SSSE3-NEXT: movdqa %xmm0, %xmm11 ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm11 = xmm11[0],xmm7[0],xmm11[1],xmm7[1],xmm11[2],xmm7[2],xmm11[3],xmm7[3],xmm11[4],xmm7[4],xmm11[5],xmm7[5],xmm11[6],xmm7[6],xmm11[7],xmm7[7] @@ -636,7 +636,7 @@ ; SSSE3-NEXT: retq ; ; SSE41-LABEL: test14: -; SSE41: ## BB#0: ## %vector.ph +; SSE41: # BB#0: # %vector.ph ; SSE41-NEXT: movdqa %xmm0, %xmm5 ; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm5[1,1,2,3] ; SSE41-NEXT: pmovzxbd {{.*#+}} xmm8 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero @@ -689,7 +689,7 @@ ; SSE41-NEXT: retq ; ; AVX1-LABEL: test14: -; AVX1: ## BB#0: ## %vector.ph +; AVX1: # BB#0: # %vector.ph ; AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,2,3] ; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm8 = xmm3[0],zero,zero,zero,xmm3[1],zero,zero,zero,xmm3[2],zero,zero,zero,xmm3[3],zero,zero,zero ; AVX1-NEXT: vpmovzxbd {{.*#+}} xmm9 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero @@ -733,11 +733,11 @@ ; AVX1-NEXT: retq ; ; AVX2-LABEL: test14: -; AVX2: ## BB#0: ## %vector.ph +; AVX2: # BB#0: # %vector.ph ; AVX2-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[2,3,0,1] ; AVX2-NEXT: vpmovzxbd {{.*#+}} ymm3 = xmm3[0],zero,zero,zero,xmm3[1],zero,zero,zero,xmm3[2],zero,zero,zero,xmm3[3],zero,zero,zero,xmm3[4],zero,zero,zero,xmm3[5],zero,zero,zero,xmm3[6],zero,zero,zero,xmm3[7],zero,zero,zero ; AVX2-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero -; AVX2-NEXT: vpbroadcastd {{.*}}(%rip), %ymm4 +; AVX2-NEXT: vpbroadcastd {{.*#+}} ymm4 = [2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648] ; AVX2-NEXT: vpxor %ymm4, %ymm1, %ymm5 ; AVX2-NEXT: vpxor %ymm4, %ymm0, %ymm6 ; AVX2-NEXT: vpcmpgtd %ymm5, %ymm6, %ymm5 @@ -775,7 +775,7 @@ define <8 x i16> @test15(<8 x i16> %x, <8 x i32> %y) nounwind { ; SSE2-LABEL: test15: -; SSE2: ## BB#0: ## %vector.ph +; SSE2: # BB#0: # %vector.ph ; SSE2-NEXT: pxor %xmm4, %xmm4 ; SSE2-NEXT: movdqa %xmm0, %xmm3 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1],xmm3[2],xmm4[2],xmm3[3],xmm4[3] @@ -808,7 +808,7 @@ ; SSE2-NEXT: retq ; ; SSSE3-LABEL: test15: -; SSSE3: ## BB#0: ## %vector.ph +; SSSE3: # BB#0: # %vector.ph ; SSSE3-NEXT: pxor %xmm4, %xmm4 ; SSSE3-NEXT: movdqa %xmm0, %xmm3 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1],xmm3[2],xmm4[2],xmm3[3],xmm4[3] @@ -836,7 +836,7 @@ ; SSSE3-NEXT: retq ; ; SSE41-LABEL: test15: -; SSE41: ## BB#0: ## %vector.ph +; SSE41: # BB#0: # %vector.ph ; SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,3,0,1] ; SSE41-NEXT: pmovzxwd {{.*#+}} xmm3 = xmm3[0],zero,xmm3[1],zero,xmm3[2],zero,xmm3[3],zero ; SSE41-NEXT: pmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero @@ -862,7 +862,7 @@ ; SSE41-NEXT: retq ; ; AVX1-LABEL: test15: -; AVX1: ## BB#0: ## %vector.ph +; AVX1: # BB#0: # %vector.ph ; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[2,3,0,1] ; AVX1-NEXT: vpmovzxwd {{.*#+}} xmm2 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero ; AVX1-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero @@ -886,9 +886,9 @@ ; AVX1-NEXT: retq ; ; AVX2-LABEL: test15: -; AVX2: ## BB#0: ## %vector.ph +; AVX2: # BB#0: # %vector.ph ; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero -; AVX2-NEXT: vpbroadcastd {{.*}}(%rip), %ymm2 +; AVX2-NEXT: vpbroadcastd {{.*#+}} ymm2 = [2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648] ; AVX2-NEXT: vpxor %ymm2, %ymm1, %ymm3 ; AVX2-NEXT: vpxor %ymm2, %ymm0, %ymm2 ; AVX2-NEXT: vpcmpgtd %ymm3, %ymm2, %ymm2 @@ -911,7 +911,7 @@ define <8 x i16> @test16(<8 x i16> %x, <8 x i32> %y) nounwind { ; SSE2-LABEL: test16: -; SSE2: ## BB#0: ## %vector.ph +; SSE2: # BB#0: # %vector.ph ; SSE2-NEXT: pxor %xmm4, %xmm4 ; SSE2-NEXT: movdqa %xmm0, %xmm3 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1],xmm3[2],xmm4[2],xmm3[3],xmm4[3] @@ -944,7 +944,7 @@ ; SSE2-NEXT: retq ; ; SSSE3-LABEL: test16: -; SSSE3: ## BB#0: ## %vector.ph +; SSSE3: # BB#0: # %vector.ph ; SSSE3-NEXT: pxor %xmm4, %xmm4 ; SSSE3-NEXT: movdqa %xmm0, %xmm3 ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1],xmm3[2],xmm4[2],xmm3[3],xmm4[3] @@ -972,7 +972,7 @@ ; SSSE3-NEXT: retq ; ; SSE41-LABEL: test16: -; SSE41: ## BB#0: ## %vector.ph +; SSE41: # BB#0: # %vector.ph ; SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,3,0,1] ; SSE41-NEXT: pmovzxwd {{.*#+}} xmm3 = xmm3[0],zero,xmm3[1],zero,xmm3[2],zero,xmm3[3],zero ; SSE41-NEXT: pmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero @@ -998,7 +998,7 @@ ; SSE41-NEXT: retq ; ; AVX1-LABEL: test16: -; AVX1: ## BB#0: ## %vector.ph +; AVX1: # BB#0: # %vector.ph ; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm0[2,3,0,1] ; AVX1-NEXT: vpmovzxwd {{.*#+}} xmm2 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero ; AVX1-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero @@ -1022,9 +1022,9 @@ ; AVX1-NEXT: retq ; ; AVX2-LABEL: test16: -; AVX2: ## BB#0: ## %vector.ph +; AVX2: # BB#0: # %vector.ph ; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero -; AVX2-NEXT: vpbroadcastd {{.*}}(%rip), %ymm2 +; AVX2-NEXT: vpbroadcastd {{.*#+}} ymm2 = [2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648,2147483648] ; AVX2-NEXT: vpxor %ymm2, %ymm1, %ymm3 ; AVX2-NEXT: vpxor %ymm2, %ymm0, %ymm2 ; AVX2-NEXT: vpcmpgtd %ymm3, %ymm2, %ymm2