Index: lib/Target/Mips/MipsISelLowering.cpp
===================================================================
--- lib/Target/Mips/MipsISelLowering.cpp
+++ lib/Target/Mips/MipsISelLowering.cpp
@@ -4063,7 +4063,12 @@
 
   // Create frame object.
   EVT PtrTy = getPointerTy(DAG.getDataLayout());
-  int FI = MFI.CreateFixedObject(FrameObjSize, FrameObjOffset, true);
+  // Make the fixed object stored to mutable so that the load instructions 
+  // referencing it have their memory dependencies added.
+  // Set the frame object as isAliased which clears the underlying objects 
+  // vector in ScheduleDAGInstrs::buildSchedGraph() resulting in addition of all
+  // stores as dependencies for loads referencing this fixed object.
+  int FI = MFI.CreateFixedObject(FrameObjSize, FrameObjOffset, false, true);
   SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
   InVals.push_back(FIN);
 
Index: test/CodeGen/Mips/fastcc_byval.ll
===================================================================
--- test/CodeGen/Mips/fastcc_byval.ll
+++ test/CodeGen/Mips/fastcc_byval.ll
@@ -0,0 +1,27 @@
+; RUN: llc -mtriple=mipsel-linux-gnu -O3 -relocation-model=pic < %s | FileCheck %s
+
+; Test that a load comes after a store to the same memory location when passing 
+; a byVal parameter to a function which has a fastcc function call
+
+%struct.str = type { i32, i32, [3 x i32*] }
+
+declare fastcc void @_Z1F3str(%struct.str* noalias nocapture sret %agg.result, %struct.str* byval nocapture readonly align 4 %s)
+
+define i32 @_Z1g3str(%struct.str* byval nocapture readonly align 4 %s) {
+; CHECK-LABEL: _Z1g3str:
+; CHECK: sw  $7, [[OFFSET:[0-9]+]]($sp)
+; CHECK: lw  ${{[0-9]+}}, [[OFFSET]]($sp)
+entry:
+  %ref.tmp = alloca %struct.str, align 4
+  %0 = bitcast %struct.str* %ref.tmp to i8*
+  call void @llvm.lifetime.start.p0i8(i64 20, i8* nonnull %0)
+  call fastcc void @_Z1F3str(%struct.str* nonnull sret %ref.tmp, %struct.str* byval nonnull align 4 %s)
+  %cl.sroa.3.0..sroa_idx2 = getelementptr inbounds %struct.str, %struct.str* %ref.tmp, i32 0, i32 1
+  %cl.sroa.3.0.copyload = load i32, i32* %cl.sroa.3.0..sroa_idx2, align 4
+  call void @llvm.lifetime.end.p0i8(i64 20, i8* nonnull %0)
+  ret i32 %cl.sroa.3.0.copyload
+}
+
+declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture)
+
+declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture)
Index: test/CodeGen/Mips/o32_cc_byval.ll
===================================================================
--- test/CodeGen/Mips/o32_cc_byval.ll
+++ test/CodeGen/Mips/o32_cc_byval.ll
@@ -243,10 +243,9 @@
 ; CHECK-NEXT:    lw $7, 52($sp)
 ; CHECK-NEXT:    lw $6, 48($sp)
 ; CHECK-NEXT:    lw $5, 44($sp)
-; CHECK-NEXT:    lw $4, 40($sp)
 ; CHECK-NEXT:    lw $25, %call16(f6)($gp)
 ; CHECK-NEXT:    jalr $25
-; CHECK-NEXT:    nop
+; CHECK-NEXT:    lw $4, 40($sp)
 ; CHECK-NEXT:    lw $ra, 28($sp) # 4-byte Folded Reload
 ; CHECK-NEXT:    jr $ra
 ; CHECK-NEXT:    addiu $sp, $sp, 32