Index: include/llvm/IR/IntrinsicsPowerPC.td
===================================================================
--- include/llvm/IR/IntrinsicsPowerPC.td
+++ include/llvm/IR/IntrinsicsPowerPC.td
@@ -57,6 +57,8 @@
   def int_ppc_bpermd : GCCBuiltin<"__builtin_bpermd">,
                        Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty],
                                  [IntrNoMem]>;
+  def int_ppc_popcntb : GCCBuiltin<"__builtin_popcntb">,
+                       Intrinsic<[llvm_i64_ty], [llvm_i64_ty], [IntrNoMem]>;
 }
 
 
Index: lib/Target/PowerPC/PPC.td
===================================================================
--- lib/Target/PowerPC/PPC.td
+++ lib/Target/PowerPC/PPC.td
@@ -163,7 +163,7 @@
                    [FeatureVSX]>;
 def FeaturePOPCNTD   : SubtargetFeature<"popcntd","HasPOPCNTD",
                                         "POPCNTD_Fast",
-                                        "Enable the popcnt[dw] instructions">;
+                                        "Enable the popcnt[dwb] instructions">;
 // Note that for the a2/a2q processor models we should not use popcnt[dw] by
 // default. These processors do support the instructions, but they're
 // microcoded, and the software emulation is about twice as fast.
@@ -225,7 +225,6 @@
 // recent ISA levels:
 //
 // DFP          p6, p6x, p7        decimal floating-point instructions
-// POPCNTB      p5 through p7      popcntb and related instructions
 
 //===----------------------------------------------------------------------===//
 // Classes used for relation maps.
Index: lib/Target/PowerPC/PPCInstr64Bit.td
===================================================================
--- lib/Target/PowerPC/PPCInstr64Bit.td
+++ lib/Target/PowerPC/PPCInstr64Bit.td
@@ -673,6 +673,11 @@
                        "popcntw $rA, $rS", IIC_IntGeneral,
                        [(set i32:$rA, (ctpop i32:$rS))]>;
 
+// popcntb sets a popcount in each byte.
+def POPCNTB : XForm_11<31, 122, (outs g8rc:$rA), (ins g8rc:$rS),
+                       "popcntb $rA, $rS", IIC_IntGeneral,
+                       [(set i64:$rA, (int_ppc_popcntb g8rc:$rS))]>;
+
 defm DIVD  : XOForm_1rcr<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
                           "divd", "$rT, $rA, $rB", IIC_IntDivD,
                           [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64;
Index: test/MC/Disassembler/PowerPC/ppc64-encoding.txt
===================================================================
--- test/MC/Disassembler/PowerPC/ppc64-encoding.txt
+++ test/MC/Disassembler/PowerPC/ppc64-encoding.txt
@@ -565,6 +565,9 @@
 # CHECK: popcntd 2, 3                    
 0x7c 0x62 0x03 0xf4
 
+# CHECK: popcntb 2, 3
+0x7c 0x62 0x00 0xf4
+
 # CHECK: bpermd 2, 3, 4
 0x7c 0x62 0x21 0xf8
 
Index: test/MC/PowerPC/ppc64-encoding.s
===================================================================
--- test/MC/PowerPC/ppc64-encoding.s
+++ test/MC/PowerPC/ppc64-encoding.s
@@ -726,7 +726,9 @@
             cmpb 7, 21, 4
 # CHECK-BE: cmpb 7, 21, 4                   # encoding: [0x7e,0xa7,0x23,0xf8]
 # CHECK-LE: cmpb 7, 21, 4                   # encoding: [0xf8,0x23,0xa7,0x7e]
-# FIXME:    popcntb 2, 3
+            popcntb 2, 3
+# CHECK-BE: popcntb 2, 3                    # encoding: [0x7c,0x62,0x00,0xf4]
+# CHECK-LE: popcntb 2, 3                    # encoding: [0xf4,0x00,0x62,0x7c]
 # CHECK-BE: popcntw 2, 3                    # encoding: [0x7c,0x62,0x02,0xf4]
 # CHECK-LE: popcntw 2, 3                    # encoding: [0xf4,0x02,0x62,0x7c]
             popcntw 2, 3