Index: lib/CodeGen/SelectionDAG/DAGCombiner.cpp =================================================================== --- lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -15489,7 +15489,8 @@ static SDValue combineShuffleToVectorExtend(ShuffleVectorSDNode *SVN, SelectionDAG &DAG, const TargetLowering &TLI, - bool LegalOperations) { + bool LegalOperations, + bool LegalTypes) { EVT VT = SVN->getValueType(0); bool IsBigEndian = DAG.getDataLayout().isBigEndian(); @@ -15522,9 +15523,10 @@ EVT OutSVT = EVT::getIntegerVT(*DAG.getContext(), EltSizeInBits * Scale); EVT OutVT = EVT::getVectorVT(*DAG.getContext(), OutSVT, NumElts / Scale); - if (!LegalOperations || - TLI.isOperationLegalOrCustom(ISD::ANY_EXTEND_VECTOR_INREG, OutVT)) - return DAG.getBitcast(VT, + if (!LegalTypes || TLI.isTypeLegal(OutVT)) + if (!LegalOperations || + TLI.isOperationLegalOrCustom(ISD::ANY_EXTEND_VECTOR_INREG, OutVT)) + return DAG.getBitcast(VT, DAG.getAnyExtendVectorInReg(N0, SDLoc(SVN), OutVT)); } @@ -15755,7 +15757,7 @@ return S; // Match shuffles that can be converted to any_vector_extend_in_reg. - if (SDValue V = combineShuffleToVectorExtend(SVN, DAG, TLI, LegalOperations)) + if (SDValue V = combineShuffleToVectorExtend(SVN, DAG, TLI, LegalOperations, LegalTypes)) return V; // Combine "truncate_vector_in_reg" style shuffles. Index: test/CodeGen/X86/pr34397.ll =================================================================== --- /dev/null +++ test/CodeGen/X86/pr34397.ll @@ -0,0 +1,22 @@ +target triple = "x86_64-unknown-linux-gnu" + +define internal fastcc <32 x i64> @test(<32 x i64> %s.0.6, <32 x i64> %s.0.7) { +entry: + %s.1.6 = shufflevector <32 x i64> %s.0.6, <32 x i64> %s.0.7, <32 x i32> + %s.2.5 = shufflevector <32 x i64> undef, <32 x i64> %s.1.6, <32 x i32> + %s.3.4 = shufflevector <32 x i64> undef, <32 x i64> %s.2.5, <32 x i32> + %s.4.4 = shufflevector <32 x i64> %s.3.4, <32 x i64> undef, <32 x i32> + %s.5.4 = shufflevector <32 x i64> %s.4.4, <32 x i64> undef, <32 x i32> + %s.6.3 = shufflevector <32 x i64> undef, <32 x i64> %s.5.4, <32 x i32> + %s.7.2 = shufflevector <32 x i64> undef, <32 x i64> %s.6.3, <32 x i32> + %s.8.2 = shufflevector <32 x i64> %s.7.2, <32 x i64> zeroinitializer, <32 x i32> + %s.9.2 = shufflevector <32 x i64> %s.8.2, <32 x i64> undef, <32 x i32> + %s.10.1 = shufflevector <32 x i64> undef, <32 x i64> %s.9.2, <32 x i32> + %s.11.1 = shufflevector <32 x i64> %s.10.1, <32 x i64> undef, <32 x i32> + %s.12.1 = shufflevector <32 x i64> %s.11.1, <32 x i64> undef, <32 x i32> + %s.13.1 = shufflevector <32 x i64> %s.12.1, <32 x i64> undef, <32 x i32> + %s.14.0 = shufflevector <32 x i64> undef, <32 x i64> %s.13.1, <32 x i32> + %s.15.0 = shufflevector <32 x i64> %s.14.0, <32 x i64> undef, <32 x i32> + %s.16.0 = shufflevector <32 x i64> %s.15.0, <32 x i64> undef, <32 x i32> + ret <32 x i64> %s.16.0 +}