Index: lib/Target/Mips/Mips32r6InstrInfo.td
===================================================================
--- lib/Target/Mips/Mips32r6InstrInfo.td
+++ lib/Target/Mips/Mips32r6InstrInfo.td
@@ -88,6 +88,13 @@
 class BEQZC_ENC  : CMP_BRANCH_OFF21_FM<0b110110>;
 class BNEZC_ENC  : CMP_BRANCH_OFF21_FM<0b111110>;
 
+class BLEZALC_ENC: CMP_BRANCH_RT_OFF16_FM<0b000110>;
+class BGEZALC_ENC: CMP_BRANCH_OFF16_FM<0b000110>;
+class BGTZALC_ENC: CMP_BRANCH_RT_OFF16_FM<0b000111>;
+class BLTZALC_ENC: CMP_BRANCH_OFF16_FM<0b000111>;
+class BEQZALC_ENC: CMP_BRANCH_RT_OFF16_FM<0b001000>;
+class BNEZALC_ENC: CMP_BRANCH_RT_OFF16_FM<0b011000>;
+
 class MUH_ENC    : SPECIAL_3R_FM<0b00011, 0b011000>;
 class MUHU_ENC   : SPECIAL_3R_FM<0b00011, 0b011001>;
 class MUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011000>;
@@ -158,6 +165,31 @@
 class BEQZC_DESC  : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21, GPR32Opnd>;
 class BNEZC_DESC  : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21, GPR32Opnd>;
 
+class BEQZALC_DESC  : CMP_CBR_RT_Z_DESC_BASE<"beqzalc", brtarget, GPR32Opnd> {
+  list<Register> Defs = [RA];
+}
+
+class BGEZALC_DESC  : CMP_CBR_RT_Z_DESC_BASE<"bgezalc", brtarget, GPR32Opnd> {
+  string Constraints = "$rs = $rt";
+  list<Register> Defs = [RA];
+}
+
+class BGTZALC_DESC  : CMP_CBR_RT_Z_DESC_BASE<"bgtzalc", brtarget, GPR32Opnd> {
+  list<Register> Defs = [RA];
+}
+
+class BLEZALC_DESC  : CMP_CBR_RT_Z_DESC_BASE<"blezalc", brtarget, GPR32Opnd> {
+  list<Register> Defs = [RA];
+}
+
+class BLTZALC_DESC  : CMP_CBR_RT_Z_DESC_BASE<"bltzalc", brtarget, GPR32Opnd> {
+  string Constraints = "$rs = $rt";
+  list<Register> Defs = [RA];
+}
+
+class BNEZALC_DESC  : CMP_CBR_RT_Z_DESC_BASE<"bnezalc", brtarget, GPR32Opnd> {
+  list<Register> Defs = [RA];
+}
 class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
   dag OutOperandList = (outs GPROpnd:$rd);
   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
@@ -188,23 +220,23 @@
 def BC2NEZ;
 def BC        : BC_ENC, BC_DESC, ISA_MIPS32R6;
 def BEQC      : BEQC_ENC, BEQC_DESC, ISA_MIPS32R6;
-def BEQZALC;
+def BEQZALC   : BEQZALC_ENC, BEQZALC_DESC, ISA_MIPS32R6;
 def BEQZC     : BEQZC_ENC, BEQZC_DESC, ISA_MIPS32R6;
 def BGEC;  // Also aliased to blec with operands swapped
 def BGEUC; // Also aliased to bleuc with operands swapped
-def BGEZALC;
+def BGEZALC   : BGEZALC_ENC, BGEZALC_DESC, ISA_MIPS32R6;
 def BGEZC     : BGEZC_ENC, BGEZC_DESC, ISA_MIPS32R6;
-def BGTZALC;
+def BGTZALC   : BGTZALC_ENC, BGTZALC_DESC, ISA_MIPS32R6;
 def BGTZC     : BGTZC_ENC, BGTZC_DESC, ISA_MIPS32R6;
 def BITSWAP; // Known as BITREV in DSP ASE
-def BLEZALC;
+def BLEZALC   :BLEZALC_ENC, BLEZALC_DESC, ISA_MIPS32R6;
 def BLEZC     : BLEZC_ENC, BLEZC_DESC, ISA_MIPS32R6;
 def BLTC; // Also aliased to bgtc with operands swapped
 def BLTUC; // Also aliased to bgtuc with operands swapped
-def BLTZALC;
+def BLTZALC   : BLTZALC_ENC, BLTZALC_DESC, ISA_MIPS32R6;
 def BLTZC     : BLTZC_ENC, BLTZC_DESC, ISA_MIPS32R6;
 def BNEC      : BNEC_ENC, BNEC_DESC, ISA_MIPS32R6;
-def BNEZALC;
+def BNEZALC   : BNEZALC_ENC, BNEZALC_DESC, ISA_MIPS32R6;
 def BNEZC     : BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6;
 def BNVC;
 def BOVC;
Index: test/MC/Mips/mips32r6/valid.s
===================================================================
--- test/MC/Mips/mips32r6/valid.s
+++ test/MC/Mips/mips32r6/valid.s
@@ -4,6 +4,12 @@
 
         .set noat
         # FIXME: Add the instructions carried forward from older ISA's
+        blezalc $2,1332          # CHECK: blezalc $2,1332  # encoding: [0x18,0x02,0x01,0x4d]
+        bgezalc $2,1332          # CHECK: bgezalc $2,1332  # encoding: [0x18,0x42,0x01,0x4d]
+        bgtzalc $2,1332          # CHECK: bgtzalc $2,1332  # encoding: [0x1c,0x02,0x01,0x4d]
+        bltzalc $2,1332          # CHECK: bltzalc $2,1332  # encoding: [0x1c,0x42,0x01,0x4d]
+        beqzalc $2,1332          # CHECK: beqzalc $2,1332  # encoding: [0x20,0x02,0x01,0x4d]
+        bnezalc $2,1332          # CHECK: bnezalc $2,1332  # encoding: [0x60,0x02,0x01,0x4d]
         mul     $2,$3,$4         # CHECK: mul $2, $3, $4   # encoding: [0x00,0x64,0x10,0x98]
         muh     $2,$3,$4         # CHECK: muh $2, $3, $4   # encoding: [0x00,0x64,0x10,0xd8]
         mulu    $2,$3,$4         # CHECK: mulu $2, $3, $4  # encoding: [0x00,0x64,0x10,0x99]
Index: test/MC/Mips/mips64r6/valid.s
===================================================================
--- test/MC/Mips/mips64r6/valid.s
+++ test/MC/Mips/mips64r6/valid.s
@@ -4,6 +4,12 @@
 
         .set noat
         # FIXME: Add the instructions carried forward from older ISA's
+        blezalc $2,1332          # CHECK: blezalc $2,1332  # encoding: [0x18,0x02,0x01,0x4d]
+        bgezalc $2,1332          # CHECK: bgezalc $2,1332  # encoding: [0x18,0x42,0x01,0x4d]
+        bgtzalc $2,1332          # CHECK: bgtzalc $2,1332  # encoding: [0x1c,0x02,0x01,0x4d]
+        bltzalc $2,1332          # CHECK: bltzalc $2,1332  # encoding: [0x1c,0x42,0x01,0x4d]
+        beqzalc $2,1332          # CHECK: beqzalc $2,1332  # encoding: [0x20,0x02,0x01,0x4d]
+        bnezalc $2,1332          # CHECK: bnezalc $2,1332  # encoding: [0x60,0x02,0x01,0x4d]
         mul     $2,$3,$4         # CHECK: mul $2, $3, $4   # encoding: [0x00,0x64,0x10,0x98]
         muh     $2,$3,$4         # CHECK: muh $2, $3, $4   # encoding: [0x00,0x64,0x10,0xd8]
         mulu    $2,$3,$4         # CHECK: mulu $2, $3, $4  # encoding: [0x00,0x64,0x10,0x99]