Index: lib/Target/Mips/Mips32r6InstrFormats.td
===================================================================
--- lib/Target/Mips/Mips32r6InstrFormats.td
+++ lib/Target/Mips/Mips32r6InstrFormats.td
@@ -87,3 +87,18 @@
   let Inst{20-16} = rt;
   let Inst{15-0}  = offset;
 }
+
+class MAX_MIN_FM<bits<6> funct, bits<5> fmt> : MipsR6Inst {
+  bits<5> fd;
+  bits<5> fs;
+  bits<5> ft;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 0b010001;
+  let Inst{25-21} = fmt;
+  let Inst{20-16} = ft;
+  let Inst{15-11} = fs;
+  let Inst{10-6}  = fd;
+  let Inst{5-0}   = funct;
+}
Index: lib/Target/Mips/Mips32r6InstrInfo.td
===================================================================
--- lib/Target/Mips/Mips32r6InstrInfo.td
+++ lib/Target/Mips/Mips32r6InstrInfo.td
@@ -101,6 +101,16 @@
 class JIALC_ENC  : JMP_IDX_COMPACT_FM<0b111110>;
 class JIC_ENC    : JMP_IDX_COMPACT_FM<0b110110>;
 
+class MAX_S_ENC  : MAX_MIN_FM<0b011101, 0b10000>;
+class MAX_D_ENC  : MAX_MIN_FM<0b011101, 0b10001>;
+class MIN_S_ENC  : MAX_MIN_FM<0b011100, 0b10000>;
+class MIN_D_ENC  : MAX_MIN_FM<0b011100, 0b10001>;
+
+class MAXA_S_ENC  : MAX_MIN_FM<0b011111, 0b10000>;
+class MAXA_D_ENC  : MAX_MIN_FM<0b011111, 0b10001>;
+class MINA_S_ENC  : MAX_MIN_FM<0b011110, 0b10000>;
+class MINA_D_ENC  : MAX_MIN_FM<0b011110, 0b10001>;
+
 class MUH_ENC    : SPECIAL_3R_FM<0b00011, 0b011000>;
 class MUHU_ENC   : SPECIAL_3R_FM<0b00011, 0b011001>;
 class MUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011000>;
@@ -192,6 +202,23 @@
   list<Register> Defs = [AT];
 }
 
+class MAX_MIN_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
+  dag OutOperandList = (outs FGROpnd:$fd);
+  dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
+  string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
+  list<dag> Pattern = [];
+}
+
+class MAX_S_DESC  : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>;
+class MAX_D_DESC  : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>;
+class MIN_S_DESC  : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>;
+class MIN_D_DESC  : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>;
+
+class MAXA_S_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>;
+class MAXA_D_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>;
+class MINA_S_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>;
+class MINA_D_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>;
+
 class MUL_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
   dag OutOperandList = (outs GPROpnd:$rd);
   dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
@@ -254,13 +281,14 @@
 def LWPC;
 def LWUPC;
 def MADDF;
-def MAXA_D;
-def MAXA_S;
-def MAX_D;
-def MAX_S;
-def MINA_D;
-def MINA_S;
-def MIN_D;
+def MAXA_D    : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6;
+def MAXA_S    : MAXA_S_ENC, MAXA_S_DESC, ISA_MIPS32R6;
+def MAX_D     : MAX_D_ENC, MAX_D_DESC, ISA_MIPS32R6;
+def MAX_S     : MAX_S_ENC, MAX_S_DESC, ISA_MIPS32R6;
+def MINA_D    : MINA_D_ENC, MINA_D_DESC, ISA_MIPS32R6;
+def MINA_S    : MINA_S_ENC, MINA_S_DESC, ISA_MIPS32R6;
+def MIN_D     : MIN_D_ENC, MIN_D_DESC, ISA_MIPS32R6;
+def MIN_S     : MIN_S_ENC, MIN_S_DESC, ISA_MIPS32R6;
 def MOD;
 def MODU;
 def MSUBF;
Index: test/MC/Mips/mips32r6/valid.s
===================================================================
--- test/MC/Mips/mips32r6/valid.s
+++ test/MC/Mips/mips32r6/valid.s
@@ -20,3 +20,11 @@
         bgtzc   $5, 256          # CHECK: bgtzc $5, 256    # encoding: [0x5c,0x05,0x00,0x40]
         jialc   $5, 256          # CHECK: jialc $5, 256    # encoding: [0xf8,0x05,0x01,0x00]
         jic     $5, 256          # CHECK: jic $5, 256      # encoding: [0xd8,0x05,0x01,0x00]
+        max.s   $f0, $f2, $f4    # CHECK: max.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1d]
+        max.d   $f0, $f2, $f4    # CHECK: max.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1d]
+        min.s   $f0, $f2, $f4    # CHECK: min.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1c]
+        min.d   $f0, $f2, $f4    # CHECK: min.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1c]
+        maxa.s  $f0, $f2, $f4    # CHECK: maxa.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1f]
+        maxa.d  $f0, $f2, $f4    # CHECK: maxa.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1f]
+        mina.s  $f0, $f2, $f4    # CHECK: mina.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1e]
+        mina.d  $f0, $f2, $f4    # CHECK: mina.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1e]
Index: test/MC/Mips/mips64r6/valid.s
===================================================================
--- test/MC/Mips/mips64r6/valid.s
+++ test/MC/Mips/mips64r6/valid.s
@@ -24,3 +24,11 @@
         bgtzc   $5, 256          # CHECK: bgtzc $5, 256    # encoding: [0x5c,0x05,0x00,0x40]
         jialc   $5, 256          # CHECK: jialc $5, 256    # encoding: [0xf8,0x05,0x01,0x00]
         jic     $5, 256          # CHECK: jic $5, 256      # encoding: [0xd8,0x05,0x01,0x00]
+        max.s   $f0, $f2, $f4    # CHECK: max.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1d]
+        max.d   $f0, $f2, $f4    # CHECK: max.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1d]
+        min.s   $f0, $f2, $f4    # CHECK: min.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1c]
+        min.d   $f0, $f2, $f4    # CHECK: min.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1c]
+        maxa.s  $f0, $f2, $f4    # CHECK: maxa.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1f]
+        maxa.d  $f0, $f2, $f4    # CHECK: maxa.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1f]
+        mina.s  $f0, $f2, $f4    # CHECK: mina.s $f0, $f2, $f4 # encoding: [0x46,0x04,0x10,0x1e]
+        mina.d  $f0, $f2, $f4    # CHECK: mina.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x1e]