Index: lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp =================================================================== --- lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -8645,7 +8645,8 @@ for (unsigned i = 0, e = Ins.size(); i != e; ++i) { assert(InVals[i].getNode() && "LowerFormalArguments emitted a null value!"); - assert(EVT(Ins[i].VT) == InVals[i].getValueType() && + assert((EVT(Ins[i].VT) == InVals[i].getValueType() || + EVT(Ins[i].ArgVT) == InVals[i].getValueType()) && "LowerFormalArguments emitted a value with the wrong type!"); } }); Index: lib/Target/X86/X86ISelLowering.cpp =================================================================== --- lib/Target/X86/X86ISelLowering.cpp +++ lib/Target/X86/X86ISelLowering.cpp @@ -2997,25 +2997,28 @@ // right size. if (VA.getLocInfo() == CCValAssign::SExt) ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, - DAG.getValueType(VA.getValVT())); + DAG.getValueType(Ins[InsIndex].ArgVT)); else if (VA.getLocInfo() == CCValAssign::ZExt) ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, - DAG.getValueType(VA.getValVT())); + DAG.getValueType(Ins[InsIndex].ArgVT)); else if (VA.getLocInfo() == CCValAssign::BCvt) ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue); if (VA.isExtInLoc()) { // Handle MMX values passed in XMM regs. - if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1) + if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1) { ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue); - else if (VA.getValVT().isVector() && + } else if (VA.getValVT().isVector() && VA.getValVT().getScalarType() == MVT::i1 && ((VA.getLocVT() == MVT::i64) || (VA.getLocVT() == MVT::i32) || (VA.getLocVT() == MVT::i16) || (VA.getLocVT() == MVT::i8))) { // Promoting a mask type (v*i1) into a register of type i64/i32/i16/i8 ArgValue = lowerRegToMasks(ArgValue, VA.getValVT(), RegVT, dl, DAG); - } else + } else if (!Ins[InsIndex].ArgVT.isVector() && !VA.getValVT().isVector()) { + ArgValue = DAG.getNode(ISD::TRUNCATE, dl, Ins[InsIndex].ArgVT, ArgValue); + } else { ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); + } } } else { assert(VA.isMemLoc()); Index: test/CodeGen/X86/bool-zext.ll =================================================================== --- test/CodeGen/X86/bool-zext.ll +++ test/CodeGen/X86/bool-zext.ll @@ -2,7 +2,7 @@ ; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s -check-prefix=X32 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s -check-prefix=X64 -; Check that the argument gets zero-extended before calling. +; It's not necessary to zero-extend the arg because it is specified 'zeroext'. define void @bar1(i1 zeroext %v1) nounwind ssp { ; X32-LABEL: bar1: ; X32: # BB#0: @@ -14,7 +14,6 @@ ; ; X64-LABEL: bar1: ; X64: # BB#0: -; X64-NEXT: movzbl %dil, %edi ; X64-NEXT: xorl %eax, %eax ; X64-NEXT: jmp foo1 # TAILCALL %conv = zext i1 %v1 to i32 Index: test/CodeGen/X86/critical-edge-split-2.ll =================================================================== --- test/CodeGen/X86/critical-edge-split-2.ll +++ test/CodeGen/X86/critical-edge-split-2.ll @@ -12,7 +12,7 @@ ; CHECK-LABEL: test1: ; CHECK: # BB#0: # %entry ; CHECK-NEXT: movw $1, %ax -; CHECK-NEXT: testb %dil, %dil +; CHECK-NEXT: testl %edi, %edi ; CHECK-NEXT: jne .LBB0_2 ; CHECK-NEXT: # BB#1: # %cond.false.i ; CHECK-NEXT: movl $g_4, %eax Index: test/CodeGen/X86/fp128-select.ll =================================================================== --- test/CodeGen/X86/fp128-select.ll +++ test/CodeGen/X86/fp128-select.ll @@ -11,7 +11,7 @@ define void @test_select(fp128* %p, fp128* %q, i1 zeroext %c) { ; MMX-LABEL: test_select: ; MMX: # BB#0: -; MMX-NEXT: testb %dl, %dl +; MMX-NEXT: testl %edx, %edx ; MMX-NEXT: jne .LBB0_1 ; MMX-NEXT: # BB#2: ; MMX-NEXT: movaps {{.*}}(%rip), %xmm0 @@ -25,7 +25,7 @@ ; CHECK-LABEL: test_select: ; CHECK: # BB#0: ; CHECK-NEXT: xorl %eax, %eax -; CHECK-NEXT: testb %dl, %dl +; CHECK-NEXT: testl %edx, %edx ; CHECK-NEXT: cmovneq (%rdi), %rax ; CHECK-NEXT: movabsq $9223231299366420480, %rcx # imm = 0x7FFF800000000000 ; CHECK-NEXT: cmovneq 8(%rdi), %rcx Index: test/CodeGen/X86/illegal-bitfield-loadstore.ll =================================================================== --- test/CodeGen/X86/illegal-bitfield-loadstore.ll +++ test/CodeGen/X86/illegal-bitfield-loadstore.ll @@ -87,16 +87,15 @@ ; ; X64-LABEL: i24_insert_bit: ; X64: # BB#0: -; X64-NEXT: movzbl %sil, %eax -; X64-NEXT: movzwl (%rdi), %ecx -; X64-NEXT: movzbl 2(%rdi), %edx -; X64-NEXT: movb %dl, 2(%rdi) -; X64-NEXT: shll $16, %edx -; X64-NEXT: orl %ecx, %edx -; X64-NEXT: shll $13, %eax -; X64-NEXT: andl $16769023, %edx # imm = 0xFFDFFF -; X64-NEXT: orl %eax, %edx -; X64-NEXT: movw %dx, (%rdi) +; X64-NEXT: movzwl (%rdi), %eax +; X64-NEXT: movzbl 2(%rdi), %ecx +; X64-NEXT: movb %cl, 2(%rdi) +; X64-NEXT: shll $16, %ecx +; X64-NEXT: orl %eax, %ecx +; X64-NEXT: shll $13, %esi +; X64-NEXT: andl $16769023, %ecx # imm = 0xFFDFFF +; X64-NEXT: orl %esi, %ecx +; X64-NEXT: movw %cx, (%rdi) ; X64-NEXT: retq %extbit = zext i1 %bit to i24 %b = load i24, i24* %a, align 1 @@ -185,23 +184,23 @@ ; ; X64-LABEL: i56_insert_bit: ; X64: # BB#0: -; X64-NEXT: movzbl %sil, %eax -; X64-NEXT: movzwl 4(%rdi), %ecx -; X64-NEXT: movzbl 6(%rdi), %edx -; X64-NEXT: movl (%rdi), %esi -; X64-NEXT: movb %dl, 6(%rdi) -; X64-NEXT: # kill: %EDX %EDX %RDX %RDX -; X64-NEXT: shll $16, %edx -; X64-NEXT: orl %ecx, %edx -; X64-NEXT: shlq $32, %rdx -; X64-NEXT: orq %rdx, %rsi -; X64-NEXT: shlq $13, %rax -; X64-NEXT: movabsq $72057594037919743, %rcx # imm = 0xFFFFFFFFFFDFFF -; X64-NEXT: andq %rsi, %rcx -; X64-NEXT: orq %rax, %rcx -; X64-NEXT: movl %ecx, (%rdi) -; X64-NEXT: shrq $32, %rcx -; X64-NEXT: movw %cx, 4(%rdi) +; X64-NEXT: # kill: %ESI %ESI %RSI +; X64-NEXT: movzwl 4(%rdi), %eax +; X64-NEXT: movzbl 6(%rdi), %ecx +; X64-NEXT: movl (%rdi), %edx +; X64-NEXT: movb %cl, 6(%rdi) +; X64-NEXT: # kill: %ECX %ECX %RCX %RCX +; X64-NEXT: shll $16, %ecx +; X64-NEXT: orl %eax, %ecx +; X64-NEXT: shlq $32, %rcx +; X64-NEXT: orq %rcx, %rdx +; X64-NEXT: shlq $13, %rsi +; X64-NEXT: movabsq $72057594037919743, %rax # imm = 0xFFFFFFFFFFDFFF +; X64-NEXT: andq %rdx, %rax +; X64-NEXT: orq %rsi, %rax +; X64-NEXT: movl %eax, (%rdi) +; X64-NEXT: shrq $32, %rax +; X64-NEXT: movw %ax, 4(%rdi) ; X64-NEXT: retq %extbit = zext i1 %bit to i56 %b = load i56, i56* %a, align 1 Index: test/CodeGen/X86/mask-negated-bool.ll =================================================================== --- test/CodeGen/X86/mask-negated-bool.ll +++ test/CodeGen/X86/mask-negated-bool.ll @@ -16,7 +16,7 @@ define i32 @mask_negated_zext_bool2(i1 zeroext %x) { ; CHECK-LABEL: mask_negated_zext_bool2: ; CHECK: # BB#0: -; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: movl %edi, %eax ; CHECK-NEXT: retq %ext = zext i1 %x to i32 %neg = sub i32 0, %ext @@ -50,7 +50,7 @@ define i32 @mask_negated_sext_bool2(i1 zeroext %x) { ; CHECK-LABEL: mask_negated_sext_bool2: ; CHECK: # BB#0: -; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: movl %edi, %eax ; CHECK-NEXT: retq %ext = sext i1 %x to i32 %neg = sub i32 0, %ext Index: test/CodeGen/X86/negate-i1.ll =================================================================== --- test/CodeGen/X86/negate-i1.ll +++ test/CodeGen/X86/negate-i1.ll @@ -58,9 +58,8 @@ define i16 @select_i16_neg1_or_0_zeroext(i1 zeroext %a) { ; X64-LABEL: select_i16_neg1_or_0_zeroext: ; X64: # BB#0: -; X64-NEXT: movzbl %dil, %eax -; X64-NEXT: negl %eax -; X64-NEXT: # kill: %AX %AX %EAX +; X64-NEXT: negl %edi +; X64-NEXT: movl %edi, %eax ; X64-NEXT: retq ; ; X32-LABEL: select_i16_neg1_or_0_zeroext: @@ -94,8 +93,8 @@ define i32 @select_i32_neg1_or_0_zeroext(i1 zeroext %a) { ; X64-LABEL: select_i32_neg1_or_0_zeroext: ; X64: # BB#0: -; X64-NEXT: movzbl %dil, %eax -; X64-NEXT: negl %eax +; X64-NEXT: negl %edi +; X64-NEXT: movl %edi, %eax ; X64-NEXT: retq ; ; X32-LABEL: select_i32_neg1_or_0_zeroext: @@ -130,8 +129,9 @@ define i64 @select_i64_neg1_or_0_zeroext(i1 zeroext %a) { ; X64-LABEL: select_i64_neg1_or_0_zeroext: ; X64: # BB#0: -; X64-NEXT: movzbl %dil, %eax -; X64-NEXT: negq %rax +; X64-NEXT: # kill: %EDI %EDI %RDI +; X64-NEXT: negq %rdi +; X64-NEXT: movq %rdi, %rax ; X64-NEXT: retq ; ; X32-LABEL: select_i64_neg1_or_0_zeroext: Index: test/CodeGen/X86/select_const.ll =================================================================== --- test/CodeGen/X86/select_const.ll +++ test/CodeGen/X86/select_const.ll @@ -53,7 +53,7 @@ define i32 @select_1_or_0_zeroext(i1 zeroext %cond) { ; CHECK-LABEL: select_1_or_0_zeroext: ; CHECK: # BB#0: -; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: movl %edi, %eax ; CHECK-NEXT: retq %sel = select i1 %cond, i32 1, i32 0 ret i32 %sel @@ -62,8 +62,8 @@ define i32 @select_1_or_0_signext(i1 signext %cond) { ; CHECK-LABEL: select_1_or_0_signext: ; CHECK: # BB#0: -; CHECK-NEXT: andb $1, %dil -; CHECK-NEXT: movzbl %dil, %eax +; CHECK-NEXT: andl $1, %edi +; CHECK-NEXT: movl %edi, %eax ; CHECK-NEXT: retq %sel = select i1 %cond, i32 1, i32 0 ret i32 %sel @@ -85,8 +85,8 @@ define i32 @select_0_or_neg1_zeroext(i1 zeroext %cond) { ; CHECK-LABEL: select_0_or_neg1_zeroext: ; CHECK: # BB#0: -; CHECK-NEXT: movzbl %dil, %eax -; CHECK-NEXT: decl %eax +; CHECK-NEXT: # kill: %EDI %EDI %RDI +; CHECK-NEXT: leal -1(%rdi), %eax ; CHECK-NEXT: retq %sel = select i1 %cond, i32 0, i32 -1 ret i32 %sel @@ -95,9 +95,8 @@ define i32 @select_0_or_neg1_signext(i1 signext %cond) { ; CHECK-LABEL: select_0_or_neg1_signext: ; CHECK: # BB#0: -; CHECK-NEXT: andb $1, %dil -; CHECK-NEXT: movzbl %dil, %eax -; CHECK-NEXT: decl %eax +; CHECK-NEXT: notl %edi +; CHECK-NEXT: movl %edi, %eax ; CHECK-NEXT: retq %sel = select i1 %cond, i32 0, i32 -1 ret i32 %sel @@ -119,8 +118,8 @@ define i32 @select_neg1_or_0_zeroext(i1 zeroext %cond) { ; CHECK-LABEL: select_neg1_or_0_zeroext: ; CHECK: # BB#0: -; CHECK-NEXT: movzbl %dil, %eax -; CHECK-NEXT: negl %eax +; CHECK-NEXT: negl %edi +; CHECK-NEXT: movl %edi, %eax ; CHECK-NEXT: retq %sel = select i1 %cond, i32 -1, i32 0 ret i32 %sel @@ -129,7 +128,7 @@ define i32 @select_neg1_or_0_signext(i1 signext %cond) { ; CHECK-LABEL: select_neg1_or_0_signext: ; CHECK: # BB#0: -; CHECK-NEXT: movsbl %dil, %eax +; CHECK-NEXT: movl %edi, %eax ; CHECK-NEXT: retq %sel = select i1 %cond, i32 -1, i32 0 ret i32 %sel @@ -151,8 +150,8 @@ define i32 @select_Cplus1_C_zeroext(i1 zeroext %cond) { ; CHECK-LABEL: select_Cplus1_C_zeroext: ; CHECK: # BB#0: -; CHECK-NEXT: movzbl %dil, %eax -; CHECK-NEXT: addl $41, %eax +; CHECK-NEXT: # kill: %EDI %EDI %RDI +; CHECK-NEXT: leal 41(%rdi), %eax ; CHECK-NEXT: retq %sel = select i1 %cond, i32 42, i32 41 ret i32 %sel @@ -161,9 +160,8 @@ define i32 @select_Cplus1_C_signext(i1 signext %cond) { ; CHECK-LABEL: select_Cplus1_C_signext: ; CHECK: # BB#0: -; CHECK-NEXT: andb $1, %dil -; CHECK-NEXT: movzbl %dil, %eax -; CHECK-NEXT: addl $41, %eax +; CHECK-NEXT: movl $41, %eax +; CHECK-NEXT: subl %edi, %eax ; CHECK-NEXT: retq %sel = select i1 %cond, i32 42, i32 41 ret i32 %sel @@ -185,9 +183,8 @@ define i32 @select_C_Cplus1_zeroext(i1 zeroext %cond) { ; CHECK-LABEL: select_C_Cplus1_zeroext: ; CHECK: # BB#0: -; CHECK-NEXT: movzbl %dil, %ecx ; CHECK-NEXT: movl $42, %eax -; CHECK-NEXT: subl %ecx, %eax +; CHECK-NEXT: subl %edi, %eax ; CHECK-NEXT: retq %sel = select i1 %cond, i32 41, i32 42 ret i32 %sel @@ -196,10 +193,9 @@ define i32 @select_C_Cplus1_signext(i1 signext %cond) { ; CHECK-LABEL: select_C_Cplus1_signext: ; CHECK: # BB#0: -; CHECK-NEXT: andb $1, %dil -; CHECK-NEXT: movzbl %dil, %ecx +; CHECK-NEXT: andl $1, %edi ; CHECK-NEXT: movl $42, %eax -; CHECK-NEXT: subl %ecx, %eax +; CHECK-NEXT: subl %edi, %eax ; CHECK-NEXT: retq %sel = select i1 %cond, i32 41, i32 42 ret i32 %sel @@ -357,9 +353,9 @@ define i32 @select_pow2_diff_neg(i1 zeroext %cond) { ; CHECK-LABEL: select_pow2_diff_neg: ; CHECK: # BB#0: -; CHECK-NEXT: shlb $4, %dil -; CHECK-NEXT: movzbl %dil, %eax -; CHECK-NEXT: orl $-25, %eax +; CHECK-NEXT: # kill: %EDI %EDI %RDI +; CHECK-NEXT: shll $4, %edi +; CHECK-NEXT: leal -25(%rdi), %eax ; CHECK-NEXT: retq %sel = select i1 %cond, i32 -9, i32 -25 ret i32 %sel @@ -413,7 +409,7 @@ define i32 @select_C1_C2_zeroext(i1 zeroext %cond) { ; CHECK-LABEL: select_C1_C2_zeroext: ; CHECK: # BB#0: -; CHECK-NEXT: testb %dil, %dil +; CHECK-NEXT: testl %edi, %edi ; CHECK-NEXT: movl $421, %ecx # imm = 0x1A5 ; CHECK-NEXT: movl $42, %eax ; CHECK-NEXT: cmovnel %ecx, %eax Index: test/CodeGen/X86/sext-i1.ll =================================================================== --- test/CodeGen/X86/sext-i1.ll +++ test/CodeGen/X86/sext-i1.ll @@ -144,8 +144,8 @@ ; ; X64-LABEL: select_0_or_1s_zeroext: ; X64: # BB#0: -; X64-NEXT: movzbl %dil, %eax -; X64-NEXT: decl %eax +; X64-NEXT: # kill: %EDI %EDI %RDI +; X64-NEXT: leal -1(%rdi), %eax ; X64-NEXT: retq %not = xor i1 %cond, 1 %sext = sext i1 %not to i32 @@ -165,9 +165,8 @@ ; ; X64-LABEL: select_0_or_1s_signext: ; X64: # BB#0: -; X64-NEXT: andb $1, %dil -; X64-NEXT: movzbl %dil, %eax -; X64-NEXT: decl %eax +; X64-NEXT: notl %edi +; X64-NEXT: movl %edi, %eax ; X64-NEXT: retq %not = xor i1 %cond, 1 %sext = sext i1 %not to i32 Index: test/CodeGen/X86/split-store.ll =================================================================== --- test/CodeGen/X86/split-store.ll +++ test/CodeGen/X86/split-store.ll @@ -179,16 +179,15 @@ } ; getTypeSizeInBits(i14) != getTypeStoreSizeInBits(i14), so store split doesn't kick in. -; CHECK-LABEL: int7_int7_pair -; CHECK: movzbl %sil, %eax -; CHECK: shll $7, %eax -; CHECK: andb $127, %dil -; CHECK: movzbl %dil, %ecx -; CHECK: orl %eax, %ecx -; CHECK: andl $16383, %ecx -; CHECK: movw %cx, (%rdx) define void @int7_int7_pair(i7 signext %tmp1, i7 signext %tmp2, i14* %ref.tmp) { -entry: +; CHECK-LABEL: int7_int7_pair: +; CHECK: # BB#0: +; CHECK-NEXT: shll $7, %esi +; CHECK-NEXT: andl $127, %edi +; CHECK-NEXT: orl %esi, %edi +; CHECK-NEXT: andl $16383, %edi # imm = 0x3FFF +; CHECK-NEXT: movw %di, (%rdx) +; CHECK-NEXT: retq %t1 = zext i7 %tmp2 to i14 %t2 = shl nuw i14 %t1, 7 %t3 = zext i7 %tmp1 to i14