Index: lib/Target/AArch64/AArch64SystemOperands.td
===================================================================
--- lib/Target/AArch64/AArch64SystemOperands.td
+++ lib/Target/AArch64/AArch64SystemOperands.td
@@ -426,6 +426,10 @@
 let Requires = [{ {AArch64::FeatureRAS} }] in {
 def : ROSysReg<"ERRIDR_EL1", 0b11, 0b000, 0b0101, 0b0011, 0b000>;
 def : ROSysReg<"ERXFR_EL1",  0b11, 0b000, 0b0101, 0b0100, 0b000>;
+
+// v8.3a Javascript data type conversion support
+let Requires = [{ {AArch64::HasV8_3aOps} }] in
+def : ROSysReg<"ID_ISAR6_EL1",       0b11, 0b000, 0b0000, 0b0010, 0b111>;
 }
 
 //===----------------------
Index: test/MC/AArch64/armv8.3a-ID_ISAR6_EL1.s
===================================================================
--- /dev/null
+++ test/MC/AArch64/armv8.3a-ID_ISAR6_EL1.s
@@ -0,0 +1,9 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.3a < %s 2>&1 | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-REQ %s < %t
+
+  mrs x0, ID_ISAR6_EL1
+// CHECK: mrs x0, ID_ISAR6_EL1        // encoding: [0xe0,0x02,0x38,0xd5]
+// CHECK-REQ: error: expected readable system register
+// CHECK-REQ-NEXT: mrs x0, ID_ISAR6_EL1
+// CHECK-REQ-NEXT:         ^
Index: test/MC/Disassembler/AArch64/armv8.3a-ID_ISAR6_EL1.txt
===================================================================
--- /dev/null
+++ test/MC/Disassembler/AArch64/armv8.3a-ID_ISAR6_EL1.txt
@@ -0,0 +1,4 @@
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.3a --disassemble < %s | FileCheck %s
+
+# CHECK: mrs x0, ID_ISAR6_EL1
+0xe0,0x02,0x38,0xd5