Index: llvm/trunk/lib/Target/ARM/ARM.td
===================================================================
--- llvm/trunk/lib/Target/ARM/ARM.td
+++ llvm/trunk/lib/Target/ARM/ARM.td
@@ -323,8 +323,9 @@
 def FeatureUseMISched: SubtargetFeature<"use-misched", "UseMISched", "true",
                                         "Use the MachineScheduler">;
 
-def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
-    "UsePostRAScheduler", "true", "Schedule again after register allocation">;
+def FeatureNoPostRASched : SubtargetFeature<"disable-postra-scheduler",
+    "DisablePostRAScheduler", "true",
+    "Don't schedule again after register allocation">;
 
 //===----------------------------------------------------------------------===//
 // ARM architecture class
@@ -829,7 +830,8 @@
                                                          FeatureSlowLoadDSubreg,
                                                          FeatureSlowVGETLNi32,
                                                          FeatureSlowVDUP32,
-                                                         FeatureUseMISched]>;
+                                                         FeatureUseMISched,
+                                                         FeatureNoPostRASched]>;
 
 def : ProcessorModel<"cortex-r4",   CortexA8Model,      [ARMv7r, ProcR4,
                                                          FeatureHasRetAddrStack,
@@ -876,8 +878,7 @@
 
 def : ProcessorModel<"cortex-m3", CortexM3Model,        [ARMv7m,
                                                          ProcM3,
-                                                         FeatureHasNoBranchPredictor,
-                                                         FeaturePostRAScheduler]>;
+                                                         FeatureHasNoBranchPredictor]>;
 
 def : ProcessorModel<"sc300",     CortexM3Model,        [ARMv7m,
                                                          ProcM3,
@@ -887,13 +888,11 @@
                                                          FeatureVFP4,
                                                          FeatureVFPOnlySP,
                                                          FeatureD16,
-                                                         FeatureHasNoBranchPredictor,
-                                                         FeaturePostRAScheduler]>;
+                                                         FeatureHasNoBranchPredictor]>;
 
 def : ProcNoItin<"cortex-m7",                           [ARMv7em,
                                                          FeatureFPARMv8,
-                                                         FeatureD16,
-                                                         FeaturePostRAScheduler]>;
+                                                         FeatureD16]>;
 
 def : ProcNoItin<"cortex-m23",                          [ARMv8mBaseline,
                                                          FeatureNoMovt]>;
@@ -903,8 +902,7 @@
                                                          FeatureFPARMv8,
                                                          FeatureD16,
                                                          FeatureVFPOnlySP,
-                                                         FeatureHasNoBranchPredictor,
-                                                         FeaturePostRAScheduler]>;
+                                                         FeatureHasNoBranchPredictor]>;
 
 def : ProcNoItin<"cortex-a32",                           [ARMv8a,
                                                          FeatureHWDivThumb,
@@ -968,7 +966,8 @@
                                                          FeatureHasSlowFPVMLx,
                                                          FeatureCrypto,
                                                          FeatureUseMISched,
-                                                         FeatureZCZeroing]>;
+                                                         FeatureZCZeroing,
+                                                         FeatureNoPostRASched]>;
 
 def : ProcNoItin<"exynos-m1",                           [ARMv8a, ProcExynosM1,
                                                          FeatureHWDivThumb,
Index: llvm/trunk/lib/Target/ARM/ARMScheduleR52.td
===================================================================
--- llvm/trunk/lib/Target/ARM/ARMScheduleR52.td
+++ llvm/trunk/lib/Target/ARM/ARMScheduleR52.td
@@ -24,7 +24,6 @@
   let IssueWidth = 2;         // 2 micro-ops dispatched per cycle
   let LoadLatency = 1;        // Optimistic, assuming no misses
   let MispredictPenalty = 8;  // A branch direction mispredict, including PFU
-  let PostRAScheduler = 1;    // Enable PostRA scheduler pass.
   let CompleteModel = 0;      // Covers instructions applicable to cortex-r52.
 }
 
Index: llvm/trunk/lib/Target/ARM/ARMSubtarget.h
===================================================================
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.h
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h
@@ -194,9 +194,9 @@
   /// UseMISched - True if MachineScheduler should be used for this subtarget.
   bool UseMISched = false;
 
-  /// UsePostRAScheduler - True if scheduling should happen again after
+  /// DisablePostRAScheduler - False if scheduling should happen again after
   /// register allocation.
-  bool UsePostRAScheduler = false;
+  bool DisablePostRAScheduler = false;
 
   /// HasThumb2 - True if Thumb2 instructions are supported.
   bool HasThumb2 = false;
@@ -667,7 +667,7 @@
   bool isRWPI() const;
 
   bool useMachineScheduler() const { return UseMISched; }
-  bool usePostRAScheduler() const { return UsePostRAScheduler; }
+  bool disablePostRAScheduler() const { return DisablePostRAScheduler; }
   bool useSoftFloat() const { return UseSoftFloat; }
   bool isThumb() const { return InThumbMode; }
   bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
Index: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
===================================================================
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
@@ -366,15 +366,10 @@
 
 // This overrides the PostRAScheduler bit in the SchedModel for any CPU.
 bool ARMSubtarget::enablePostRAScheduler() const {
-  if (usePostRAScheduler())
-    return true;
-  if (SchedModel.PostRAScheduler)
-    return true;
-  // No need for PostRA scheduling on subtargets where we use the
-  // MachineScheduler.
-  if (useMachineScheduler())
+  if (disablePostRAScheduler())
     return false;
-  return (!isThumb() || hasThumb2());
+  // Don't reschedule potential IT blocks.
+  return !isThumb1Only();
 }
 
 bool ARMSubtarget::enableAtomicExpand() const { return hasAnyDataBarrier(); }