Index: lib/Target/SystemZ/SystemZISelLowering.h
===================================================================
--- lib/Target/SystemZ/SystemZISelLowering.h
+++ lib/Target/SystemZ/SystemZISelLowering.h
@@ -359,6 +359,9 @@
 class SystemZTargetMachine;
 
 class SystemZTargetLowering : public TargetLowering {
+
+  unsigned NumLOCRMux;
+
 public:
   explicit SystemZTargetLowering(const TargetMachine &TM,
                                  const SystemZSubtarget &STI);
Index: lib/Target/SystemZ/SystemZISelLowering.cpp
===================================================================
--- lib/Target/SystemZ/SystemZISelLowering.cpp
+++ lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -5507,6 +5507,10 @@
   return Reg;
 }
 
+// EXPERIMENTAL
+static cl::opt<bool> LOCRCONSTRAIN("locr-constrain", cl::Hidden, cl::init(false));
+static cl::opt<bool> LOCRXALTERNATE("locrx-alternate", cl::Hidden, cl::init(false));
+
 // Implement EmitInstrWithCustomInserter for pseudo Select* instruction MI.
 MachineBasicBlock *
 SystemZTargetLowering::emitSelect(MachineInstr &MI,
@@ -5528,6 +5532,34 @@
       .addReg(FalseReg).addReg(TrueReg)
       .addImm(CCValid).addImm(CCMask);
     MI.eraseFromParent();
+
+    if (LOCROpcode == SystemZ::LOCRMux && LOCRCONSTRAIN) {
+      // Try to help regalloc by constraining GRX32 as called for.
+      const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
+      MachineRegisterInfo *MRI = &MBB->getParent()->getRegInfo();
+      // Find smallest common reg class of dest/true/false regs.
+      const TargetRegisterClass *RC =
+        TRI->getCommonSubClass(MRI->getRegClass(FalseReg),
+                               MRI->getRegClass(TrueReg));
+      RC = TRI->getCommonSubClass(RC, MRI->getRegClass(DestReg));
+      if (RC == &SystemZ::GRX32BitRegClass) {
+        if (LOCRXALTERNATE) {
+          // Alternate between GR32 and GRH32 reg classes.
+          // UGLY
+          const_cast<SystemZTargetLowering*>(this)->NumLOCRMux++;
+          RC = ((NumLOCRMux % 2) ? &SystemZ::GR32BitRegClass :
+                &SystemZ::GRH32BitRegClass);
+        }
+        else
+          RC = nullptr;
+      }
+      if (RC) {
+        MRI->setRegClass(DestReg, RC);
+        MRI->setRegClass(FalseReg, RC);
+        MRI->setRegClass(TrueReg, RC);
+      }
+    }
+
     return MBB;
   }
 
Index: lib/Target/SystemZ/SystemZRegisterInfo.h
===================================================================
--- lib/Target/SystemZ/SystemZRegisterInfo.h
+++ lib/Target/SystemZ/SystemZRegisterInfo.h
@@ -42,6 +42,13 @@
     return &SystemZ::ADDR64BitRegClass;
   }
 
+  void getRegAllocationHints(unsigned VirtReg,
+                             ArrayRef<MCPhysReg> Order,
+                             SmallVectorImpl<MCPhysReg> &Hints,
+                             const MachineFunction &MF,
+                             const VirtRegMap *VRM,
+                             const LiveRegMatrix *Matrix) const override;
+
   // Override TargetRegisterInfo.h.
   bool requiresRegisterScavenging(const MachineFunction &MF) const override {
     return true;
Index: lib/Target/SystemZ/SystemZRegisterInfo.cpp
===================================================================
--- lib/Target/SystemZ/SystemZRegisterInfo.cpp
+++ lib/Target/SystemZ/SystemZRegisterInfo.cpp
@@ -12,6 +12,7 @@
 #include "SystemZSubtarget.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/VirtRegMap.h"
 #include "llvm/Target/TargetFrameLowering.h"
 
 using namespace llvm;
@@ -22,6 +23,57 @@
 SystemZRegisterInfo::SystemZRegisterInfo()
     : SystemZGenRegisterInfo(SystemZ::R14D) {}
 
+// EXPERIMENTAL
+void
+SystemZRegisterInfo::getRegAllocationHints(unsigned VirtReg,
+                                           ArrayRef<MCPhysReg> Order,
+                                           SmallVectorImpl<MCPhysReg> &Hints,
+                                           const MachineFunction &MF,
+                                           const VirtRegMap *VRM,
+                                           const LiveRegMatrix *Matrix) const {
+  const MachineRegisterInfo &MRI = MF.getRegInfo();
+  if (MRI.getRegClass(VirtReg) == &SystemZ::GRX32BitRegClass) {
+    for (auto &Use : MRI.use_instructions(VirtReg)) {
+      if (Use.getOpcode() == SystemZ::LOCRMux) {
+        MachineOperand &TrueMO = Use.getOperand(1);
+        MachineOperand &FalseMO = Use.getOperand(2);
+        MachineOperand &OtherMO = ((VirtReg == TrueMO.getReg()) ? FalseMO : TrueMO);
+        const TargetRegisterClass *RC32 = nullptr;
+        const TargetRegisterClass *OtherRC = MRI.getRegClass(OtherMO.getReg());
+        if (OtherRC == &SystemZ::GRX32BitRegClass) {
+          // Both regs are GRX32: Try to follow the other reg if allocated.
+          if (VRM && VRM->hasPhys(OtherMO.getReg())) {
+            unsigned OtherPhys = VRM->getPhys(OtherMO.getReg());
+            if (SystemZ::GR32BitRegClass.contains(OtherPhys))
+              RC32 = &SystemZ::GR32BitRegClass;
+            else if (SystemZ::GRH32BitRegClass.contains(OtherPhys))
+              RC32 = &SystemZ::GRH32BitRegClass;
+          }
+        }
+        else {
+          // Other reg has either high or low reclass.
+          if (SystemZ::GR32BitRegClass.hasSubClassEq(OtherRC) ||
+              OtherMO.getSubReg() == SystemZ::subreg_l32)
+            RC32 = &SystemZ::GR32BitRegClass;
+          else if (OtherRC == &SystemZ::GRH32BitRegClass ||
+                   OtherMO.getSubReg() == SystemZ::subreg_h32)
+            RC32 = &SystemZ::GRH32BitRegClass;
+        }
+        if (RC32) {
+          // Add all regs in the allocation order of VirtReg that are part of
+          // RC32 as hints.
+          for (MCPhysReg Reg : Order)
+            if (RC32->contains(Reg) && !MRI.isReserved(Reg))
+              Hints.push_back(Reg);
+          return;
+        }
+      } // LOCRMux
+    } // use_instructions
+  }
+
+  TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM);
+}
+
 const MCPhysReg *
 SystemZRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
   if (MF->getSubtarget().getTargetLowering()->supportSwiftError() &&