Index: lib/Target/AArch64/AArch64InstrFormats.td =================================================================== --- lib/Target/AArch64/AArch64InstrFormats.td +++ lib/Target/AArch64/AArch64InstrFormats.td @@ -189,6 +189,11 @@ // are encoded as the eight bit value 'abcdefgh'. def SIMDImmType10Operand : AsmOperandClass { let Name = "SIMDImmType10"; } +// Authenticated loads for v8.3 can have scaled 10-bit immediate offsets. +def SImm10s8Operand : AsmOperandClass { + let Name = "SImm10s8"; + let DiagnosticType = "InvalidMemoryIndexedSImm10"; +} //===----------------------------------------------------------------------===// // Operand Definitions. @@ -216,6 +221,12 @@ let ParserMatchClass = AdrOperand; } +def simm10Scaled : Operand { + let ParserMatchClass = SImm10s8Operand; + let DecoderMethod = "DecodeSImm<10>"; + let PrintMethod = "printImmScale<8>"; +} + // simm9 predicate - True if the immediate is in the range [-256, 255]. def SImm9Operand : AsmOperandClass { let Name = "SImm9"; @@ -913,6 +924,17 @@ let Inst{7-5} = opc; } +class SystemNoOperands op2, string asm, list pattern = []> + : SimpleSystemI<0, (ins), asm, "", pattern>, + Sched<[]> { + bits<4> CRm; + let CRm = 0b0011; + let Inst{31-12} = 0b11010101000000110010; + let Inst{11-8} = CRm; + let Inst{7-5} = op2; + let Inst{4-0} = 0b11111; +} + // MRS/MSR system instructions. These have different operand classes because // a different subset of registers can be accessed through each instruction. def MRSSystemRegisterOperand : AsmOperandClass { @@ -1098,6 +1120,72 @@ let Inst{9-5} = 0b11111; } +class AuthBase M, dag oops, dag iops, string asm, string operands, + list pattern> + : I, Sched<[]> { + let Inst{31-25} = 0b1101011; + let Inst{20-11} = 0b1111100001; + let Inst{10} = M; + let Inst{4-0} = 0b11111; +} + +class AuthBranchTwoOperands op, bits<1> M, string asm> + : AuthBase { + bits<5> Rn; + bits<5> Rm; + let Inst{24-22} = 0b100; + let Inst{21} = op; + let Inst{9-5} = Rn; + let Inst{4-0} = Rm; +} + +class AuthOneOperand opc, bits<1> M, string asm> + : AuthBase { + bits<5> Rn; + let Inst{24} = 0; + let Inst{23-21} = opc; + let Inst{9-5} = Rn; +} + +class AuthReturn op, bits<1> M, string asm> + : AuthBase { + let Inst{24} = 0; + let Inst{23-21} = op; + let Inst{9-0} = 0b1111111111; +} + +let mayLoad = 1 in +class BaseAuthLoad + : I, Sched<[]> { + bits<10> offset; + bits<5> Rn; + bits<5> Rt; + let Inst{31-24} = 0b11111000; + let Inst{23} = M; + let Inst{22} = offset{9}; + let Inst{21} = 1; + let Inst{20-12} = offset{8-0}; + let Inst{11} = W; + let Inst{10} = 1; + let Inst{9-5} = Rn; + let Inst{4-0} = Rt; +} + +multiclass AuthLoad { + def indexed : BaseAuthLoad; + def writeback : BaseAuthLoad { + let DecoderMethod = "DecodeAuthLoadWriteback"; + } + + def : InstAlias(NAME # "indexed") GPR64:$Rt, GPR64sp:$Rn, 0)>; +} + //--- // Conditional branch instruction. //--- @@ -1320,6 +1408,46 @@ let Inst{31} = 1; } +class SignAuthOneData opcode_prefix, bits<2> opcode, string asm> + : I<(outs GPR64:$Rd), (ins GPR64sp:$Rn), asm, "\t$Rd, $Rn", "", + []>, + Sched<[WriteI, ReadI]> { + bits<5> Rd; + bits<5> Rn; + let Inst{31-15} = 0b11011010110000010; + let Inst{14-12} = opcode_prefix; + let Inst{11-10} = opcode; + let Inst{9-5} = Rn; + let Inst{4-0} = Rd; +} + +class SignAuthZero opcode_prefix, bits<2> opcode, string asm> + : I<(outs GPR64:$Rd), (ins), asm, "\t$Rd", "", []>, Sched<[]> { + bits<5> Rd; + let Inst{31-15} = 0b11011010110000010; + let Inst{14-12} = opcode_prefix; + let Inst{11-10} = opcode; + let Inst{9-5} = 0b11111; + let Inst{4-0} = Rd; +} + +class SignAuthTwoOperand opc, string asm, + SDPatternOperator OpNode> + : I<(outs GPR64:$Rd), (ins GPR64:$Rn, GPR64sp:$Rm), + asm, "\t$Rd, $Rn, $Rm", "", + [(set GPR64:$Rd, (OpNode GPR64:$Rn, GPR64sp:$Rm))]>, + Sched<[WriteI, ReadI, ReadI]> { + bits<5> Rd; + bits<5> Rn; + bits<5> Rm; + let Inst{31-21} = 0b10011010110; + let Inst{20-16} = Rm; + let Inst{15-14} = 0b00; + let Inst{13-10} = opc; + let Inst{9-5} = Rn; + let Inst{4-0} = Rd; +} + //--- // Basic two-operand data processing instructions. //--- Index: lib/Target/AArch64/AArch64InstrInfo.td =================================================================== --- lib/Target/AArch64/AArch64InstrInfo.td +++ lib/Target/AArch64/AArch64InstrInfo.td @@ -434,6 +434,72 @@ [(int_aarch64_isb (i32 imm32_0_15:$CRm))]>; } +let Predicates = [HasV8_3a] in { + // v8.3a Pointer Authentication + let Uses = [LR], Defs = [LR] in { + def PACIAZ : SystemNoOperands<0b000, "paciaz">; + def PACIBZ : SystemNoOperands<0b010, "pacibz">; + def AUTIAZ : SystemNoOperands<0b100, "autiaz">; + def AUTIBZ : SystemNoOperands<0b110, "autibz">; + } + let Uses = [LR, SP], Defs = [LR] in { + def PACIASP : SystemNoOperands<0b001, "paciasp">; + def PACIBSP : SystemNoOperands<0b011, "pacibsp">; + def AUTIASP : SystemNoOperands<0b101, "autiasp">; + def AUTIBSP : SystemNoOperands<0b111, "autibsp">; + } + let Uses = [X16, X17], Defs = [X17], CRm = 0b0001 in { + def PACIA1716 : SystemNoOperands<0b000, "pacia1716">; + def PACIB1716 : SystemNoOperands<0b010, "pacib1716">; + def AUTIA1716 : SystemNoOperands<0b100, "autia1716">; + def AUTIB1716 : SystemNoOperands<0b110, "autib1716">; + } + + let Uses = [LR], Defs = [LR], CRm = 0b0000 in { + def XPACLRI : SystemNoOperands<0b111, "xpaclri">; + } + + multiclass SignAuth prefix, bits<3> prefix_z, string asm> { + def IA : SignAuthOneData; + def IB : SignAuthOneData; + def DA : SignAuthOneData; + def DB : SignAuthOneData; + def IZA : SignAuthZero; + def DZA : SignAuthZero; + def IZB : SignAuthZero; + def DZB : SignAuthZero; + } + + defm PAC : SignAuth<0b000, 0b010, "pac">; + defm AUT : SignAuth<0b001, 0b011, "aut">; + + def XPACI : SignAuthZero<0b100, 0b00, "xpaci">; + def XPACD : SignAuthZero<0b100, 0b01, "xpacd">; + def PACGA : SignAuthTwoOperand<0b1100, "pacga", null_frag>; + + // Combined Instructions + def BRAA : AuthBranchTwoOperands<0, 0, "braa">; + def BRAB : AuthBranchTwoOperands<0, 1, "brab">; + def BLRAA : AuthBranchTwoOperands<1, 0, "blraa">; + def BLRAB : AuthBranchTwoOperands<1, 1, "blrab">; + + def BRAAZ : AuthOneOperand<0b000, 0, "braaz">; + def BRABZ : AuthOneOperand<0b000, 1, "brabz">; + def BLRAAZ : AuthOneOperand<0b001, 0, "blraaz">; + def BLRABZ : AuthOneOperand<0b001, 1, "blrabz">; + + let isReturn = 1 in { + def RETAA : AuthReturn<0b010, 0, "retaa">; + def RETAB : AuthReturn<0b010, 1, "retab">; + def ERETAA : AuthReturn<0b100, 0, "eretaa">; + def ERETAB : AuthReturn<0b100, 1, "eretab">; + } + + defm LDRAA : AuthLoad<0, "ldraa", simm10Scaled>; + defm LDRAB : AuthLoad<1, "ldrab", simm10Scaled>; + +} // HasV8_3A + def : InstAlias<"clrex", (CLREX 0xf)>; def : InstAlias<"isb", (ISB 0xf)>; Index: lib/Target/AArch64/AArch64SchedThunderX.td =================================================================== --- lib/Target/AArch64/AArch64SchedThunderX.td +++ lib/Target/AArch64/AArch64SchedThunderX.td @@ -239,20 +239,20 @@ //--- // Branch //--- -def : InstRW<[THXT8XWriteBR], (instregex "^B")>; -def : InstRW<[THXT8XWriteBR], (instregex "^BL")>; -def : InstRW<[THXT8XWriteBR], (instregex "^B.*")>; +def : InstRW<[THXT8XWriteBR], (instregex "^B$")>; +def : InstRW<[THXT8XWriteBR], (instregex "^BL$")>; +def : InstRW<[THXT8XWriteBR], (instregex "^B..$")>; def : InstRW<[THXT8XWriteBR], (instregex "^CBNZ")>; def : InstRW<[THXT8XWriteBR], (instregex "^CBZ")>; def : InstRW<[THXT8XWriteBR], (instregex "^TBNZ")>; def : InstRW<[THXT8XWriteBR], (instregex "^TBZ")>; -def : InstRW<[THXT8XWriteBRR], (instregex "^BR")>; -def : InstRW<[THXT8XWriteBRR], (instregex "^BLR")>; +def : InstRW<[THXT8XWriteBRR], (instregex "^BR$")>; +def : InstRW<[THXT8XWriteBRR], (instregex "^BLR$")>; //--- // Ret //--- -def : InstRW<[THXT8XWriteRET], (instregex "^RET")>; +def : InstRW<[THXT8XWriteRET], (instregex "^RET$")>; //--- // Miscellaneous Index: lib/Target/AArch64/AArch64SchedThunderX2T99.td =================================================================== --- lib/Target/AArch64/AArch64SchedThunderX2T99.td +++ lib/Target/AArch64/AArch64SchedThunderX2T99.td @@ -398,7 +398,7 @@ //--- def : InstRW<[THX2T99Write_1Cyc_I2], (instrs B, BL, BR, BLR)>; def : InstRW<[THX2T99Write_1Cyc_I2], (instrs RET)>; -def : InstRW<[THX2T99Write_1Cyc_I2], (instregex "^B.*")>; +def : InstRW<[THX2T99Write_1Cyc_I2], (instregex "^B..$")>; def : InstRW<[THX2T99Write_1Cyc_I2], (instregex "^CBZ", "^CBNZ", "^TBZ", "^TBNZ")>; Index: lib/Target/AArch64/AArch64SystemOperands.td =================================================================== --- lib/Target/AArch64/AArch64SystemOperands.td +++ lib/Target/AArch64/AArch64SystemOperands.td @@ -1016,6 +1016,21 @@ def : RWSysReg<"VSESR_EL2", 0b11, 0b100, 0b0101, 0b0010, 0b011>; } +// v8.3a "Pointer authentication extension" registers +// Op0 Op1 CRn CRm Op2 +let Requires = [{ {AArch64::HasV8_3aOps} }] in { +def : RWSysReg<"APIAKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b000>; +def : RWSysReg<"APIAKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b001>; +def : RWSysReg<"APIBKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b010>; +def : RWSysReg<"APIBKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0001, 0b011>; +def : RWSysReg<"APDAKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0010, 0b000>; +def : RWSysReg<"APDAKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0010, 0b001>; +def : RWSysReg<"APDBKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0010, 0b010>; +def : RWSysReg<"APDBKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0010, 0b011>; +def : RWSysReg<"APGAKeyLo_EL1", 0b11, 0b000, 0b0010, 0b0011, 0b000>; +def : RWSysReg<"APGAKeyHi_EL1", 0b11, 0b000, 0b0010, 0b0011, 0b001>; +} + // Cyclone specific system registers // Op0 Op1 CRn CRm Op2 let Requires = [{ {AArch64::ProcCyclone} }] in Index: lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp =================================================================== --- lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -465,6 +465,15 @@ int64_t Val = MCE->getValue(); return (Val >= -256 && Val < 256); } + bool isSImm10s8() const { + if (!isImm()) + return false; + const MCConstantExpr *MCE = dyn_cast(getImm()); + if (!MCE) + return false; + int64_t Val = MCE->getValue(); + return (Val >= -4096 && Val < 4089 && (Val & 7) == 0); + } bool isSImm7s4() const { if (!isImm()) return false; @@ -1213,6 +1222,12 @@ Inst.addOperand(MCOperand::createImm(MCE->getValue())); } + void addSImm10s8Operands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + const MCConstantExpr *MCE = cast(getImm()); + Inst.addOperand(MCOperand::createImm(MCE->getValue() / 8)); + } + void addSImm7s4Operands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); const MCConstantExpr *MCE = cast(getImm()); @@ -3297,6 +3312,8 @@ "expected compatible register or floating-point constant"); case Match_InvalidMemoryIndexedSImm9: return Error(Loc, "index must be an integer in range [-256, 255]."); + case Match_InvalidMemoryIndexedSImm10: + return Error(Loc, "index must be a multiple of 8 in range [-4096, 4088]."); case Match_InvalidMemoryIndexed4SImm7: return Error(Loc, "index must be a multiple of 4 in range [-256, 252]."); case Match_InvalidMemoryIndexed8SImm7: @@ -3764,6 +3781,7 @@ case Match_InvalidMemoryIndexed8SImm7: case Match_InvalidMemoryIndexed16SImm7: case Match_InvalidMemoryIndexedSImm9: + case Match_InvalidMemoryIndexedSImm10: case Match_InvalidImm0_1: case Match_InvalidImm0_7: case Match_InvalidImm0_15: Index: lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp =================================================================== --- lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp +++ lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp @@ -179,6 +179,12 @@ unsigned RegNo, uint64_t Addr, const void *Decoder); +template +static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeAuthLoadWriteback(llvm::MCInst &Inst, uint32_t insn, + uint64_t Address, + const void *Decoder); static bool Check(DecodeStatus &Out, DecodeStatus In) { switch (In) { @@ -1588,3 +1594,39 @@ AArch64::XSeqPairsClassRegClassID, RegNo, Addr, Decoder); } + +template +static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm, + uint64_t Address, const void *Decoder) { + if (Imm & ~((1LL << Bits) - 1)) + return Fail; + + // Imm is a signed immediate, so sign extend it. + if (Imm & (1 << (Bits - 1))) + Imm |= ~((1LL << Bits) - 1); + + Inst.addOperand(MCOperand::createImm(Imm)); + return Success; +} + +static DecodeStatus DecodeAuthLoadWriteback(llvm::MCInst &Inst, uint32_t insn, + uint64_t Address, + const void *Decoder) { + unsigned Rt = fieldFromInstruction(insn, 0, 5); + unsigned Rn = fieldFromInstruction(insn, 5, 5); + unsigned Imm9 = fieldFromInstruction(insn, 12, 9); + unsigned S = fieldFromInstruction(insn, 22, 1); + + unsigned Imm = Imm9 | (S << 9); + + // Address writeback + DecodeGPR64spRegisterClass(Inst, Rn, Address, Decoder); + // Destination + DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder); + // Address + DecodeGPR64spRegisterClass(Inst, Rn, Address, Decoder); + // Offset + DecodeSImm<10>(Inst, Imm, Address, Decoder); + + return Success; +} Index: lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp =================================================================== --- lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp +++ lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp @@ -84,6 +84,12 @@ SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const; + /// getAuthSImmOpValue - Return encoding for a 10-bit immediate which is + /// encoded as a sign bit and an 9-bit immediate, separated by a single bit. + uint32_t getAuthSImmOpValue(const MCInst &MI, unsigned OpIdx, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + /// getCondBranchTargetOpValue - Return the encoded value for a conditional /// branch target. uint32_t getCondBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, @@ -282,6 +288,18 @@ return ShiftVal == 0 ? 0 : (1 << ShiftVal); } +/// getAuthSImmOpValue - encode a 10-bit scale signed immediate within an 11-bit +/// field in which bit 10 of that field is not used to encode any information +/// about the immediate. +uint32_t +AArch64MCCodeEmitter::getAuthSImmOpValue(const MCInst &MI, unsigned OpIdx, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + const MCOperand &MO = MI.getOperand(OpIdx); + int32_t offset = MO.getImm(); + return (uint32_t)offset; +} + /// getCondBranchTargetOpValue - Return the encoded value for a conditional /// branch target. uint32_t AArch64MCCodeEmitter::getCondBranchTargetOpValue( Index: test/MC/AArch64/armv8.3a-diagnostics.s =================================================================== --- /dev/null +++ test/MC/AArch64/armv8.3a-diagnostics.s @@ -0,0 +1,20 @@ +// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.3a < %s 2> %t +// RUN: FileCheck %s < %t + + msr ID_ISAR6_EL1, x0 +// CHECK: error: expected writable system register or pstate +// CHECK-NEXT: msr ID_ISAR6_EL1, x0 +// CHECK-NEXT: ^ + + ldraa x0, [x1, 4089] +// CHECK: error: index must be a multiple of 8 in range [-4096, 4088]. + ldraa x0, [x1, -4097] +// CHECK: error: index must be a multiple of 8 in range [-4096, 4088]. + ldraa x0, [x1, 4086] +// CHECK: error: index must be a multiple of 8 in range [-4096, 4088]. + ldrab x0, [x1, 4089] +// CHECK: error: index must be a multiple of 8 in range [-4096, 4088]. + ldrab x0, [x1, -4097] +// CHECK: error: index must be a multiple of 8 in range [-4096, 4088]. + ldrab x0, [x1, 4086] +// CHECK: error: index must be a multiple of 8 in range [-4096, 4088]. Index: test/MC/AArch64/armv8.3a-signed-pointer.s =================================================================== --- /dev/null +++ test/MC/AArch64/armv8.3a-signed-pointer.s @@ -0,0 +1,235 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.3a < %s 2> %t | FileCheck %s +// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2> %t +// RUN: FileCheck --check-prefix=CHECK-REQ %s < %t + + mrs x0, apiakeylo_el1 + mrs x0, apiakeyhi_el1 + mrs x0, apibkeylo_el1 + mrs x0, apibkeyhi_el1 + mrs x0, apdakeylo_el1 + mrs x0, apdakeyhi_el1 + mrs x0, apdbkeylo_el1 + mrs x0, apdbkeyhi_el1 + mrs x0, apgakeylo_el1 + mrs x0, apgakeyhi_el1 + +// CHECK: mrs x0, APIAKeyLo_EL1 // encoding: [0x00,0x21,0x38,0xd5] +// CHECK: mrs x0, APIAKeyHi_EL1 // encoding: [0x20,0x21,0x38,0xd5] +// CHECK: mrs x0, APIBKeyLo_EL1 // encoding: [0x40,0x21,0x38,0xd5] +// CHECK: mrs x0, APIBKeyHi_EL1 // encoding: [0x60,0x21,0x38,0xd5] +// CHECK: mrs x0, APDAKeyLo_EL1 // encoding: [0x00,0x22,0x38,0xd5] +// CHECK: mrs x0, APDAKeyHi_EL1 // encoding: [0x20,0x22,0x38,0xd5] +// CHECK: mrs x0, APDBKeyLo_EL1 // encoding: [0x40,0x22,0x38,0xd5] +// CHECK: mrs x0, APDBKeyHi_EL1 // encoding: [0x60,0x22,0x38,0xd5] +// CHECK: mrs x0, APGAKeyLo_EL1 // encoding: [0x00,0x23,0x38,0xd5] +// CHECK: mrs x0, APGAKeyHi_EL1 // encoding: [0x20,0x23,0x38,0xd5] + +// CHECK-REQ: error: expected readable system register +// CHECK-REQ: error: expected readable system register +// CHECK-REQ: error: expected readable system register +// CHECK-REQ: error: expected readable system register +// CHECK-REQ: error: expected readable system register +// CHECK-REQ: error: expected readable system register +// CHECK-REQ: error: expected readable system register +// CHECK-REQ: error: expected readable system register +// CHECK-REQ: error: expected readable system register +// CHECK-REQ: error: expected readable system register + + msr apiakeylo_el1, x0 + msr apiakeyhi_el1, x0 + msr apibkeylo_el1, x0 + msr apibkeyhi_el1, x0 + msr apdakeylo_el1, x0 + msr apdakeyhi_el1, x0 + msr apdbkeylo_el1, x0 + msr apdbkeyhi_el1, x0 + msr apgakeylo_el1, x0 + msr apgakeyhi_el1, x0 + +// CHECK: msr APIAKeyLo_EL1, x0 // encoding: [0x00,0x21,0x18,0xd5] +// CHECK: msr APIAKeyHi_EL1, x0 // encoding: [0x20,0x21,0x18,0xd5] +// CHECK: msr APIBKeyLo_EL1, x0 // encoding: [0x40,0x21,0x18,0xd5] +// CHECK: msr APIBKeyHi_EL1, x0 // encoding: [0x60,0x21,0x18,0xd5] +// CHECK: msr APDAKeyLo_EL1, x0 // encoding: [0x00,0x22,0x18,0xd5] +// CHECK: msr APDAKeyHi_EL1, x0 // encoding: [0x20,0x22,0x18,0xd5] +// CHECK: msr APDBKeyLo_EL1, x0 // encoding: [0x40,0x22,0x18,0xd5] +// CHECK: msr APDBKeyHi_EL1, x0 // encoding: [0x60,0x22,0x18,0xd5] +// CHECK: msr APGAKeyLo_EL1, x0 // encoding: [0x00,0x23,0x18,0xd5] +// CHECK: msr APGAKeyHi_EL1, x0 // encoding: [0x20,0x23,0x18,0xd5] + +// CHECK-REQ: error: expected writable system register or pstate +// CHECK-REQ: error: expected writable system register or pstate +// CHECK-REQ: error: expected writable system register or pstate +// CHECK-REQ: error: expected writable system register or pstate +// CHECK-REQ: error: expected writable system register or pstate +// CHECK-REQ: error: expected writable system register or pstate +// CHECK-REQ: error: expected writable system register or pstate +// CHECK-REQ: error: expected writable system register or pstate +// CHECK-REQ: error: expected writable system register or pstate +// CHECK-REQ: error: expected writable system register or pstate + + paciasp +// CHECK: paciasp // encoding: [0x3f,0x23,0x03,0xd5] +// CHECK-REQ: error: instruction requires: armv8.3a + autiasp +// CHECK: autiasp // encoding: [0xbf,0x23,0x03,0xd5] +// CHECK-REQ: error: instruction requires: armv8.3a + paciaz +// CHECK: paciaz // encoding: [0x1f,0x23,0x03,0xd5] +// CHECK-REQ: error: instruction requires: armv8.3a + autiaz +// CHECK: autiaz // encoding: [0x9f,0x23,0x03,0xd5] +// CHECK-REQ: error: instruction requires: armv8.3a + pacia1716 +// CHECK: pacia1716 // encoding: [0x1f,0x21,0x03,0xd5] +// CHECK-REQ: error: instruction requires: armv8.3a + autia1716 +// CHECK: autia1716 // encoding: [0x9f,0x21,0x03,0xd5] +// CHECK-REQ: error: instruction requires: armv8.3a + pacibsp +// CHECK: pacibsp // encoding: [0x7f,0x23,0x03,0xd5] +// CHECK-REQ: error: instruction requires: armv8.3a + autibsp +// CHECK: autibsp // encoding: [0xff,0x23,0x03,0xd5] +// CHECK-REQ: error: instruction requires: armv8.3a + pacibz +// CHECK: pacibz // encoding: [0x5f,0x23,0x03,0xd5] +// CHECK-REQ: error: instruction requires: armv8.3a + autibz +// CHECK: autibz // encoding: [0xdf,0x23,0x03,0xd5] +// CHECK-REQ: error: instruction requires: armv8.3a + pacib1716 +// CHECK: pacib1716 // encoding: [0x5f,0x21,0x03,0xd5] +// CHECK-REQ: error: instruction requires: armv8.3a + autib1716 +// CHECK: autib1716 // encoding: [0xdf,0x21,0x03,0xd5] +// CHECK-REQ: error: instruction requires: armv8.3a + xpaclri +// CHECK: xpaclri // encoding: [0xff,0x20,0x03,0xd5] +// CHECK-REQ: error: instruction requires: armv8.3a + + pacia x0, x1 +// CHECK: pacia x0, x1 // encoding: [0x20,0x00,0xc1,0xda] +// CHECK-REQ: error: instruction requires: armv8.3a + autia x0, x1 +// CHECK: autia x0, x1 // encoding: [0x20,0x10,0xc1,0xda] +// CHECK-REQ: error: instruction requires: armv8.3a + pacda x0, x1 +// CHECK: pacda x0, x1 // encoding: [0x20,0x08,0xc1,0xda] +// CHECK-REQ: error: instruction requires: armv8.3a + autda x0, x1 +// CHECK: autda x0, x1 // encoding: [0x20,0x18,0xc1,0xda] +// CHECK-REQ: error: instruction requires: armv8.3a + pacib x0, x1 +// CHECK: pacib x0, x1 // encoding: [0x20,0x04,0xc1,0xda] +// CHECK-REQ: error: instruction requires: armv8.3a + autib x0, x1 +// CHECK: autib x0, x1 // encoding: [0x20,0x14,0xc1,0xda] +// CHECK-REQ: error: instruction requires: armv8.3a + pacdb x0, x1 +// CHECK: pacdb x0, x1 // encoding: [0x20,0x0c,0xc1,0xda] +// CHECK-REQ: error: instruction requires: armv8.3a + autdb x0, x1 +// CHECK: autdb x0, x1 // encoding: [0x20,0x1c,0xc1,0xda] +// CHECK-REQ: error: instruction requires: armv8.3a + pacga x0, x1, x2 +// CHECK: pacga x0, x1, x2 // encoding: [0x20,0x30,0xc2,0x9a] +// CHECK-REQ: error: instruction requires: armv8.3a + paciza x0 +// CHECK: paciza x0 // encoding: [0xe0,0x23,0xc1,0xda] +// CHECK-REQ: error: instruction requires: armv8.3a + autiza x0 +// CHECK: autiza x0 // encoding: [0xe0,0x33,0xc1,0xda] +// CHECK-REQ: error: instruction requires: armv8.3a + pacdza x0 +// CHECK: pacdza x0 // encoding: [0xe0,0x2b,0xc1,0xda] +// CHECK-REQ: error: instruction requires: armv8.3a + autdza x0 +// CHECK: autdza x0 // encoding: [0xe0,0x3b,0xc1,0xda] +// CHECK-REQ: error: instruction requires: armv8.3a + pacizb x0 +// CHECK: pacizb x0 // encoding: [0xe0,0x27,0xc1,0xda] +// CHECK-REQ: error: instruction requires: armv8.3a + autizb x0 +// CHECK: autizb x0 // encoding: [0xe0,0x37,0xc1,0xda] +// CHECK-REQ: error: instruction requires: armv8.3a + pacdzb x0 +// CHECK: pacdzb x0 // encoding: [0xe0,0x2f,0xc1,0xda] +// CHECK-REQ: error: instruction requires: armv8.3a + autdzb x0 +// CHECK: autdzb x0 // encoding: [0xe0,0x3f,0xc1,0xda] +// CHECK-REQ: error: instruction requires: armv8.3a + xpaci x0 +// CHECK: xpaci x0 // encoding: [0xe0,0x43,0xc1,0xda] +// CHECK-REQ: error: instruction requires: armv8.3a + xpacd x0 +// CHECK: xpacd x0 // encoding: [0xe0,0x47,0xc1,0xda] +// CHECK-REQ: error: instruction requires: armv8.3a + + braa x0, x1 +// CHECK: braa x0, x1 // encoding: [0x01,0x08,0x1f,0xd7] +// CHECK-REQ: error: instruction requires: armv8.3a + brab x0, x1 +// CHECK: brab x0, x1 // encoding: [0x01,0x0c,0x1f,0xd7] +// CHECK-REQ: error: instruction requires: armv8.3a + blraa x0, x1 +// CHECK: blraa x0, x1 // encoding: [0x01,0x08,0x3f,0xd7] +// CHECK-REQ: error: instruction requires: armv8.3a + blrab x0, x1 +// CHECK: blrab x0, x1 // encoding: [0x01,0x0c,0x3f,0xd7] +// CHECK-REQ: error: instruction requires: armv8.3a + + braaz x0 +// CHECK: braaz x0 // encoding: [0x1f,0x08,0x1f,0xd6] +// CHECK-REQ: error: instruction requires: armv8.3a + brabz x0 +// CHECK: brabz x0 // encoding: [0x1f,0x0c,0x1f,0xd6] +// CHECK-REQ: error: instruction requires: armv8.3a + blraaz x0 +// CHECK: blraaz x0 // encoding: [0x1f,0x08,0x3f,0xd6] +// CHECK-REQ: error: instruction requires: armv8.3a + blrabz x0 +// CHECK: blrabz x0 // encoding: [0x1f,0x0c,0x3f,0xd6] +// CHECK-REQ: error: instruction requires: armv8.3a + retaa +// CHECK: retaa // encoding: [0xff,0x0b,0x5f,0xd6] +// CHECK-REQ: error: instruction requires: armv8.3a + retab +// CHECK: retab // encoding: [0xff,0x0f,0x5f,0xd6] +// CHECK-REQ: error: instruction requires: armv8.3a + eretaa +// CHECK: eretaa // encoding: [0xff,0x0b,0x9f,0xd6] +// CHECK-REQ: error: instruction requires: armv8.3a + eretab +// CHECK: eretab // encoding: [0xff,0x0f,0x9f,0xd6] +// CHECK-REQ: error: instruction requires: armv8.3a + ldraa x0, [x1, 4088] +// CHECK: ldraa x0, [x1, #4088] // encoding: [0x20,0xf4,0x3f,0xf8] +// CHECK-REQ: error: instruction requires: armv8.3a + ldraa x0, [x1, -4096] +// CHECK: ldraa x0, [x1, #-4096] // encoding: [0x20,0x04,0x60,0xf8] +// CHECK-REQ: error: instruction requires: armv8.3a + ldrab x0, [x1, 4088] +// CHECK: ldrab x0, [x1, #4088] // encoding: [0x20,0xf4,0xbf,0xf8] +// CHECK-REQ: error: instruction requires: armv8.3a + ldrab x0, [x1, -4096] +// CHECK: ldrab x0, [x1, #-4096] // encoding: [0x20,0x04,0xe0,0xf8] +// CHECK-REQ: error: instruction requires: armv8.3a + ldraa x0, [x1, 4088]! +// CHECK: ldraa x0, [x1, #4088]! // encoding: [0x20,0xfc,0x3f,0xf8] +// CHECK-REQ: error: instruction requires: armv8.3a + ldraa x0, [x1, -4096]! +// CHECK: ldraa x0, [x1, #-4096]! // encoding: [0x20,0x0c,0x60,0xf8] +// CHECK-REQ: error: instruction requires: armv8.3a + ldrab x0, [x1, 4088]! +// CHECK: ldrab x0, [x1, #4088]! // encoding: [0x20,0xfc,0xbf,0xf8] +// CHECK-REQ: error: instruction requires: armv8.3a + ldrab x0, [x1, -4096]! +// CHECK: ldrab x0, [x1, #-4096]! // encoding: [0x20,0x0c,0xe0,0xf8] +// CHECK-REQ: error: instruction requires: armv8.3a + ldraa x0, [x1] +// CHECK: ldraa x0, [x1] // encoding: [0x20,0x04,0x20,0xf8] +// CHECK-REQ: error: instruction requires: armv8.3a + ldrab x0, [x1] +// CHECK: ldrab x0, [x1] // encoding: [0x20,0x04,0xa0,0xf8] +// CHECK-REQ: error: instruction requires: armv8.3a Index: test/MC/Disassembler/AArch64/armv8.3a-signed-pointer.txt =================================================================== --- /dev/null +++ test/MC/Disassembler/AArch64/armv8.3a-signed-pointer.txt @@ -0,0 +1,114 @@ +# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.3a --disassemble < %s | FileCheck %s + +# CHECK: paciasp +# CHECK: autiasp +# CHECK: paciaz +# CHECK: autiaz +# CHECK: pacia1716 +# CHECK: autia1716 +# CHECK: pacibsp +# CHECK: autibsp +# CHECK: pacibz +# CHECK: autibz +# CHECK: pacib1716 +# CHECK: autib1716 +# CHECK: xpaclri +[0x3f,0x23,0x03,0xd5] +[0xbf,0x23,0x03,0xd5] +[0x1f,0x23,0x03,0xd5] +[0x9f,0x23,0x03,0xd5] +[0x1f,0x21,0x03,0xd5] +[0x9f,0x21,0x03,0xd5] +[0x7f,0x23,0x03,0xd5] +[0xff,0x23,0x03,0xd5] +[0x5f,0x23,0x03,0xd5] +[0xdf,0x23,0x03,0xd5] +[0x5f,0x21,0x03,0xd5] +[0xdf,0x21,0x03,0xd5] +[0xff,0x20,0x03,0xd5] + +# CHECK: pacia x0, x1 +# CHECK: autia x0, x1 +# CHECK: pacda x0, x1 +# CHECK: autda x0, x1 +# CHECK: pacib x0, x1 +# CHECK: autib x0, x1 +# CHECK: pacdb x0, x1 +# CHECK: autdb x0, x1 +# CHECK: pacga x0, x1, x2 +# CHECK: paciza x0 +# CHECK: autiza x0 +# CHECK: pacdza x0 +# CHECK: autdza x0 +# CHECK: pacizb x0 +# CHECK: autizb x0 +# CHECK: pacdzb x0 +# CHECK: autdzb x0 +# CHECK: xpaci x0 +# CHECK: xpacd x0 +[0x20,0x00,0xc1,0xda] +[0x20,0x10,0xc1,0xda] +[0x20,0x08,0xc1,0xda] +[0x20,0x18,0xc1,0xda] +[0x20,0x04,0xc1,0xda] +[0x20,0x14,0xc1,0xda] +[0x20,0x0c,0xc1,0xda] +[0x20,0x1c,0xc1,0xda] +[0x20,0x30,0xc2,0x9a] +[0xe0,0x23,0xc1,0xda] +[0xe0,0x33,0xc1,0xda] +[0xe0,0x2b,0xc1,0xda] +[0xe0,0x3b,0xc1,0xda] +[0xe0,0x27,0xc1,0xda] +[0xe0,0x37,0xc1,0xda] +[0xe0,0x2f,0xc1,0xda] +[0xe0,0x3f,0xc1,0xda] +[0xe0,0x43,0xc1,0xda] +[0xe0,0x47,0xc1,0xda] + +# CHECK: braa x0, x1 +# CHECK: brab x0, x1 +# CHECK: blraa x0, x1 +# CHECK: blrab x0, x1 +[0x01,0x08,0x1f,0xd7] +[0x01,0x0c,0x1f,0xd7] +[0x01,0x08,0x3f,0xd7] +[0x01,0x0c,0x3f,0xd7] + +# CHECK: braaz x0 +# CHECK: brabz x0 +# CHECK: blraaz x0 +# CHECK: blrabz x0 +# CHECK: retaa +# CHECK: retab +# CHECK: eretaa +# CHECK: eretab +# CHECK: ldraa x0, [x1, #4088] +# CHECK: ldraa x0, [x1, #-4096] +# CHECK: ldrab x0, [x1, #4088] +# CHECK: ldrab x0, [x1, #-4096] +# CHECK: ldraa x0, [x1, #4088]! +# CHECK: ldraa x0, [x1, #-4096]! +# CHECK: ldrab x0, [x1, #4088]! +# CHECK: ldrab x0, [x1, #-4096]! +[0x1f,0x08,0x1f,0xd6] +[0x1f,0x0c,0x1f,0xd6] +[0x1f,0x08,0x3f,0xd6] +[0x1f,0x0c,0x3f,0xd6] +[0xff,0x0b,0x5f,0xd6] +[0xff,0x0f,0x5f,0xd6] +[0xff,0x0b,0x9f,0xd6] +[0xff,0x0f,0x9f,0xd6] +[0x20,0xf4,0x3f,0xf8] +[0x20,0x04,0x60,0xf8] +[0x20,0xf4,0xbf,0xf8] +[0x20,0x04,0xe0,0xf8] +[0x20,0xfc,0x3f,0xf8] +[0x20,0x0c,0x60,0xf8] +[0x20,0xfc,0xbf,0xf8] +[0x20,0x0c,0xe0,0xf8] + +# CHECK: ldraa x0, [x1] +# CHECK: ldrab x0, [x1] +[0x20,0x04,0x20,0xf8] +[0x20,0x04,0xa0,0xf8]