Index: lib/Target/AMDGPU/AMDGPU.td
===================================================================
--- lib/Target/AMDGPU/AMDGPU.td
+++ lib/Target/AMDGPU/AMDGPU.td
@@ -214,6 +214,12 @@
   "Has i16/f16 instructions"
 >;
 
+def Feature16BitLegacyInsts : SubtargetFeature<"16-bit-legacy-insts",
+  "Has16BitLegacyInsts",
+  "true",
+  "Has opcodes with the same name but another semantics in next generation ISA"
+>;
+
 def FeatureVOP3P : SubtargetFeature<"vop3p",
   "HasVOP3PInsts",
   "true",
@@ -455,7 +461,7 @@
 def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
   [FeatureFP64, FeatureLocalMemorySize65536,
    FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
-   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
+   FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts, Feature16BitLegacyInsts,
    FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel,
    FeatureScalarStores, FeatureInv2PiInlineImm,
    FeatureSDWA, FeatureSDWAOutModsVOPC, FeatureSDWAMac, FeatureDPP
@@ -698,6 +704,8 @@
 
 def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
   AssemblerPredicate<"Feature16BitInsts">;
+def Has16BitLegacyInsts : Predicate<"Subtarget->has16BitLegacyInsts()">,
+  AssemblerPredicate<"Feature16BitLegacyInsts">;
 def HasVOP3PInsts : Predicate<"Subtarget->hasVOP3PInsts()">,
   AssemblerPredicate<"FeatureVOP3P">;
 
Index: lib/Target/AMDGPU/AMDGPUInstrInfo.cpp
===================================================================
--- lib/Target/AMDGPU/AMDGPUInstrInfo.cpp
+++ lib/Target/AMDGPU/AMDGPUInstrInfo.cpp
@@ -70,7 +70,8 @@
   SI = 0,
   VI = 1,
   SDWA = 2,
-  SDWA9 = 3
+  SDWA9 = 3,
+  LEGACY = 4
 };
 
 // Wrapper for Tablegen'd function.  enum Subtarget is not defined in any
@@ -110,6 +111,10 @@
     Gen = ST.getGeneration() == AMDGPUSubtarget::GFX9 ? SIEncodingFamily::SDWA9
                                                       : SIEncodingFamily::SDWA;
 
+  if ((get(Opcode).TSFlags & SIInstrFlags::LEGACY) != 0 &&
+      ST.getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS)
+    Gen = SIEncodingFamily::LEGACY;
+
   int MCOp = AMDGPU::getMCOpcode(Opcode, Gen);
 
   // -1 means that Opcode is already a native instruction.
Index: lib/Target/AMDGPU/AMDGPUSubtarget.h
===================================================================
--- lib/Target/AMDGPU/AMDGPUSubtarget.h
+++ lib/Target/AMDGPU/AMDGPUSubtarget.h
@@ -143,6 +143,7 @@
   bool SGPRInitBug;
   bool HasSMemRealTime;
   bool Has16BitInsts;
+  bool Has16BitLegacyInsts;
   bool HasVOP3PInsts;
   bool HasMovrel;
   bool HasVGPRIndexMode;
@@ -239,6 +240,10 @@
     return Has16BitInsts;
   }
 
+  bool has16BitLegacyInsts() const {
+    return Has16BitLegacyInsts;
+  }
+
   bool hasVOP3PInsts() const {
     return HasVOP3PInsts;
   }
Index: lib/Target/AMDGPU/AMDGPUSubtarget.cpp
===================================================================
--- lib/Target/AMDGPU/AMDGPUSubtarget.cpp
+++ lib/Target/AMDGPU/AMDGPUSubtarget.cpp
@@ -147,6 +147,7 @@
     SGPRInitBug(false),
     HasSMemRealTime(false),
     Has16BitInsts(false),
+    Has16BitLegacyInsts(false),
     HasVOP3PInsts(false),
     HasMovrel(false),
     HasVGPRIndexMode(false),
Index: lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
===================================================================
--- lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -208,6 +208,9 @@
     if (Res) break;
 
     Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address);
+    if (Res) break;
+
+    Res = tryDecodeInst(DecoderTableLEGACY64, MI, QW, Address);
   } while (false);
 
   if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi ||
Index: lib/Target/AMDGPU/SIDefines.h
===================================================================
--- lib/Target/AMDGPU/SIDefines.h
+++ lib/Target/AMDGPU/SIDefines.h
@@ -69,7 +69,8 @@
   VOPAsmPrefer32Bit = UINT64_C(1) << 41,
   HasFPClamp = UINT64_C(1) << 42,
   VOP3_OPSEL = UINT64_C(1) << 43,
-  maybeAtomic = UINT64_C(1) << 44
+  maybeAtomic = UINT64_C(1) << 44,
+  LEGACY = UINT64_C(1) << 45
 };
 
 // v_cmp_class_* etc. use a 10-bit mask for what operation is checked.
Index: lib/Target/AMDGPU/SIFoldOperands.cpp
===================================================================
--- lib/Target/AMDGPU/SIFoldOperands.cpp
+++ lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -134,7 +134,7 @@
     if (static_cast<int>(OpNo) == Src2Idx) {
       bool IsF32 = Opc == AMDGPU::V_MAC_F32_e64;
       const MCInstrDesc &MadDesc
-        = TII->get(IsF32 ? AMDGPU::V_MAD_F32 : AMDGPU::V_MAD_F16);
+        = TII->get(IsF32 ? AMDGPU::V_MAD_F32 : TII->getMadF16Opcode());
       return TII->isInlineConstant(OpToFold, MadDesc.OpInfo[OpNo].OperandType);
     }
     return false;
@@ -201,7 +201,7 @@
 
       // Check if changing this to a v_mad_{f16, f32} instruction will allow us
       // to fold the operand.
-      MI->setDesc(TII->get(IsF32 ? AMDGPU::V_MAD_F32 : AMDGPU::V_MAD_F16));
+      MI->setDesc(TII->get(IsF32 ? AMDGPU::V_MAD_F32 : TII->getMadF16Opcode()));
       bool FoldAsMAD = tryAddToFoldList(FoldList, MI, OpNo, OpToFold, TII);
       if (FoldAsMAD) {
         MI->untieRegOperand(OpNo);
Index: lib/Target/AMDGPU/SIInstrFormats.td
===================================================================
--- lib/Target/AMDGPU/SIInstrFormats.td
+++ lib/Target/AMDGPU/SIInstrFormats.td
@@ -90,6 +90,10 @@
   // Is it possible for this instruction to be atomic?
   field bit maybeAtomic = 0;
 
+  // This bit indicates that this is a legacy opcode which has the same
+  // name but another semantics in next generation ISA
+  field bit LEGACY = 0;
+
   // These need to be kept in sync with the enum in SIInstrFlags.
   let TSFlags{0} = SALU;
   let TSFlags{1} = VALU;
@@ -137,6 +141,7 @@
   let TSFlags{43} = VOP3_OPSEL;
 
   let TSFlags{44} = maybeAtomic;
+  let TSFlags{45} = LEGACY;
 
   let SchedRW = [Write32Bit];
 
Index: lib/Target/AMDGPU/SIInstrInfo.h
===================================================================
--- lib/Target/AMDGPU/SIInstrInfo.h
+++ lib/Target/AMDGPU/SIInstrInfo.h
@@ -183,6 +183,8 @@
   // DstRC, then AMDGPU::COPY is returned.
   unsigned getMovOpcode(const TargetRegisterClass *DstRC) const;
 
+  unsigned getMadF16Opcode() const;
+
   LLVM_READONLY
   int commuteOpcode(unsigned Opc) const;
 
Index: lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- lib/Target/AMDGPU/SIInstrInfo.cpp
+++ lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -698,6 +698,11 @@
   return AMDGPU::COPY;
 }
 
+unsigned SIInstrInfo::getMadF16Opcode() const {
+  return (ST.getGeneration() < SISubtarget::GFX9)?
+         AMDGPU::V_MAD_F16_GFX8 : AMDGPU::V_MAD_LEGACY_F16;
+}
+
 static unsigned getSGPRSpillSaveOpcode(unsigned Size) {
   switch (Size) {
   case 4:
@@ -1819,7 +1824,7 @@
   }
 
   if (Opc == AMDGPU::V_MAD_F32 || Opc == AMDGPU::V_MAC_F32_e64 ||
-      Opc == AMDGPU::V_MAD_F16 || Opc == AMDGPU::V_MAC_F16_e64) {
+      Opc == getMadF16Opcode() || Opc == AMDGPU::V_MAC_F16_e64) {
     // Don't fold if we are using source or output modifiers. The new VOP2
     // instructions don't have them.
     if (hasAnyModifiersSet(UseMI))
@@ -2061,7 +2066,7 @@
   const MachineOperand *Omod = getNamedOperand(MI, AMDGPU::OpName::omod);
 
   return BuildMI(*MBB, MI, MI.getDebugLoc(),
-                 get(IsF16 ? AMDGPU::V_MAD_F16 : AMDGPU::V_MAD_F32))
+                 get(IsF16 ? getMadF16Opcode() : AMDGPU::V_MAD_F32))
       .add(*Dst)
       .addImm(Src0Mods ? Src0Mods->getImm() : 0)
       .add(*Src0)
Index: lib/Target/AMDGPU/SIInstrInfo.td
===================================================================
--- lib/Target/AMDGPU/SIInstrInfo.td
+++ lib/Target/AMDGPU/SIInstrInfo.td
@@ -22,6 +22,7 @@
   int VI = 1;
   int SDWA = 2;
   int SDWA9 = 3;
+  int LEGACY = 4;
 }
 
 //===----------------------------------------------------------------------===//
@@ -1756,7 +1757,8 @@
   let ValueCols = [[!cast<string>(SIEncodingFamily.SI)],
                    [!cast<string>(SIEncodingFamily.VI)],
                    [!cast<string>(SIEncodingFamily.SDWA)],
-                   [!cast<string>(SIEncodingFamily.SDWA9)]];
+                   [!cast<string>(SIEncodingFamily.SDWA9)],
+                   [!cast<string>(SIEncodingFamily.LEGACY)]];
 }
 
 // Get equivalent SOPK instruction.
Index: lib/Target/AMDGPU/VOP3Instructions.td
===================================================================
--- lib/Target/AMDGPU/VOP3Instructions.td
+++ lib/Target/AMDGPU/VOP3Instructions.td
@@ -310,18 +310,43 @@
 
 let SubtargetPredicate = Has16BitInsts in {
 
-def V_DIV_FIXUP_F16   : VOP3Inst <"v_div_fixup_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, AMDGPUdiv_fixup>;
+let LEGACY = 1 in {
+let Predicates = [Has16BitLegacyInsts], SubtargetPredicate = Has16BitLegacyInsts in {
+def V_DIV_FIXUP_F16_GFX8 : VOP3Inst <"v_div_fixup_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, AMDGPUdiv_fixup>;
+} // End Predicates = [Has16BitLegacyInsts], SubtargetPredicate = Has16BitLegacyInsts
+}
+
+let SubtargetPredicate = isGFX9 in {
+def V_DIV_FIXUP_LEGACY_F16 : VOP3Inst <"v_div_fixup_legacy_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, AMDGPUdiv_fixup>;
+def V_DIV_FIXUP_F16_GFX9   : VOP3Inst <"v_div_fixup_f16", VOP3_Profile<VOP_F16_F16_F16_F16>>;
+}
 
 let isCommutable = 1 in {
 
-def V_FMA_F16         : VOP3Inst <"v_fma_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fma>;
+let LEGACY = 1 in {
+let Predicates = [Has16BitLegacyInsts], SubtargetPredicate = Has16BitLegacyInsts in {
+def V_MAD_F16_GFX8 : VOP3Inst <"v_mad_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fmad>;
+def V_MAD_U16_GFX8 : VOP3Inst <"v_mad_u16", VOP3_Profile<VOP_I16_I16_I16_I16>>;
+def V_MAD_I16_GFX8 : VOP3Inst <"v_mad_i16", VOP3_Profile<VOP_I16_I16_I16_I16>>;
+def V_FMA_F16_GFX8 : VOP3Inst <"v_fma_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fma>;
+} // End Predicates = [Has16BitLegacyInsts], SubtargetPredicate = Has16BitLegacyInsts
+}
+
+let SubtargetPredicate = isGFX9 in {
+def V_MAD_LEGACY_F16 : VOP3Inst <"v_mad_legacy_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fmad>;
+def V_MAD_LEGACY_U16 : VOP3Inst <"v_mad_legacy_u16", VOP3_Profile<VOP_I16_I16_I16_I16>>;
+def V_MAD_LEGACY_I16 : VOP3Inst <"v_mad_legacy_i16", VOP3_Profile<VOP_I16_I16_I16_I16>>;
+def V_FMA_LEGACY_F16 : VOP3Inst <"v_fma_legacy_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fma>;
+
+def V_MAD_F16_GFX9   : VOP3Inst <"v_mad_f16", VOP3_Profile<VOP_F16_F16_F16_F16>>;
+def V_MAD_U16_GFX9   : VOP3Inst <"v_mad_u16", VOP3_Profile<VOP_I16_I16_I16_I16>>;
+def V_MAD_I16_GFX9   : VOP3Inst <"v_mad_i16", VOP3_Profile<VOP_I16_I16_I16_I16>>;
+def V_FMA_F16_GFX9   : VOP3Inst <"v_fma_f16", VOP3_Profile<VOP_F16_F16_F16_F16>>;
+} // End SubtargetPredicate = isGFX9
+
 def V_INTERP_P1LL_F16 : VOP3Inst <"v_interp_p1ll_f16", VOP3_Profile<VOP_F32_F32_F16>>;
 def V_INTERP_P1LV_F16 : VOP3Inst <"v_interp_p1lv_f16", VOP3_Profile<VOP_F32_F32_F16_F16>>;
 def V_INTERP_P2_F16   : VOP3Inst <"v_interp_p2_f16", VOP3_Profile<VOP_F16_F32_F16_F32>>;
-def V_MAD_F16         : VOP3Inst <"v_mad_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fmad>;
-
-def V_MAD_U16 : VOP3Inst <"v_mad_u16", VOP3_Profile<VOP_I16_I16_I16_I16>>;
-def V_MAD_I16 : VOP3Inst <"v_mad_i16", VOP3_Profile<VOP_I16_I16_I16_I16>>;
 
 }  // End isCommutable = 1
 } // End SubtargetPredicate = Has16BitInsts
@@ -352,8 +377,11 @@
 >;
 }
 
-defm: Ternary_i16_Pats<mul, add, V_MAD_U16, zext>;
-defm: Ternary_i16_Pats<mul, add, V_MAD_I16, sext>;
+defm: Ternary_i16_Pats<mul, add, V_MAD_U16_GFX8, zext>;
+defm: Ternary_i16_Pats<mul, add, V_MAD_I16_GFX8, sext>;
+
+defm: Ternary_i16_Pats<mul, add, V_MAD_LEGACY_U16, zext>;
+defm: Ternary_i16_Pats<mul, add, V_MAD_LEGACY_I16, sext>;
 
 } // End Predicates = [Has16BitInsts]
 
@@ -514,6 +542,15 @@
 
 } // End AssemblerPredicates = [isVI], DecoderNamespace = "VI"
 
+let AssemblerPredicates = [isVI], DecoderNamespace = "LEGACY" in {
+
+multiclass VOP3_Legacy_Real_vi<bits<10> op> {
+  def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.LEGACY>,
+            VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
+}
+
+} // End AssemblerPredicates = [isVI], DecoderNamespace = "LEGACY"
+
 defm V_MAD_U64_U32      : VOP3be_Real_vi <0x1E8>;
 defm V_MAD_I64_I32      : VOP3be_Real_vi <0x1E9>;
 
@@ -558,14 +595,25 @@
 defm V_MQSAD_PK_U16_U8  : VOP3_Real_vi <0x1e6>;
 defm V_MQSAD_U32_U8     : VOP3_Real_vi <0x1e7>;
 
-defm V_MAD_F16          : VOP3_Real_vi <0x1ea>;
-defm V_MAD_U16          : VOP3_Real_vi <0x1eb>;
-defm V_MAD_I16          : VOP3_Real_vi <0x1ec>;
-
 defm V_PERM_B32         : VOP3_Real_vi <0x1ed>;
 
-defm V_FMA_F16          : VOP3_Real_vi <0x1ee>;
-defm V_DIV_FIXUP_F16    : VOP3_Real_vi <0x1ef>;
+defm V_MAD_F16_GFX8         : VOP3_Legacy_Real_vi <0x1ea>;
+defm V_MAD_U16_GFX8         : VOP3_Legacy_Real_vi <0x1eb>;
+defm V_MAD_I16_GFX8         : VOP3_Legacy_Real_vi <0x1ec>;
+defm V_FMA_F16_GFX8         : VOP3_Legacy_Real_vi <0x1ee>;
+defm V_DIV_FIXUP_F16_GFX8   : VOP3_Legacy_Real_vi <0x1ef>;
+
+defm V_MAD_LEGACY_F16       : VOP3_Real_vi <0x1ea>;
+defm V_MAD_LEGACY_U16       : VOP3_Real_vi <0x1eb>;
+defm V_MAD_LEGACY_I16       : VOP3_Real_vi <0x1ec>;
+defm V_FMA_LEGACY_F16       : VOP3_Real_vi <0x1ee>;
+defm V_DIV_FIXUP_LEGACY_F16 : VOP3_Real_vi <0x1ef>;
+
+defm V_MAD_F16_GFX9         : VOP3_Real_vi <0x203>;
+defm V_MAD_U16_GFX9         : VOP3_Real_vi <0x204>;
+defm V_MAD_I16_GFX9         : VOP3_Real_vi <0x205>;
+defm V_FMA_F16_GFX9         : VOP3_Real_vi <0x206>;
+defm V_DIV_FIXUP_F16_GFX9   : VOP3_Real_vi <0x207>;
 
 defm V_INTERP_P1LL_F16  : VOP3_Real_vi <0x274>;
 defm V_INTERP_P1LV_F16  : VOP3_Real_vi <0x275>;
Index: test/MC/AMDGPU/vop3-gfx9.s
===================================================================
--- test/MC/AMDGPU/vop3-gfx9.s
+++ test/MC/AMDGPU/vop3-gfx9.s
@@ -190,3 +190,135 @@
 
 v_sub_i16 v5, v1, v2 clamp
 // GFX9: v_sub_i16 v5, v1, v2 clamp ; encoding: [0x05,0x80,0x9f,0xd2,0x01,0x05,0x02,0x00]
+
+v_fma_f16_e64 v5, v1, v2, v3
+// GFX9: v_fma_f16 v5, v1, v2, v3 ; encoding: [0x05,0x00,0x06,0xd2,0x01,0x05,0x0e,0x04]
+
+v_fma_f16 v5, v1, -v2, v3
+// GFX9: v_fma_f16 v5, v1, -v2, v3 ; encoding: [0x05,0x00,0x06,0xd2,0x01,0x05,0x0e,0x44]
+
+v_fma_f16 v5, v1, v2, |v3|
+// GFX9: v_fma_f16 v5, v1, v2, |v3| ; encoding: [0x05,0x04,0x06,0xd2,0x01,0x05,0x0e,0x04]
+
+v_fma_f16 v5, v1, v2, v3 clamp
+// GFX9: v_fma_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0x06,0xd2,0x01,0x05,0x0e,0x04]
+
+v_fma_legacy_f16_e64 v5, v1, v2, v3
+// GFX9: v_fma_legacy_f16 v5, v1, v2, v3 ; encoding:  [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_legacy_f16 v5, -v1, v2, v3
+// GFX9: v_fma_legacy_f16 v5, -v1, v2, v3 ; encoding:  [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x24]
+
+v_fma_legacy_f16 v5, v1, |v2|, v3
+// GFX9: v_fma_legacy_f16 v5, v1, |v2|, v3 ; encoding:  [0x05,0x02,0xee,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_legacy_f16 v5, v1, v2, v3 clamp
+// GFX9: v_fma_legacy_f16 v5, v1, v2, v3 clamp ; encoding:  [0x05,0x80,0xee,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f16_e64 v5, 0.5, v2, v3
+// GFX9: v_div_fixup_f16 v5, 0.5, v2, v3 ; encoding: [0x05,0x00,0x07,0xd2,0xf0,0x04,0x0e,0x04]
+
+v_div_fixup_f16 v5, v1, 0.5, v3
+// GFX9: v_div_fixup_f16 v5, v1, 0.5, v3 ; encoding: [0x05,0x00,0x07,0xd2,0x01,0xe1,0x0d,0x04]
+
+v_div_fixup_f16 v5, v1, v2, 0.5
+// GFX9: v_div_fixup_f16 v5, v1, v2, 0.5 ; encoding: [0x05,0x00,0x07,0xd2,0x01,0x05,0xc2,0x03]
+
+v_div_fixup_f16 v5, -v1, v2, v3
+// GFX9: v_div_fixup_f16 v5, -v1, v2, v3 ; encoding: [0x05,0x00,0x07,0xd2,0x01,0x05,0x0e,0x24]
+
+v_div_fixup_f16 v5, |v1|, v2, v3
+// GFX9: v_div_fixup_f16 v5, |v1|, v2, v3 ; encoding: [0x05,0x01,0x07,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f16 v5, v1, v2, v3 clamp
+// GFX9: v_div_fixup_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0x07,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_legacy_f16_e64 v5, 0.5, v2, v3
+// GFX9: v_div_fixup_legacy_f16 v5, 0.5, v2, v3 ; encoding: [0x05,0x00,0xef,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_div_fixup_legacy_f16 v5, v1, 0.5, v3
+// GFX9: v_div_fixup_legacy_f16 v5, v1, 0.5, v3 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_div_fixup_legacy_f16 v5, v1, v2, 0.5
+// GFX9: v_div_fixup_legacy_f16 v5, v1, v2, 0.5 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x05,0xc2,0x03]
+
+v_div_fixup_legacy_f16 v5, -v1, v2, v3
+// GFX9: v_div_fixup_legacy_f16 v5, -v1, v2, v3 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0x24]
+
+v_div_fixup_legacy_f16 v5, v1, |v2|, v3
+// GFX9: v_div_fixup_legacy_f16 v5, v1, |v2|, v3 ; encoding: [0x05,0x02,0xef,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_legacy_f16 v5, v1, v2, v3 clamp
+// GFX9: v_div_fixup_legacy_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xef,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_f16_e64 v5, 0.5, v2, v3
+// GFX9: v_mad_f16 v5, 0.5, v2, v3 ; encoding: [0x05,0x00,0x03,0xd2,0xf0,0x04,0x0e,0x04]
+
+v_mad_f16 v5, v1, 0.5, v3
+// GFX9: v_mad_f16 v5, v1, 0.5, v3 ; encoding: [0x05,0x00,0x03,0xd2,0x01,0xe1,0x0d,0x04]
+
+v_mad_f16 v5, v1, v2, 0.5
+// GFX9: v_mad_f16 v5, v1, v2, 0.5 ; encoding: [0x05,0x00,0x03,0xd2,0x01,0x05,0xc2,0x03]
+
+v_mad_f16 v5, v1, v2, -v3
+// GFX9: v_mad_f16 v5, v1, v2, -v3 ; encoding: [0x05,0x00,0x03,0xd2,0x01,0x05,0x0e,0x84]
+
+v_mad_f16 v5, v1, v2, |v3|
+// GFX9: v_mad_f16 v5, v1, v2, |v3| ; encoding: [0x05,0x04,0x03,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_f16 v5, v1, v2, v3 clamp
+// GFX9: v_mad_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0x03,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_i16_e64 v5, 0, v2, v3
+// GFX9: v_mad_i16 v5, 0, v2, v3 ; encoding: [0x05,0x00,0x05,0xd2,0x80,0x04,0x0e,0x04]
+
+v_mad_i16 v5, v1, -1, v3
+// GFX9: v_mad_i16 v5, v1, -1, v3 ; encoding: [0x05,0x00,0x05,0xd2,0x01,0x83,0x0d,0x04]
+
+v_mad_i16 v5, v1, v2, -4.0
+// GFX9: v_mad_i16 v5, v1, v2, -4.0 ; encoding: [0x05,0x00,0x05,0xd2,0x01,0x05,0xde,0x03]
+
+v_mad_legacy_f16_e64 v5, 0.5, v2, v3
+// GFX9: v_mad_legacy_f16 v5, 0.5, v2, v3 ; encoding: [0x05,0x00,0xea,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_mad_legacy_f16 v5, v1, 0.5, v3
+// GFX9: v_mad_legacy_f16 v5, v1, 0.5, v3 ; encoding: [0x05,0x00,0xea,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_mad_legacy_f16 v5, v1, v2, 0.5
+// GFX9: v_mad_legacy_f16 v5, v1, v2, 0.5 ; encoding: [0x05,0x00,0xea,0xd1,0x01,0x05,0xc2,0x03]
+
+v_mad_legacy_f16 v5, v1, -v2, v3
+// GFX9: v_mad_legacy_f16 v5, v1, -v2, v3 ; encoding: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0x44]
+
+v_mad_legacy_f16 v5, v1, |v2|, v3
+// GFX9: v_mad_legacy_f16 v5, v1, |v2|, v3 ; encoding: [0x05,0x02,0xea,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_legacy_f16 v5, v1, v2, v3 clamp
+// GFX9: v_mad_legacy_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xea,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_legacy_i16_e64 v5, 0, v2, v3
+// GFX9: v_mad_legacy_i16 v5, 0, v2, v3 ; encoding: [0x05,0x00,0xec,0xd1,0x80,0x04,0x0e,0x04]
+
+v_mad_legacy_i16 v5, v1, -1, v3
+// GFX9: v_mad_legacy_i16 v5, v1, -1, v3 ; encoding: [0x05,0x00,0xec,0xd1,0x01,0x83,0x0d,0x04]
+
+v_mad_legacy_i16 v5, v1, v2, -4.0
+// GFX9: v_mad_legacy_i16 v5, v1, v2, -4.0 ; encoding: [0x05,0x00,0xec,0xd1,0x01,0x05,0xde,0x03]
+
+v_mad_legacy_u16_e64 v5, 0, v2, v3
+// GFX9: v_mad_legacy_u16 v5, 0, v2, v3 ; encoding: [0x05,0x00,0xeb,0xd1,0x80,0x04,0x0e,0x04]
+
+v_mad_legacy_u16 v5, v1, -1, v3
+// GFX9: v_mad_legacy_u16 v5, v1, -1, v3 ; encoding: [0x05,0x00,0xeb,0xd1,0x01,0x83,0x0d,0x04]
+
+v_mad_legacy_u16 v5, v1, v2, -4.0
+// GFX9: v_mad_legacy_u16 v5, v1, v2, -4.0 ; encoding: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xde,0x03]
+
+v_mad_u16_e64 v5, 0, v2, v3
+// GFX9: v_mad_u16 v5, 0, v2, v3 ; encoding: [0x05,0x00,0x04,0xd2,0x80,0x04,0x0e,0x04]
+
+v_mad_u16 v5, v1, -1, v3
+// GFX9: v_mad_u16 v5, v1, -1, v3 ; encoding: [0x05,0x00,0x04,0xd2,0x01,0x83,0x0d,0x04]
+
+v_mad_u16 v5, v1, v2, -4.0
+// GFX9: v_mad_u16 v5, v1, v2, -4.0 ; encoding: [0x05,0x00,0x04,0xd2,0x01,0x05,0xde,0x03]
Index: test/MC/AMDGPU/vop3.s
===================================================================
--- test/MC/AMDGPU/vop3.s
+++ test/MC/AMDGPU/vop3.s
@@ -435,3 +435,85 @@
 v_cubeid_f32 v0, |-1|, |-1.0|, |1.0|
 // SICI: v_cubeid_f32 v0, |-1|, |-1.0|, |1.0| ; encoding: [0x00,0x07,0x88,0xd2,0xc1,0xe6,0xc9,0x03]
 // VI:   v_cubeid_f32 v0, |-1|, |-1.0|, |1.0| ; encoding: [0x00,0x07,0xc4,0xd1,0xc1,0xe6,0xc9,0x03]
+
+///===---------------------------------------------------------------------===//
+// VOP3 Legacy
+///===---------------------------------------------------------------------===//
+
+v_fma_f16_e64 v5, v1, v2, v3
+// VI: v_fma_f16 v5, v1, v2, v3 ; encoding: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_f16 v5, v1, v2, 0.5
+// VI: v_fma_f16 v5, v1, v2, 0.5 ; encoding: [0x05,0x00,0xee,0xd1,0x01,0x05,0xc2,0x03]
+
+v_fma_f16 v5, -v1, -v2, -v3
+// VI: v_fma_f16 v5, -v1, -v2, -v3 ; encoding: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0xe4]
+
+v_fma_f16 v5, |v1|, |v2|, |v3|
+// VI: v_fma_f16 v5, |v1|, |v2|, |v3| ; encoding: [0x05,0x07,0xee,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_f16 v5, v1, v2, v3 clamp
+// VI: v_fma_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xee,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f16_e64 v5, v1, v2, v3
+// VI: v_div_fixup_f16 v5, v1, v2, v3 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f16 v5, 0.5, v2, v3
+// VI: v_div_fixup_f16 v5, 0.5, v2, v3 ; encoding: [0x05,0x00,0xef,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_div_fixup_f16 v5, v1, 0.5, v3
+// VI: v_div_fixup_f16 v5, v1, 0.5, v3 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_div_fixup_f16 v5, v1, v2, 0.5
+// VI: v_div_fixup_f16 v5, v1, v2, 0.5 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x05,0xc2,0x03]
+
+v_div_fixup_f16 v5, v1, v2, -4.0
+// VI: v_div_fixup_f16 v5, v1, v2, -4.0 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x05,0xde,0x03]
+
+v_div_fixup_f16 v5, -v1, v2, v3
+// VI: v_div_fixup_f16 v5, -v1, v2, v3 ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0x24]
+
+v_div_fixup_f16 v5, v1, |v2|, v3
+// VI: v_div_fixup_f16 v5, v1, |v2|, v3 ; encoding: [0x05,0x02,0xef,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f16 v5, v1, v2, v3 clamp
+// VI: v_div_fixup_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xef,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_f16_e64 v5, v1, v2, v3
+// VI: v_mad_f16 v5, v1, v2, v3 ; encoding: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_f16 v5, 0.5, v2, v3
+// VI: v_mad_f16 v5, 0.5, v2, v3 ; encoding: [0x05,0x00,0xea,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_mad_f16 v5, v1, 0.5, v3
+// VI: v_mad_f16 v5, v1, 0.5, v3 ; encoding: [0x05,0x00,0xea,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_mad_f16 v5, v1, v2, 0.5
+// VI: v_mad_f16 v5, v1, v2, 0.5 ; encoding: [0x05,0x00,0xea,0xd1,0x01,0x05,0xc2,0x03]
+
+v_mad_f16 v5, v1, -v2, v3
+// VI: v_mad_f16 v5, v1, -v2, v3 ; encoding: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0x44]
+
+v_mad_f16 v5, v1, v2, |v3|
+// VI: v_mad_f16 v5, v1, v2, |v3| ; encoding: [0x05,0x04,0xea,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_f16 v5, v1, v2, v3 clamp
+// VI: v_mad_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0xea,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_i16_e64 v5, -1, v2, v3
+// VI: v_mad_i16 v5, -1, v2, v3 ; encoding: [0x05,0x00,0xec,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_mad_i16 v5, v1, -4.0, v3
+// VI: v_mad_i16 v5, v1, -4.0, v3 ; encoding: [0x05,0x00,0xec,0xd1,0x01,0xef,0x0d,0x04]
+
+v_mad_i16 v5, v1, v2, 0
+// VI: v_mad_i16 v5, v1, v2, 0 ; encoding: [0x05,0x00,0xec,0xd1,0x01,0x05,0x02,0x02]
+
+v_mad_u16_e64 v5, -1, v2, v3
+// VI: v_mad_u16 v5, -1, v2, v3 ; encoding: [0x05,0x00,0xeb,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_mad_u16 v5, v1, 0, v3
+// VI: v_mad_u16 v5, v1, 0, v3 ; encoding: [0x05,0x00,0xeb,0xd1,0x01,0x01,0x0d,0x04]
+
+v_mad_u16 v5, v1, v2, -4.0
+// VI: v_mad_u16 v5, v1, v2, -4.0 ; encoding: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xde,0x03]
Index: test/MC/Disassembler/AMDGPU/vop3_gfx9.txt
===================================================================
--- /dev/null
+++ test/MC/Disassembler/AMDGPU/vop3_gfx9.txt
@@ -0,0 +1,133 @@
+# RUN: llvm-mc -arch=amdgcn -mcpu=gfx901 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GFX9
+
+# GFX9: v_fma_f16 v5, v1, v2, v3    ; encoding: [0x05,0x00,0x06,0xd2,0x01,0x05,0x0e,0x04]
+0x05,0x00,0x06,0xd2,0x01,0x05,0x0e,0x04
+
+# GFX9: v_fma_f16 v5, -v1, v2, v3    ; encoding: [0x05,0x00,0x06,0xd2,0x01,0x05,0x0e,0x24]
+0x05,0x00,0x06,0xd2,0x01,0x05,0x0e,0x24
+
+# GFX9: v_fma_f16 v5, v1, |v2|, v3    ; encoding: [0x05,0x02,0x06,0xd2,0x01,0x05,0x0e,0x04]
+0x05,0x02,0x06,0xd2,0x01,0x05,0x0e,0x04
+
+# GFX9: v_fma_f16 v5, v1, v2, v3 clamp    ; encoding: [0x05,0x80,0x06,0xd2,0x01,0x05,0x0e,0x04]
+0x05,0x80,0x06,0xd2,0x01,0x05,0x0e,0x04
+
+# CHECK: v_fma_legacy_f16 v5, v1, v2, v3    ; encoding: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x04]
+0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x04
+
+# CHECK: v_fma_legacy_f16 v5, v1, v2, -v3    ; encoding: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x84]
+0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x84
+
+# CHECK: v_fma_legacy_f16 v5, |v1|, v2, v3    ; encoding: [0x05,0x01,0xee,0xd1,0x01,0x05,0x0e,0x04]
+0x05,0x01,0xee,0xd1,0x01,0x05,0x0e,0x04
+
+# CHECK: v_fma_legacy_f16 v5, v1, v2, v3 clamp    ; encoding: [0x05,0x80,0xee,0xd1,0x01,0x05,0x0e,0x04]
+0x05,0x80,0xee,0xd1,0x01,0x05,0x0e,0x04
+
+# CHECK: v_div_fixup_f16 v5, 0.5, v2, v3    ; encoding: [0x05,0x00,0x07,0xd2,0xf0,0x04,0x0e,0x04]
+0x05,0x00,0x07,0xd2,0xf0,0x04,0x0e,0x04
+
+# CHECK: v_div_fixup_f16 v5, v1, 0.5, v3    ; encoding: [0x05,0x00,0x07,0xd2,0x01,0xe1,0x0d,0x04]
+0x05,0x00,0x07,0xd2,0x01,0xe1,0x0d,0x04
+
+# CHECK: v_div_fixup_f16 v5, v1, v2, 0.5    ; encoding: [0x05,0x00,0x07,0xd2,0x01,0x05,0xc2,0x03]
+0x05,0x00,0x07,0xd2,0x01,0x05,0xc2,0x03
+
+# CHECK: v_div_fixup_f16 v5, -v1, -v2, -v3    ; encoding: [0x05,0x00,0x07,0xd2,0x01,0x05,0x0e,0xe4]
+0x05,0x00,0x07,0xd2,0x01,0x05,0x0e,0xe4
+
+# CHECK: v_div_fixup_f16 v5, |v1|, |v2|, |v3|    ; encoding: [0x05,0x07,0x07,0xd2,0x01,0x05,0x0e,0x04]
+0x05,0x07,0x07,0xd2,0x01,0x05,0x0e,0x04
+
+# CHECK: v_div_fixup_f16 v5, v1, v2, v3 clamp    ; encoding: [0x05,0x80,0x07,0xd2,0x01,0x05,0x0e,0x04]
+0x05,0x80,0x07,0xd2,0x01,0x05,0x0e,0x04
+
+# CHECK: v_div_fixup_legacy_f16 v5, 0.5, v2, v3    ; encoding: [0x05,0x00,0xef,0xd1,0xf0,0x04,0x0e,0x04]
+0x05,0x00,0xef,0xd1,0xf0,0x04,0x0e,0x04
+
+# CHECK: v_div_fixup_legacy_f16 v5, v1, 0.5, v3    ; encoding: [0x05,0x00,0xef,0xd1,0x01,0xe1,0x0d,0x04]
+0x05,0x00,0xef,0xd1,0x01,0xe1,0x0d,0x04
+
+# CHECK: v_div_fixup_legacy_f16 v5, v1, v2, 0.5    ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x05,0xc2,0x03]
+0x05,0x00,0xef,0xd1,0x01,0x05,0xc2,0x03
+
+# CHECK: v_div_fixup_legacy_f16 v5, -v1, -v2, -v3    ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0xe4]
+0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0xe4
+
+# CHECK: v_div_fixup_legacy_f16 v5, |v1|, |v2|, |v3|    ; encoding: [0x05,0x07,0xef,0xd1,0x01,0x05,0x0e,0x04]
+0x05,0x07,0xef,0xd1,0x01,0x05,0x0e,0x04
+
+# CHECK: v_div_fixup_legacy_f16 v5, v1, v2, v3 clamp    ; encoding: [0x05,0x80,0xef,0xd1,0x01,0x05,0x0e,0x04]
+0x05,0x80,0xef,0xd1,0x01,0x05,0x0e,0x04
+
+# CHECK: v_mad_f16 v5, 0.5, v2, v3    ; encoding: [0x05,0x00,0x03,0xd2,0xf0,0x04,0x0e,0x04]
+0x05,0x00,0x03,0xd2,0xf0,0x04,0x0e,0x04
+
+# CHECK: v_mad_f16 v5, v1, 0.5, v3    ; encoding: [0x05,0x00,0x03,0xd2,0x01,0xe1,0x0d,0x04]
+0x05,0x00,0x03,0xd2,0x01,0xe1,0x0d,0x04
+
+# CHECK: v_mad_f16 v5, v1, v2, 0.5    ; encoding: [0x05,0x00,0x03,0xd2,0x01,0x05,0xc2,0x03]
+0x05,0x00,0x03,0xd2,0x01,0x05,0xc2,0x03
+
+# CHECK: v_mad_f16 v5, -v1, -v2, -v3    ; encoding: [0x05,0x00,0x03,0xd2,0x01,0x05,0x0e,0xe4]
+0x05,0x00,0x03,0xd2,0x01,0x05,0x0e,0xe4
+
+# CHECK: v_mad_f16 v5, |v1|, |v2|, |v3|    ; encoding: [0x05,0x07,0x03,0xd2,0x01,0x05,0x0e,0x04]
+0x05,0x07,0x03,0xd2,0x01,0x05,0x0e,0x04
+
+# CHECK: v_mad_f16 v5, v1, v2, v3 clamp    ; encoding: [0x05,0x80,0x03,0xd2,0x01,0x05,0x0e,0x04]
+0x05,0x80,0x03,0xd2,0x01,0x05,0x0e,0x04
+
+# CHECK: v_mad_i16 v5, 0, v2, v3    ; encoding: [0x05,0x00,0x05,0xd2,0x80,0x04,0x0e,0x04]
+0x05,0x00,0x05,0xd2,0x80,0x04,0x0e,0x04
+
+# CHECK: v_mad_i16 v5, v1, -1, v3    ; encoding: [0x05,0x00,0x05,0xd2,0x01,0x83,0x0d,0x04]
+0x05,0x00,0x05,0xd2,0x01,0x83,0x0d,0x04
+
+# CHECK: v_mad_i16 v5, v1, v2, -4.0    ; encoding: [0x05,0x00,0x05,0xd2,0x01,0x05,0xde,0x03]
+0x05,0x00,0x05,0xd2,0x01,0x05,0xde,0x03
+
+# CHECK: v_mad_legacy_f16 v5, 0.5, v2, v3    ; encoding: [0x05,0x00,0xea,0xd1,0xf0,0x04,0x0e,0x04]
+0x05,0x00,0xea,0xd1,0xf0,0x04,0x0e,0x04
+
+# CHECK: v_mad_legacy_f16 v5, v1, 0.5, v3    ; encoding: [0x05,0x00,0xea,0xd1,0x01,0xe1,0x0d,0x04]
+0x05,0x00,0xea,0xd1,0x01,0xe1,0x0d,0x04
+
+# CHECK: v_mad_legacy_f16 v5, v1, v2, 0.5    ; encoding: [0x05,0x00,0xea,0xd1,0x01,0x05,0xc2,0x03]
+0x05,0x00,0xea,0xd1,0x01,0x05,0xc2,0x03
+
+# CHECK: v_mad_legacy_f16 v5, -v1, -v2, -v3    ; encoding: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0xe4]
+0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0xe4
+
+# CHECK: v_mad_legacy_f16 v5, |v1|, |v2|, |v3|    ; encoding: [0x05,0x07,0xea,0xd1,0x01,0x05,0x0e,0x04]
+0x05,0x07,0xea,0xd1,0x01,0x05,0x0e,0x04
+
+# CHECK: v_mad_legacy_f16 v5, v1, v2, v3 clamp    ; encoding: [0x05,0x80,0xea,0xd1,0x01,0x05,0x0e,0x04]
+0x05,0x80,0xea,0xd1,0x01,0x05,0x0e,0x04
+
+# CHECK: v_mad_legacy_i16 v5, 0, v2, v3    ; encoding: [0x05,0x00,0xec,0xd1,0x80,0x04,0x0e,0x04]
+0x05,0x00,0xec,0xd1,0x80,0x04,0x0e,0x04
+
+# CHECK: v_mad_legacy_i16 v5, v1, -1, v3    ; encoding: [0x05,0x00,0xec,0xd1,0x01,0x83,0x0d,0x04]
+0x05,0x00,0xec,0xd1,0x01,0x83,0x0d,0x04
+
+# CHECK: v_mad_legacy_i16 v5, v1, v2, -4.0    ; encoding: [0x05,0x00,0xec,0xd1,0x01,0x05,0xde,0x03]
+0x05,0x00,0xec,0xd1,0x01,0x05,0xde,0x03
+
+# CHECK: v_mad_legacy_u16 v5, 0, v2, v3    ; encoding: [0x05,0x00,0xeb,0xd1,0x80,0x04,0x0e,0x04]
+0x05,0x00,0xeb,0xd1,0x80,0x04,0x0e,0x04
+
+# CHECK: v_mad_legacy_u16 v5, v1, -1, v3    ; encoding: [0x05,0x00,0xeb,0xd1,0x01,0x83,0x0d,0x04]
+0x05,0x00,0xeb,0xd1,0x01,0x83,0x0d,0x04
+
+# CHECK: v_mad_legacy_u16 v5, v1, v2, -4.0    ; encoding: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xde,0x03]
+0x05,0x00,0xeb,0xd1,0x01,0x05,0xde,0x03
+
+# CHECK: v_mad_u16 v5, 0, v2, v3    ; encoding: [0x05,0x00,0x04,0xd2,0x80,0x04,0x0e,0x04]
+0x05,0x00,0x04,0xd2,0x80,0x04,0x0e,0x04
+
+# CHECK: v_mad_u16 v5, v1, -1, v3    ; encoding: [0x05,0x00,0x04,0xd2,0x01,0x83,0x0d,0x04]
+0x05,0x00,0x04,0xd2,0x01,0x83,0x0d,0x04
+
+# CHECK: v_mad_u16 v5, v1, v2, -4.0    ; encoding: [0x05,0x00,0x04,0xd2,0x01,0x05,0xde,0x03]
+0x05,0x00,0x04,0xd2,0x01,0x05,0xde,0x03
Index: test/MC/Disassembler/AMDGPU/vop3_vi.txt
===================================================================
--- test/MC/Disassembler/AMDGPU/vop3_vi.txt
+++ test/MC/Disassembler/AMDGPU/vop3_vi.txt
@@ -239,3 +239,69 @@
 
 # VI:   v_ceil_f32_e64 v0, neg(-1.0)    ; encoding: [0x00,0x00,0x5d,0xd1,0xf3,0x00,0x00,0x20]
 0x00,0x00,0x5d,0xd1,0xf3,0x00,0x00,0x20
+
+# VI: v_fma_f16 v5, v1, v2, v3    ; encoding: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x04]
+0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x04
+
+# VI: v_fma_f16 v5, 0.5, v2, v3    ; encoding: [0x05,0x00,0xee,0xd1,0xf0,0x04,0x0e,0x04]
+0x05,0x00,0xee,0xd1,0xf0,0x04,0x0e,0x04
+
+# VI: v_fma_f16 v5, v1, v2, |v3|    ; encoding: [0x05,0x04,0xee,0xd1,0x01,0x05,0x0e,0x04]
+0x05,0x04,0xee,0xd1,0x01,0x05,0x0e,0x04
+
+# VI: v_fma_f16 v5, v1, v2, v3 clamp    ; encoding: [0x05,0x80,0xee,0xd1,0x01,0x05,0x0e,0x04]
+0x05,0x80,0xee,0xd1,0x01,0x05,0x0e,0x04
+
+# CHECK: v_div_fixup_f16 v5, 0.5, v2, v3    ; encoding: [0x05,0x00,0xef,0xd1,0xf0,0x04,0x0e,0x04]
+0x05,0x00,0xef,0xd1,0xf0,0x04,0x0e,0x04
+
+# CHECK: v_div_fixup_f16 v5, v1, 0.5, v3    ; encoding: [0x05,0x00,0xef,0xd1,0x01,0xe1,0x0d,0x04]
+0x05,0x00,0xef,0xd1,0x01,0xe1,0x0d,0x04
+
+# CHECK: v_div_fixup_f16 v5, v1, v2, 0.5    ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x05,0xc2,0x03]
+0x05,0x00,0xef,0xd1,0x01,0x05,0xc2,0x03
+
+# CHECK: v_div_fixup_f16 v5, -v1, -v2, -v3    ; encoding: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0xe4]
+0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0xe4
+
+# CHECK: v_div_fixup_f16 v5, |v1|, |v2|, |v3|    ; encoding: [0x05,0x07,0xef,0xd1,0x01,0x05,0x0e,0x04]
+0x05,0x07,0xef,0xd1,0x01,0x05,0x0e,0x04
+
+# CHECK: v_div_fixup_f16 v5, v1, v2, v3 clamp    ; encoding: [0x05,0x80,0xef,0xd1,0x01,0x05,0x0e,0x04]
+0x05,0x80,0xef,0xd1,0x01,0x05,0x0e,0x04
+
+# CHECK: v_mad_f16 v5, 0.5, v2, v3    ; encoding: [0x05,0x00,0xea,0xd1,0xf0,0x04,0x0e,0x04]
+0x05,0x00,0xea,0xd1,0xf0,0x04,0x0e,0x04
+
+# CHECK: v_mad_f16 v5, v1, 0.5, v3    ; encoding: [0x05,0x00,0xea,0xd1,0x01,0xe1,0x0d,0x04]
+0x05,0x00,0xea,0xd1,0x01,0xe1,0x0d,0x04
+
+# CHECK: v_mad_f16 v5, v1, v2, 0.5    ; encoding: [0x05,0x00,0xea,0xd1,0x01,0x05,0xc2,0x03]
+0x05,0x00,0xea,0xd1,0x01,0x05,0xc2,0x03
+
+# CHECK: v_mad_f16 v5, -v1, -v2, -v3    ; encoding: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0xe4]
+0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0xe4
+
+# CHECK: v_mad_f16 v5, |v1|, |v2|, |v3|    ; encoding: [0x05,0x07,0xea,0xd1,0x01,0x05,0x0e,0x04]
+0x05,0x07,0xea,0xd1,0x01,0x05,0x0e,0x04
+
+# CHECK: v_mad_f16 v5, v1, v2, v3 clamp    ; encoding: [0x05,0x80,0xea,0xd1,0x01,0x05,0x0e,0x04]
+0x05,0x80,0xea,0xd1,0x01,0x05,0x0e,0x04
+
+# CHECK: v_mad_i16 v5, 0.5, v2, v3    ; encoding: [0x05,0x00,0xec,0xd1,0xf0,0x04,0x0e,0x04]
+0x05,0x00,0xec,0xd1,0xf0,0x04,0x0e,0x04
+
+# CHECK: v_mad_i16 v5, v1, 0.5, v3    ; encoding: [0x05,0x00,0xec,0xd1,0x01,0xe1,0x0d,0x04]
+0x05,0x00,0xec,0xd1,0x01,0xe1,0x0d,0x04
+
+# CHECK: v_mad_i16 v5, v1, v2, 0.5    ; encoding: [0x05,0x00,0xec,0xd1,0x01,0x05,0xc2,0x03]
+0x05,0x00,0xec,0xd1,0x01,0x05,0xc2,0x03
+
+# CHECK: v_mad_u16 v5, 0, v2, v3    ; encoding: [0x05,0x00,0xeb,0xd1,0x80,0x04,0x0e,0x04]
+0x05,0x00,0xeb,0xd1,0x80,0x04,0x0e,0x04
+
+# CHECK: v_mad_u16 v5, v1, -1, v3    ; encoding: [0x05,0x00,0xeb,0xd1,0x01,0x83,0x0d,0x04]
+0x05,0x00,0xeb,0xd1,0x01,0x83,0x0d,0x04
+
+# CHECK: v_mad_u16 v5, v1, v2, -4.0    ; encoding: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xde,0x03]
+0x05,0x00,0xeb,0xd1,0x01,0x05,0xde,0x03