Index: lib/Target/ARM/ARMISelDAGToDAG.cpp =================================================================== --- lib/Target/ARM/ARMISelDAGToDAG.cpp +++ lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -3765,41 +3765,10 @@ // which mode it is to be used, e.g. usr. Returns -1 to signify that the string // was invalid. static inline int getBankedRegisterMask(StringRef RegString) { - return StringSwitch(RegString.lower()) - .Case("r8_usr", 0x00) - .Case("r9_usr", 0x01) - .Case("r10_usr", 0x02) - .Case("r11_usr", 0x03) - .Case("r12_usr", 0x04) - .Case("sp_usr", 0x05) - .Case("lr_usr", 0x06) - .Case("r8_fiq", 0x08) - .Case("r9_fiq", 0x09) - .Case("r10_fiq", 0x0a) - .Case("r11_fiq", 0x0b) - .Case("r12_fiq", 0x0c) - .Case("sp_fiq", 0x0d) - .Case("lr_fiq", 0x0e) - .Case("lr_irq", 0x10) - .Case("sp_irq", 0x11) - .Case("lr_svc", 0x12) - .Case("sp_svc", 0x13) - .Case("lr_abt", 0x14) - .Case("sp_abt", 0x15) - .Case("lr_und", 0x16) - .Case("sp_und", 0x17) - .Case("lr_mon", 0x1c) - .Case("sp_mon", 0x1d) - .Case("elr_hyp", 0x1e) - .Case("sp_hyp", 0x1f) - .Case("spsr_fiq", 0x2e) - .Case("spsr_irq", 0x30) - .Case("spsr_svc", 0x32) - .Case("spsr_abt", 0x34) - .Case("spsr_und", 0x36) - .Case("spsr_mon", 0x3c) - .Case("spsr_hyp", 0x3e) - .Default(-1); + auto TheReg = ARMBankedReg::lookupBankedRegByName(RegString.lower()); + if (!TheReg) + return -1; + return TheReg->Encoding; } // The flags here are common to those allowed for apsr in the A class cores and Index: lib/Target/ARM/ARMSystemRegister.td =================================================================== --- lib/Target/ARM/ARMSystemRegister.td +++ lib/Target/ARM/ARMSystemRegister.td @@ -106,3 +106,51 @@ def : MClassSysReg<0, 0, 1, 0x894, "control_ns">; def : MClassSysReg<0, 0, 1, 0x898, "sp_ns">; } + + +// Banked Registers +// +class BankedReg enc> + : SearchableTable { + string Name; + bits<8> Encoding; + let Name = name; + let Encoding = enc; + let SearchableFields = ["Name", "Encoding"]; +} + +// The values here come from B9.2.3 of the ARM ARM, where bits 4-0 are SysM +// and bit 5 is R. +def : BankedReg<"r8_usr", 0x00>; +def : BankedReg<"r9_usr", 0x01>; +def : BankedReg<"r10_usr", 0x02>; +def : BankedReg<"r11_usr", 0x03>; +def : BankedReg<"r12_usr", 0x04>; +def : BankedReg<"sp_usr", 0x05>; +def : BankedReg<"lr_usr", 0x06>; +def : BankedReg<"r8_fiq", 0x08>; +def : BankedReg<"r9_fiq", 0x09>; +def : BankedReg<"r10_fiq", 0x0a>; +def : BankedReg<"r11_fiq", 0x0b>; +def : BankedReg<"r12_fiq", 0x0c>; +def : BankedReg<"sp_fiq", 0x0d>; +def : BankedReg<"lr_fiq", 0x0e>; +def : BankedReg<"lr_irq", 0x10>; +def : BankedReg<"sp_irq", 0x11>; +def : BankedReg<"lr_svc", 0x12>; +def : BankedReg<"sp_svc", 0x13>; +def : BankedReg<"lr_abt", 0x14>; +def : BankedReg<"sp_abt", 0x15>; +def : BankedReg<"lr_und", 0x16>; +def : BankedReg<"sp_und", 0x17>; +def : BankedReg<"lr_mon", 0x1c>; +def : BankedReg<"sp_mon", 0x1d>; +def : BankedReg<"elr_hyp", 0x1e>; +def : BankedReg<"sp_hyp", 0x1f>; +def : BankedReg<"spsr_fiq", 0x2e>; +def : BankedReg<"spsr_irq", 0x30>; +def : BankedReg<"spsr_svc", 0x32>; +def : BankedReg<"spsr_abt", 0x34>; +def : BankedReg<"spsr_und", 0x36>; +def : BankedReg<"spsr_mon", 0x3c>; +def : BankedReg<"spsr_hyp", 0x3e>; Index: lib/Target/ARM/AsmParser/ARMAsmParser.cpp =================================================================== --- lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -4175,46 +4175,10 @@ return MatchOperand_NoMatch; StringRef RegName = Tok.getString(); - // The values here come from B9.2.3 of the ARM ARM, where bits 4-0 are SysM - // and bit 5 is R. - unsigned Encoding = StringSwitch(RegName.lower()) - .Case("r8_usr", 0x00) - .Case("r9_usr", 0x01) - .Case("r10_usr", 0x02) - .Case("r11_usr", 0x03) - .Case("r12_usr", 0x04) - .Case("sp_usr", 0x05) - .Case("lr_usr", 0x06) - .Case("r8_fiq", 0x08) - .Case("r9_fiq", 0x09) - .Case("r10_fiq", 0x0a) - .Case("r11_fiq", 0x0b) - .Case("r12_fiq", 0x0c) - .Case("sp_fiq", 0x0d) - .Case("lr_fiq", 0x0e) - .Case("lr_irq", 0x10) - .Case("sp_irq", 0x11) - .Case("lr_svc", 0x12) - .Case("sp_svc", 0x13) - .Case("lr_abt", 0x14) - .Case("sp_abt", 0x15) - .Case("lr_und", 0x16) - .Case("sp_und", 0x17) - .Case("lr_mon", 0x1c) - .Case("sp_mon", 0x1d) - .Case("elr_hyp", 0x1e) - .Case("sp_hyp", 0x1f) - .Case("spsr_fiq", 0x2e) - .Case("spsr_irq", 0x30) - .Case("spsr_svc", 0x32) - .Case("spsr_abt", 0x34) - .Case("spsr_und", 0x36) - .Case("spsr_mon", 0x3c) - .Case("spsr_hyp", 0x3e) - .Default(~0U); - - if (Encoding == ~0U) + auto TheReg = ARMBankedReg::lookupBankedRegByName(RegName.lower()); + if (!TheReg) return MatchOperand_NoMatch; + unsigned Encoding = TheReg->Encoding; Parser.Lex(); // Eat identifier token. Operands.push_back(ARMOperand::CreateBankedReg(Encoding, S)); Index: lib/Target/ARM/Utils/ARMBaseInfo.h =================================================================== --- lib/Target/ARM/Utils/ARMBaseInfo.h +++ lib/Target/ARM/Utils/ARMBaseInfo.h @@ -24,6 +24,7 @@ namespace llvm { +// System Registers namespace ARMSysReg { struct MClassSysReg { const char *Name; @@ -59,6 +60,16 @@ } // end namespace ARMSysReg +// Banked Registers +namespace ARMBankedReg { + struct BankedReg { + const char *Name; + uint16_t Encoding; + }; + #define GET_BANKEDREG_DECL + #include "ARMGenSystemRegister.inc" +} // end namespace ARMBankedReg + } // end namespace llvm #endif // LLVM_LIB_TARGET_ARM_UTILS_ARMBASEINFO_H Index: lib/Target/ARM/Utils/ARMBaseInfo.cpp =================================================================== --- lib/Target/ARM/Utils/ARMBaseInfo.cpp +++ lib/Target/ARM/Utils/ARMBaseInfo.cpp @@ -18,7 +18,7 @@ using namespace llvm; namespace llvm { - namespace ARMSysReg { +namespace ARMSysReg { // lookup system register using 12-bit SYSm value. // Note: the search is uniqued using M1 mask @@ -40,5 +40,10 @@ #define GET_MCLASSSYSREG_IMPL #include "ARMGenSystemRegister.inc" - } -} +} // end namespace ARMSysReg + +namespace ARMBankedReg { +#define GET_BANKEDREG_IMPL +#include "ARMGenSystemRegister.inc" +} // end namespce ARMSysReg +} // end namespace llvm