Index: llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterInfo.td
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterInfo.td
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterInfo.td
@@ -17,8 +17,6 @@
   def sub#Index : SubRegIndex<32, !shl(Index, 5)>;
 }
 
-def INDIRECT_BASE_ADDR : Register <"INDIRECT_BASE_ADDR">;
-
 }
 
 include "R600RegisterInfo.td"
Index: llvm/trunk/lib/Target/AMDGPU/R600RegisterInfo.td
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/R600RegisterInfo.td
+++ llvm/trunk/lib/Target/AMDGPU/R600RegisterInfo.td
@@ -147,6 +147,7 @@
 def PRED_SEL_ZERO : R600Reg<"Pred_sel_zero", 2>;
 def PRED_SEL_ONE : R600Reg<"Pred_sel_one", 3>;
 def AR_X : R600Reg<"AR.x", 0>;
+def INDIRECT_BASE_ADDR : R600Reg <"INDIRECT_BASE_ADDR", 0>;
 
 def R600_ArrayBase : RegisterClass <"AMDGPU", [f32, i32], 32,
                           (add (sequence "ArrayBase%u", 448, 480))>;
Index: llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -148,7 +148,6 @@
 
 BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   BitVector Reserved(getNumRegs());
-  Reserved.set(AMDGPU::INDIRECT_BASE_ADDR);
 
   // EXEC_LO and EXEC_HI could be allocated and used as regular register, but
   // this seems likely to result in bugs, so I'm marking them as reserved.