Index: lib/Target/ARM/ARMBaseRegisterInfo.cpp
===================================================================
--- lib/Target/ARM/ARMBaseRegisterInfo.cpp
+++ lib/Target/ARM/ARMBaseRegisterInfo.cpp
@@ -92,7 +92,7 @@
     }
   }
 
-  if (STI.isTargetDarwin() && STI.getTargetLowering()->supportSwiftError() &&
+  if (STI.getTargetLowering()->supportSwiftError() &&
       F->getAttributes().hasAttrSomewhere(Attribute::SwiftError))
     return CSR_iOS_SwiftError_SaveList;
 
@@ -120,7 +120,7 @@
     // This is academic because all GHC calls are (supposed to be) tail calls
     return CSR_NoRegs_RegMask;
 
-  if (STI.isTargetDarwin() && STI.getTargetLowering()->supportSwiftError() &&
+  if (STI.getTargetLowering()->supportSwiftError() &&
       MF.getFunction()->getAttributes().hasAttrSomewhere(Attribute::SwiftError))
     return CSR_iOS_SwiftError_RegMask;
 
Index: test/CodeGen/ARM/swifterror.ll
===================================================================
--- test/CodeGen/ARM/swifterror.ll
+++ test/CodeGen/ARM/swifterror.ll
@@ -1,5 +1,6 @@
 ; RUN: llc -verify-machineinstrs < %s -mtriple=armv7-apple-ios | FileCheck --check-prefix=CHECK-APPLE --check-prefix=CHECK-ARMV7 %s
 ; RUN: llc -verify-machineinstrs -O0 < %s -mtriple=armv7-apple-ios | FileCheck --check-prefix=CHECK-O0 %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=armv7-linux-androideabi | FileCheck --check-prefix=CHECK-ANDROID %s
 
 declare i8* @malloc(i64)
 declare void @free(i8*)
@@ -503,6 +504,51 @@
 ; CHECK-ARMV7-DAG:  mov     r2, r6
 ; CHECK-ARMV7-DAG:  mov     r3, r11
 ; CHECK-ARMV7:  pop     {r4, r5, r6, r7, r10, r11, pc}
+
+; CHECK-ANDROID-LABEL: params_and_return_in_reg
+; CHECK-ANDROID:  push	{r4, r5, r6, r7, r10, r11, lr}
+; CHECK-ANDROID:  sub	sp, sp, #12
+; CHECK-ANDROID:  mov	r5, r8
+; CHECK-ANDROID:  str	r10, [sp, #4]           @ 4-byte Spill
+; CHECK-ANDROID:  mov	r6, r3
+; CHECK-ANDROID:  mov	r7, r2
+; CHECK-ANDROID:  mov	r4, r1
+; CHECK-ANDROID:  mov	r11, r0
+; CHECK-ANDROID:  mov	r0, #1
+; CHECK-ANDROID:  mov	r1, #2
+; CHECK-ANDROID:  mov	r2, #3
+; CHECK-ANDROID:  mov	r3, #4
+; CHECK-ANDROID:  mov	r10, #0
+; CHECK-ANDROID:  mov	r8, #0
+; CHECK-ANDROID:  bl	params_in_reg2
+; CHECK-ANDROID:  ldr	r10, [sp, #4]           @ 4-byte Reload
+; CHECK-ANDROID:  mov	r0, r11
+; CHECK-ANDROID:  str	r8, [sp]                @ 4-byte Spill
+; CHECK-ANDROID:  mov	r1, r4
+; CHECK-ANDROID:  mov	r2, r7
+; CHECK-ANDROID:  mov	r3, r6
+; CHECK-ANDROID:  mov	r8, r5
+; CHECK-ANDROID:  bl	params_and_return_in_reg2
+; CHECK-ANDROID:  mov	r11, r8
+; CHECK-ANDROID:  ldr	r8, [sp]                @ 4-byte Reload
+; CHECK-ANDROID:  mov	r4, r0
+; CHECK-ANDROID:  mov	r6, r1
+; CHECK-ANDROID:  mov	r7, r2
+; CHECK-ANDROID:  mov	r5, r3
+; CHECK-ANDROID:  mov	r0, #1
+; CHECK-ANDROID:  mov	r1, #2
+; CHECK-ANDROID:  mov	r2, #3
+; CHECK-ANDROID:  mov	r3, #4
+; CHECK-ANDROID:  mov	r10, #0
+; CHECK-ANDROID:  bl	params_in_reg2
+; CHECK-ANDROID:  mov	r0, r4
+; CHECK-ANDROID:  mov	r1, r6
+; CHECK-ANDROID:  mov	r2, r7
+; CHECK-ANDROID:  mov	r3, r5
+; CHECK-ANDROID:  mov	r8, r11
+; CHECK-ANDROID:  add	sp, sp, #12
+; CHECK-ANDROID:  pop	{r4, r5, r6, r7, r10, r11, pc}
+
 define swiftcc { i32, i32, i32, i32} @params_and_return_in_reg(i32, i32, i32, i32, i8* swiftself, %swift_error** nocapture swifterror %err) {
   %error_ptr_ref = alloca swifterror %swift_error*, align 8
   store %swift_error* null, %swift_error** %error_ptr_ref
@@ -522,6 +568,9 @@
 ; CHECK-APPLE: tailcall_from_swifterror:
 ; CHECK-APPLE-NOT: b _acallee
 ; CHECK-APPLE: bl _acallee
+; CHECK-ANDROID: tailcall_from_swifterror:
+; CHECK-ANDROID-NOT: b acallee
+; CHECK-ANDROID: bl acallee
 
 define swiftcc void @tailcall_from_swifterror(%swift_error** swifterror %error_ptr_ref) {
 entry:
@@ -545,6 +594,11 @@
 ; CHECK-APPLE:  bl      _foo2
 ; CHECK-APPLE:  mov     r0, r8
 
+; CHECK-ANDROID-LABEL: testAssign
+; CHECK-ANDROID:  mov     r8, #0
+; CHECK-ANDROID:  bl      foo2
+; CHECK-ANDROID:  mov     r0, r8
+
 define swiftcc %swift_error* @testAssign(i8* %error_ref) {
 entry:
   %error_ptr = alloca swifterror %swift_error*