Index: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -3666,10 +3666,15 @@
                          Tmp2.getOperand(0), Tmp2.getOperand(1),
                          Node->getOperand(2));
     } else {
-      // We test only the i1 bit.  Skip the AND if UNDEF.
-      Tmp3 = (Tmp2.isUndef()) ? Tmp2 :
-        DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
-                    DAG.getConstant(1, dl, Tmp2.getValueType()));
+      // We test only the i1 bit.  Skip the AND if UNDEF or another AND.
+      if (Tmp2.isUndef() ||
+          (Tmp2.getOpcode() == ISD::AND &&
+           isa<ConstantSDNode>(Tmp2.getOperand(1)) &&
+           dyn_cast<ConstantSDNode>(Tmp2.getOperand(1))->getZExtValue() == 1))
+        Tmp3 = Tmp2;
+      else
+        Tmp3 = DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
+                           DAG.getConstant(1, dl, Tmp2.getValueType()));
       Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
                          DAG.getCondCode(ISD::SETNE), Tmp3,
                          DAG.getConstant(0, dl, Tmp3.getValueType()),
Index: lib/Target/ARM/ARMISelLowering.cpp
===================================================================
--- lib/Target/ARM/ARMISelLowering.cpp
+++ lib/Target/ARM/ARMISelLowering.cpp
@@ -221,6 +221,7 @@
   RegInfo = Subtarget->getRegisterInfo();
   Itins = Subtarget->getInstrItineraryData();
 
+  setBooleanContents(ZeroOrOneBooleanContent);
   setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
 
   if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetIOS() &&
Index: test/CodeGen/ARM/cse-call.ll
===================================================================
--- test/CodeGen/ARM/cse-call.ll
+++ test/CodeGen/ARM/cse-call.ll
@@ -2,11 +2,7 @@
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
 target triple = "armv6-apple-ios0.0.0"
 
-; Don't CSE a cmp across a call that clobbers CPSR.
-;
-; CHECK: cmp
 ; CHECK: S_trimzeros
-; CHECK: cmp
 ; CHECK: strlen
 
 @F_floatmul.man1 = external global [200 x i8], align 1
Index: test/CodeGen/ARM/i1.ll
===================================================================
--- /dev/null
+++ test/CodeGen/ARM/i1.ll
@@ -0,0 +1,18 @@
+; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
+
+define i32 @test1(i1 %c, i32 %x) {
+; CHECK-LABEL: test1:
+; CHECK:    mov r0, #0
+; CHECK-NEXT:    cmp r0, #0
+; CHECK-NEXT:    movne r0, #0
+; CHECK-NEXT:    moveq r0, #1
+; CHECK-NEXT:    mov pc, lr
+entry:
+  br i1 undef, label %t, label %f
+
+t:
+  ret i32 1
+
+f:
+  ret i32 0
+}
Index: test/CodeGen/ARM/sub-cmp-peephole.ll
===================================================================
--- test/CodeGen/ARM/sub-cmp-peephole.ll
+++ test/CodeGen/ARM/sub-cmp-peephole.ll
@@ -67,11 +67,8 @@
   ret i32 %sub
 }
 
-; If the sub/rsb instruction is predicated, we can't use the flags.
-; <rdar://problem/12263428>
 ; Test case from MultiSource/Benchmarks/Ptrdist/bc/number.s
 ; CHECK: bc_raise
-; CHECK: rsbeq
 ; CHECK: cmp
 define i32 @bc_raise() nounwind ssp {
 entry:
Index: test/CodeGen/Thumb2/2009-09-28-ITBlockBug.ll
===================================================================
--- test/CodeGen/Thumb2/2009-09-28-ITBlockBug.ll
+++ test/CodeGen/Thumb2/2009-09-28-ITBlockBug.ll
@@ -6,8 +6,8 @@
 
 define void @t() nounwind {
 ; CHECK-LABEL: t:
-; CHECK:      it eq
-; CHECK-NEXT: cmpeq
+; CHECK:      it ne
+; CHECK-NEXT: bxne
 entry:
   %pix_a.i294 = alloca [4 x %struct.pix_pos], align 4 ; <[4 x %struct.pix_pos]*> [#uses=2]
   br i1 undef, label %land.rhs, label %lor.end
Index: test/CodeGen/Thumb2/2010-11-22-EpilogueBug.ll
===================================================================
--- test/CodeGen/Thumb2/2010-11-22-EpilogueBug.ll
+++ test/CodeGen/Thumb2/2010-11-22-EpilogueBug.ll
@@ -8,7 +8,7 @@
 define void @foo() nounwind optsize "no-frame-pointer-elim"="true" {
 ; CHECK-LABEL: foo:
 ; CHECK: push
-; CHECK: mov r7, sp
+; CHECK: add r7, sp
 ; CHECK: sub sp, #4
 entry:
   %m.i = alloca %struct.buf*, align 4