Index: lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp =================================================================== --- lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp +++ lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp @@ -1655,8 +1655,8 @@ SDValue SRsrc, VAddr, SOffset, Offset, GLC, SLC; if (SelectMUBUFAddr64(Mem->getBasePtr(), SRsrc, VAddr, SOffset, Offset, SLC)) { - unsigned Opcode = Is32 ? AMDGPU::BUFFER_ATOMIC_CMPSWAP_RTN_ADDR64 : - AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_RTN_ADDR64; + unsigned Opcode = Is32 ? AMDGPU::BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN : + AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN; SDValue CmpVal = Mem->getOperand(2); // XXX - Do we care about glue operands? @@ -1672,8 +1672,8 @@ if (!CmpSwap) { SDValue SRsrc, SOffset, Offset, SLC; if (SelectMUBUFOffset(Mem->getBasePtr(), SRsrc, SOffset, Offset, SLC)) { - unsigned Opcode = Is32 ? AMDGPU::BUFFER_ATOMIC_CMPSWAP_RTN_OFFSET : - AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_RTN_OFFSET; + unsigned Opcode = Is32 ? AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN : + AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN; SDValue CmpVal = Mem->getOperand(2); SDValue Ops[] = { Index: lib/Target/AMDGPU/BUFInstructions.td =================================================================== --- lib/Target/AMDGPU/BUFInstructions.td +++ lib/Target/AMDGPU/BUFInstructions.td @@ -617,21 +617,21 @@ def _IDXEN : MUBUF_AtomicNoRet_Pseudo ; def _BOTHEN : MUBUF_AtomicNoRet_Pseudo ; - def _RTN_OFFSET : MUBUF_AtomicRet_Pseudo , MUBUFAddr64Table <0, "_RTN">; - def _RTN_ADDR64 : MUBUF_AtomicRet_Pseudo , MUBUFAddr64Table <1, "_RTN">; - def _RTN_OFFEN : MUBUF_AtomicRet_Pseudo ; - def _RTN_IDXEN : MUBUF_AtomicRet_Pseudo ; - def _RTN_BOTHEN : MUBUF_AtomicRet_Pseudo ; + def _OFFEN_RTN : MUBUF_AtomicRet_Pseudo ; + def _IDXEN_RTN : MUBUF_AtomicRet_Pseudo ; + def _BOTHEN_RTN : MUBUF_AtomicRet_Pseudo ; } @@ -951,7 +951,7 @@ (name i32:$vdata_in, v4i32:$rsrc, 0, (MUBUFIntrinsicOffset i32:$soffset, i16:$offset), imm:$slc), - (!cast(opcode # _RTN_OFFSET) $vdata_in, $rsrc, $soffset, + (!cast(opcode # _OFFSET_RTN) $vdata_in, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $slc)) >; @@ -959,7 +959,7 @@ (name i32:$vdata_in, v4i32:$rsrc, i32:$vindex, (MUBUFIntrinsicOffset i32:$soffset, i16:$offset), imm:$slc), - (!cast(opcode # _RTN_IDXEN) $vdata_in, $vindex, $rsrc, $soffset, + (!cast(opcode # _IDXEN_RTN) $vdata_in, $vindex, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $slc)) >; @@ -967,7 +967,7 @@ (name i32:$vdata_in, v4i32:$rsrc, 0, (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset), imm:$slc), - (!cast(opcode # _RTN_OFFEN) $vdata_in, $voffset, $rsrc, $soffset, + (!cast(opcode # _OFFEN_RTN) $vdata_in, $voffset, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $slc)) >; @@ -975,7 +975,7 @@ (name i32:$vdata_in, v4i32:$rsrc, i32:$vindex, (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset), imm:$slc), - (!cast(opcode # _RTN_BOTHEN) + (!cast(opcode # _BOTHEN_RTN) $vdata_in, (REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1), $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $slc)) @@ -999,7 +999,7 @@ (MUBUFIntrinsicOffset i32:$soffset, i16:$offset), imm:$slc), (EXTRACT_SUBREG - (BUFFER_ATOMIC_CMPSWAP_RTN_OFFSET + (BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN (REG_SEQUENCE VReg_64, $data, sub0, $cmp, sub1), $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $slc)), sub0) @@ -1011,7 +1011,7 @@ (MUBUFIntrinsicOffset i32:$soffset, i16:$offset), imm:$slc), (EXTRACT_SUBREG - (BUFFER_ATOMIC_CMPSWAP_RTN_IDXEN + (BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN (REG_SEQUENCE VReg_64, $data, sub0, $cmp, sub1), $vindex, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $slc)), sub0) @@ -1023,7 +1023,7 @@ (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset), imm:$slc), (EXTRACT_SUBREG - (BUFFER_ATOMIC_CMPSWAP_RTN_OFFEN + (BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN (REG_SEQUENCE VReg_64, $data, sub0, $cmp, sub1), $voffset, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $slc)), sub0) @@ -1035,7 +1035,7 @@ (MUBUFIntrinsicVOffset i32:$soffset, i16:$offset, i32:$voffset), imm:$slc), (EXTRACT_SUBREG - (BUFFER_ATOMIC_CMPSWAP_RTN_BOTHEN + (BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN (REG_SEQUENCE VReg_64, $data, sub0, $cmp, sub1), (REG_SEQUENCE VReg_64, $vindex, sub0, $voffset, sub1), $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $slc)), @@ -1361,11 +1361,11 @@ } multiclass MUBUF_Real_Atomic_si op> : MUBUF_Real_AllAddr_si { - def _RTN_OFFSET_si : MUBUF_Real_si (NAME#"_RTN_OFFSET")>; - def _RTN_ADDR64_si : MUBUF_Real_si (NAME#"_RTN_ADDR64")>; - def _RTN_OFFEN_si : MUBUF_Real_si (NAME#"_RTN_OFFEN")>; - def _RTN_IDXEN_si : MUBUF_Real_si (NAME#"_RTN_IDXEN")>; - def _RTN_BOTHEN_si : MUBUF_Real_si (NAME#"_RTN_BOTHEN")>; + def _OFFSET_RTN_si : MUBUF_Real_si (NAME#"_OFFSET_RTN")>; + def _ADDR64_RTN_si : MUBUF_Real_si (NAME#"_ADDR64_RTN")>; + def _OFFEN_RTN_si : MUBUF_Real_si (NAME#"_OFFEN_RTN")>; + def _IDXEN_RTN_si : MUBUF_Real_si (NAME#"_IDXEN_RTN")>; + def _BOTHEN_RTN_si : MUBUF_Real_si (NAME#"_BOTHEN_RTN")>; } defm BUFFER_LOAD_FORMAT_X : MUBUF_Real_AllAddr_si <0x00>; @@ -1520,10 +1520,10 @@ multiclass MUBUF_Real_Atomic_vi op> : MUBUF_Real_AllAddr_vi { - def _RTN_OFFSET_vi : MUBUF_Real_vi (NAME#"_RTN_OFFSET")>; - def _RTN_OFFEN_vi : MUBUF_Real_vi (NAME#"_RTN_OFFEN")>; - def _RTN_IDXEN_vi : MUBUF_Real_vi (NAME#"_RTN_IDXEN")>; - def _RTN_BOTHEN_vi : MUBUF_Real_vi (NAME#"_RTN_BOTHEN")>; + def _OFFSET_RTN_vi : MUBUF_Real_vi (NAME#"_OFFSET_RTN")>; + def _OFFEN_RTN_vi : MUBUF_Real_vi (NAME#"_OFFEN_RTN")>; + def _IDXEN_RTN_vi : MUBUF_Real_vi (NAME#"_IDXEN_RTN")>; + def _BOTHEN_RTN_vi : MUBUF_Real_vi (NAME#"_BOTHEN_RTN")>; } defm BUFFER_LOAD_FORMAT_X : MUBUF_Real_AllAddr_vi <0x00>;