Index: lib/Target/ARM/ARMSubtarget.cpp =================================================================== --- lib/Target/ARM/ARMSubtarget.cpp +++ lib/Target/ARM/ARMSubtarget.cpp @@ -144,8 +144,6 @@ ? (ARMBaseInstrInfo *)new ARMInstrInfo(*this) : (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)), TLInfo(TM, *this) { - assert((isThumb() || hasARMOps()) && - "Target must either be thumb or support ARM operations!"); #ifndef LLVM_BUILD_GLOBAL_ISEL GISelAccessor *GISel = new GISelAccessor(); Index: lib/Target/ARM/ARMTargetMachine.cpp =================================================================== --- lib/Target/ARM/ARMTargetMachine.cpp +++ lib/Target/ARM/ARMTargetMachine.cpp @@ -266,7 +266,12 @@ // function that reside in TargetOptions. resetTargetOptions(F); I = llvm::make_unique(TargetTriple, CPU, FS, *this, isLittle); + + if (!I->isThumb() && !I->hasARMOps()) + F.getContext().emitError("Function '" + F.getName() + "' uses ARM " + "instructions, but the target does not support ARM mode execution."); } + return I.get(); } Index: test/CodeGen/ARM/no-arm-mode.ll =================================================================== --- test/CodeGen/ARM/no-arm-mode.ll +++ test/CodeGen/ARM/no-arm-mode.ll @@ -0,0 +1,21 @@ +; RUN: not llc -mtriple=armv7-windows-itanium -mcpu=cortex-a9 -o /dev/null %s 2>&1 \ +; RUN: | FileCheck %s -check-prefixes=CHECK-OPTIONS,CHECK-FEATURE + +; RUN: not llc -mtriple=thumb-unknown-linux -mcpu=cortex-m0 -o /dev/null %s 2>&1 \ +; RUN: | FileCheck %s -check-prefix=CHECK-FEATURE + +define void @foo() { +entry: + ret void +} + +; CHECK-OPTIONS: Function 'foo' uses ARM instructions, but the target does not support ARM mode execution. + +define void @no_thumb_mode_feature() #0 { +entry: + ret void +} + +; CHECK-FEATURE: Function 'no_thumb_mode_feature' uses ARM instructions, but the target does not support ARM mode execution. + +attributes #0 = { "target-features"="-thumb-mode" }