Index: lib/Target/Mips/AsmParser/MipsAsmParser.cpp =================================================================== --- lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -512,6 +512,9 @@ IsLittleEndian = false; else IsLittleEndian = true; + + if (getSTI().getCPU() == "mips64r6" && inMicroMipsMode()) + report_fatal_error("microMIPS64R6 is not supported", false); } /// True if all of $fcc0 - $fcc7 exist for the current ISA. @@ -1987,9 +1990,7 @@ case Mips::DDIV: case Mips::DDIVU: case Mips::DIVU_MMR6: - case Mips::DDIVU_MM64R6: case Mips::DIV_MMR6: - case Mips::DDIV_MM64R6: if (Inst.getOperand(SecondOp).getReg() == Mips::ZERO || Inst.getOperand(SecondOp).getReg() == Mips::ZERO_64) { if (Inst.getOperand(FirstOp).getReg() == Mips::ZERO || @@ -5114,8 +5115,6 @@ return Match_Success; case Mips::DATI: case Mips::DAHI: - case Mips::DATI_MM64R6: - case Mips::DAHI_MM64R6: if (static_cast(*Operands[1]) .isValidForTie(static_cast(*Operands[2]))) return Match_Success; @@ -5128,7 +5127,6 @@ // As described by the MIPSR6 spec, daui must not use the zero operand for // its source operand. case Mips::DAUI: - case Mips::DAUI_MM64R6: if (Inst.getOperand(1).getReg() == Mips::ZERO || Inst.getOperand(1).getReg() == Mips::ZERO_64) return Match_RequiresNoZeroRegister; @@ -5201,8 +5199,7 @@ if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) return Match_RequiresDifferentOperands; return Match_Success; - case Mips::DINS: - case Mips::DINS_MM64R6: { + case Mips::DINS: { assert(Inst.getOperand(2).isImm() && Inst.getOperand(3).isImm() && "Operands must be immediates for dins!"); const signed Pos = Inst.getOperand(2).getImm(); @@ -5212,9 +5209,7 @@ return Match_Success; } case Mips::DINSM: - case Mips::DINSM_MM64R6: - case Mips::DINSU: - case Mips::DINSU_MM64R6: { + case Mips::DINSU: { assert(Inst.getOperand(2).isImm() && Inst.getOperand(3).isImm() && "Operands must be immediates for dinsm/dinsu!"); const signed Pos = Inst.getOperand(2).getImm(); @@ -5223,8 +5218,7 @@ return Match_RequiresPosSizeRange33_64; return Match_Success; } - case Mips::DEXT: - case Mips::DEXT_MM64R6: { + case Mips::DEXT: { assert(Inst.getOperand(2).isImm() && Inst.getOperand(3).isImm() && "Operands must be immediates for DEXTM!"); const signed Pos = Inst.getOperand(2).getImm(); @@ -5234,9 +5228,7 @@ return Match_Success; } case Mips::DEXTM: - case Mips::DEXTU: - case Mips::DEXTM_MM64R6: - case Mips::DEXTU_MM64R6: { + case Mips::DEXTU: { assert(Inst.getOperand(2).isImm() && Inst.getOperand(3).isImm() && "Operands must be immediates for dextm/dextu!"); const signed Pos = Inst.getOperand(2).getImm(); @@ -6794,6 +6786,9 @@ if (ArchFeatureName.empty()) return reportParseError("unsupported architecture"); + if (ArchFeatureName == "mips64r6" && inMicroMipsMode()) + return reportParseError("mips64r6 does not support microMIPS"); + selectArch(ArchFeatureName); getTargetStreamer().emitDirectiveSetArch(Arch); return false; @@ -7125,6 +7120,10 @@ Parser.eatToEndOfStatement(); return false; } else if (Tok.getString() == "micromips") { + if (hasMips64r6()) { + Error(Tok.getLoc(), ".set micromips directive is not supported with MIPS64R6"); + return false; + } return parseSetFeature(Mips::FeatureMicroMips); } else if (Tok.getString() == "mips0") { return parseSetMips0Directive(); @@ -7157,6 +7156,10 @@ } else if (Tok.getString() == "mips64r5") { return parseSetFeature(Mips::FeatureMips64r5); } else if (Tok.getString() == "mips64r6") { + if (inMicroMipsMode()) { + Error(Tok.getLoc(), "MIPS64R6 is not supported with microMIPS"); + return false; + } return parseSetFeature(Mips::FeatureMips64r6); } else if (Tok.getString() == "dsp") { return parseSetFeature(Mips::FeatureDSP); Index: lib/Target/Mips/Disassembler/MipsDisassembler.cpp =================================================================== --- lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -1068,26 +1068,16 @@ unsigned Lsb = fieldFromInstruction(Insn, 6, 5); unsigned Size = 0; unsigned Pos = 0; - bool IsMicroMips = false; switch (MI.getOpcode()) { - case Mips::DEXT_MM64R6: - IsMicroMips = true; - LLVM_FALLTHROUGH; case Mips::DEXT: Pos = Lsb; Size = Msbd + 1; break; - case Mips::DEXTM_MM64R6: - IsMicroMips = true; - LLVM_FALLTHROUGH; case Mips::DEXTM: Pos = Lsb; Size = Msbd + 1 + 32; break; - case Mips::DEXTU_MM64R6: - IsMicroMips = true; - LLVM_FALLTHROUGH; case Mips::DEXTU: Pos = Lsb + 32; Size = Msbd + 1; @@ -1096,14 +1086,10 @@ llvm_unreachable("Unknown DEXT instruction!"); } - MI.setOpcode(IsMicroMips ? Mips::DEXT_MM64R6 : Mips::DEXT); + MI.setOpcode(Mips::DEXT); - // Although the format of the instruction is similar, rs and rt are swapped - // for microMIPS64R6. InsnType Rs = fieldFromInstruction(Insn, 21, 5); InsnType Rt = fieldFromInstruction(Insn, 16, 5); - if (IsMicroMips) - std::swap(Rs, Rt); MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt))); MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs))); @@ -1122,26 +1108,16 @@ unsigned Lsb = fieldFromInstruction(Insn, 6, 5); unsigned Size = 0; unsigned Pos = 0; - bool IsMicroMips = false; switch (MI.getOpcode()) { - case Mips::DINS_MM64R6: - IsMicroMips = true; - LLVM_FALLTHROUGH; case Mips::DINS: Pos = Lsb; Size = Msbd + 1 - Pos; break; - case Mips::DINSM_MM64R6: - IsMicroMips = true; - LLVM_FALLTHROUGH; case Mips::DINSM: Pos = Lsb; Size = Msbd + 33 - Pos; break; - case Mips::DINSU_MM64R6: - IsMicroMips = true; - LLVM_FALLTHROUGH; case Mips::DINSU: Pos = Lsb + 32; // mbsd = pos + size - 33 @@ -1152,14 +1128,10 @@ llvm_unreachable("Unknown DINS instruction!"); } - // Although the format of the instruction is similar, rs and rt are swapped - // for microMIPS64R6. InsnType Rs = fieldFromInstruction(Insn, 21, 5); InsnType Rt = fieldFromInstruction(Insn, 16, 5); - if (IsMicroMips) - std::swap(Rs, Rt); - MI.setOpcode(IsMicroMips ? Mips::DINS_MM64R6 : Mips::DINS); + MI.setOpcode(Mips::DINS); MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt))); MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs))); MI.addOperand(MCOperand::createImm(Pos)); @@ -1240,7 +1212,7 @@ if (hasMips32r6()) { DEBUG(dbgs() << "Trying MicroMipsR616 table (16-bit instructions):\n"); // Calling the auto-generated decoder function for microMIPS32R6 - // (and microMIPS64R6) 16-bit instructions. + // 16-bit instructions. Result = decodeInstruction(DecoderTableMicroMipsR616, Instr, Insn, Address, this, STI); if (Result != MCDisassembler::Fail) { Index: lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp +++ lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp @@ -86,18 +86,6 @@ case Mips::DROTR: Inst.setOpcode(Mips::DROTR32); return; - case Mips::DSLL_MM64R6: - Inst.setOpcode(Mips::DSLL32_MM64R6); - return; - case Mips::DSRL_MM64R6: - Inst.setOpcode(Mips::DSRL32_MM64R6); - return; - case Mips::DSRA_MM64R6: - Inst.setOpcode(Mips::DSRA32_MM64R6); - return; - case Mips::DROTR_MM64R6: - Inst.setOpcode(Mips::DROTR32_MM64R6); - return; } } @@ -178,10 +166,6 @@ case Mips::DSRL: case Mips::DSRA: case Mips::DROTR: - case Mips::DSLL_MM64R6: - case Mips::DSRL_MM64R6: - case Mips::DSRA_MM64R6: - case Mips::DROTR_MM64R6: LowerLargeShift(TmpInst); break; // Compact branches, enforce encoding restrictions. Index: lib/Target/Mips/MicroMips32r6InstrFormats.td =================================================================== --- lib/Target/Mips/MicroMips32r6InstrFormats.td +++ lib/Target/Mips/MicroMips32r6InstrFormats.td @@ -17,7 +17,7 @@ string DecoderNamespace = "MicroMipsR6"; } -// Class used for microMIPS32r6 and microMIPS64r6 instructions. +// Class used for microMIPS32r6 instructions. class MicroMipsR6Inst16 : PredicateControl { string DecoderNamespace = "MicroMipsR6"; let InsnPredicates = [HasMicroMips32r6]; Index: lib/Target/Mips/MicroMipsInstrInfo.td =================================================================== --- lib/Target/Mips/MicroMipsInstrInfo.td +++ lib/Target/Mips/MicroMipsInstrInfo.td @@ -587,24 +587,24 @@ } def ADDU16_MM : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>, - ARITH_FM_MM16<0>, ISA_MICROMIPS_NOT_32R6_64R6; + ARITH_FM_MM16<0>, ISA_MICROMIPS_NOT_32R6; def AND16_MM : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>, - LOGIC_FM_MM16<0x2>, ISA_MICROMIPS_NOT_32R6_64R6; + LOGIC_FM_MM16<0x2>, ISA_MICROMIPS_NOT_32R6; def ANDI16_MM : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>, ANDI_FM_MM16<0x0b>, - ISA_MICROMIPS_NOT_32R6_64R6; + ISA_MICROMIPS_NOT_32R6; def NOT16_MM : NotMM16<"not16", GPRMM16Opnd>, LOGIC_FM_MM16<0x0>, - ISA_MICROMIPS_NOT_32R6_64R6; + ISA_MICROMIPS_NOT_32R6; def OR16_MM : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>, LOGIC_FM_MM16<0x3>, - ISA_MICROMIPS_NOT_32R6_64R6; + ISA_MICROMIPS_NOT_32R6; def SLL16_MM : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>, - SHIFT_FM_MM16<0>, ISA_MICROMIPS_NOT_32R6_64R6; + SHIFT_FM_MM16<0>, ISA_MICROMIPS_NOT_32R6; def SRL16_MM : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>, - SHIFT_FM_MM16<1>, ISA_MICROMIPS_NOT_32R6_64R6; + SHIFT_FM_MM16<1>, ISA_MICROMIPS_NOT_32R6; def SUBU16_MM : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>, - ARITH_FM_MM16<1>, ISA_MICROMIPS_NOT_32R6_64R6; + ARITH_FM_MM16<1>, ISA_MICROMIPS_NOT_32R6; def XOR16_MM : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>, - LOGIC_FM_MM16<0x1>, ISA_MICROMIPS_NOT_32R6_64R6; + LOGIC_FM_MM16<0x1>, ISA_MICROMIPS_NOT_32R6; def LBU16_MM : LoadMM16<"lbu16", GPRMM16Opnd, zextloadi8, II_LBU, mem_mm_4>, LOAD_STORE_FM_MM16<0x02>; def LHU16_MM : LoadMM16<"lhu16", GPRMM16Opnd, zextloadi16, II_LHU, @@ -632,7 +632,7 @@ def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>; def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>; def MOVEP_MM : MovePMM16<"movep", GPRMM16OpndMoveP>, MOVEP_FM_MM16, - ISA_MICROMIPS_NOT_32R6_64R6; + ISA_MICROMIPS_NOT_32R6; def LI16_MM : LoadImmMM16<"li16", li16_imm, GPRMM16Opnd>, LI_FM_MM16, IsAsCheapAsAMove; def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>, @@ -647,9 +647,9 @@ BEQNEZ_FM_MM16<0x2b>; def B16_MM : UncondBranchMM16<"b16">, B16_FM; def BREAK16_MM : BrkSdbbp16MM<"break16", II_BREAK>, BRKSDBBP16_FM_MM<0x28>, - ISA_MICROMIPS_NOT_32R6_64R6; + ISA_MICROMIPS_NOT_32R6; def SDBBP16_MM : BrkSdbbp16MM<"sdbbp16", II_SDBBP>, BRKSDBBP16_FM_MM<0x2C>, - ISA_MICROMIPS_NOT_32R6_64R6; + ISA_MICROMIPS_NOT_32R6; let DecoderNamespace = "MicroMips" in { /// Load and Store Instructions - multiple Index: lib/Target/Mips/MicroMipsSizeReduction.cpp =================================================================== --- lib/Target/Mips/MicroMipsSizeReduction.cpp +++ lib/Target/Mips/MicroMipsSizeReduction.cpp @@ -495,8 +495,7 @@ Subtarget = &static_cast(MF.getSubtarget()); - // TODO: Add support for other subtargets: - // microMIPS32r6 and microMIPS64r6 + // TODO: Add support for the subtarget microMIPS32R6. if (!Subtarget->inMicroMipsMode() || !Subtarget->hasMips32r2() || Subtarget->hasMips32r6()) return false; Index: lib/Target/Mips/Mips64InstrInfo.td =================================================================== --- lib/Target/Mips/Mips64InstrInfo.td +++ lib/Target/Mips/Mips64InstrInfo.td @@ -99,8 +99,8 @@ def DADDi : ArithLogicI<"daddi", simm16_64, GPR64Opnd, II_DADDI>, ADDI_FM<0x18>, ISA_MIPS3_NOT_32R6_64R6; let AdditionalPredicates = [NotInMicroMips] in { - def DADDiu : StdMMR6Rel, ArithLogicI<"daddiu", simm16_64, GPR64Opnd, - II_DADDIU, immSExt16, add>, + def DADDiu : ArithLogicI<"daddiu", simm16_64, GPR64Opnd, II_DADDIU, + immSExt16, add>, ADDI_FM<0x19>, IsAsCheapAsAMove, ISA_MIPS3; } @@ -120,13 +120,13 @@ /// Arithmetic Instructions (3-Operand, R-Type) let AdditionalPredicates = [NotInMicroMips] in { - def DADD : StdMMR6Rel, ArithLogicR<"dadd", GPR64Opnd, 1, II_DADD>, - ADD_FM<0, 0x2c>, ISA_MIPS3; - def DADDu : StdMMR6Rel, ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>, - ADD_FM<0, 0x2d>, ISA_MIPS3; - def DSUBu : StdMMR6Rel, ArithLogicR<"dsubu", GPR64Opnd, 0, II_DSUBU, sub>, ADD_FM<0, 0x2f>, + def DADD : ArithLogicR<"dadd", GPR64Opnd, 1, II_DADD>, ADD_FM<0, 0x2c>, ISA_MIPS3; - def DSUB : StdMMR6Rel, ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB>, ADD_FM<0, 0x2e>, + def DADDu : ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>, + ADD_FM<0, 0x2d>, ISA_MIPS3; + def DSUBu : ArithLogicR<"dsubu", GPR64Opnd, 0, II_DSUBU, sub>, + ADD_FM<0, 0x2f>, ISA_MIPS3; + def DSUB : ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB>, ADD_FM<0, 0x2e>, ISA_MIPS3; } @@ -141,40 +141,35 @@ /// Shift Instructions let AdditionalPredicates = [NotInMicroMips] in { - def DSLL : StdMMR6Rel, shift_rotate_imm<"dsll", uimm6, GPR64Opnd, II_DSLL, - shl, immZExt6>, + def DSLL : shift_rotate_imm<"dsll", uimm6, GPR64Opnd, II_DSLL, shl, + immZExt6>, SRA_FM<0x38, 0>, ISA_MIPS3; - def DSRL : StdMMR6Rel, shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL, - srl, immZExt6>, + def DSRL : shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL, srl, + immZExt6>, SRA_FM<0x3a, 0>, ISA_MIPS3; - def DSRA : StdMMR6Rel, shift_rotate_imm<"dsra", uimm6, GPR64Opnd, II_DSRA, - sra, immZExt6>, + def DSRA : shift_rotate_imm<"dsra", uimm6, GPR64Opnd, II_DSRA, sra, + immZExt6>, SRA_FM<0x3b, 0>, ISA_MIPS3; - def DSLLV : StdMMR6Rel, shift_rotate_reg<"dsllv", GPR64Opnd, II_DSLLV, shl>, + def DSLLV : shift_rotate_reg<"dsllv", GPR64Opnd, II_DSLLV, shl>, SRLV_FM<0x14, 0>, ISA_MIPS3; - def DSRAV : StdMMR6Rel, shift_rotate_reg<"dsrav", GPR64Opnd, II_DSRAV, sra>, + def DSRAV : shift_rotate_reg<"dsrav", GPR64Opnd, II_DSRAV, sra>, SRLV_FM<0x17, 0>, ISA_MIPS3; - def DSRLV : StdMMR6Rel, shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, srl>, + def DSRLV : shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, srl>, SRLV_FM<0x16, 0>, ISA_MIPS3; - def DSLL32 : StdMMR6Rel, shift_rotate_imm<"dsll32", uimm5, GPR64Opnd, - II_DSLL32>, + def DSLL32 : shift_rotate_imm<"dsll32", uimm5, GPR64Opnd, II_DSLL32>, SRA_FM<0x3c, 0>, ISA_MIPS3; - def DSRL32 : StdMMR6Rel, shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd, - II_DSRL32>, + def DSRL32 : shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd, II_DSRL32>, SRA_FM<0x3e, 0>, ISA_MIPS3; - def DSRA32 : StdMMR6Rel, shift_rotate_imm<"dsra32", uimm5, GPR64Opnd, - II_DSRA32>, + def DSRA32 : shift_rotate_imm<"dsra32", uimm5, GPR64Opnd, II_DSRA32>, SRA_FM<0x3f, 0>, ISA_MIPS3; // Rotate Instructions - def DROTR : StdMMR6Rel, shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR, - rotr, immZExt6>, + def DROTR : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR, rotr, + immZExt6>, SRA_FM<0x3a, 1>, ISA_MIPS64R2; - def DROTRV : StdMMR6Rel, shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV, - rotr>, + def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV, rotr>, SRLV_FM<0x16, 1>, ISA_MIPS64R2; - def DROTR32 : StdMMR6Rel, shift_rotate_imm<"drotr32", uimm5, GPR64Opnd, - II_DROTR32>, + def DROTR32 : shift_rotate_imm<"drotr32", uimm5, GPR64Opnd, II_DROTR32>, SRA_FM<0x3e, 1>, ISA_MIPS64R2; } @@ -192,11 +187,11 @@ } let AdditionalPredicates = [NotInMicroMips] in { - def LWu : StdMMR6Rel, MMRel, Load<"lwu", GPR64Opnd, zextloadi32, II_LWU>, + def LWu : MMRel, Load<"lwu", GPR64Opnd, zextloadi32, II_LWU>, LW_FM<0x27>, ISA_MIPS3; - def LD : StdMMR6Rel, LoadMemory<"ld", GPR64Opnd, mem_simm16, load, II_LD>, + def LD : LoadMemory<"ld", GPR64Opnd, mem_simm16, load, II_LD>, LW_FM<0x37>, ISA_MIPS3; - def SD : StdMMR6Rel, StoreMemory<"sd", GPR64Opnd, mem_simm16, store, II_SD>, + def SD : StoreMemory<"sd", GPR64Opnd, mem_simm16, store, II_SD>, LW_FM<0x3f>, ISA_MIPS3; } @@ -221,7 +216,7 @@ /// Load-linked, Store-conditional let AdditionalPredicates = [NotInMicroMips] in { - def LLD : StdMMR6Rel, LLBase<"lld", GPR64Opnd, mem_simm16>, LW_FM<0x34>, + def LLD : LLBase<"lld", GPR64Opnd, mem_simm16>, LW_FM<0x34>, ISA_MIPS3_NOT_32R6_64R6; } def SCD : SCBase<"scd", GPR64Opnd>, LW_FM<0x3c>, ISA_MIPS3_NOT_32R6_64R6; @@ -299,10 +294,10 @@ /// Count Leading let AdditionalPredicates = [NotInMicroMips] in { - def DCLZ : StdMMR6Rel, CountLeading0<"dclz", GPR64Opnd, II_DCLZ>, - CLO_FM<0x24>, ISA_MIPS64_NOT_64R6; - def DCLO : StdMMR6Rel, CountLeading1<"dclo", GPR64Opnd, II_DCLO>, - CLO_FM<0x25>, ISA_MIPS64_NOT_64R6; + def DCLZ : CountLeading0<"dclz", GPR64Opnd, II_DCLZ>, CLO_FM<0x24>, + ISA_MIPS64_NOT_64R6; + def DCLO : CountLeading1<"dclo", GPR64Opnd, II_DCLO>, CLO_FM<0x25>, + ISA_MIPS64_NOT_64R6; /// Double Word Swap Bytes/HalfWords def DSBH : SubwordSwap<"dsbh", GPR64Opnd, II_DSBH>, SEB_FM<2, 0x24>, @@ -568,74 +563,70 @@ def : MipsPat<(MipsGotHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>; def : MipsPat<(MipsGotHi texternalsym:$in), (LUi64 texternalsym:$in)>; -multiclass MipsHighestHigherHiLoRelocs { +// highest/higher/hi/lo relocs +let AdditionalPredicates = [NotInMicroMips] in { def : MipsPat<(MipsJmpLink (i64 texternalsym:$dst)), - (JAL texternalsym:$dst)>; + (JAL texternalsym:$dst)>, SYM_64; def : MipsPat<(MipsHighest (i64 tglobaladdr:$in)), - (Lui tglobaladdr:$in)>; + (LUi64 tglobaladdr:$in)>, SYM_64; def : MipsPat<(MipsHighest (i64 tblockaddress:$in)), - (Lui tblockaddress:$in)>; + (LUi64 tblockaddress:$in)>, SYM_64; def : MipsPat<(MipsHighest (i64 tjumptable:$in)), - (Lui tjumptable:$in)>; + (LUi64 tjumptable:$in)>, SYM_64; def : MipsPat<(MipsHighest (i64 tconstpool:$in)), - (Lui tconstpool:$in)>; + (LUi64 tconstpool:$in)>, SYM_64; def : MipsPat<(MipsHighest (i64 tglobaltlsaddr:$in)), - (Lui tglobaltlsaddr:$in)>; + (LUi64 tglobaltlsaddr:$in)>, SYM_64; def : MipsPat<(MipsHighest (i64 texternalsym:$in)), - (Lui texternalsym:$in)>; + (LUi64 texternalsym:$in)>, SYM_64; def : MipsPat<(MipsHigher (i64 tglobaladdr:$in)), - (Daddiu ZERO_64, tglobaladdr:$in)>; + (DADDiu ZERO_64, tglobaladdr:$in)>, SYM_64; def : MipsPat<(MipsHigher (i64 tblockaddress:$in)), - (Daddiu ZERO_64, tblockaddress:$in)>; + (DADDiu ZERO_64, tblockaddress:$in)>, SYM_64; def : MipsPat<(MipsHigher (i64 tjumptable:$in)), - (Daddiu ZERO_64, tjumptable:$in)>; + (DADDiu ZERO_64, tjumptable:$in)>, SYM_64; def : MipsPat<(MipsHigher (i64 tconstpool:$in)), - (Daddiu ZERO_64, tconstpool:$in)>; + (DADDiu ZERO_64, tconstpool:$in)>, SYM_64; def : MipsPat<(MipsHigher (i64 tglobaltlsaddr:$in)), - (Daddiu ZERO_64, tglobaltlsaddr:$in)>; + (DADDiu ZERO_64, tglobaltlsaddr:$in)>, SYM_64; def : MipsPat<(MipsHigher (i64 texternalsym:$in)), - (Daddiu ZERO_64, texternalsym:$in)>; + (DADDiu ZERO_64, texternalsym:$in)>, SYM_64; def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tglobaladdr:$lo))), - (Daddiu GPR64:$hi, tglobaladdr:$lo)>; + (DADDiu GPR64:$hi, tglobaladdr:$lo)>, SYM_64; def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tblockaddress:$lo))), - (Daddiu GPR64:$hi, tblockaddress:$lo)>; + (DADDiu GPR64:$hi, tblockaddress:$lo)>, SYM_64; def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tjumptable:$lo))), - (Daddiu GPR64:$hi, tjumptable:$lo)>; + (DADDiu GPR64:$hi, tjumptable:$lo)>, SYM_64; def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tconstpool:$lo))), - (Daddiu GPR64:$hi, tconstpool:$lo)>; + (DADDiu GPR64:$hi, tconstpool:$lo)>, SYM_64; def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tglobaltlsaddr:$lo))), - (Daddiu GPR64:$hi, tglobaltlsaddr:$lo)>; + (DADDiu GPR64:$hi, tglobaltlsaddr:$lo)>, SYM_64; def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tglobaladdr:$lo))), - (Daddiu GPR64:$hi, tglobaladdr:$lo)>; + (DADDiu GPR64:$hi, tglobaladdr:$lo)>, SYM_64; def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tblockaddress:$lo))), - (Daddiu GPR64:$hi, tblockaddress:$lo)>; + (DADDiu GPR64:$hi, tblockaddress:$lo)>, SYM_64; def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tjumptable:$lo))), - (Daddiu GPR64:$hi, tjumptable:$lo)>; + (DADDiu GPR64:$hi, tjumptable:$lo)>, SYM_64; def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tconstpool:$lo))), - (Daddiu GPR64:$hi, tconstpool:$lo)>; + (DADDiu GPR64:$hi, tconstpool:$lo)>, SYM_64; def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tglobaltlsaddr:$lo))), - (Daddiu GPR64:$hi, tglobaltlsaddr:$lo)>; + (DADDiu GPR64:$hi, tglobaltlsaddr:$lo)>, SYM_64; def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tglobaladdr:$lo))), - (Daddiu GPR64:$hi, tglobaladdr:$lo)>; + (DADDiu GPR64:$hi, tglobaladdr:$lo)>, SYM_64; def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tblockaddress:$lo))), - (Daddiu GPR64:$hi, tblockaddress:$lo)>; + (DADDiu GPR64:$hi, tblockaddress:$lo)>, SYM_64; def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tjumptable:$lo))), - (Daddiu GPR64:$hi, tjumptable:$lo)>; + (DADDiu GPR64:$hi, tjumptable:$lo)>, SYM_64; def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tconstpool:$lo))), - (Daddiu GPR64:$hi, tconstpool:$lo)>; + (DADDiu GPR64:$hi, tconstpool:$lo)>, SYM_64; def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tglobaltlsaddr:$lo))), - (Daddiu GPR64:$hi, tglobaltlsaddr:$lo)>; - + (DADDiu GPR64:$hi, tglobaltlsaddr:$lo)>, SYM_64; } -// highest/higher/hi/lo relocs -let AdditionalPredicates = [NotInMicroMips] in -defm : MipsHighestHigherHiLoRelocs, SYM_64; - // gp_rel relocs def : MipsPat<(add GPR64:$gp, (MipsGPRel tglobaladdr:$in)), (DADDiu GPR64:$gp, tglobaladdr:$in)>, ABI_N64; Index: lib/Target/Mips/Mips64r6InstrInfo.td =================================================================== --- lib/Target/Mips/Mips64r6InstrInfo.td +++ lib/Target/Mips/Mips64r6InstrInfo.td @@ -117,21 +117,21 @@ } def DAUI : DAUI_ENC, DAUI_DESC, ISA_MIPS64R6; def DALIGN : DALIGN_ENC, DALIGN_DESC, ISA_MIPS64R6; - def DBITSWAP : R6MMR6Rel, DBITSWAP_ENC, DBITSWAP_DESC, ISA_MIPS64R6; - def DCLO_R6 : R6MMR6Rel, DCLO_R6_ENC, DCLO_R6_DESC, ISA_MIPS64R6; - def DCLZ_R6 : R6MMR6Rel, DCLZ_R6_ENC, DCLZ_R6_DESC, ISA_MIPS64R6; + def DBITSWAP : DBITSWAP_ENC, DBITSWAP_DESC, ISA_MIPS64R6; + def DCLO_R6 : DCLO_R6_ENC, DCLO_R6_DESC, ISA_MIPS64R6; + def DCLZ_R6 : DCLZ_R6_ENC, DCLZ_R6_DESC, ISA_MIPS64R6; def DDIV : DDIV_ENC, DDIV_DESC, ISA_MIPS64R6; def DDIVU : DDIVU_ENC, DDIVU_DESC, ISA_MIPS64R6; def DMOD : DMOD_ENC, DMOD_DESC, ISA_MIPS64R6; def DMODU : DMODU_ENC, DMODU_DESC, ISA_MIPS64R6; - def DLSA_R6 : R6MMR6Rel, DLSA_R6_ENC, DLSA_R6_DESC, ISA_MIPS64R6; + def DLSA_R6 : DLSA_R6_ENC, DLSA_R6_DESC, ISA_MIPS64R6; def DMUH: DMUH_ENC, DMUH_DESC, ISA_MIPS64R6; def DMUHU: DMUHU_ENC, DMUHU_DESC, ISA_MIPS64R6; def DMUL_R6: DMUL_R6_ENC, DMUL_R6_DESC, ISA_MIPS64R6; def DMULU: DMULU_ENC, DMULU_DESC, ISA_MIPS64R6; - def LLD_R6 : R6MMR6Rel, LLD_R6_ENC, LLD_R6_DESC, ISA_MIPS64R6; + def LLD_R6 : LLD_R6_ENC, LLD_R6_DESC, ISA_MIPS64R6; } -def LDPC: R6MMR6Rel, LDPC_ENC, LDPC_DESC, ISA_MIPS64R6; +def LDPC: LDPC_ENC, LDPC_DESC, ISA_MIPS64R6; def SCD_R6 : SCD_R6_ENC, SCD_R6_DESC, ISA_MIPS32R6; let DecoderNamespace = "Mips32r6_64r6_GP64" in { def SELEQZ64 : SELEQZ_ENC, SELEQZ64_DESC, ISA_MIPS32R6, GPR_64; Index: lib/Target/Mips/MipsISelLowering.cpp =================================================================== --- lib/Target/Mips/MipsISelLowering.cpp +++ lib/Target/Mips/MipsISelLowering.cpp @@ -1395,11 +1395,6 @@ case Mips::DMOD: case Mips::DMODU: return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, false); - case Mips::DDIV_MM64R6: - case Mips::DDIVU_MM64R6: - case Mips::DMOD_MM64R6: - case Mips::DMODU_MM64R6: - return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, true); case Mips::PseudoSELECT_I: case Mips::PseudoSELECT_I64: Index: lib/Target/Mips/MipsInstrInfo.cpp =================================================================== --- lib/Target/Mips/MipsInstrInfo.cpp +++ lib/Target/Mips/MipsInstrInfo.cpp @@ -593,28 +593,22 @@ case Mips::INS: case Mips::INS_MM: case Mips::DINS: - case Mips::DINS_MM64R6: return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 0, 32, 0, 32); case Mips::DINSM: - case Mips::DINSM_MM64R6: // The ISA spec has a subtle difference here in that it says: // 2 <= size <= 64 for 'dinsm', so we change the bounds so that it // is in line with the rest of instructions. return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 1, 64, 32, 64); case Mips::DINSU: - case Mips::DINSU_MM64R6: // The ISA spec has a subtle difference here in that it says: // 2 <= size <= 64 for 'dinsm', so we change the bounds so that it // is in line with the rest of instructions. return verifyInsExtInstruction(MI, ErrInfo, 32, 64, 1, 32, 32, 64); case Mips::DEXT: - case Mips::DEXT_MM64R6: return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 0, 32, 0, 63); case Mips::DEXTM: - case Mips::DEXTM_MM64R6: return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 32, 64, 32, 64); case Mips::DEXTU: - case Mips::DEXTU_MM64R6: return verifyInsExtInstruction(MI, ErrInfo, 32, 64, 0, 32, 32, 64); default: return true; Index: lib/Target/Mips/MipsInstrInfo.td =================================================================== --- lib/Target/Mips/MipsInstrInfo.td +++ lib/Target/Mips/MipsInstrInfo.td @@ -208,8 +208,6 @@ AssemblerPredicate<"!FeatureMips64r6">; def HasMicroMips32r6 : Predicate<"Subtarget->inMicroMips32r6Mode()">, AssemblerPredicate<"FeatureMicroMips,FeatureMips32r6">; -def HasMicroMips64r6 : Predicate<"Subtarget->inMicroMips64r6Mode()">, - AssemblerPredicate<"FeatureMicroMips,FeatureMips64r6">; def InMips16Mode : Predicate<"Subtarget->inMips16Mode()">, AssemblerPredicate<"FeatureMips16">; def NotInMips16Mode : Predicate<"!Subtarget->inMips16Mode()">, @@ -313,9 +311,6 @@ class ISA_MICROMIPS32R6 { list InsnPredicates = [HasMicroMips32r6]; } -class ISA_MICROMIPS64R6 { - list InsnPredicates = [HasMicroMips64r6]; -} class ISA_MICROMIPS32_NOT_MIPS32R6 { list InsnPredicates = [InMicroMips, NotMips32r6]; } @@ -393,8 +388,8 @@ // Class used for separating microMIPSr6 and microMIPS (r3) instruction. // It can be used only on instructions that doesn't inherit PredicateControl. -class ISA_MICROMIPS_NOT_32R6_64R6 : PredicateControl { - let InsnPredicates = [InMicroMips, NotMips32r6, NotMips64r6]; +class ISA_MICROMIPS_NOT_32R6 : PredicateControl { + let InsnPredicates = [InMicroMips, NotMips32r6]; } class ASE_NOT_DSP { @@ -3014,10 +3009,6 @@ include "MicroMips32r6InstrFormats.td" include "MicroMips32r6InstrInfo.td" -// Micromips64 r6 -include "MicroMips64r6InstrFormats.td" -include "MicroMips64r6InstrInfo.td" - // Micromips DSP include "MicroMipsDSPInstrFormats.td" include "MicroMipsDSPInstrInfo.td" Index: lib/Target/Mips/MipsMachineFunction.cpp =================================================================== --- lib/Target/Mips/MipsMachineFunction.cpp +++ lib/Target/Mips/MipsMachineFunction.cpp @@ -41,9 +41,7 @@ STI.inMips16Mode() ? &Mips::CPU16RegsRegClass : STI.inMicroMipsMode() - ? STI.hasMips64() - ? &Mips::GPRMM16_64RegClass - : &Mips::GPRMM16RegClass + ? &Mips::GPRMM16RegClass : static_cast(MF.getTarget()) .getABI() .IsN64() Index: lib/Target/Mips/MipsRegisterInfo.cpp =================================================================== --- lib/Target/Mips/MipsRegisterInfo.cpp +++ lib/Target/Mips/MipsRegisterInfo.cpp @@ -54,8 +54,7 @@ case MipsPtrClass::Default: return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; case MipsPtrClass::GPR16MM: - return ABI.ArePtrs64bit() ? &Mips::GPRMM16_64RegClass - : &Mips::GPRMM16RegClass; + return &Mips::GPRMM16RegClass; case MipsPtrClass::StackPointer: return ABI.ArePtrs64bit() ? &Mips::SP64RegClass : &Mips::SP32RegClass; case MipsPtrClass::GlobalPointer: Index: lib/Target/Mips/MipsRegisterInfo.td =================================================================== --- lib/Target/Mips/MipsRegisterInfo.td +++ lib/Target/Mips/MipsRegisterInfo.td @@ -349,12 +349,6 @@ // Reserved K0_64, K1_64, GP_64, SP_64, FP_64, RA_64)>; -def GPRMM16_64 : RegisterClass<"Mips", [i64], 64, (add - // Callee save - S0_64, S1_64, - // Return Values and Arguments - V0_64, V1_64, A0_64, A1_64, A2_64, A3_64)>; - def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add // Return Values and Arguments V0, V1, A0, A1, A2, A3, Index: lib/Target/Mips/MipsScheduleP5600.td =================================================================== --- lib/Target/Mips/MipsScheduleP5600.td +++ lib/Target/Mips/MipsScheduleP5600.td @@ -18,8 +18,8 @@ list UnsupportedFeatures = [HasMips32r6, HasMips64r6, HasMips64, HasMips64r2, HasCnMips, InMicroMips, InMips16Mode, - HasMicroMips32r6, HasMicroMips64r6, - HasDSP, HasDSPR2, HasMT]; + HasMicroMips32r6, HasDSP, + HasDSPR2, HasMT]; } Index: lib/Target/Mips/MipsSubtarget.h =================================================================== --- lib/Target/Mips/MipsSubtarget.h +++ lib/Target/Mips/MipsSubtarget.h @@ -265,7 +265,6 @@ } bool inMicroMipsMode() const { return InMicroMipsMode; } bool inMicroMips32r6Mode() const { return InMicroMipsMode && hasMips32r6(); } - bool inMicroMips64r6Mode() const { return InMicroMipsMode && hasMips64r6(); } bool hasDSP() const { return HasDSP; } bool hasDSPR2() const { return HasDSPR2; } bool hasDSPR3() const { return HasDSPR3; } Index: lib/Target/Mips/MipsSubtarget.cpp =================================================================== --- lib/Target/Mips/MipsSubtarget.cpp +++ lib/Target/Mips/MipsSubtarget.cpp @@ -104,6 +104,9 @@ if (IsFPXX && (isABI_N32() || isABI_N64())) report_fatal_error("FPXX is not permitted for the N32/N64 ABI's.", false); + if (hasMips64r6() && InMicroMipsMode) + report_fatal_error("microMIPS64R6 is not supported", false); + if (hasMips32r6()) { StringRef ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6"; Index: lib/Target/Mips/Relocation.txt =================================================================== --- lib/Target/Mips/Relocation.txt +++ lib/Target/Mips/Relocation.txt @@ -69,40 +69,7 @@ The instantiation in Mips64InstrInfo.td is used for MIPS64 in ILP32 mode, as guarded by the predicate "SYM_32" and also for a submode of -LP64 where symbols are assumed to be 32 bits wide. A similar -multiclass for MIPS64 in LP64 mode is also defined: - - // lib/Target/Mips/Mips64InstrInfo.td - multiclass MipsHighestHigherHiLoRelocs { - ... - def : MipsPat<(MipsHighest (i64 tglobaladdr:$in)), - (Lui tglobaladdr:$in)>; - ... - def : MipsPat<(MipsHigher (i64 tglobaladdr:$in)), - (Daddiu ZERO_64, tglobaladdr:$in)>; - ... - def : MipsPat<(add GPR64:$hi, (MipsHigher (i64 tglobaladdr:$lo))), - (Daddiu GPR64:$hi, tglobaladdr:$lo)>; - ... - def : MipsPat<(add GPR64:$hi, (MipsHi (i64 tglobaladdr:$lo))), - (Daddiu GPR64:$hi, tglobaladdr:$lo)>; - ... - def : MipsPat<(add GPR64:$hi, (MipsLo (i64 tglobaladdr:$lo))), - (Daddiu GPR64:$hi, tglobaladdr:$lo)>; - } - -and it is instantiated twice: - - // lib/Target/Mips/Mips64InstrInfo.td - defm : MipsHighestHigherHiLoRelocs, SYM_64; - // lib/Target/Mips/MicroMips64r6InstrInfo.td - defm : MipsHighestHigherHiLoRelocs, SYM_64, - ISA_MICROMIPS64R6; - -These patterns are used during instruction selection to match -MipsISD::{Highest, Higher, Hi, Lo} to a specific machine instruction -and operands. +LP64 where symbols are assumed to be 32 bits wide. More details on how multiclasses in TableGen work can be found in the section "Multiclass definitions and instances" in the document Index: test/CodeGen/Mips/countleading.ll =================================================================== --- test/CodeGen/Mips/countleading.ll +++ test/CodeGen/Mips/countleading.ll @@ -5,7 +5,6 @@ ; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck -check-prefixes=ALL,MIPS64-GT-R1 %s ; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck -check-prefixes=ALL,MIPS64-GT-R1 %s ; RUN: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck -check-prefixes=ALL,MIPS64-GT-R1 %s -; RUN: llc -march=mips64el -mcpu=mips64r6 -mattr=micromips < %s | FileCheck -check-prefixes=ALL,MICROMIPS64 %s ; Prefixes: ; ALL - All @@ -22,8 +21,6 @@ ; MIPS64-GT-R1: clz $2, $4 -; MICROMIPS64: clz $2, $4 - %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %X, i1 true) ret i32 %tmp1 } @@ -40,8 +37,6 @@ ; MIPS64-GT-R1: clo $2, $4 -; MICROMIPS64: clo $2, $4 - %neg = xor i32 %X, -1 %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %neg, i1 true) ret i32 %tmp1 @@ -63,7 +58,6 @@ ; MIPS32-GT-R1-DAG: addiu $3, $zero, 0 ; MIPS64-GT-R1: dclz $2, $4 -; MICROMIPS64: dclz $2, $4 %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true) ret i64 %tmp1 @@ -89,7 +83,6 @@ ; MIPS32-GT-R1-DAG: addiu $3, $zero, 0 ; MIPS64-GT-R1: dclo $2, $4 -; MICROMIPS64: dclo $2, $4 %neg = xor i64 %X, -1 %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true) Index: test/CodeGen/Mips/fcmp.ll =================================================================== --- test/CodeGen/Mips/fcmp.ll +++ test/CodeGen/Mips/fcmp.ll @@ -16,8 +16,6 @@ ; RUN: -check-prefixes=ALL,MM,MM32R3 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ ; RUN: -check-prefixes=ALL,MM,MMR6,MM32R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \ -; RUN: -check-prefixes=ALL,MM,MMR6,MM64R6 define i32 @false_f32(float %a, float %b) nounwind { ; ALL-LABEL: false_f32: @@ -61,7 +59,6 @@ ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14 -; MM64R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: andi16 $2, $[[T1]], 1 @@ -95,7 +92,6 @@ ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f14, $f12 -; MM64R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f13, $f12 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: andi16 $2, $[[T1]], 1 @@ -129,7 +125,6 @@ ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f14, $f12 -; MM64R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f13, $f12 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: andi16 $2, $[[T1]], 1 @@ -163,7 +158,6 @@ ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f14 -; MM64R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f13 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: andi16 $2, $[[T1]], 1 @@ -197,7 +191,6 @@ ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f14 -; MM64R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f13 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: andi16 $2, $[[T1]], 1 @@ -233,7 +226,6 @@ ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14 -; MM64R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]] ; MMR6-DAG: andi16 $2, $[[T2]], 1 @@ -270,7 +262,6 @@ ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14 -; MM64R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]] ; MMR6-DAG: andi16 $2, $[[T2]], 1 @@ -305,7 +296,6 @@ ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14 -; MM64R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: andi16 $2, $[[T1]], 1 @@ -339,7 +329,6 @@ ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f14, $f12 -; MM64R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f13, $f12 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: andi16 $2, $[[T1]], 1 @@ -373,7 +362,6 @@ ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f14, $f12 -; MM64R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f13, $f12 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: andi16 $2, $[[T1]], 1 @@ -407,7 +395,6 @@ ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f14 -; MM64R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f13 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: andi16 $2, $[[T1]], 1 @@ -441,7 +428,6 @@ ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f14 -; MM64R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f13 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: andi16 $2, $[[T1]], 1 @@ -477,7 +463,6 @@ ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14 -; MM64R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]] ; MMR6-DAG: andi16 $2, $[[T2]], 1 @@ -512,7 +497,6 @@ ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14 -; MM64R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: andi16 $2, $[[T1]], 1 @@ -580,7 +564,6 @@ ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14 -; MM64R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: andi16 $2, $[[T1]], 1 @@ -614,7 +597,6 @@ ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f14, $f12 -; MM64R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f13, $f12 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: andi16 $2, $[[T1]], 1 @@ -648,7 +630,6 @@ ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f14, $f12 -; MM64R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f13, $f12 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: andi16 $2, $[[T1]], 1 @@ -682,7 +663,6 @@ ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f14 -; MM64R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f13 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: andi16 $2, $[[T1]], 1 @@ -716,7 +696,6 @@ ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f14 -; MM64R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f13 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: andi16 $2, $[[T1]], 1 @@ -752,7 +731,6 @@ ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14 -; MM64R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]] ; MMR6-DAG: andi16 $2, $[[T2]], 1 @@ -789,7 +767,6 @@ ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14 -; MM64R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]] ; MMR6-DAG: andi16 $2, $[[T2]], 1 @@ -824,7 +801,6 @@ ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14 -; MM64R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: andi16 $2, $[[T1]], 1 @@ -858,7 +834,6 @@ ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f14, $f12 -; MM64R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f13, $f12 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: andi16 $2, $[[T1]], 1 @@ -892,7 +867,6 @@ ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f14, $f12 -; MM64R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f13, $f12 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: andi16 $2, $[[T1]], 1 @@ -926,7 +900,6 @@ ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f14 -; MM64R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f13 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: andi16 $2, $[[T1]], 1 @@ -960,7 +933,6 @@ ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f14 -; MM64R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f13 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: andi16 $2, $[[T1]], 1 @@ -996,7 +968,6 @@ ; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14 -; MM64R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]] ; MMR6-DAG: andi16 $2, $[[T2]], 1 @@ -1031,7 +1002,6 @@ ; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 ; MM32R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14 -; MM64R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13 ; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; MMR6-DAG: andi16 $2, $[[T1]], 1 @@ -1102,18 +1072,6 @@ ; MM32R6-DAG: andi16 $[[T5:[0-9]+]], $[[T4]], 1 ; MM32R6-DAG: bnezc $[[T5]], -; MM64R6-DAG: add.s $[[T0:f[0-9]+]], $f13, $f12 -; MM64R6-DAG: lui $[[T1:[0-9]+]], %highest(.LCPI32_0) -; MM64R6-DAG: daddiu $[[T2:[0-9]+]], $[[T1]], %higher(.LCPI32_0) -; MM64R6-DAG: dsll $[[T3:[0-9]+]], $[[T2]], 16 -; MM64R6-DAG: daddiu $[[T4:[0-9]+]], $[[T3]], %hi(.LCPI32_0) -; MM64R6-DAG: dsll $[[T5:[0-9]+]], $[[T4]], 16 -; MM64R6-DAG: lwc1 $[[T6:f[0-9]+]], %lo(.LCPI32_0)($[[T5]]) -; MM64R6-DAG: cmp.le.s $[[T7:f[0-9]+]], $[[T0]], $[[T6]] -; MM64R6-DAG: mfc1 $[[T8:[0-9]+]], $[[T7]] -; MM64R6-DAG: andi16 $[[T9:[0-9]+]], $[[T8]], 1 -; MM64R6-DAG: bnezc $[[T9]], - %add = fadd fast float %at, %angle %cmp = fcmp ogt float %add, 1.000000e+00 br i1 %cmp, label %if.then, label %if.end @@ -1172,18 +1130,6 @@ ; MM32R6-DAG: andi16 $[[T5:[0-9]+]], $[[T4]], 1 ; MM32R6-DAG: bnezc $[[T5]], -; MM64R6-DAG: add.d $[[T0:f[0-9]+]], $f13, $f12 -; MM64R6-DAG: lui $[[T1:[0-9]+]], %highest(.LCPI33_0) -; MM64R6-DAG: daddiu $[[T2:[0-9]+]], $[[T1]], %higher(.LCPI33_0) -; MM64R6-DAG: dsll $[[T3:[0-9]+]], $[[T2]], 16 -; MM64R6-DAG: daddiu $[[T4:[0-9]+]], $[[T3]], %hi(.LCPI33_0) -; MM64R6-DAG: dsll $[[T5:[0-9]+]], $[[T4]], 16 -; MM64R6-DAG: ldc1 $[[T6:f[0-9]+]], %lo(.LCPI33_0)($[[T5]]) -; MM64R6-DAG: cmp.le.d $[[T7:f[0-9]+]], $[[T0]], $[[T6]] -; MM64R6-DAG: mfc1 $[[T8:[0-9]+]], $[[T7]] -; MM64R6-DAG: andi16 $[[T9:[0-9]+]], $[[T8]], 1 -; MM64R6-DAG: bnezc $[[T9]], - %add = fadd fast double %at, %angle %cmp = fcmp ogt double %add, 1.000000e+00 br i1 %cmp, label %if.then, label %if.end Index: test/CodeGen/Mips/llvm-ir/add.ll =================================================================== --- test/CodeGen/Mips/llvm-ir/add.ll +++ test/CodeGen/Mips/llvm-ir/add.ll @@ -28,8 +28,6 @@ ; RUN: -check-prefixes=ALL,MMR3,MM32 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -O2 | FileCheck %s \ ; RUN: -check-prefixes=ALL,MMR6,MM32 -; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -O2 | FileCheck %s \ -; RUN: -check-prefixes=ALL,MM64 ; FIXME: This code sequence is inefficient as it should be 'subu $[[T0]], $zero, $[[T0]'. @@ -122,8 +120,6 @@ ; MM32: sltu $[[T1:[0-9]+]], $3, $5 ; MM32: addu16 $2, $[[T0]], $[[T1]] - ; MM64: daddu $2, $4, $5 - %r = add i64 %a, %b ret i64 %r } @@ -228,13 +224,6 @@ ; MMR6: addu16 $2, $[[T16]], $[[T20]] ; MMR6: addu16 $2, $[[T20]], $[[T21]] - ; MM64: daddu $[[T0:[0-9]+]], $4, $6 - ; MM64: daddu $3, $5, $7 - ; MM64: sltu $[[T1:[0-9]+]], $3, $5 - ; MM64: dsll $[[T2:[0-9]+]], $[[T1]], 32 - ; MM64: dsrl $[[T3:[0-9]+]], $[[T2]], 32 - ; MM64: daddu $2, $[[T0]], $[[T3]] - %r = add i128 %a, %b ret i128 %r } @@ -262,9 +251,6 @@ ; MM32: addiur2 $[[T0:[0-9]+]], $4, 4 ; MM32: seb $2, $[[T0]] - ; MM64: addiur2 $[[T0:[0-9]+]], $4, 4 - ; MM64: seb $2, $[[T0]] - %r = add i8 4, %a ret i8 %r } @@ -283,9 +269,6 @@ ; MM32: addiur2 $[[T0:[0-9]+]], $4, 4 ; MM32: seh $2, $[[T0]] - ; MM64: addiur2 $[[T0:[0-9]+]], $4, 4 - ; MM64: seh $2, $[[T0]] - %r = add i16 4, %a ret i16 %r } @@ -299,8 +282,6 @@ ; MM32: addiur2 $2, $4, 4 - ; MM64: addiur2 $2, $4, 4 - %r = add i32 4, %a ret i32 %r } @@ -319,8 +300,6 @@ ; GP64: daddiu $2, $4, 4 - ; MM64: daddiu $2, $4, 4 - %r = add i64 4, %a ret i64 %r } @@ -384,12 +363,6 @@ ; MMR6: move $4, $7 ; MMR6: move $5, $[[T1]] - ; MM64: daddiu $[[T0:[0-9]+]], $5, 4 - ; MM64: sltu $[[T1:[0-9]+]], $[[T0]], $5 - ; MM64: dsll $[[T2:[0-9]+]], $[[T1]], 32 - ; MM64: dsrl $[[T3:[0-9]+]], $[[T2]], 32 - ; MM64: daddu $2, $4, $[[T3]] - %r = add i128 4, %a ret i128 %r } @@ -477,8 +450,6 @@ ; MM32: sltu $[[T2:[0-9]+]], $[[T1]], $5 ; MM32: addu16 $2, $4, $[[T2]] - ; MM64: daddiu $2, $4, 3 - %r = add i64 3, %a ret i64 %r } @@ -545,12 +516,6 @@ ; MMR6: move $4, $[[T5]] ; MMR6: move $5, $[[T1]] - ; MM64: daddiu $[[T0:[0-9]+]], $5, 3 - ; MM64: sltu $[[T1:[0-9]+]], $[[T0]], $5 - ; MM64: dsll $[[T2:[0-9]+]], $[[T1]], 32 - ; MM64: dsrl $[[T3:[0-9]+]], $[[T2]], 32 - ; MM64: daddu $2, $4, $[[T3]] - %r = add i128 3, %a ret i128 %r } Index: test/CodeGen/Mips/llvm-ir/and.ll =================================================================== --- test/CodeGen/Mips/llvm-ir/and.ll +++ test/CodeGen/Mips/llvm-ir/and.ll @@ -28,8 +28,6 @@ ; RUN: -check-prefixes=ALL,MM,MM32 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ ; RUN: -check-prefixes=ALL,MM,MM32 -; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips | FileCheck %s \ -; RUN: -check-prefixes=ALL,MM,MM64 define signext i1 @and_i1(i1 signext %a, i1 signext %b) { entry: @@ -42,8 +40,6 @@ ; MM32: and16 $[[T0:[0-9]+]], $5 ; MM32: move $2, $[[T0]] - ; MM64: and $1, $4, $5 - %r = and i1 %a, %b ret i1 %r } @@ -59,8 +55,6 @@ ; MM32: and16 $[[T0:[0-9]+]], $5 ; MM32: move $2, $[[T0]] - ; MM64: and $1, $4, $5 - %r = and i8 %a, %b ret i8 %r } @@ -76,8 +70,6 @@ ; MM32: and16 $[[T0:[0-9]+]], $5 ; MM32 move $2, $[[T0]] - ; MM64: and $1, $4, $5 - %r = and i16 %a, %b ret i16 %r } @@ -94,9 +86,6 @@ ; MM32: and16 $[[T0:[0-9]+]], $5 ; MM32: move $2, $[[T0]] - ; MM64: and $[[T0:[0-9]+]], $4, $5 - ; MM64: sll $2, $[[T0]], 0 - %r = and i32 %a, %b ret i32 %r } @@ -115,8 +104,6 @@ ; MM32: move $2, $[[T0]] ; MM32: move $3, $[[T1]] - ; MM64: and $2, $4, $5 - %r = and i64 %a, %b ret i64 %r } @@ -146,9 +133,6 @@ ; MM32: lw $[[T3:[0-9]+]], 28($sp) ; MM32: and16 $[[T3]], $7 - ; MM64: and $2, $4, $6 - ; MM64: and $3, $5, $7 - %r = and i128 %a, %b ret i128 %r } @@ -221,8 +205,6 @@ ; MM32: andi16 $3, $5, 4 ; MM32: li16 $2, 0 - ; MM64: andi $2, $4, 4 - %r = and i64 4, %b ret i64 %r } @@ -244,9 +226,6 @@ ; MM32: li16 $3, 0 ; MM32: li16 $4, 0 - ; MM64: andi $3, $5, 4 - ; MM64: daddiu $2, $zero, 0 - %r = and i128 4, %b ret i128 %r } @@ -315,8 +294,6 @@ ; MM32: andi16 $3, $5, 31 ; MM32: li16 $2, 0 - ; MM64: andi $2, $4, 31 - %r = and i64 31, %b ret i64 %r } @@ -338,9 +315,6 @@ ; MM32: li16 $3, 0 ; MM32: li16 $4, 0 - ; MM64: andi $3, $5, 31 - ; MM64: daddiu $2, $zero, 0 - %r = and i128 31, %b ret i128 %r } @@ -405,8 +379,6 @@ ; MM32: andi16 $3, $5, 255 ; MM32: li16 $2, 0 - ; MM64: andi $2, $4, 255 - %r = and i64 255, %b ret i64 %r } @@ -428,9 +400,6 @@ ; MM32: li16 $3, 0 ; MM32: li16 $4, 0 - ; MM64: andi $3, $5, 255 - ; MM64: daddiu $2, $zero, 0 - %r = and i128 255, %b ret i128 %r } @@ -506,8 +475,6 @@ ; MM32: andi16 $3, $5, 32768 ; MM32: li16 $2, 0 - ; MM64: andi $2, $4, 32768 - %r = and i64 32768, %b ret i64 %r } @@ -529,9 +496,6 @@ ; MM32: li16 $3, 0 ; MM32: li16 $4, 0 - ; MM64: andi $3, $5, 32768 - ; MM64: daddiu $2, $zero, 0 - %r = and i128 32768, %b ret i128 %r } @@ -588,8 +552,6 @@ ; MM32-DAG: andi $3, $5, 65 ; MM32-DAG: li16 $2, 0 - ; MM64: andi $2, $4, 65 - %r = and i64 65, %b ret i64 %r } @@ -611,9 +573,6 @@ ; MM32-DAG: li16 $3, 0 ; MM32-DAG: li16 $4, 0 - ; MM64: andi $3, $5, 65 - ; MM64: daddiu $2, $zero, 0 - %r = and i128 65, %b ret i128 %r } @@ -678,8 +637,6 @@ ; MM32-DAG: andi $3, $5, 256 ; MM32-DAG: li16 $2, 0 - ; MM64: andi $2, $4, 256 - %r = and i64 256, %b ret i64 %r } @@ -701,9 +658,6 @@ ; MM32-DAG: li16 $3, 0 ; MM32-DAG: li16 $4, 0 - ; MM64: andi $3, $5, 256 - ; MM64: daddiu $2, $zero, 0 - %r = and i128 256, %b ret i128 %r } Index: test/CodeGen/Mips/llvm-ir/lh_lhu.ll =================================================================== --- test/CodeGen/Mips/llvm-ir/lh_lhu.ll +++ test/CodeGen/Mips/llvm-ir/lh_lhu.ll @@ -1,7 +1,6 @@ ; RUN: llc < %s -march=mips -mcpu=mips32r2 -mattr=+micromips -relocation-model=pic | FileCheck %s ; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s -; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -relocation-model=pic | FileCheck %s @us = global i16 0, align 2 Index: test/CodeGen/Mips/llvm-ir/mul.ll =================================================================== --- test/CodeGen/Mips/llvm-ir/mul.ll +++ test/CodeGen/Mips/llvm-ir/mul.ll @@ -26,8 +26,6 @@ ; RUN: FileCheck %s -check-prefixes=MM32,MM32R3 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | \ ; RUN: FileCheck %s -check-prefixes=MM32,MM32R6 -; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips -target-abi n64 -relocation-model=pic | \ -; RUN: FileCheck %s -check-prefix=MM64R6 define signext i1 @mul_i1(i1 signext %a, i1 signext %b) { entry: @@ -59,11 +57,6 @@ ; 64R6: andi $[[T0]], $[[T0]], 1 ; 64R6: negu $2, $[[T0]] - ; MM64R6: mul $[[T0:[0-9]+]], $4, $5 - ; MM64R6: andi16 $[[T0]], $[[T0]], 1 - ; MM64R6: li16 $[[T1:[0-9]+]], 0 - ; MM64R6: subu16 $2, $[[T1]], $[[T0]] - ; MM32: mul $[[T0:[0-9]+]], $4, $5 ; MM32: andi16 $[[T0]], $[[T0]], 1 ; MM32: li16 $[[T1:[0-9]+]], 0 @@ -107,9 +100,6 @@ ; 64R6: mul $[[T0:[0-9]+]], $4, $5 ; 64R6: seb $2, $[[T0]] - ; MM64R6: mul $[[T0:[0-9]+]], $4, $5 - ; MM64R6: seb $2, $[[T0]] - ; MM32: mul $[[T0:[0-9]+]], $4, $5 ; MM32: seb $2, $[[T0]] @@ -151,9 +141,6 @@ ; 64R6: mul $[[T0:[0-9]+]], $4, $5 ; 64R6: seh $2, $[[T0]] - ; MM64R6: mul $[[T0:[0-9]+]], $4, $5 - ; MM64R6: seh $2, $[[T0]] - ; MM32: mul $[[T0:[0-9]+]], $4, $5 ; MM32: seh $2, $[[T0]] @@ -173,7 +160,6 @@ ; 64R1-R5: mul $2, $4, $5 ; 64R6: mul $2, $4, $5 - ; MM64R6: mul $2, $4, $5 ; MM32: mul $2, $4, $5 @@ -217,7 +203,6 @@ ; 64R1-R5: mflo $2 ; 64R6: dmul $2, $4, $5 - ; MM64R6: dmul $2, $4, $5 ; MM32R3: multu $[[T0:[0-9]+]], $7 ; MM32R3: mflo $[[T1:[0-9]+]] @@ -261,13 +246,6 @@ ; 64R6: daddu $2, $[[T1]], $[[T0]] ; 64R6-DAG: dmul $3, $5, $7 - ; MM64R6-DAG: dmul $[[T1:[0-9]+]], $5, $6 - ; MM64R6: dmuhu $[[T2:[0-9]+]], $5, $7 - ; MM64R6: daddu $[[T3:[0-9]+]], $[[T2]], $[[T1]] - ; MM64R6-DAG: dmul $[[T0:[0-9]+]], $4, $7 - ; MM64R6: daddu $2, $[[T1]], $[[T0]] - ; MM64R6-DAG: dmul $3, $5, $7 - ; MM32: lw $25, %call16(__multi3)($16) %r = mul i128 %a, %b Index: test/CodeGen/Mips/llvm-ir/not.ll =================================================================== --- test/CodeGen/Mips/llvm-ir/not.ll +++ test/CodeGen/Mips/llvm-ir/not.ll @@ -26,8 +26,6 @@ ; RUN: -check-prefixes=ALL,MM,MM32 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ ; RUN: -check-prefixes=ALL,MM,MM32 -; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips | FileCheck %s \ -; RUN: -check-prefixes=ALL,MM,MM64 define signext i1 @not_i1(i1 signext %a) { entry: @@ -98,9 +96,6 @@ ; MM32: not16 $2, $4 ; MM32: not16 $3, $5 - ; MM64: daddiu $[[T0:[0-9]+]], $zero, -1 - ; MM64: xor $2, $4, $[[T0]] - %r = xor i64 %a, -1 ret i64 %r } @@ -123,10 +118,6 @@ ; MM32: not16 $4, $6 ; MM32: not16 $5, $7 - ; MM64: daddiu $[[T0:[0-9]+]], $zero, -1 - ; MM64: xor $2, $4, $[[T0]] - ; MM64: xor $3, $5, $[[T0]] - %r = xor i128 %a, -1 ret i128 %r } @@ -138,7 +129,6 @@ ; GP32: nor $2, $5, $4 ; GP64: or $1, $5, $4 ; MM32: nor $2, $5, $4 - ; MM64: or $1, $5, $4 %or = or i1 %b, %a %r = xor i1 %or, -1 @@ -152,7 +142,6 @@ ; GP32: nor $2, $5, $4 ; GP64: or $1, $5, $4 ; MM32: nor $2, $5, $4 - ; MM64: or $1, $5, $4 %or = or i8 %b, %a %r = xor i8 %or, -1 @@ -166,7 +155,6 @@ ; GP32: nor $2, $5, $4 ; GP64: or $1, $5, $4 ; MM32: nor $2, $5, $4 - ; MM64: or $1, $5, $4 %or = or i16 %b, %a %r = xor i16 %or, -1 @@ -185,10 +173,6 @@ ; MM32: nor $2, $5, $4 - ; MM64: or $[[T0:[0-9]+]], $5, $4 - ; MM64: sll $[[T1:[0-9]+]], $[[T0]], 0 - ; MM64: not16 $2, $[[T1]] - %or = or i32 %b, %a %r = xor i32 %or, -1 ret i32 %r @@ -207,8 +191,6 @@ ; MM32: nor $2, $6, $4 ; MM32: nor $3, $7, $5 - ; MM64: nor $2, $5, $4 - %or = or i64 %b, %a %r = xor i64 %or, -1 ret i64 %r @@ -239,9 +221,6 @@ ; MM32: lw $[[T3:[0-9]+]], 28($sp) ; MM32: nor $5, $[[T3]], $7 - ; MM64: nor $2, $6, $4 - ; MM64: nor $3, $7, $5 - %or = or i128 %b, %a %r = xor i128 %or, -1 ret i128 %r Index: test/CodeGen/Mips/llvm-ir/or.ll =================================================================== --- test/CodeGen/Mips/llvm-ir/or.ll +++ test/CodeGen/Mips/llvm-ir/or.ll @@ -15,8 +15,6 @@ ; RUN: -check-prefixes=ALL,MM,MM32 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ ; RUN: -check-prefixes=ALL,MM,MM32 -; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips | FileCheck %s \ -; RUN: -check-prefixes=ALL,MM,MM64 define signext i1 @or_i1(i1 signext %a, i1 signext %b) { entry: @@ -29,8 +27,6 @@ ; MM32: or16 $[[T0:[0-9]+]], $5 ; MM32 move $2, $[[T0]] - ; MM64: or $1, $4, $5 - %r = or i1 %a, %b ret i1 %r } @@ -46,8 +42,6 @@ ; MM32: or16 $[[T0:[0-9]+]], $5 ; MM32 move $2, $[[T0]] - ; MM64: or $1, $4, $5 - %r = or i8 %a, %b ret i8 %r } @@ -63,8 +57,6 @@ ; MM32: or16 $[[T0:[0-9]+]], $5 ; MM32 move $2, $[[T0]] - ; MM64: or $1, $4, $5 - %r = or i16 %a, %b ret i16 %r } @@ -82,9 +74,6 @@ ; MM32: or16 $[[T0:[0-9]+]], $5 ; MM32: move $2, $[[T0]] - ; MM64: or $[[T0:[0-9]+]], $4, $5 - ; MM64: sll $2, $[[T0]], 0 - %r = or i32 %a, %b ret i32 %r } @@ -103,8 +92,6 @@ ; MM32: move $2, $[[T0]] ; MM32: move $3, $[[T1]] - ; MM64: or $2, $4, $5 - %r = or i64 %a, %b ret i64 %r } @@ -134,9 +121,6 @@ ; MM32: lw $[[T3:[0-9]+]], 28($sp) ; MM32: or16 $[[T3]], $7 - ; MM64: or $2, $4, $6 - ; MM64: or $3, $5, $7 - %r = or i128 %a, %b ret i128 %r } @@ -193,8 +177,6 @@ ; MM32: ori $3, $5, 4 ; MM32: move $2, $4 - ; MM64: ori $2, $4, 4 - %r = or i64 4, %b ret i64 %r } @@ -218,9 +200,6 @@ ; MM32: move $4, $6 ; MM32: move $5, $[[T0]] - ; MM64: ori $3, $5, 4 - ; MM64: move $2, $4 - %r = or i128 4, %b ret i128 %r } @@ -281,8 +260,6 @@ ; MM32: ori $3, $5, 31 ; MM32: move $2, $4 - ; MM64: ori $2, $4, 31 - %r = or i64 31, %b ret i64 %r } @@ -306,9 +283,6 @@ ; MM32: move $4, $6 ; MM32: move $5, $[[T0]] - ; MM64: ori $3, $5, 31 - ; MM64: move $2, $4 - %r = or i128 31, %b ret i128 %r } @@ -373,8 +347,6 @@ ; MM32: ori $3, $5, 255 ; MM32: move $2, $4 - ; MM64: ori $2, $4, 255 - %r = or i64 255, %b ret i64 %r } @@ -398,9 +370,6 @@ ; MM32: move $4, $6 ; MM32: move $5, $[[T0]] - ; MM64: ori $3, $5, 255 - ; MM64: move $2, $4 - %r = or i128 255, %b ret i128 %r } @@ -464,8 +433,6 @@ ; MM32: ori $3, $5, 32768 ; MM32: move $2, $4 - ; MM64: ori $2, $4, 32768 - %r = or i64 32768, %b ret i64 %r } @@ -489,9 +456,6 @@ ; MM32: move $4, $6 ; MM32: move $5, $[[T0]] - ; MM64: ori $3, $5, 32768 - ; MM64: move $2, $4 - %r = or i128 32768, %b ret i128 %r } @@ -552,8 +516,6 @@ ; MM32: ori $3, $5, 65 ; MM32: move $2, $4 - ; MM64: ori $2, $4, 65 - %r = or i64 65, %b ret i64 %r } @@ -577,9 +539,6 @@ ; MM32: move $4, $6 ; MM32: move $5, $[[T0]] - ; MM64: ori $3, $5, 65 - ; MM64: move $2, $4 - %r = or i128 65, %b ret i128 %r } @@ -636,8 +595,6 @@ ; MM32: ori $3, $5, 256 ; MM32: move $2, $4 - ; MM64: ori $2, $4, 256 - %r = or i64 256, %b ret i64 %r } @@ -661,9 +618,6 @@ ; MM32: move $4, $6 ; MM32: move $5, $[[T0]] - ; MM64: ori $3, $5, 256 - ; MM64: move $2, $4 - %r = or i128 256, %b ret i128 %r } Index: test/CodeGen/Mips/llvm-ir/sdiv.ll =================================================================== --- test/CodeGen/Mips/llvm-ir/sdiv.ll +++ test/CodeGen/Mips/llvm-ir/sdiv.ll @@ -30,8 +30,6 @@ ; RUN: -check-prefixes=ALL,MMR3,MM32 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ ; RUN: -check-prefixes=ALL,MMR6,MM32 -; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips -target-abi n64 -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,MMR6,MM64 define signext i1 @sdiv_i1(i1 signext %a, i1 signext %b) { entry: @@ -174,9 +172,6 @@ ; MM32: lw $25, %call16(__divdi3)($2) - ; MM64: ddiv $2, $4, $5 - ; MM64: teq $5, $zero, 7 - %r = sdiv i64 %a, %b ret i64 %r } @@ -192,8 +187,6 @@ ; MM32: lw $25, %call16(__divti3)($16) - ; MM64: ld $25, %call16(__divti3)($2) - %r = sdiv i128 %a, %b ret i128 %r } Index: test/CodeGen/Mips/llvm-ir/srem.ll =================================================================== --- test/CodeGen/Mips/llvm-ir/srem.ll +++ test/CodeGen/Mips/llvm-ir/srem.ll @@ -30,8 +30,6 @@ ; RUN: -check-prefixes=ALL,MMR3,MM32 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ ; RUN: -check-prefixes=ALL,MMR6,MM32 -; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,MMR6,MM64 define signext i1 @srem_i1(i1 signext %a, i1 signext %b) { entry: @@ -166,9 +164,6 @@ ; MM32: lw $25, %call16(__moddi3)($2) - ; MM64: dmod $2, $4, $5 - ; MM64: teq $5, $zero, 7 - %r = srem i64 %a, %b ret i64 %r } @@ -184,8 +179,6 @@ ; MM32: lw $25, %call16(__modti3)($16) - ; MM64: ld $25, %call16(__modti3)($2) - %r = srem i128 %a, %b ret i128 %r } Index: test/CodeGen/Mips/llvm-ir/sub.ll =================================================================== --- test/CodeGen/Mips/llvm-ir/sub.ll +++ test/CodeGen/Mips/llvm-ir/sub.ll @@ -28,8 +28,6 @@ ; RUN: -check-prefixes=R2-R6,GP64,NOT-MM,GP64-R2 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ ; RUN: -check-prefixes=R2-R6,GP64,NOT-MM,GP64-R2 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \ -; RUN: -check-prefixes=GP64,MM64 define signext i1 @sub_i1(i1 signext %a, i1 signext %b) { entry: @@ -213,16 +211,6 @@ ; GP64-R2: dsubu $2, $1, $[[T1]] ; GP64-R2: dsubu $3, $5, $7 -; FIXME: Again, redundant sign extension. Also, microMIPSR6 has the -; dext instruction which should be used here. - -; MM64: dsubu $[[T0:[0-9]+]], $4, $6 -; MM64: sltu $[[T1:[0-9]+]], $5, $7 -; MM64: dsll $[[T2:[0-9]+]], $[[T1]], 32 -; MM64: dsrl $[[T3:[0-9]+]], $[[T2]], 32 -; MM64: dsubu $2, $[[T0]], $[[T3]] -; MM64: dsubu $3, $5, $7 - %r = sub i128 %a, %b ret i128 %r } Index: test/CodeGen/Mips/llvm-ir/udiv.ll =================================================================== --- test/CodeGen/Mips/llvm-ir/udiv.ll +++ test/CodeGen/Mips/llvm-ir/udiv.ll @@ -30,8 +30,6 @@ ; RUN: -check-prefixes=ALL,MMR3,MM32 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ ; RUN: -check-prefixes=ALL,MMR6,MM32 -; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,MMR6,MM64 define zeroext i1 @udiv_i1(i1 zeroext %a, i1 zeroext %b) { entry: @@ -136,9 +134,6 @@ ; MM32: lw $25, %call16(__udivdi3)($2) - ; MM64: ddivu $2, $4, $5 - ; MM64: teq $5, $zero, 7 - %r = udiv i64 %a, %b ret i64 %r } @@ -154,8 +149,6 @@ ; MM32: lw $25, %call16(__udivti3)($16) - ; MM64: ld $25, %call16(__udivti3)($2) - %r = udiv i128 %a, %b ret i128 %r } Index: test/CodeGen/Mips/llvm-ir/urem.ll =================================================================== --- test/CodeGen/Mips/llvm-ir/urem.ll +++ test/CodeGen/Mips/llvm-ir/urem.ll @@ -30,8 +30,6 @@ ; RUN: -check-prefixes=ALL,MMR3,MM32 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ ; RUN: -check-prefixes=ALL,MMR6,MM32 -; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -relocation-model=pic | FileCheck %s \ -; RUN: -check-prefixes=ALL,MMR6,MM64 define signext i1 @urem_i1(i1 signext %a, i1 signext %b) { entry: @@ -192,9 +190,6 @@ ; MM32: lw $25, %call16(__umoddi3)($2) - ; MM64: dmodu $2, $4, $5 - ; MM64: teq $5, $zero, 7 - %r = urem i64 %a, %b ret i64 %r } @@ -210,8 +205,6 @@ ; MM32: lw $25, %call16(__umodti3)($16) - ; MM64: ld $25, %call16(__umodti3)($2) - %r = urem i128 %a, %b ret i128 %r } Index: test/CodeGen/Mips/llvm-ir/xor.ll =================================================================== --- test/CodeGen/Mips/llvm-ir/xor.ll +++ test/CodeGen/Mips/llvm-ir/xor.ll @@ -26,8 +26,6 @@ ; RUN: -check-prefixes=ALL,MM,MM32 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ ; RUN: -check-prefixes=ALL,MM,MM32 -; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips | FileCheck %s \ -; RUN: -check-prefixes=ALL,MM,MM64 define signext i1 @xor_i1(i1 signext %a, i1 signext %b) { entry: @@ -40,8 +38,6 @@ ; MM32: xor16 $[[T0:[0-9]+]], $5 ; MM32: move $2, $[[T0]] - ; MM64: xor $1, $4, $5 - %r = xor i1 %a, %b ret i1 %r } @@ -57,8 +53,6 @@ ; MM32: xor16 $[[T0:[0-9]+]], $5 ; MM32: move $2, $[[T0]] - ; MM64: xor $1, $4, $5 - %r = xor i8 %a, %b ret i8 %r } @@ -74,8 +68,6 @@ ; MM32: xor16 $[[T0:[0-9]+]], $5 ; MM32: move $2, $[[T0]] - ; MM64: xor $1, $4, $5 - %r = xor i16 %a, %b ret i16 %r } @@ -92,9 +84,6 @@ ; MM32: xor16 $[[T0:[0-9]+]], $5 ; MM32: move $2, $[[T0]] - ; MM64: xor $[[T0:[0-9]+]], $4, $5 - ; MM64: sll $2, $[[T0]], 0 - %r = xor i32 %a, %b ret i32 %r } @@ -113,8 +102,6 @@ ; MM32: move $2, $[[T0]] ; MM32: move $3, $[[T1]] - ; MM64: xor $2, $4, $5 - %r = xor i64 %a, %b ret i64 %r } @@ -144,9 +131,6 @@ ; MM32: lw $[[T3:[0-9]+]], 28($sp) ; MM32: xor16 $[[T3]], $7 - ; MM64: xor $2, $4, $6 - ; MM64: xor $3, $5, $7 - %r = xor i128 %a, %b ret i128 %r } @@ -203,8 +187,6 @@ ; MM32: xori $3, $5, 4 ; MM32: move $2, $4 - ; MM64: xori $2, $4, 4 - %r = xor i64 4, %b ret i64 %r } @@ -228,9 +210,6 @@ ; MM32: move $4, $6 ; MM32: move $5, $[[T0]] - ; MM64: xori $3, $5, 4 - ; MM64: move $2, $4 - %r = xor i128 4, %b ret i128 %r } Index: test/CodeGen/Mips/lw16-base-reg.ll =================================================================== --- test/CodeGen/Mips/lw16-base-reg.ll +++ test/CodeGen/Mips/lw16-base-reg.ll @@ -1,7 +1,5 @@ ; RUN: llc %s -march=mips -mcpu=mips32r3 -mattr=micromips -filetype=asm \ ; RUN: -relocation-model=pic -O3 -o - | FileCheck %s -; RUN: llc %s -march=mips64 -mcpu=mips64r6 -mattr=micromips -filetype=asm \ -; RUN: -relocation-model=pic -O3 -o - | FileCheck %s ; The purpose of this test is to check whether the CodeGen selects ; LW16 instruction with the base register in a range of $2-$7, $16, $17. Index: test/CodeGen/Mips/micromips-lwc1-swc1.ll =================================================================== --- test/CodeGen/Mips/micromips-lwc1-swc1.ll +++ test/CodeGen/Mips/micromips-lwc1-swc1.ll @@ -4,9 +4,6 @@ ; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips \ ; RUN: -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefixes=ALL,MM32 -; RUN: llc -march=mips -mcpu=mips64r6 -mattr=+micromips -target-abi n64 \ -; RUN: -relocation-model=pic < %s | \ -; RUN: FileCheck %s -check-prefixes=ALL,MM64 @gf0 = external global float @@ -19,12 +16,6 @@ ; MM32: lw $[[R3:[0-9]+]], %got(gf0)($[[R2]]) ; MM32: lwc1 $f0, 0($[[R3]]) -; MM64: lui $[[R0:[0-9]+]], %hi(%neg(%gp_rel(test_lwc1))) -; MM64: daddu $[[R1:[0-9]+]], $[[R0]], $25 -; MM64: daddiu $[[R2:[0-9]+]], $[[R1]], %lo(%neg(%gp_rel(test_lwc1))) -; MM64: ld $[[R3:[0-9]+]], %got_disp(gf0)($[[R2]]) -; MM64: lwc1 $f0, 0($[[R3]]) - %0 = load float, float* @gf0, align 4 ret float %0 } @@ -38,12 +29,6 @@ ; MM32: lw $[[R3:[0-9]+]], %got(gf0)($[[R2]]) ; MM32: swc1 $f12, 0($[[R3]]) -; MM64: lui $[[R0:[0-9]+]], %hi(%neg(%gp_rel(test_swc1))) -; MM64: daddu $[[R1:[0-9]+]], $[[R0]], $25 -; MM64: daddiu $[[R2:[0-9]+]], $[[R1]], %lo(%neg(%gp_rel(test_swc1))) -; MM64: ld $[[R3:[0-9]+]], %got_disp(gf0)($[[R2]]) -; MM64: swc1 $f12, 0($[[R3]]) - store float %a, float* @gf0, align 4 ret void } Index: test/CodeGen/Mips/mips64fpldst.ll =================================================================== --- test/CodeGen/Mips/mips64fpldst.ll +++ test/CodeGen/Mips/mips64fpldst.ll @@ -2,8 +2,6 @@ ; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32 ; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64 ; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32 -; RUN: llc < %s -march=mipsel -mcpu=mips64r6 -mattr=+micromips -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32 -; RUN: llc < %s -march=mipsel -mcpu=mips64r6 -mattr=+micromips -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64 @f0 = common global float 0.000000e+00, align 4 @d0 = common global double 0.000000e+00, align 8 Index: test/CodeGen/Mips/mips64shift.ll =================================================================== --- test/CodeGen/Mips/mips64shift.ll +++ test/CodeGen/Mips/mips64shift.ll @@ -1,5 +1,4 @@ ; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck -check-prefixes=ALL,MIPS %s -; RUN: llc -march=mips64el -mcpu=mips64r6 -mattr=micromips < %s | FileCheck -check-prefixes=ALL,MICROMIPS %s define i64 @f0(i64 %a0, i64 %a1) nounwind readnone { entry: Index: test/CodeGen/Mips/tailcall/tailcall.ll =================================================================== --- test/CodeGen/Mips/tailcall/tailcall.ll +++ test/CodeGen/Mips/tailcall/tailcall.ll @@ -28,10 +28,6 @@ ; RUN: -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,PIC32MM ; RUN: llc -march=mipsel -relocation-model=static -mcpu=mips32r6 \ ; RUN: -mattr=+micromips -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,STATIC32MMR6 -; RUN: llc -march=mips64el -relocation-model=pic -mcpu=mips64r6 \ -; RUN: -mattr=+micromips -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=PIC64R6MM -; RUN: llc -march=mips64el -relocation-model=static -mcpu=mips64r6 \ -; RUN: -mattr=+micromips -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=STATIC64 @g0 = common global i32 0, align 4 @g1 = common global i32 0, align 4 @@ -169,7 +165,6 @@ ; STATIC32MMR6: bc ; PIC64: jr $25 ; PIC64R6: jrc $25 -; PIC64R6MM: jrc $25 ; STATIC64: j ; PIC16: jalrc Index: test/MC/Mips/mips64extins.s =================================================================== --- test/MC/Mips/mips64extins.s +++ test/MC/Mips/mips64extins.s @@ -1,13 +1,8 @@ # RUN: llvm-mc -arch=mips64el -filetype=obj -mcpu=mips64r2 -target-abi=n64 %s -o - \ # RUN: | llvm-objdump -disassemble - | FileCheck --check-prefix=OBJ %s -# RUN: llvm-mc -arch=mips64el -filetype=obj -mcpu=mips64r6 -mattr=+micromips \ -# RUN: -target-abi=n64 %s -o - | llvm-objdump -disassemble - \ -# RUN: | FileCheck --check-prefix=OBJ %s # RUN: llvm-mc -arch=mips64el -mcpu=mips64r2 -target-abi=n64 %s -o - \ # RUN: | FileCheck --check-prefix=ASM %s -# RUN: llvm-mc -arch=mips64el -mcpu=mips64r6 -mattr=+micromips -target-abi=n64 \ -# RUN: %s -o - | FileCheck --check-prefix=ASM %s dext $2, $4, 5, 10 # OBJ: dext ${{[0-9]+}}, ${{[0-9]+}}, 5, 10 dextu $2, $4, 34, 6 # OBJ: dext ${{[0-9]+}}, ${{[0-9]+}}, 34, 6