Index: test/CodeGen/Mips/cannot-copy-registers.ll
===================================================================
--- test/CodeGen/Mips/cannot-copy-registers.ll
+++ /dev/null
@@ -1,24 +0,0 @@
-; RUN: llc -march=mips64 -mcpu=mips64r6 -mattr=+micromips \
-; RUN:   -relocation-model=pic -O3 < %s
-
-; Check that message "Cannot copy registers" is not asserted in case of microMIPS64r6.
-
-@x = global i32 65504, align 4
-@y = global i32 60929, align 4
-@.str = private unnamed_addr constant [7 x i8] c"%08x \0A\00", align 1
-
-define i32 @main() nounwind {
-entry:
-  %0 = load i32, i32* @x, align 4
-  %and1 = and i32 %0, 4
-  %call1 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds
-                                  ([7 x i8], [7 x i8]* @.str, i32 0, i32 0), i32 %and1)
-
-  %1 = load i32, i32* @y, align 4
-  %and2 = and i32 %1, 5
-  %call2 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds
-                                  ([7 x i8], [7 x i8]* @.str, i32 0, i32 0), i32 %and2)
-  ret i32 0
-}
-
-declare i32 @printf(i8*, ...)
Index: CodeGen/Mips/countleading.ll
===================================================================
--- CodeGen/Mips/countleading.ll
+++ CodeGen/Mips/countleading.ll
@@ -5,7 +5,6 @@
 ; RUN: llc -march=mips64el -mcpu=mips64   < %s | FileCheck -check-prefixes=ALL,MIPS64-GT-R1 %s
 ; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck -check-prefixes=ALL,MIPS64-GT-R1 %s
 ; RUN: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck -check-prefixes=ALL,MIPS64-GT-R1 %s
-; RUN: llc -march=mips64el -mcpu=mips64r6 -mattr=micromips < %s | FileCheck -check-prefixes=ALL,MICROMIPS64 %s
 
 ; Prefixes:
 ;   ALL      - All
@@ -22,8 +21,6 @@
 
 ; MIPS64-GT-R1:  clz $2, $4
 
-; MICROMIPS64:   clz $2, $4
-
   %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %X, i1 true)
   ret i32 %tmp1
 }
@@ -40,8 +37,6 @@
 
 ; MIPS64-GT-R1:  clo $2, $4
 
-; MICROMIPS64:   clo $2, $4
-
   %neg = xor i32 %X, -1
   %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %neg, i1 true)
   ret i32 %tmp1
@@ -63,7 +58,6 @@
 ; MIPS32-GT-R1-DAG: addiu $3, $zero, 0
 
 ; MIPS64-GT-R1:  dclz $2, $4
-; MICROMIPS64:   dclz $2, $4
 
   %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true)
   ret i64 %tmp1
@@ -89,7 +83,6 @@
 ; MIPS32-GT-R1-DAG: addiu $3, $zero, 0
 
 ; MIPS64-GT-R1:  dclo $2, $4
-; MICROMIPS64:   dclo $2, $4
 
   %neg = xor i64 %X, -1
   %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true)
Index: CodeGen/Mips/fcmp.ll
===================================================================
--- CodeGen/Mips/fcmp.ll
+++ CodeGen/Mips/fcmp.ll
@@ -16,8 +16,6 @@
 ; RUN:    -check-prefixes=ALL,MM,MM32R3
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,MM,MMR6,MM32R6
-; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \
-; RUN:    -check-prefixes=ALL,MM,MMR6,MM64R6
 
 define i32 @false_f32(float %a, float %b) nounwind {
 ; ALL-LABEL: false_f32:
@@ -61,7 +59,6 @@
 ; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG:    cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      andi16 $2, $[[T1]], 1
 
@@ -95,7 +92,6 @@
 ; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.lt.s $[[T0:f[0-9]+]], $f14, $f12
-; MM64R6-DAG:    cmp.lt.s $[[T0:f[0-9]+]], $f13, $f12
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      andi16 $2, $[[T1]], 1
 
@@ -129,7 +125,6 @@
 ; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.le.s $[[T0:f[0-9]+]], $f14, $f12
-; MM64R6-DAG:    cmp.le.s $[[T0:f[0-9]+]], $f13, $f12
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      andi16 $2, $[[T1]], 1
 
@@ -163,7 +158,6 @@
 ; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.lt.s $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG:    cmp.lt.s $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      andi16 $2, $[[T1]], 1
 
@@ -197,7 +191,6 @@
 ; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.le.s $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG:    cmp.le.s $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      andi16 $2, $[[T1]], 1
 
@@ -233,7 +226,6 @@
 ; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG:    cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      not $[[T2:[0-9]+]], $[[T1]]
 ; MMR6-DAG:      andi16 $2, $[[T2]], 1
@@ -270,7 +262,6 @@
 ; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG:    cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      not $[[T2:[0-9]+]], $[[T1]]
 ; MMR6-DAG:      andi16 $2, $[[T2]], 1
@@ -305,7 +296,6 @@
 ; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG:    cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      andi16 $2, $[[T1]], 1
 
@@ -339,7 +329,6 @@
 ; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.ult.s $[[T0:f[0-9]+]], $f14, $f12
-; MM64R6-DAG:    cmp.ult.s $[[T0:f[0-9]+]], $f13, $f12
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      andi16 $2, $[[T1]], 1
 
@@ -373,7 +362,6 @@
 ; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.ule.s $[[T0:f[0-9]+]], $f14, $f12
-; MM64R6-DAG:    cmp.ule.s $[[T0:f[0-9]+]], $f13, $f12
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      andi16 $2, $[[T1]], 1
 
@@ -407,7 +395,6 @@
 ; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.ult.s $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG:    cmp.ult.s $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      andi16 $2, $[[T1]], 1
 
@@ -441,7 +428,6 @@
 ; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.ule.s $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG:    cmp.ule.s $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      andi16 $2, $[[T1]], 1
 
@@ -477,7 +463,6 @@
 ; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG:    cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      not $[[T2:[0-9]+]], $[[T1]]
 ; MMR6-DAG:      andi16 $2, $[[T2]], 1
@@ -512,7 +497,6 @@
 ; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG:    cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      andi16 $2, $[[T1]], 1
 
@@ -580,7 +564,6 @@
 ; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG:    cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      andi16 $2, $[[T1]], 1
 
@@ -614,7 +597,6 @@
 ; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.lt.d $[[T0:f[0-9]+]], $f14, $f12
-; MM64R6-DAG:    cmp.lt.d $[[T0:f[0-9]+]], $f13, $f12
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      andi16 $2, $[[T1]], 1
 
@@ -648,7 +630,6 @@
 ; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.le.d $[[T0:f[0-9]+]], $f14, $f12
-; MM64R6-DAG:    cmp.le.d $[[T0:f[0-9]+]], $f13, $f12
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      andi16 $2, $[[T1]], 1
 
@@ -682,7 +663,6 @@
 ; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.lt.d $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG:    cmp.lt.d $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      andi16 $2, $[[T1]], 1
 
@@ -716,7 +696,6 @@
 ; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.le.d $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG:    cmp.le.d $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      andi16 $2, $[[T1]], 1
 
@@ -752,7 +731,6 @@
 ; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG:    cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      not $[[T2:[0-9]+]], $[[T1]]
 ; MMR6-DAG:      andi16 $2, $[[T2]], 1
@@ -789,7 +767,6 @@
 ; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG:    cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      not $[[T2:[0-9]+]], $[[T1]]
 ; MMR6-DAG:      andi16 $2, $[[T2]], 1
@@ -824,7 +801,6 @@
 ; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG:    cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      andi16 $2, $[[T1]], 1
 
@@ -858,7 +834,6 @@
 ; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.ult.d $[[T0:f[0-9]+]], $f14, $f12
-; MM64R6-DAG:    cmp.ult.d $[[T0:f[0-9]+]], $f13, $f12
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      andi16 $2, $[[T1]], 1
 
@@ -892,7 +867,6 @@
 ; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.ule.d $[[T0:f[0-9]+]], $f14, $f12
-; MM64R6-DAG:    cmp.ule.d $[[T0:f[0-9]+]], $f13, $f12
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      andi16 $2, $[[T1]], 1
 
@@ -926,7 +900,6 @@
 ; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.ult.d $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG:    cmp.ult.d $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      andi16 $2, $[[T1]], 1
 
@@ -960,7 +933,6 @@
 ; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.ule.d $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG:    cmp.ule.d $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      andi16 $2, $[[T1]], 1
 
@@ -996,7 +968,6 @@
 ; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG:    cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      not $[[T2:[0-9]+]], $[[T1]]
 ; MMR6-DAG:      andi16 $2, $[[T2]], 1
@@ -1031,7 +1002,6 @@
 ; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
 
 ; MM32R6-DAG:    cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
-; MM64R6-DAG:    cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
 ; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
 ; MMR6-DAG:      andi16 $2, $[[T1]], 1
 
@@ -1102,18 +1072,6 @@
 ; MM32R6-DAG:    andi16   $[[T5:[0-9]+]], $[[T4]], 1
 ; MM32R6-DAG:    bnez     $[[T5]],
 
-; MM64R6-DAG:    add.s    $[[T0:f[0-9]+]], $f13, $f12
-; MM64R6-DAG:    lui      $[[T1:[0-9]+]], %highest(.LCPI32_0)
-; MM64R6-DAG:    daddiu   $[[T2:[0-9]+]], $[[T1]], %higher(.LCPI32_0)
-; MM64R6-DAG:    dsll     $[[T3:[0-9]+]], $[[T2]], 16
-; MM64R6-DAG:    daddiu   $[[T4:[0-9]+]], $[[T3]], %hi(.LCPI32_0)
-; MM64R6-DAG:    dsll     $[[T5:[0-9]+]], $[[T4]], 16
-; MM64R6-DAG:    lwc1     $[[T6:f[0-9]+]], %lo(.LCPI32_0)($[[T5]])
-; MM64R6-DAG:    cmp.le.s $[[T7:f[0-9]+]], $[[T0]], $[[T6]]
-; MM64R6-DAG:    mfc1     $[[T8:[0-9]+]], $[[T7]]
-; MM64R6-DAG:    andi16   $[[T9:[0-9]+]], $[[T8]], 1
-; MM64R6-DAG:    bnez     $[[T9]],
-
   %add = fadd fast float %at, %angle
   %cmp = fcmp ogt float %add, 1.000000e+00
   br i1 %cmp, label %if.then, label %if.end
@@ -1172,18 +1130,6 @@
 ; MM32R6-DAG:    andi16   $[[T5:[0-9]+]], $[[T4]], 1
 ; MM32R6-DAG:    bnez     $[[T5]],
 
-; MM64R6-DAG:    add.d    $[[T0:f[0-9]+]], $f13, $f12
-; MM64R6-DAG:    lui      $[[T1:[0-9]+]], %highest(.LCPI33_0)
-; MM64R6-DAG:    daddiu   $[[T2:[0-9]+]], $[[T1]], %higher(.LCPI33_0)
-; MM64R6-DAG:    dsll     $[[T3:[0-9]+]], $[[T2]], 16
-; MM64R6-DAG:    daddiu   $[[T4:[0-9]+]], $[[T3]], %hi(.LCPI33_0)
-; MM64R6-DAG:    dsll     $[[T5:[0-9]+]], $[[T4]], 16
-; MM64R6-DAG:    ldc1     $[[T6:f[0-9]+]], %lo(.LCPI33_0)($[[T5]])
-; MM64R6-DAG:    cmp.le.d $[[T7:f[0-9]+]], $[[T0]], $[[T6]]
-; MM64R6-DAG:    mfc1     $[[T8:[0-9]+]], $[[T7]]
-; MM64R6-DAG:    andi16   $[[T9:[0-9]+]], $[[T8]], 1
-; MM64R6-DAG:    bnez     $[[T9]],
-
   %add = fadd fast double %at, %angle
   %cmp = fcmp ogt double %add, 1.000000e+00
   br i1 %cmp, label %if.then, label %if.end
Index: CodeGen/Mips/llvm-ir/add.ll
===================================================================
--- CodeGen/Mips/llvm-ir/add.ll
+++ CodeGen/Mips/llvm-ir/add.ll
@@ -28,8 +28,6 @@
 ; RUN:    -check-prefixes=ALL,MMR3,MM32
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -O2 | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,MMR6,MM32
-; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -O2 | FileCheck %s \
-; RUN:    -check-prefixes=ALL,MM64
 
 
 ; FIXME: This code sequence is inefficient as it should be 'subu $[[T0]], $zero, $[[T0]'. 
@@ -122,8 +120,6 @@
   ; MM32:       sltu    $[[T1:[0-9]+]], $3, $5
   ; MM32:       addu16  $2, $[[T0]], $[[T1]]
 
-  ; MM64:       daddu   $2, $4, $5
-
   %r = add i64 %a, %b
   ret i64 %r
 }
@@ -228,13 +224,6 @@
   ; MMR6:        addu16    $2, $[[T16]], $[[T20]]
   ; MMR6:        addu16    $2, $[[T20]], $[[T21]]
 
-  ; MM64:       daddu     $[[T0:[0-9]+]], $4, $6
-  ; MM64:       daddu     $3, $5, $7
-  ; MM64:       sltu      $[[T1:[0-9]+]], $3, $5
-  ; MM64:       dsll      $[[T2:[0-9]+]], $[[T1]], 32
-  ; MM64:       dsrl      $[[T3:[0-9]+]], $[[T2]], 32
-  ; MM64:       daddu     $2, $[[T0]], $[[T3]]
-
   %r = add i128 %a, %b
   ret i128 %r
 }
@@ -262,9 +251,6 @@
   ; MM32:       addiur2 $[[T0:[0-9]+]], $4, 4
   ; MM32:       seb     $2, $[[T0]]
 
-  ; MM64:       addiur2 $[[T0:[0-9]+]], $4, 4
-  ; MM64:       seb     $2, $[[T0]]
-
   %r = add i8 4, %a
   ret i8 %r
 }
@@ -283,9 +269,6 @@
   ; MM32:       addiur2 $[[T0:[0-9]+]], $4, 4
   ; MM32:       seh     $2, $[[T0]]
 
-  ; MM64:       addiur2 $[[T0:[0-9]+]], $4, 4
-  ; MM64:       seh     $2, $[[T0]]
-
   %r = add i16 4, %a
   ret i16 %r
 }
@@ -299,8 +282,6 @@
 
   ; MM32:       addiur2 $2, $4, 4
 
-  ; MM64:       addiur2 $2, $4, 4
-
   %r = add i32 4, %a
   ret i32 %r
 }
@@ -319,8 +300,6 @@
   ; GP64:       daddiu  $2, $4, 4
 
 
-  ; MM64:       daddiu  $2, $4, 4
-
   %r = add i64 4, %a
   ret i64 %r
 }
@@ -384,12 +363,6 @@
   ; MMR6: move    $4, $7
   ; MMR6: move    $5, $[[T1]]
 
-  ; MM64:       daddiu  $[[T0:[0-9]+]], $5, 4
-  ; MM64:       sltu    $[[T1:[0-9]+]], $[[T0]], $5
-  ; MM64:       dsll    $[[T2:[0-9]+]], $[[T1]], 32
-  ; MM64:       dsrl    $[[T3:[0-9]+]], $[[T2]], 32
-  ; MM64:       daddu   $2, $4, $[[T3]]
-
   %r = add i128 4, %a
   ret i128 %r
 }
@@ -477,8 +450,6 @@
   ; MM32:       sltu    $[[T2:[0-9]+]], $[[T1]], $5
   ; MM32:       addu16  $2, $4, $[[T2]]
 
-  ; MM64:       daddiu  $2, $4, 3
-
   %r = add i64 3, %a
   ret i64 %r
 }
@@ -545,12 +516,6 @@
   ; MMR6: move    $4, $[[T5]]
   ; MMR6: move    $5, $[[T1]]
 
-  ; MM64:       daddiu  $[[T0:[0-9]+]], $5, 3
-  ; MM64:       sltu    $[[T1:[0-9]+]], $[[T0]], $5
-  ; MM64:       dsll    $[[T2:[0-9]+]], $[[T1]], 32
-  ; MM64:       dsrl    $[[T3:[0-9]+]], $[[T2]], 32
-  ; MM64:       daddu   $2, $4, $[[T3]]
-
   %r = add i128 3, %a
   ret i128 %r
 }
Index: CodeGen/Mips/llvm-ir/and.ll
===================================================================
--- CodeGen/Mips/llvm-ir/and.ll
+++ CodeGen/Mips/llvm-ir/and.ll
@@ -28,8 +28,6 @@
 ; RUN:    -check-prefixes=ALL,MM,MM32
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,MM,MM32
-; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips | FileCheck %s \
-; RUN:    -check-prefixes=ALL,MM,MM64
 
 define signext i1 @and_i1(i1 signext %a, i1 signext %b) {
 entry:
@@ -88,9 +86,6 @@
   ; MM32:         and16   $[[T0:[0-9]+]], $5
   ; MM32:         move    $2, $[[T0]]
 
-  ; MM64:         and     $[[T0:[0-9]+]], $4, $5
-  ; MM64:         sll     $2, $[[T0]], 0
-
   %r = and i32 %a, %b
   ret i32 %r
 }
@@ -109,8 +104,6 @@
   ; MM32:         move    $2, $[[T0]]
   ; MM32:         move    $3, $[[T1]]
 
-  ; MM64:         and     $2, $4, $5
-
   %r = and i64 %a, %b
   ret i64 %r
 }
@@ -140,9 +133,6 @@
   ; MM32:         lw      $[[T3:[0-9]+]], 28($sp)
   ; MM32:         and16   $[[T3]], $7
 
-  ; MM64:         and     $2, $4, $6
-  ; MM64:         and     $3, $5, $7
-
   %r = and i128 %a, %b
   ret i128 %r
 }
@@ -215,8 +205,6 @@
   ; MM32:         andi16  $3, $5, 4
   ; MM32:         li16     $2, 0
 
-  ; MM64:         andi    $2, $4, 4
-
   %r = and i64 4, %b
   ret i64 %r
 }
@@ -238,9 +226,6 @@
   ; MM32:         li16    $3, 0
   ; MM32:         li16    $4, 0
 
-  ; MM64:         andi    $3, $5, 4
-  ; MM64:         daddiu  $2, $zero, 0
-
   %r = and i128 4, %b
   ret i128 %r
 }
@@ -309,8 +294,6 @@
   ; MM32:         andi16  $3, $5, 31
   ; MM32:         li16    $2, 0
 
-  ; MM64:         andi    $2, $4, 31
-
   %r = and i64 31, %b
   ret i64 %r
 }
@@ -332,9 +315,6 @@
   ; MM32:         li16    $3, 0
   ; MM32:         li16    $4, 0
 
-  ; MM64:         andi    $3, $5, 31
-  ; MM64:         daddiu  $2, $zero, 0
-
   %r = and i128 31, %b
   ret i128 %r
 }
@@ -399,8 +379,6 @@
   ; MM32:         andi16  $3, $5, 255
   ; MM32:         li16    $2, 0
 
-  ; MM64:         andi    $2, $4, 255
-
   %r = and i64 255, %b
   ret i64 %r
 }
@@ -422,9 +400,6 @@
   ; MM32:         li16    $3, 0
   ; MM32:         li16    $4, 0
 
-  ; MM64:         andi    $3, $5, 255
-  ; MM64:         daddiu  $2, $zero, 0
-
   %r = and i128 255, %b
   ret i128 %r
 }
@@ -500,8 +475,6 @@
   ; MM32:         andi16  $3, $5, 32768
   ; MM32:         li16    $2, 0
 
-  ; MM64:         andi    $2, $4, 32768
-
   %r = and i64 32768, %b
   ret i64 %r
 }
@@ -523,9 +496,6 @@
   ; MM32:         li16    $3, 0
   ; MM32:         li16    $4, 0
 
-  ; MM64:         andi    $3, $5, 32768
-  ; MM64:         daddiu  $2, $zero, 0
-
   %r = and i128 32768, %b
   ret i128 %r
 }
@@ -582,8 +552,6 @@
   ; MM32-DAG:     andi    $3, $5, 65
   ; MM32-DAG:     li16    $2, 0
 
-  ; MM64:         andi    $2, $4, 65
-
   %r = and i64 65, %b
   ret i64 %r
 }
@@ -605,9 +573,6 @@
   ; MM32-DAG:     li16    $3, 0
   ; MM32-DAG:     li16    $4, 0
 
-  ; MM64:         andi    $3, $5, 65
-  ; MM64:         daddiu  $2, $zero, 0
-
   %r = and i128 65, %b
   ret i128 %r
 }
@@ -672,8 +637,6 @@
   ; MM32-DAG:     andi    $3, $5, 256
   ; MM32-DAG:     li16    $2, 0
 
-  ; MM64:         andi    $2, $4, 256
-
   %r = and i64 256, %b
   ret i64 %r
 }
@@ -695,9 +658,6 @@
   ; MM32-DAG:     li16    $3, 0
   ; MM32-DAG:     li16    $4, 0
 
-  ; MM64:         andi    $3, $5, 256
-  ; MM64:         daddiu  $2, $zero, 0
-
   %r = and i128 256, %b
   ret i128 %r
 }
Index: CodeGen/Mips/llvm-ir/lh_lhu.ll
===================================================================
--- CodeGen/Mips/llvm-ir/lh_lhu.ll
+++ CodeGen/Mips/llvm-ir/lh_lhu.ll
@@ -1,7 +1,6 @@
 ; RUN: llc < %s -march=mips -mcpu=mips32r2 -mattr=+micromips -relocation-model=pic | FileCheck %s
 ; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s
-; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -relocation-model=pic | FileCheck %s
 
 @us = global i16 0, align 2
 
Index: CodeGen/Mips/llvm-ir/mul.ll
===================================================================
--- CodeGen/Mips/llvm-ir/mul.ll
+++ CodeGen/Mips/llvm-ir/mul.ll
@@ -26,8 +26,6 @@
 ; RUN:   FileCheck %s -check-prefixes=MM32,MM32R3
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | \
 ; RUN:   FileCheck %s -check-prefixes=MM32,MM32R6
-; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips -target-abi n64 -relocation-model=pic | \
-; RUN:   FileCheck %s -check-prefix=MM64R6
 
 define signext i1 @mul_i1(i1 signext %a, i1 signext %b) {
 entry:
@@ -59,11 +57,6 @@
   ; 64R6:       andi    $[[T0]], $[[T0]], 1
   ; 64R6:       negu    $2, $[[T0]]
 
-  ; MM64R6:     mul     $[[T0:[0-9]+]], $4, $5
-  ; MM64R6:     andi16  $[[T0]], $[[T0]], 1
-  ; MM64R6:     li16    $[[T1:[0-9]+]], 0
-  ; MM64R6:     subu16  $2, $[[T1]], $[[T0]]
-
   ; MM32:       mul     $[[T0:[0-9]+]], $4, $5
   ; MM32:       andi16  $[[T0]], $[[T0]], 1
   ; MM32:       li16    $[[T1:[0-9]+]], 0
@@ -107,9 +100,6 @@
   ; 64R6:       mul     $[[T0:[0-9]+]], $4, $5
   ; 64R6:       seb     $2, $[[T0]]
 
-  ; MM64R6:     mul     $[[T0:[0-9]+]], $4, $5
-  ; MM64R6:     seb     $2, $[[T0]]
-
   ; MM32:       mul     $[[T0:[0-9]+]], $4, $5
   ; MM32:       seb     $2, $[[T0]]
 
@@ -151,9 +141,6 @@
   ; 64R6:       mul     $[[T0:[0-9]+]], $4, $5
   ; 64R6:       seh     $2, $[[T0]]
 
-  ; MM64R6:     mul     $[[T0:[0-9]+]], $4, $5
-  ; MM64R6:     seh     $2, $[[T0]]
-
   ; MM32:       mul     $[[T0:[0-9]+]], $4, $5
   ; MM32:       seh     $2, $[[T0]]
 
@@ -173,7 +160,6 @@
 
   ; 64R1-R5:    mul     $2, $4, $5
   ; 64R6:       mul     $2, $4, $5
-  ; MM64R6:     mul     $2, $4, $5
 
   ; MM32:       mul     $2, $4, $5
 
@@ -217,7 +203,6 @@
   ; 64R1-R5:    mflo    $2
 
   ; 64R6:       dmul    $2, $4, $5
-  ; MM64R6:     dmul    $2, $4, $5
 
   ; MM32R3:     multu   $[[T0:[0-9]+]], $7
   ; MM32R3:     mflo    $[[T1:[0-9]+]]
@@ -261,13 +246,6 @@
   ; 64R6:           daddu   $2, $[[T1]], $[[T0]]
   ; 64R6-DAG:       dmul    $3, $5, $7
 
-  ; MM64R6-DAG:     dmul    $[[T1:[0-9]+]], $5, $6
-  ; MM64R6:         dmuhu   $[[T2:[0-9]+]], $5, $7
-  ; MM64R6:         daddu   $[[T3:[0-9]+]], $[[T2]], $[[T1]]
-  ; MM64R6-DAG:     dmul    $[[T0:[0-9]+]], $4, $7
-  ; MM64R6:         daddu   $2, $[[T1]], $[[T0]]
-  ; MM64R6-DAG:     dmul    $3, $5, $7
-
   ; MM32:           lw      $25, %call16(__multi3)($16)
 
   %r = mul i128 %a, %b
Index: CodeGen/Mips/llvm-ir/not.ll
===================================================================
--- CodeGen/Mips/llvm-ir/not.ll
+++ CodeGen/Mips/llvm-ir/not.ll
@@ -26,8 +26,6 @@
 ; RUN:    -check-prefixes=ALL,MM,MM32
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,MM,MM32
-; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips | FileCheck %s \
-; RUN:    -check-prefixes=ALL,MM,MM64
 
 define signext i1 @not_i1(i1 signext %a) {
 entry:
@@ -98,9 +96,6 @@
   ; MM32:         not16   $2, $4
   ; MM32:         not16   $3, $5
 
-  ; MM64:         daddiu  $[[T0:[0-9]+]], $zero, -1
-  ; MM64:         xor     $2, $4, $[[T0]]
-
   %r = xor i64 %a, -1
   ret i64 %r
 }
@@ -123,10 +118,6 @@
   ; MM32:         not16   $4, $6
   ; MM32:         not16   $5, $7
 
-  ; MM64:         daddiu  $[[T0:[0-9]+]], $zero, -1
-  ; MM64:         xor     $2, $4, $[[T0]]
-  ; MM64:         xor     $3, $5, $[[T0]]
-
   %r = xor i128 %a, -1
   ret i128 %r
 }
@@ -176,10 +167,6 @@
 
   ; MM32:         nor     $2, $5, $4
 
-  ; MM64:         or      $[[T0:[0-9]+]], $5, $4
-  ; MM64:         sll     $[[T1:[0-9]+]], $[[T0]], 0
-  ; MM64:         not16   $2, $[[T1]]
-
   %or = or i32 %b, %a
   %r = xor i32 %or, -1
   ret i32 %r
@@ -198,8 +185,6 @@
   ; MM32:         nor     $2, $6, $4
   ; MM32:         nor     $3, $7, $5
 
-  ; MM64:         nor     $2, $5, $4
-
   %or = or i64 %b, %a
   %r = xor i64 %or, -1
   ret i64 %r
@@ -230,9 +215,6 @@
   ; MM32:         lw      $[[T3:[0-9]+]], 28($sp)
   ; MM32:         nor     $5, $[[T3]], $7
 
-  ; MM64:         nor     $2, $6, $4
-  ; MM64:         nor     $3, $7, $5
-
   %or = or i128 %b, %a
   %r = xor i128 %or, -1
   ret i128 %r
Index: CodeGen/Mips/llvm-ir/or.ll
===================================================================
--- CodeGen/Mips/llvm-ir/or.ll
+++ CodeGen/Mips/llvm-ir/or.ll
@@ -15,8 +15,6 @@
 ; RUN:    -check-prefixes=ALL,MM,MM32
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,MM,MM32
-; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips | FileCheck %s \
-; RUN:    -check-prefixes=ALL,MM,MM64
 
 define signext i1 @or_i1(i1 signext %a, i1 signext %b) {
 entry:
@@ -76,9 +74,6 @@
   ; MM32:         or16    $[[T0:[0-9]+]], $5
   ; MM32:         move    $2, $[[T0]]
 
-  ; MM64:         or      $[[T0:[0-9]+]], $4, $5
-  ; MM64:         sll     $2, $[[T0]], 0
-
   %r = or i32 %a, %b
   ret i32 %r
 }
@@ -97,8 +92,6 @@
   ; MM32:         move    $2, $[[T0]]
   ; MM32:         move    $3, $[[T1]]
 
-  ; MM64:         or      $2, $4, $5
-
   %r = or i64 %a, %b
   ret i64 %r
 }
@@ -128,9 +121,6 @@
   ; MM32:         lw      $[[T3:[0-9]+]], 28($sp)
   ; MM32:         or16    $[[T3]], $7
 
-  ; MM64:         or      $2, $4, $6
-  ; MM64:         or      $3, $5, $7
-
   %r = or i128 %a, %b
   ret i128 %r
 }
@@ -187,8 +177,6 @@
   ; MM32:         ori     $3, $5, 4
   ; MM32:         move    $2, $4
 
-  ; MM64:         ori     $2, $4, 4
-
   %r = or i64 4, %b
   ret i64 %r
 }
@@ -212,9 +200,6 @@
   ; MM32:         move    $4, $6
   ; MM32:         move    $5, $[[T0]]
 
-  ; MM64:         ori     $3, $5, 4
-  ; MM64:         move    $2, $4
-
   %r = or i128 4, %b
   ret i128 %r
 }
@@ -275,8 +260,6 @@
   ; MM32:         ori     $3, $5, 31
   ; MM32:         move    $2, $4
 
-  ; MM64:         ori     $2, $4, 31
-
   %r = or i64 31, %b
   ret i64 %r
 }
@@ -300,9 +283,6 @@
   ; MM32:         move    $4, $6
   ; MM32:         move    $5, $[[T0]]
 
-  ; MM64:         ori     $3, $5, 31
-  ; MM64:         move    $2, $4
-
   %r = or i128 31, %b
   ret i128 %r
 }
@@ -367,8 +347,6 @@
   ; MM32:         ori     $3, $5, 255
   ; MM32:         move    $2, $4
 
-  ; MM64:         ori     $2, $4, 255
-
   %r = or i64 255, %b
   ret i64 %r
 }
@@ -392,9 +370,6 @@
   ; MM32:         move    $4, $6
   ; MM32:         move    $5, $[[T0]]
 
-  ; MM64:         ori     $3, $5, 255
-  ; MM64:         move    $2, $4
-
   %r = or i128 255, %b
   ret i128 %r
 }
@@ -458,8 +433,6 @@
   ; MM32:         ori     $3, $5, 32768
   ; MM32:         move    $2, $4
 
-  ; MM64:         ori     $2, $4, 32768
-
   %r = or i64 32768, %b
   ret i64 %r
 }
@@ -483,9 +456,6 @@
   ; MM32:         move    $4, $6
   ; MM32:         move    $5, $[[T0]]
 
-  ; MM64:         ori     $3, $5, 32768
-  ; MM64:         move    $2, $4
-
   %r = or i128 32768, %b
   ret i128 %r
 }
@@ -546,8 +516,6 @@
   ; MM32:         ori     $3, $5, 65
   ; MM32:         move    $2, $4
 
-  ; MM64:         ori     $2, $4, 65
-
   %r = or i64 65, %b
   ret i64 %r
 }
@@ -571,9 +539,6 @@
   ; MM32:         move    $4, $6
   ; MM32:         move    $5, $[[T0]]
 
-  ; MM64:         ori     $3, $5, 65
-  ; MM64:         move    $2, $4
-
   %r = or i128 65, %b
   ret i128 %r
 }
@@ -630,8 +595,6 @@
   ; MM32:         ori     $3, $5, 256
   ; MM32:         move    $2, $4
 
-  ; MM64:         ori     $2, $4, 256
-
   %r = or i64 256, %b
   ret i64 %r
 }
@@ -655,9 +618,6 @@
   ; MM32:         move    $4, $6
   ; MM32:         move    $5, $[[T0]]
 
-  ; MM64:         ori     $3, $5, 256
-  ; MM64:         move    $2, $4
-
   %r = or i128 256, %b
   ret i128 %r
 }
Index: CodeGen/Mips/llvm-ir/sdiv.ll
===================================================================
--- CodeGen/Mips/llvm-ir/sdiv.ll
+++ CodeGen/Mips/llvm-ir/sdiv.ll
@@ -30,8 +30,6 @@
 ; RUN:    -check-prefixes=ALL,MMR3,MM32
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,MMR6,MM32
-; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips -target-abi n64 -relocation-model=pic | FileCheck %s \
-; RUN:    -check-prefixes=ALL,MMR6,MM64
 
 define signext i1 @sdiv_i1(i1 signext %a, i1 signext %b) {
 entry:
@@ -174,9 +172,6 @@
 
   ; MM32:         lw      $25, %call16(__divdi3)($2)
 
-  ; MM64:         ddiv    $2, $4, $5
-  ; MM64:         teq     $5, $zero, 7
-
   %r = sdiv i64 %a, %b
   ret i64 %r
 }
@@ -192,8 +187,6 @@
 
   ; MM32:         lw      $25, %call16(__divti3)($16)
 
-  ; MM64:         ld      $25, %call16(__divti3)($2)
-
   %r = sdiv i128 %a, %b
   ret i128 %r
 }
Index: CodeGen/Mips/llvm-ir/srem.ll
===================================================================
--- CodeGen/Mips/llvm-ir/srem.ll
+++ CodeGen/Mips/llvm-ir/srem.ll
@@ -30,8 +30,6 @@
 ; RUN:    -check-prefixes=ALL,MMR3,MM32
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,MMR6,MM32
-; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -relocation-model=pic | FileCheck %s \
-; RUN:    -check-prefixes=ALL,MMR6,MM64
 
 define signext i1 @srem_i1(i1 signext %a, i1 signext %b) {
 entry:
@@ -166,9 +164,6 @@
 
   ; MM32:         lw      $25, %call16(__moddi3)($2)
 
-  ; MM64:         dmod    $2, $4, $5
-  ; MM64:         teq     $5, $zero, 7
-
   %r = srem i64 %a, %b
   ret i64 %r
 }
@@ -184,8 +179,6 @@
 
   ; MM32:         lw      $25, %call16(__modti3)($16)
 
-  ; MM64:         ld      $25, %call16(__modti3)($2)
-
   %r = srem i128 %a, %b
   ret i128 %r
 }
Index: CodeGen/Mips/llvm-ir/sub.ll
===================================================================
--- CodeGen/Mips/llvm-ir/sub.ll
+++ CodeGen/Mips/llvm-ir/sub.ll
@@ -28,8 +28,6 @@
 ; RUN:    -check-prefixes=R2-R6,GP64,NOT-MM,GP64-R2
 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
 ; RUN:    -check-prefixes=R2-R6,GP64,NOT-MM,GP64-R2
-; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \
-; RUN:    -check-prefixes=GP64,MM64
 
 define signext i1 @sub_i1(i1 signext %a, i1 signext %b) {
 entry:
@@ -213,17 +211,6 @@
 ; GP64-R2:     dsubu     $2, $1, $[[T1]]
 ; GP64-R2:     dsubu     $3, $5, $7
 
-; FIXME: Again, redundant sign extension. Also, microMIPSR6 has the
-;        dext instruction which should be used here.
-
-; MM64: dsubu   $[[T0:[0-9]+]], $4, $6
-; MM64: sltu    $[[T1:[0-9]+]], $5, $7
-; MM64: dsll    $[[T2:[0-9]+]], $[[T1]], 32
-; MM64: dsrl    $[[T3:[0-9]+]], $[[T2]], 32
-; MM64: dsubu   $2, $[[T0]], $[[T3]]
-; MM64: dsubu   $3, $5, $7
-; MM64: jr      $ra
-
   %r = sub i128 %a, %b
   ret i128 %r
 }
Index: CodeGen/Mips/llvm-ir/udiv.ll
===================================================================
--- CodeGen/Mips/llvm-ir/udiv.ll
+++ CodeGen/Mips/llvm-ir/udiv.ll
@@ -30,8 +30,6 @@
 ; RUN:    -check-prefixes=ALL,MMR3,MM32
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,MMR6,MM32
-; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -relocation-model=pic | FileCheck %s \
-; RUN:    -check-prefixes=ALL,MMR6,MM64
 
 define zeroext i1 @udiv_i1(i1 zeroext %a, i1 zeroext %b) {
 entry:
@@ -136,9 +134,6 @@
 
   ; MM32:         lw      $25, %call16(__udivdi3)($2)
 
-  ; MM64:         ddivu   $2, $4, $5
-  ; MM64:         teq     $5, $zero, 7
-
   %r = udiv i64 %a, %b
   ret i64 %r
 }
@@ -154,8 +149,6 @@
 
   ; MM32:         lw      $25, %call16(__udivti3)($16)
 
-  ; MM64:         ld      $25, %call16(__udivti3)($2)
-
   %r = udiv i128 %a, %b
   ret i128 %r
 }
Index: CodeGen/Mips/llvm-ir/urem.ll
===================================================================
--- CodeGen/Mips/llvm-ir/urem.ll
+++ CodeGen/Mips/llvm-ir/urem.ll
@@ -30,8 +30,6 @@
 ; RUN:    -check-prefixes=ALL,MMR3,MM32
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,MMR6,MM32
-; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -relocation-model=pic | FileCheck %s \
-; RUN:    -check-prefixes=ALL,MMR6,MM64
 
 define signext i1 @urem_i1(i1 signext %a, i1 signext %b) {
 entry:
@@ -192,9 +190,6 @@
 
   ; MM32:         lw      $25, %call16(__umoddi3)($2)
 
-  ; MM64:         dmodu   $2, $4, $5
-  ; MM64:         teq     $5, $zero, 7
-
   %r = urem i64 %a, %b
   ret i64 %r
 }
@@ -210,8 +205,6 @@
 
   ; MM32:         lw      $25, %call16(__umodti3)($16)
 
-  ; MM64:         ld      $25, %call16(__umodti3)($2)
-
     %r = urem i128 %a, %b
     ret i128 %r
 }
Index: CodeGen/Mips/llvm-ir/xor.ll
===================================================================
--- CodeGen/Mips/llvm-ir/xor.ll
+++ CodeGen/Mips/llvm-ir/xor.ll
@@ -26,8 +26,6 @@
 ; RUN:    -check-prefixes=ALL,MM,MM32
 ; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
 ; RUN:    -check-prefixes=ALL,MM,MM32
-; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips | FileCheck %s \
-; RUN:    -check-prefixes=ALL,MM,MM64
 
 define signext i1 @xor_i1(i1 signext %a, i1 signext %b) {
 entry:
@@ -86,9 +84,6 @@
   ; MM32:         xor16   $[[T0:[0-9]+]], $5
   ; MM32:         move    $2, $[[T0]]
 
-  ; MM64:         xor     $[[T0:[0-9]+]], $4, $5
-  ; MM64:         sll     $2, $[[T0]], 0
-
   %r = xor i32 %a, %b
   ret i32 %r
 }
@@ -107,8 +102,6 @@
   ; MM32:         move    $2, $[[T0]]
   ; MM32:         move    $3, $[[T1]]
 
-  ; MM64:         xor     $2, $4, $5
-
   %r = xor i64 %a, %b
   ret i64 %r
 }
@@ -138,9 +131,6 @@
   ; MM32:         lw      $[[T3:[0-9]+]], 28($sp)
   ; MM32:         xor16   $[[T3]], $7
 
-  ; MM64:         xor     $2, $4, $6
-  ; MM64:         xor     $3, $5, $7
-
   %r = xor i128 %a, %b
   ret i128 %r
 }
@@ -197,8 +187,6 @@
   ; MM32:         xori    $3, $5, 4
   ; MM32:         move    $2, $4
 
-  ; MM64:         xori    $2, $4, 4
-
   %r = xor i64 4, %b
   ret i64 %r
 }
@@ -222,9 +210,6 @@
   ; MM32:         move    $4, $6
   ; MM32:         move    $5, $[[T0]]
 
-  ; MM64:         xori    $3, $5, 4
-  ; MM64:         move    $2, $4
-
   %r = xor i128 4, %b
   ret i128 %r
 }
Index: CodeGen/Mips/lw16-base-reg.ll
===================================================================
--- CodeGen/Mips/lw16-base-reg.ll
+++ CodeGen/Mips/lw16-base-reg.ll
@@ -1,7 +1,5 @@
 ; RUN: llc %s -march=mips -mcpu=mips32r3 -mattr=micromips -filetype=asm \
 ; RUN: -relocation-model=pic -O3 -o - | FileCheck %s
-; RUN: llc %s -march=mips64 -mcpu=mips64r6 -mattr=micromips -filetype=asm \
-; RUN: -relocation-model=pic -O3 -o - | FileCheck %s
 
 ; The purpose of this test is to check whether the CodeGen selects
 ; LW16 instruction with the base register in a range of $2-$7, $16, $17.
Index: CodeGen/Mips/micromips-lwc1-swc1.ll
===================================================================
--- CodeGen/Mips/micromips-lwc1-swc1.ll
+++ CodeGen/Mips/micromips-lwc1-swc1.ll
@@ -4,9 +4,6 @@
 ; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips \
 ; RUN:   -relocation-model=pic < %s | \
 ; RUN:   FileCheck %s -check-prefixes=ALL,MM32
-; RUN: llc -march=mips -mcpu=mips64r6 -mattr=+micromips -target-abi n64 \
-; RUN:   -relocation-model=pic < %s | \
-; RUN:   FileCheck %s -check-prefixes=ALL,MM64
 
 @gf0 = external global float
 
@@ -19,12 +16,6 @@
 ; MM32:      lw      $[[R3:[0-9]+]], %got(gf0)($[[R2]])
 ; MM32:      lwc1    $f0, 0($[[R3]])
 
-; MM64:      lui     $[[R0:[0-9]+]], %hi(%neg(%gp_rel(test_lwc1)))
-; MM64:      daddu   $[[R1:[0-9]+]], $[[R0]], $25
-; MM64:      daddiu  $[[R2:[0-9]+]], $[[R1]], %lo(%neg(%gp_rel(test_lwc1)))
-; MM64:      ld      $[[R3:[0-9]+]], %got_disp(gf0)($[[R2]])
-; MM64:      lwc1    $f0, 0($[[R3]])
-
   %0 = load float, float* @gf0, align 4
   ret float %0
 }
@@ -38,12 +29,6 @@
 ; MM32:      lw      $[[R3:[0-9]+]], %got(gf0)($[[R2]])
 ; MM32:      swc1    $f12, 0($[[R3]])
 
-; MM64:      lui     $[[R0:[0-9]+]], %hi(%neg(%gp_rel(test_swc1)))
-; MM64:      daddu   $[[R1:[0-9]+]], $[[R0]], $25
-; MM64:      daddiu  $[[R2:[0-9]+]], $[[R1]], %lo(%neg(%gp_rel(test_swc1)))
-; MM64:      ld      $[[R3:[0-9]+]], %got_disp(gf0)($[[R2]])
-; MM64:      swc1    $f12, 0($[[R3]])
-
   store float %a, float* @gf0, align 4
   ret void
 }
Index: CodeGen/Mips/mips64fpldst.ll
===================================================================
--- CodeGen/Mips/mips64fpldst.ll
+++ CodeGen/Mips/mips64fpldst.ll
@@ -2,8 +2,6 @@
 ; RUN: llc  < %s -march=mips64el -mcpu=mips4 -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32
 ; RUN: llc  < %s -march=mips64el -mcpu=mips64 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64
 ; RUN: llc  < %s -march=mips64el -mcpu=mips64 -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32
-; RUN: llc  < %s -march=mipsel -mcpu=mips64r6 -mattr=+micromips -target-abi n32 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N32
-; RUN: llc  < %s -march=mipsel -mcpu=mips64r6 -mattr=+micromips -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefix=CHECK-N64
 
 @f0 = common global float 0.000000e+00, align 4
 @d0 = common global double 0.000000e+00, align 8
Index: CodeGen/Mips/mips64shift.ll
===================================================================
--- CodeGen/Mips/mips64shift.ll
+++ CodeGen/Mips/mips64shift.ll
@@ -1,5 +1,4 @@
 ; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck -check-prefixes=ALL,MIPS %s
-; RUN: llc -march=mips64el -mcpu=mips64r6 -mattr=micromips < %s | FileCheck -check-prefixes=ALL,MICROMIPS %s
 
 define i64 @f0(i64 %a0, i64 %a1) nounwind readnone {
 entry:
Index: CodeGen/Mips/tailcall/tailcall.ll
===================================================================
--- CodeGen/Mips/tailcall/tailcall.ll
+++ CodeGen/Mips/tailcall/tailcall.ll
@@ -28,10 +28,6 @@
 ; RUN:      -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,PIC32MM
 ; RUN: llc -march=mipsel -relocation-model=static -mcpu=mips32r6 \
 ; RUN:     -mattr=+micromips -mips-tail-calls=1 < %s | FileCheck %s -check-prefixes=ALL,STATIC32
-; RUN: llc -march=mips64el -relocation-model=pic -mcpu=mips64r6 \
-; RUN:     -mattr=+micromips -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=PIC64R6MM
-; RUN: llc -march=mips64el -relocation-model=static -mcpu=mips64r6 \
-; RUN:     -mattr=+micromips -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=STATIC64
 
 @g0 = common global i32 0, align 4
 @g1 = common global i32 0, align 4
@@ -163,7 +159,6 @@
 ; STATIC32: j
 ; PIC64: jr $25
 ; PIC64R6: jrc $25
-; PIC64R6MM: jr $25
 ; STATIC64: j
 ; PIC16: jalrc
 
Index: test/MC/Disassembler/Mips/micromips64r6/valid.txt
===================================================================
--- test/MC/Disassembler/Mips/micromips64r6/valid.txt
+++ /dev/null
@@ -1,324 +0,0 @@
-# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips64r6 -mattr=micromips | FileCheck %s
-
-0x6f 0x83 # CHECK: addiur1sp $7, 4
-0x6f 0x7e # CHECK: addiur2 $6, $7, -1
-0x6f 0x76 # CHECK: addiur2 $6, $7, 12
-0x4c 0xfc # CHECK: addius5 $7, -2
-0x4f 0xff # CHECK: addiusp -1028
-0x4f 0xfd # CHECK: addiusp -1032
-0x4c 0x01 # CHECK: addiusp 1024
-0x4c 0x03 # CHECK: addiusp 1028
-0x4f 0xf9 # CHECK: addiusp -16
-0x44 0x21 # CHECK: and16 $16, $2
-0x2e 0x56 # CHECK: andi16 $4, $5, 8
-0xcc 0x42 # CHECK: bc16 132
-0x8f 0x0a # CHECK: beqzc16 $6, 20
-0xaf 0x0a # CHECK: bnezc16 $6, 20
-0x65 0x88 # CHECK: lw $3, 32($gp)
-0x48 0x66 # CHECK: lw $3, 24($sp)
-0x6a 0x12 # CHECK: lw16 $4, 8($17)
-0x29 0x82 # CHECK: lhu16 $3, 4($16)
-0x09 0x94 # CHECK: lbu16 $3, 4($17)
-0x09 0x9f # CHECK: lbu16 $3, -1($17)
-0x45 0x2b # CHECK: jalr $9
-0x45 0x23 # CHECK: jrc16 $9
-0x44 0xb3 # CHECK: jrcaddiusp 20
-0x84 0x34 # CHECK: movep $5, $6, $2, $3
-0x45 0xf9 # CHECK: or16 $3, $7
-0x60 0x44 0x30 0x08 # CHECK: ll $2, 8($4)
-0x20 0x44 0x50 0x08 # CHECK: lwm32 $16, $17, 8($4)
-0x21 0x3b 0x59 0x84 # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, -1660($27)
-0x01 0x26 0x38 0xc0 # CHECK: rotr $9, $6, 7
-0x00 0xc7 0x48 0xd0 # CHECK: rotrv $9, $6, $7
-0x60 0x44 0xb0 0x08 # CHECK: sc $2, 8($4)
-0x20 0x44 0xd0 0x08 # CHECK: swm32 $16, $17, 8($4)
-0x00 0x00 0x8b 0x7c # CHECK: syscall
-0x01 0x8c 0x8b 0x7c # CHECK: syscall 396
-0xf0 0x64 0x00 0x05 # CHECK: daui $3, $4, 5
-0x42 0x23 0x00 0x04 # CHECK: dahi $3, $3, 4
-0x42 0x03 0x00 0x04 # CHECK: dati $3, $3, 4
-0x59 0x26 0x30 0xec # CHECK: dext $9, $6, 3, 7
-0x59 0x26 0x30 0xe4 # CHECK: dextm $9, $6, 3, 39
-0x59 0x26 0x30 0xd4 # CHECK: dextu $9, $6, 35, 7
-0x58 0x43 0x25 0x1c # CHECK: dalign $4, $2, $3, 5
-0x58 0xa4 0x19 0x18 # CHECK: ddiv $3, $4, $5
-0x58 0xa4 0x19 0x58 # CHECK: dmod $3, $4, $5
-0x58 0xa4 0x19 0x98 # CHECK: ddivu $3, $4, $5
-0x58 0xa4 0x19 0xd8 # CHECK: dmodu $3, $4, $5
-0x54 0xa4 0x18 0x30 # CHECK: add.s $f3, $f4, $f5
-0x54 0xc4 0x11 0x30 # CHECK: add.d $f2, $f4, $f6
-0x54 0xa4 0x18 0x70 # CHECK: sub.s $f3, $f4, $f5
-0x54 0xc4 0x11 0x70 # CHECK: sub.d $f2, $f4, $f6
-0x54 0xa4 0x18 0xb0 # CHECK: mul.s $f3, $f4, $f5
-0x54 0xc4 0x11 0xb0 # CHECK: mul.d $f2, $f4, $f6
-0x54 0xa4 0x18 0xf0 # CHECK: div.s $f3, $f4, $f5
-0x54 0xc4 0x11 0xf0 # CHECK: div.d $f2, $f4, $f6
-0x54 0xa4 0x19 0xb8 # CHECK: maddf.s $f3, $f4, $f5
-0x54 0xa4 0x1b 0xb8 # CHECK: maddf.d $f3, $f4, $f5
-0x54 0xa4 0x19 0xf8 # CHECK: msubf.s $f3, $f4, $f5
-0x54 0xa4 0x1b 0xf8 # CHECK: msubf.d $f3, $f4, $f5
-0x54 0xc7 0x00 0x7b # CHECK: mov.s $f6, $f7
-0x54 0x86 0x20 0x7b # CHECK: mov.d $f4, $f6
-0x54 0xc7 0x0b 0x7b # CHECK: neg.s $f6, $f7
-0x54 0x86 0x2b 0x7b # CHECK: neg.d $f4, $f6
-0x54 0x64 0x28 0x0b # CHECK: max.s $f5, $f4, $f3
-0x54 0x64 0x2a 0x0b # CHECK: max.d $f5, $f4, $f3
-0x54 0x64 0x28 0x2b # CHECK: maxa.s $f5, $f4, $f3
-0x54 0x64 0x2a 0x2b # CHECK: maxa.d $f5, $f4, $f3
-0x54 0x64 0x28 0x03 # CHECK: min.s $f5, $f4, $f3
-0x54 0x64 0x2a 0x03 # CHECK: min.d $f5, $f4, $f3
-0x54 0x64 0x28 0x23 # CHECK: mina.s $f5, $f4, $f3
-0x54 0x64 0x2a 0x23 # CHECK: mina.d $f5, $f4, $f3
-0x54 0x83 0x10 0x05 # CHECK: cmp.af.s $f2, $f3, $f4
-0x54 0x83 0x10 0x45 # CHECK: cmp.un.s $f2, $f3, $f4
-0x54 0x83 0x10 0x85 # CHECK: cmp.eq.s $f2, $f3, $f4
-0x54 0x83 0x10 0xc5 # CHECK: cmp.ueq.s $f2, $f3, $f4
-0x54 0x83 0x11 0x05 # CHECK: cmp.lt.s $f2, $f3, $f4
-0x54 0x83 0x11 0x45 # CHECK: cmp.ult.s $f2, $f3, $f4
-0x54 0x83 0x11 0x85 # CHECK: cmp.le.s $f2, $f3, $f4
-0x54 0x83 0x11 0xc5 # CHECK: cmp.ule.s $f2, $f3, $f4
-0x54 0x83 0x12 0x05 # CHECK: cmp.saf.s $f2, $f3, $f4
-0x54 0x83 0x12 0x45 # CHECK: cmp.sun.s $f2, $f3, $f4
-0x54 0x83 0x12 0x85 # CHECK: cmp.seq.s $f2, $f3, $f4
-0x54 0x83 0x12 0xc5 # CHECK: cmp.sueq.s $f2, $f3, $f4
-0x54 0x83 0x13 0x05 # CHECK: cmp.slt.s $f2, $f3, $f4
-0x54 0x83 0x13 0x45 # CHECK: cmp.sult.s $f2, $f3, $f4
-0x54 0x83 0x13 0x85 # CHECK: cmp.sle.s $f2, $f3, $f4
-0x54 0x83 0x13 0xc5 # CHECK: cmp.sule.s $f2, $f3, $f4
-0x54 0x83 0x10 0x15 # CHECK: cmp.af.d $f2, $f3, $f4
-0x54 0x83 0x10 0x55 # CHECK: cmp.un.d $f2, $f3, $f4
-0x54 0x83 0x10 0x95 # CHECK: cmp.eq.d $f2, $f3, $f4
-0x54 0x83 0x10 0xd5 # CHECK: cmp.ueq.d $f2, $f3, $f4
-0x54 0x83 0x11 0x15 # CHECK: cmp.lt.d $f2, $f3, $f4
-0x54 0x83 0x11 0x55 # CHECK: cmp.ult.d $f2, $f3, $f4
-0x54 0x83 0x11 0x95 # CHECK: cmp.le.d $f2, $f3, $f4
-0x54 0x83 0x11 0xd5 # CHECK: cmp.ule.d $f2, $f3, $f4
-0x54 0x83 0x12 0x15 # CHECK: cmp.saf.d $f2, $f3, $f4
-0x54 0x83 0x12 0x55 # CHECK: cmp.sun.d $f2, $f3, $f4
-0x54 0x83 0x12 0x95 # CHECK: cmp.seq.d $f2, $f3, $f4
-0x54 0x83 0x12 0xd5 # CHECK: cmp.sueq.d $f2, $f3, $f4
-0x54 0x83 0x13 0x15 # CHECK: cmp.slt.d $f2, $f3, $f4
-0x54 0x83 0x13 0x55 # CHECK: cmp.sult.d $f2, $f3, $f4
-0x54 0x83 0x13 0x95 # CHECK: cmp.sle.d $f2, $f3, $f4
-0x54 0x83 0x13 0xd5 # CHECK: cmp.sule.d $f2, $f3, $f4
-0x54 0x64 0x01 0x3b # CHECK: cvt.l.s $f3, $f4
-0x54 0x64 0x41 0x3b # CHECK: cvt.l.d $f3, $f4
-0x54 0x64 0x09 0x3b # CHECK: cvt.w.s $f3, $f4
-0x54 0x64 0x49 0x3b # CHECK: cvt.w.d $f3, $f4
-0x54 0x44 0x13 0x7b # CHECK: cvt.d.s $f2, $f4
-0x54 0x44 0x33 0x7b # CHECK: cvt.d.w $f2, $f4
-0x54 0x44 0x53 0x7b # CHECK: cvt.d.l $f2, $f4
-0x54 0x44 0x1b 0x7b # CHECK: cvt.s.d $f2, $f4
-0x54 0x64 0x3b 0x7b # CHECK: cvt.s.w $f3, $f4
-0x54 0x64 0x5b 0x7b # CHECK: cvt.s.l $f3, $f4
-0x54 0x65 0x03 0x7b # CHECK: abs.s $f3, $f5
-0x54 0x44 0x23 0x7b # CHECK: abs.d $f2, $f4
-0x54 0x65 0x03 0x3b # CHECK: floor.l.s $f3, $f5
-0x54 0x44 0x43 0x3b # CHECK: floor.l.d $f2, $f4
-0x54 0x65 0x0b 0x3b # CHECK: floor.w.s $f3, $f5
-0x54 0x44 0x4b 0x3b # CHECK: floor.w.d $f2, $f4
-0x54 0x65 0x13 0x3b # CHECK: ceil.l.s $f3, $f5
-0x54 0x44 0x53 0x3b # CHECK: ceil.l.d $f2, $f4
-0x54 0x65 0x1b 0x3b # CHECK: ceil.w.s $f3, $f5
-0x54 0x44 0x5b 0x3b # CHECK: ceil.w.d $f2, $f4
-0x54 0x65 0x23 0x3b # CHECK: trunc.l.s $f3, $f5
-0x54 0x44 0x63 0x3b # CHECK: trunc.l.d $f2, $f4
-0x54 0x65 0x2b 0x3b # CHECK: trunc.w.s $f3, $f5
-0x54 0x44 0x6b 0x3b # CHECK: trunc.w.d $f2, $f4
-0x54 0x65 0x0a 0x3b # CHECK: sqrt.s $f3, $f5
-0x54 0x44 0x4a 0x3b # CHECK: sqrt.d $f2, $f4
-0x54 0x65 0x02 0x3b # CHECK: rsqrt.s $f3, $f5
-0x54 0x44 0x42 0x3b # CHECK: rsqrt.d $f2, $f4
-0x01 0x28 0x00 0x3c # CHECK: teq $8, $9
-0x00 0xe5 0xf0 0x3c # CHECK: teq $5, $7, 15
-0x01 0x47 0x02 0x3c # CHECK: tge $7, $10
-0x02 0x67 0xf2 0x3c # CHECK: tge $7, $19, 15
-0x03 0x96 0x04 0x3c # CHECK: tgeu $22, $gp
-0x01 0xd4 0xf4 0x3c # CHECK: tgeu $20, $14, 15
-0x01 0xaf 0x08 0x3c # CHECK: tlt $15, $13
-0x02 0x62 0xf8 0x3c # CHECK: tlt $2, $19, 15
-0x02 0x0b 0x0a 0x3c # CHECK: tltu $11, $16
-0x03 0xb0 0xfa 0x3c # CHECK: tltu $16, $sp, 15
-0x02 0x26 0x0c 0x3c # CHECK: tne $6, $17
-0x01 0x07 0xfc 0x3c # CHECK: tne $7, $8, 15
-0x60 0x25 0xa6 0x08 # CHECK: cachee 1, 8($5)
-0x00 0x64 0xf1 0x7c # CHECK: wrpgpr $3, $4
-0x00 0x64 0x7b 0x3c # CHECK: wsbh $3, $4
-0x78 0x58 0x00 0x02 # CHECK: ldpc $2, 16
-0x65 0x88 # CHECK: lw $3, 32($gp)
-0x48 0x66 # CHECK: lw $3, 24($sp)
-0x6a 0x12 # CHECK: lw16 $4, 8($17)
-0x29 0x82 # CHECK: lhu16 $3, 4($16)
-0x09 0x94 # CHECK: lbu16 $3, 4($17)
-0x09 0x9f # CHECK: lbu16 $3, -1($17)
-0x46 0x1B # CHECK: break16 8
-0xed 0xff # CHECK: li16 $3, -1
-0x0c 0x65 # CHECK: move16 $3, $5
-0x46 0x3b # CHECK: sdbbp16 8
-0x04 0x3b # CHECK: subu16 $5, $16, $3
-0x44 0xd8 # CHECK: xor16 $17, $5
-0x45 0x22 # CHECK: lwm16 $16, $17, $ra, 8($sp)
-0x89 0x84 # CHECK: sb16 $3, 4($16)
-0xaa 0x14 # CHECK: sh16 $4, 8($17)
-0xc8 0x9f # CHECK: sw $4, 124($sp)
-0xea 0x11 # CHECK: sw16 $4, 4($17)
-0xe8 0x11 # CHECK: sw16 $zero, 4($17)
-0x45 0x2a # CHECK: swm16 $16, $17, $ra, 8($sp)
-0x54 0x44 0x12 0x3b # CHECK: recip.s $f2, $f4
-0x54 0x44 0x52 0x3b # CHECK: recip.d $f2, $f4
-0x54 0x82 0x00 0x20 # CHECK: rint.s $f2, $f4
-0x54 0x82 0x02 0x20 # CHECK: rint.d $f2, $f4
-0x54 0x44 0x33 0x3b # CHECK: round.l.s $f2, $f4
-0x54 0x44 0x73 0x3b # CHECK: round.l.d $f2, $f4
-0x54 0x44 0x3b 0x3b # CHECK: round.w.s $f2, $f4
-0x54 0x44 0x7b 0x3b # CHECK: round.w.d $f2, $f4
-0x54 0x41 0x08 0xb8 # CHECK: sel.s $f1, $f1, $f2
-0x54 0x82 0x02 0xb8 # CHECK: sel.d $f0, $f2, $f4
-0x54 0x62 0x08 0x38 # CHECK: seleqz.s $f1, $f2, $f3
-0x55 0x04 0x12 0x38 # CHECK: seleqz.d $f2, $f4, $f8
-0x54 0x62 0x08 0x78 # CHECK: selnez.s $f1, $f2, $f3
-0x55 0x04 0x12 0x78 # CHECK: selnez.d $f2, $f4, $f8
-0x54 0x62 0x00 0x60 # CHECK: class.s $f2, $f3
-0x54 0x82 0x02 0x60 # CHECK: class.d $f2, $f4
-0x00 0x00 0xe3 0x7c # CHECK: deret
-0x00 0x00 0x47 0x7c # CHECK: di
-0x00 0x0f 0x47 0x7c # CHECK: di $15
-0x00 0x11 0x19 0x7c # CHECK: dvp $17
-0x00 0x00 0x19 0x7c # CHECK: dvp $zero
-0x00 0x10 0x39 0x7c # CHECK: evp $16
-0x00 0x00 0x39 0x7c # CHECK: evp $zero
-0x00 0x00 0x43 0x7c # CHECK: tlbinv
-0x00 0x00 0x53 0x7c # CHECK: tlbinvf
-0x58 0x82 0x20 0x34 # CHECK: dinsu $4, $2, 32, 5
-0x58 0x82 0x38 0xc4 # CHECK: dinsm $4, $2, 3, 5
-0x58 0x82 0x38 0xcc # CHECK: dins $4, $2, 3, 5
-0x00 0xa9 0x02 0xfc # CHECK: mtc0 $5, $9, 0
-0x00 0xa9 0x02 0xfc # CHECK: mtc0 $5, $9
-0x00 0x22 0x3a 0xfc # CHECK: mtc0 $1, $2, 7
-0x54 0x64 0x28 0x3b # CHECK: mtc1 $3, $f4
-0x00 0xa6 0x5d 0x3c # CHECK: mtc2 $5, $6
-0x00 0xe8 0x02 0xf4 # CHECK: mthc0 $7, $8, 0
-0x00 0xe8 0x02 0xf4 # CHECK: mthc0 $7, $8
-0x01 0x2a 0x0a 0xf4 # CHECK: mthc0 $9, $10, 1
-0x55 0x6c 0x38 0x3b # CHECK: mthc1 $11, $f12
-0x01 0xae 0x9d 0x3c # CHECK: mthc2 $13, $14
-0x59 0xf0 0x02 0xfc # CHECK: dmtc0 $15, $16, 0
-0x59 0xf0 0x02 0xfc # CHECK: dmtc0 $15, $16
-0x5a 0x32 0x2a 0xfc # CHECK: dmtc0 $17, $18, 5
-0x56 0x74 0x2c 0x3b # CHECK: dmtc1 $19, $f20
-0x02 0xb6 0x7d 0x3c # CHECK: dmtc2 $21, $22
-0x5a 0x51 0x00 0xfc # CHECK: dmfc0 $18, $17
-0x59 0x21 0x08 0xfc # CHECK: dmfc0 $9, $1, 1
-0x55 0x24 0x24 0x3b # CHECK: dmfc1 $9, $f4
-0x01 0xd2 0x6d 0x3c # CHECK: dmfc2 $14, $18
-0x58 0xe6 0x49 0x10 # CHECK: dadd $9, $6, $7
-0x5b 0xe1 0x99 0x10 # CHECK: dadd $19, $1, $ra
-0x5f 0x02 0x46 0x9f # CHECK: daddiu $24, $2, 18079
-0x5d 0x26 0xc5 0x67 # CHECK: daddiu $9, $6, -15001
-0x5d 0x29 0xc5 0x67 # CHECK: daddiu $9, $9, -15001
-0x5d 0x23 0x00 0x20 # CHECK: daddiu $9, $3, 32
-0x5f 0x56 0xee 0x16 # CHECK: daddiu $26, $22, -4586
-0x5d 0xeb 0xec 0x5f # CHECK: daddiu $15, $11, -5025
-0x5d 0xce 0x11 0xea # CHECK: daddiu $14, $14, 4586
-0x5e 0x73 0x69 0x3f # CHECK: daddiu $19, $19, 26943
-0x5d 0x7a 0x7c 0xcd # CHECK: daddiu $11, $26, 31949
-0x5f 0xbd 0xff 0xe0 # CHECK: daddiu $sp, $sp, -32
-0x59 0x61 0xd1 0x50 # CHECK: daddu $26, $1, $11
-0x5b 0xe1 0x99 0x50 # CHECK: daddu $19, $1, $ra
-0x58 0xe6 0x49 0x50 # CHECK: daddu $9, $6, $7
-0x58 0x69 0x49 0x50 # CHECK: daddu $9, $9, $3
-0x5d 0x26 0xc5 0x67 # CHECK: daddiu $9, $6, -15001
-0x5d 0x29 0x00 0x0a # CHECK: daddiu $9, $9, 10
-0x5e 0x73 0x69 0x3f # CHECK: daddiu $19, $19, 26943
-0x5f 0x02 0x46 0x9f # CHECK: daddiu $24, $2, 18079
-0x5c 0x63 0xff 0xfb # CHECK: daddiu $3, $3, -5
-0x5c 0x64 0xff 0xfb # CHECK: daddiu $3, $4, -5
-0x00 0x00 0x03 0x7c # CHECK: tlbp
-0x00 0x00 0x13 0x7c # CHECK: tlbr
-0x00 0x00 0x23 0x7c # CHECK: tlbwi
-0x00 0x00 0x33 0x7c # CHECK: tlbwr
-0x00 0x00 0x19 0x7c # CHECK: dvp
-0x00 0x04 0x19 0x7c # CHECK: dvp $4
-0x00 0x00 0x39 0x7c # CHECK: evp
-0x00 0x04 0x39 0x7c # CHECK: evp $4
-0x03 0xe4 0x1f 0x3c # CHECK: jalrc.hb $4
-0x00 0x85 0x1f 0x3c # CHECK: jalrc.hb $4, $5
-0x00 0x83 0x38 0x00 # CHECK: sll $4, $3, 7
-0x00 0x65 0x10 0x10 # CHECK: sllv $2, $3, $5
-0x00 0x83 0x38 0x80 # CHECK: sra $4, $3, 7
-0x00 0x65 0x10 0x90 # CHECK: srav $2, $3, $5
-0x00 0x83 0x38 0x40 # CHECK: srl $4, $3, 7
-0x00 0x65 0x10 0x50 # CHECK: srlv $2, $3, $5
-0x58 0x62 0x09 0x90 # CHECK: dsub $1, $2, $3
-0x59 0xe7 0x19 0xd0 # CHECK: dsubu $3, $7, $15
-0x59 0xe0 0x39 0x90 # CHECK: dneg $7, $15
-0x59 0x40 0x51 0x90 # CHECK: dneg $10, $10
-0x59 0x60 0x09 0xd0 # CHECK: dnegu $1, $11
-0x58 0xa0 0x29 0xd0 # CHECK: dnegu $5, $5
-0x3c 0x44 0x00 0x08 # CHECK: lh $2, 8($4)
-0x60 0x82 0x6a 0x08 # CHECK: lhe $4, 8($2)
-0x34 0x82 0x00 0x08 # CHECK: lhu $4, 8($2)
-0x60 0x82 0x62 0x08 # CHECK: lhue $4, 8($2)
-0x00 0xa4 0x18 0x18 # CHECK: mul $3, $4, $5
-0x00 0xa4 0x18 0x58 # CHECK: muh $3, $4, $5
-0x00 0xa4 0x18 0x98 # CHECK: mulu $3, $4, $5
-0x00 0xa4 0x18 0xd8 # CHECK: muhu $3, $4, $5
-0x58 0xa4 0x18 0x18 # CHECK: dmul $3, $4, $5
-0x58 0xa4 0x18 0x58 # CHECK: dmuh $3, $4, $5
-0x58 0xa4 0x18 0x98 # CHECK: dmulu $3, $4, $5
-0x58 0xa4 0x18 0xd8 # CHECK: dmuhu $3, $4, $5
-0x22 0x04 0x10 0x08 # CHECK: lwp $16, 8($4)
-0x22 0x04 0x90 0x08 # CHECK: swp $16, 8($4)
-0x58 0x64 0x7b 0x3c # CHECK: dsbh $3, $4
-0x58 0x64 0xfb 0x3c # CHECK: dshd $3, $4
-0x58 0x64 0x28 0x00 # CHECK: dsll $3, $4, 5
-0x58 0x64 0x28 0x08 # CHECK: dsll32 $3, $4, 5
-0x58 0xa6 0x20 0x10 # CHECK: dsllv $4, $5, $6
-0x58 0x85 0x28 0x80 # CHECK: dsra $4, $5, 5
-0x58 0xa6 0x20 0x90 # CHECK: dsrav $4, $5, $6
-0x41 0x1f 0x00 0x02 # CHECK: bc1eqzc $f31, 8
-0x41 0x3f 0x00 0x02 # CHECK: bc1nezc $f31, 8
-0x41 0x5f 0x00 0x04 # CHECK: bc2eqzc $31, 12
-0x41 0x7f 0x00 0x04 # CHECK: bc2nezc $31, 12
-0x00 0xa4 0x1a 0x50 # CHECK: and $3, $4, $5
-0xd0 0x64 0x04 0xd2 # CHECK: andi $3, $4, 1234
-0x00 0xa4 0x1a 0x90 # CHECK: or $3, $4, $5
-0x50 0x64 0x04 0xd2 # CHECK: ori $3, $4, 1234
-0x00 0xa4 0x1b 0x10 # CHECK: xor $3, $4, $5
-0x70 0x64 0x04 0xd2 # CHECK: xori $3, $4, 1234
-0x00 0xa4 0x1a 0xd0 # CHECK: nor $3, $4, $5
-0x00 0x04 0x1a 0xd0 # CHECK: not $3, $4
-0x58 0x22 0x4b 0x3c # CHECK: dclo $1, $2
-0x58 0x22 0x5b 0x3c # CHECK: dclz $1, $2
-0x58 0xaa 0x40 0xc0 # CHECK: drotr $5, $10, 8
-0x58 0x22 0x20 0xc8 # CHECK: drotr32 $1, $2, 4
-0x58 0xc4 0x18 0xd0 # CHECK: drotrv $3, $6, $4
-0xdc 0x82 0x00 0x05 # CHECK: ld $4, 5($2)
-0x60 0x48 0x70 0x03 # CHECK: lld $2, 3($8)
-0x60 0x22 0xe0 0x0a # CHECK: lwu $1, 10($2)
-0xd8 0x83 0x00 0x05 # CHECK: sd $4, 5($3)
-0x58 0x22 0x10 0x40 # CHECK: dsrl $1, $2, 2
-0x58 0x64 0x28 0x48 # CHECK: dsrl32 $3, $4, 5
-0x58 0x63 0x08 0x50 # CHECK: dsrlv $1, $3, $3
-0xbc 0xea 0x01 0x2c # CHECK: ldc1 $f7, 300($10)
-0xbd 0x0a 0x01 0x2c # CHECK: ldc1 $f8, 300($10)
-0x21 0x6c 0x23 0xff # CHECK: ldc2 $11, 1023($12)
-0x9c 0x45 0x00 0x20 # CHECK: lwc1 $f2, 32($5)
-0x20 0x24 0x00 0x10 # CHECK: lwc2 $1, 16($4)
-0xb8 0xea 0x00 0x40 # CHECK: sdc1 $f7, 64($10)
-0xb9 0x0a 0x00 0x40 # CHECK: sdc1 $f8, 64($10)
-0x20 0x50 0xa0 0x08 # CHECK: sdc2 $2, 8($16)
-0x98 0xcd 0x01 0x71 # CHECK: swc1 $f6, 369($13)
-0x20 0xf1 0x83 0x09 # CHECK: swc2 $7, 777($17)
-0x54 0x22 0x10 0x3b # CHECK: cfc1 $1, $2
-0x00 0x64 0xcd 0x3c # CHECK: cfc2 $3, $4
-0x54 0xa6 0x18 0x3b # CHECK: ctc1 $5, $6
-0x00 0xe8 0xdd 0x3c # CHECK: ctc2 $7, $8
-0xd4 0xc6 0x00 0x20 # CHECK: bltzc $6, 132
-0xf4 0x40 0x00 0x40 # CHECK: blezc $2, 260
-0xf6 0x10 0x00 0x80 # CHECK: bgezc $16, 516
-0xd5 0x80 0x01 0x00 # CHECK: bgtzc $12, 1028
-0x10 0x64 0x01 0x00 # CHECK: aui $3, $4, 256
-0x58 0x83 0x0b 0x3c # CHECK: dbitswap $3, $4
-0x58 0x64 0x2d 0x04 # CHECK: dlsa $3, $4, $5, 3
-0x78 0x50 0x00 0x43 # CHECK: lwupc $2, 268
Index: test/MC/Mips/micromips64r6/invalid-wrong-error.s
===================================================================
--- test/MC/Mips/micromips64r6/invalid-wrong-error.s
+++ /dev/null
@@ -1,52 +0,0 @@
-# Instructions that are correctly rejected but emit a wrong or misleading error.
-# RUN: not llvm-mc %s -triple=mips -show-encoding -mcpu=mips64r6 -mattr=micromips 2>%t1
-# RUN: FileCheck %s < %t1
-
-
-  # The LLD instruction with invalid memory operand should emit "expected memory with 12-bit signed offset".
-  lld $31, 4096($31)       # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
-  lld $31, 2048($31)       # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
-  lld $31, -2049($31)      # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
-  # The LWU instruction with invalid memory operand should emit "expected memory with 12-bit signed offset".
-  lwu $31, 4096($31)           # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
-  lwu $31, 2048($31)           # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
-  lwu $31, -2049($31)          # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
-  # The 10-bit immediate supported by the standard encodings cause us to emit
-  # the diagnostic for the 10-bit form. This isn't exactly wrong but it is
-  # misleading. Ideally, we'd emit every way to achieve a valid match instead
-  # of picking only one.
-  teq $8, $9, $2           # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
-  teq $8, $9, -1           # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
-  teq $8, $9, 16           # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
-  tge $8, $9, $2           # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
-  tge $8, $9, -1           # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
-  tge $8, $9, 16           # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
-  tgeu $8, $9, $2          # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate
-  tgeu $8, $9, -1          # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate
-  tgeu $8, $9, 16          # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
-  tlt $8, $9, $2           # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
-  tlt $8, $9, -1           # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
-  tlt $8, $9, 16           # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
-  tltu $8, $9, $2          # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate
-  tltu $8, $9, -1          # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate
-  tltu $8, $9, 16          # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
-  tne $8, $9, $2           # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
-  tne $8, $9, -1           # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
-  tne $8, $9, 16           # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
-  dins $2, $3, -1, 1       # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate
-  dins $2, $3, 32, 1       # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
-  syscall -1               # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate
-  syscall $4               # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate
-  syscall 1024             # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
-  ldc2 $1, -2049($12)      # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
-  ldc2 $1, 2048($12)       # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
-  ldc2 $1, 1023($32)       # CHECK: :[[@LINE]]:12: error: expected memory with 16-bit signed offset
-  lwc2 $1, -2049($4)       # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
-  lwc2 $1, 2048($4)        # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
-  lwc2 $1, 16($32)         # CHECK: :[[@LINE]]:12: error: expected memory with 16-bit signed offset
-  sdc2 $1, -2049($16)      # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
-  sdc2 $1, 2048($16)       # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
-  sdc2 $1, 8($32)          # CHECK: :[[@LINE]]:12: error: expected memory with 16-bit signed offset
-  swc2 $1, -2049($17)      # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
-  swc2 $1, 2048($17)       # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
-  swc2 $1, 777($32)        # CHECK: :[[@LINE]]:12: error: expected memory with 16-bit signed offset
Index: test/MC/Mips/micromips64r6/invalid.s
===================================================================
--- test/MC/Mips/micromips64r6/invalid.s
+++ /dev/null
@@ -1,414 +0,0 @@
-# RUN: not llvm-mc %s -triple=mips -show-encoding -mcpu=mips64r6 -mattr=micromips 2>%t1
-# RUN: FileCheck %s < %t1
-
-  addiur1sp $7, 260        # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and multiple of 4
-  addiur1sp $7, 241        # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and multiple of 4
-  addiur1sp $8, 240        # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
-  addiur2 $9, $7, -1       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  addiur2 $6, $7, 10       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
-  addius5 $2, -9           # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate
-  addius5 $2, 8            # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate
-  addiusp 1032             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
-  align $4, $2, $3, -1     # CHECK: :[[@LINE]]:21: error: expected 2-bit unsigned immediate
-  align $4, $2, $3, 4      # CHECK: :[[@LINE]]:21: error: expected 2-bit unsigned immediate
-  beqzc16 $9, 20           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  beqzc16 $6, 31           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
-  beqzc16 $6, 130          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
-  bnezc16 $9, 20           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  bnezc16 $6, 31           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
-  bnezc16 $6, 130          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
-  cache -1, 255($7)        # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate
-  cache 32, 255($7)        # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate
-  dahi    $4, $4, 65536    # CHECK: :[[@LINE]]:19: error: expected 16-bit unsigned immediate
-  dahi    $4, $4, -1       # CHECK: :[[@LINE]]:19: error: expected 16-bit unsigned immediate
-  dahi    $4, $5, 1        # CHECK: :[[@LINE]]:3: error: source and destination must match
-  dati    $4, $4, 65536    # CHECK: :[[@LINE]]:19: error: expected 16-bit unsigned immediate
-  dati    $4, $4, -1       # CHECK: :[[@LINE]]:19: error: expected 16-bit unsigned immediate
-  dati    $4, $5, 1        # CHECK: :[[@LINE]]:3: error: source and destination must match
-  daui    $4, $0, 1        # CHECK: :[[@LINE]]:3: error: invalid operand ($zero) for instruction
-  daui    $4, $4, 65536    # CHECK: :[[@LINE]]:19: error: expected 16-bit unsigned immediate
-  daui    $4, $4, -1       # CHECK: :[[@LINE]]:19: error: expected 16-bit unsigned immediate
-  dati    $4, $4, -1       # CHECK: :[[@LINE]]:19: error: expected 16-bit unsigned immediate
-  dati    $4, $5, 1        # CHECK: :[[@LINE]]:3: error: source and destination must match
-  # FIXME: Check various 'pos + size' constraints on dext*
-  dext $2, $3, -1, 1   # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate
-  dext $2, $3, 64, 1   # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate
-  dext $2, $3, 1, 0    # CHECK: :[[@LINE]]:19: error: expected immediate in range 1 .. 32
-  dext $2, $3, 1, 33   # CHECK: :[[@LINE]]:19: error: expected immediate in range 1 .. 32
-  dextm $2, $3, -1, 1  # CHECK: :[[@LINE]]:17: error: expected 5-bit unsigned immediate
-  dextm $2, $3, 32, 1  # CHECK: :[[@LINE]]:17: error: expected 5-bit unsigned immediate
-  dextm $2, $3, -1, 33 # CHECK: :[[@LINE]]:17: error: expected 5-bit unsigned immediate
-  dextm $2, $3, 32, 33 # CHECK: :[[@LINE]]:17: error: expected 5-bit unsigned immediate
-  dextm $2, $3, 1, 32  # CHECK: :[[@LINE]]:20: error: expected immediate in range 33 .. 64
-  dextm $2, $3, 1, 65  # CHECK: :[[@LINE]]:20: error: expected immediate in range 33 .. 64
-  dextu $2, $3, 31, 1  # CHECK: :[[@LINE]]:17: error: expected immediate in range 32 .. 63
-  dextu $2, $3, 64, 1  # CHECK: :[[@LINE]]:17: error: expected immediate in range 32 .. 63
-  dextu $2, $3, 32, 0  # CHECK: :[[@LINE]]:21: error: expected immediate in range 1 .. 32
-  dextu $2, $3, 32, 33 # CHECK: :[[@LINE]]:21: error: expected immediate in range 1 .. 32
-  dins $2, $3, 31, 33  # CHECK: :[[@LINE]]:20: error: expected immediate in range 1 .. 32
-  dins $2, $3, 31, 0   # CHECK: :[[@LINE]]:20: error: expected immediate in range 1 .. 32
-  # FIXME: Check '32 <= pos + size <= 64' constraint on dinsm
-  dinsm $2, $3, -1, 1  # CHECK: :[[@LINE]]:17: error: expected 5-bit unsigned immediate
-  dinsm $2, $3, 32, 1  # CHECK: :[[@LINE]]:17: error: expected 5-bit unsigned immediate
-  dinsm $2, $3, 31, 0  # CHECK: :[[@LINE]]:21: error: expected immediate in range 2 .. 64
-  dinsm $2, $3, 31, 65 # CHECK: :[[@LINE]]:21: error: expected immediate in range 2 .. 64
-  dinsu $2, $3, 31, 1  # CHECK: :[[@LINE]]:17: error: expected immediate in range 32 .. 63
-  dinsu $2, $3, 64, 1  # CHECK: :[[@LINE]]:17: error: expected immediate in range 32 .. 63
-  dinsu $2, $3, 63, 0  # CHECK: :[[@LINE]]:21: error: expected immediate in range 1 .. 32
-  dinsu $2, $3, 32, 33 # CHECK: :[[@LINE]]:21: error: expected immediate in range 1 .. 32
-  # FIXME: Check '0 < pos + size <= 32' constraint on ext
-  ext $2, $3, -1, 31       # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
-  ext $2, $3, 32, 31       # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
-  ext $2, $3, 1, 0         # CHECK: :[[@LINE]]:18: error: expected immediate in range 1 .. 32
-  ext $2, $3, 1, 33        # CHECK: :[[@LINE]]:18: error: expected immediate in range 1 .. 32
-  ins $2, $3, -1, 31       # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
-  ins $2, $3, 32, 31       # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
-  dalign  $4, $2, $3, -1   # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
-  dalign  $4, $2, $3, 8    # CHECK: :[[@LINE]]:23: error: expected 3-bit unsigned immediate
-  lbu16 $9, 8($16)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  lbu16 $3, -2($16)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
-  lbu16 $3, -2($16)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
-  lbu16 $16, 8($9)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  lhu16 $9, 4($16)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  lhu16 $3, 64($16)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
-  lhu16 $3, 64($16)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
-  lhu16 $16, 4($9)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  li16 $4, -2              # CHECK: :[[@LINE]]:12: error: expected immediate in range -1 .. 126
-  li16 $4, 127             # CHECK: :[[@LINE]]:12: error: expected immediate in range -1 .. 126
-  lsa   $4, $2, $3, 0      # CHECK: :[[@LINE]]:21: error: expected immediate in range 1 .. 4
-  lsa   $4, $2, $3, 5      # CHECK: :[[@LINE]]:21: error: expected immediate in range 1 .. 4
-  lw16  $9, 8($17)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  lw16  $4, 68($17)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
-  lw16  $4, 68($17)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
-  lw16  $17, 8($10)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  ddiv $32, $4, $5         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  ddiv $3, $34, $5         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  ddiv $3, $4, $35         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  dmod $32, $4, $5         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  dmod $3, $34, $5         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  dmod $3, $4, $35         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  ddivu $32, $4, $5        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  ddivu $3, $34, $5        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  ddivu $3, $4, $35        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  dmodu $32, $4, $5        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  dmodu $3, $34, $5        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  dmodu $3, $4, $35        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  pref -1, 255($7)         # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate
-  pref 32, 255($7)         # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate
-  teq $34, $9, 5           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  teq $8, $35, 6           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  tge $34, $9, 5           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  tge $8, $35, 6           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  tgeu $34, $9, 5          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  tgeu $8, $35, 6          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  tlt $34, $9, 5           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  tlt $8, $35, 6           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  tltu $34, $9, 5          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  tltu $8, $35, 6          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  tne $34, $9, 5           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  tne $8, $35, 6           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  wrpgpr $34, $4           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  wrpgpr $3, $33           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  wsbh $34, $4             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  wsbh $3, $33             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  jrcaddiusp 1             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4
-  jrcaddiusp 2             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4
-  jrcaddiusp 3             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4
-  jrcaddiusp 10            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4
-  jrcaddiusp 18            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4
-  jrcaddiusp 31            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4
-  jrcaddiusp 33            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4
-  jrcaddiusp 125           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4
-  jrcaddiusp 128           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4
-  jrcaddiusp 132           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4
-  lwm16 $5, $6, $ra, 8($sp)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
-  lwm16 $16, $19, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected
-  lwm16 $16-$25, $ra, 8($sp)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
-  lwm16 $16, 8($sp)           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  lwm16 $16, $17, 8($sp)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  lwm16 $16-$20, 8($sp)       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  lwm16 $16, $17, $ra, 8($fp)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  lwm16 $16, $17, $ra, 64($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  sb16 $9, 4($16)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  sb16 $3, 64($16)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
-  sb16 $16, 4($16)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  sb16 $7, 4($9)           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  sh16  $9, 8($17)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  sh16  $4, 68($17)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
-  sh16  $16, 8($17)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  sh16  $7, 8($9)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  sw16  $9, 4($17)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  sw16  $4, 64($17)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
-  sw16  $16, 4($17)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  sw16  $7, 4($10)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  swm16 $5, $6, $ra, 8($sp)   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
-  swm16 $16, $19, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected
-  swm16 $16-$25, $ra, 8($sp)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
-  swm16 $16, 8($sp)           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  swm16 $16, $17, 8($sp)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  swm16 $16-$20, 8($sp)       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  swm16 $16, $17, $ra, 8($fp)  # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  swm16 $16, $17, $ra, 64($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  mtc0  $4, $3, -1             # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
-  mtc0  $4, $3, 8              # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
-  mthc0 $4, $3, -1             # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
-  mthc0 $4, $3, 8              # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate
-  dmtc0  $4, $3, -1            # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate
-  dmtc0  $4, $3, 8             # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate
-  dmfc0  $4, $3, -1            # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate
-  dmfc0  $4, $3, 8             # CHECK: :[[@LINE]]:18: error: expected 3-bit unsigned immediate
-  tlbp $3                      # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
-  tlbp 5                       # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
-  tlbp $4, 6                   # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
-  tlbr $3                      # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
-  tlbr 5                       # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
-  tlbr $4, 6                   # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
-  tlbwi $3                     # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
-  tlbwi 5                      # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
-  tlbwi $4, 6                  # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
-  tlbwr $3                     # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
-  tlbwr 5                      # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
-  tlbwr $4, 6                  # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
-  dvp 3                        # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
-  dvp $4, 5                    # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
-  evp 3                        # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
-  evp $4, 5                    # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
-  jalrc.hb $31                 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
-  jalrc.hb $31, $31            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
-  sll $4, $3, -1               # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
-  sll $4, $3, 32               # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
-  sra $4, $3, -1               # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
-  sra $4, $3, 32               # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
-  srl $4, $3, -1               # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
-  srl $4, $3, 32               # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
-  sll $3, -1                   # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
-  sll $3, 32                   # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
-  sra $3, -1                   # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
-  sra $3, 32                   # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
-  srl $3, -1                   # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
-  srl $3, 32                   # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
-  dneg $7, 5                   # CHECK: :[[@LINE]]:12: error: invalid operand for instruction
-  dneg 4                       # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
-  dnegu $1, 3                  # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
-  dnegu 7                      # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
-  lle $33, 8($5)               # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
-  lle $4, 8($33)               # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
-  lle $4, 512($5)              # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
-  lle $4, -513($5)             # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
-  lwe $33, 8($5)               # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
-  lwe $4, 8($33)               # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
-  lwe $4, 512($5)              # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
-  lwe $4, -513($5)             # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
-  sbe $33, 8($5)               # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
-  sbe $4, 8($33)               # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
-  sbe $4, 512($5)              # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
-  sbe $4, -513($5)             # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
-  sce $33, 8($5)               # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
-  sce $4, 8($33)               # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
-  sce $4, 512($5)              # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
-  sce $4, -513($5)             # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
-  she $33, 8($5)               # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
-  she $4, 8($33)               # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
-  she $4, 512($5)              # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
-  she $4, -513($5)             # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
-  swe $33, 8($4)               # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
-  swe $5, 8($34)               # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
-  swe $5, 512($4)              # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
-  swe $5, -513($4)             # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset
-  lh $33, 8($4)                # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  lhe $34, 8($2)               # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  lhu $35, 8($2)               # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  lhue $36, 8($2)              # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  lh $2, 8($34)                # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
-  lhe $4, 8($33)               # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-  lhu $4, 8($35)               # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
-  lhue $4, 8($37)              # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-  lh $2, -65536($4)            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
-  lh $2, 65536($4)             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
-  lhe $4, -512($2)             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-  lhe $4, 512($2)              # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-  lhu $4, -65536($2)           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
-  lhu $4, 65536($2)            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
-  lhue $4, -512($2)            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-  lhue $4, 512($2)             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset
-  lwm32 $5, $6, 8($4)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
-  lwm32 $16, $19, 8($4)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected
-  lwm32 $16-$25, 8($4)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
-  lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $24, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
-  movep $5, $6, $2, $9         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  movep $5, $6, $5, $3         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  movep $5, $21, $2, $3        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  movep $8, $6, $2, $3         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  rotr $2, -1                  # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate
-  rotr $2, 32                  # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate
-  rotr $2, $3, -1              # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate
-  rotr $2, $3, 32              # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate
-  rotrv $9, $6, 5              # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  swm32 $5, $6, 8($4)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected
-  swm32 $16, $19, 8($4)        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected
-  swm32 $16-$25, 8($4)         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand
-  lwp $31, 8($4)               # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-                               # FIXME: This ought to point at the $34 but memory is treated as one operand.
-  lwp $16, 8($34)              # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset
-  lwp $16, 4096($4)            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset
-  lwp $16, 8($16)              # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different
-  swp $31, 8($4)               # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
-  swp $16, 8($34)              # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset
-  swp $16, 4096($4)            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset
-  dsll $3, $4, 64              # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate
-  dsll $3, $4, -1              # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate
-  dsll32 $3, $4, 32            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate
-  dsll32 $3, $4, -1            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate
-  dsra $4, $5, 64              # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate
-  dsra $4, $5, -1              # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate
-  dsra32 $4, $5, 32            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate
-  dsra32 $4, $5, -1            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate
-                               # bposge32 is microMIPS DSP instruction
-  bposge32 342                 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
-  bc1eqzc $f32, 4              # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
-  bc1eqzc $f31, -65535         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
-  bc1eqzc $f31, -65537         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
-  bc1eqzc $f31, 65535          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
-  bc1eqzc $f31, 65536          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
-  bc1nezc $f32, 4              # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
-  bc1nezc $f31, -65535         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
-  bc1nezc $f31, -65537         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
-  bc1nezc $f31, 65535          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
-  bc1nezc $f31, 65536          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
-  bc2eqzc $32, 4               # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
-  bc2eqzc $31, -65535          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
-  bc2eqzc $31, -65537          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
-  bc2eqzc $31, 65535           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
-  bc2eqzc $31, 65536           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
-  bc2nezc $32, 4               # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
-  bc2nezc $31, -65535          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
-  bc2nezc $31, -65537          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
-  bc2nezc $31, 65535           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
-  bc2nezc $31, 65536           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
-  andi $3, $4, -1              # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate
-  andi $3, $4, 65536           # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate
-  andi $3, -1                  # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate
-  andi $3, 65536               # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate
-  ori $3, $4, -1               # CHECK: :[[@LINE]]:15: error: expected 16-bit unsigned immediate
-  ori $3, $4, 65536            # CHECK: :[[@LINE]]:15: error: expected 16-bit unsigned immediate
-  ori $3, -1                   # CHECK: :[[@LINE]]:11: error: expected 16-bit unsigned immediate
-  ori $3, 65536                # CHECK: :[[@LINE]]:11: error: expected 16-bit unsigned immediate
-  xori $3, $4, -1              # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate
-  xori $3, $4, 65536           # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate
-  xori $3, -1                  # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate
-  xori $3, 65536               # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate
-  not $3, 4                    # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
-  drotr $5, $10, 64            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate
-  drotr $5, $10, -1            # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 6-bit unsigned immediate
-  drotr32 $1, $2, 32           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate
-  drotr32 $1, $2, -1           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected 5-bit unsigned immediate
-  ld $31, 65536($31)           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
-  ld $31, 32768($31)           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
-  ld $31, -32769($31)          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset
-  sd $31, 65536($31)           # CHECK: :[[@LINE]]:11: error: expected memory with 16-bit signed offset
-  sd $31, 32768($31)           # CHECK: :[[@LINE]]:11: error: expected memory with 16-bit signed offset
-  sd $31, -32769($31)          # CHECK: :[[@LINE]]:11: error: expected memory with 16-bit signed offset
-  lb $32, 8($5)                # CHECK: :[[@LINE]]:6: error: invalid operand for instruction
-  lb $4, -32769($5)            # CHECK: :[[@LINE]]:10: error: expected memory with 16-bit signed offset
-  lb $4, 32768($5)             # CHECK: :[[@LINE]]:10: error: expected memory with 16-bit signed offset
-  lb $4, 8($32)                # CHECK: :[[@LINE]]:10: error: expected memory with 16-bit signed offset
-  lbu $32, 8($5)               # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
-  lbu $4, -32769($5)           # CHECK: :[[@LINE]]:11: error: expected memory with 16-bit signed offset
-  lbu $4, 32768($5)            # CHECK: :[[@LINE]]:11: error: expected memory with 16-bit signed offset
-  lbu $4, 8($32)               # CHECK: :[[@LINE]]:11: error: expected memory with 16-bit signed offset
-  ldc1 $f32, 300($10)          # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
-  ldc1 $f7, -32769($10)        # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset
-  ldc1 $f7, 32768($10)         # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset
-  ldc1 $f7, 300($32)           # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset
-  sdc1 $f32, 64($10)           # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
-  sdc1 $f7, -32769($10)        # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset
-  sdc1 $f7, 32768($10)         # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset
-  sdc1 $f7, 64($32)            # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset
-  lwc1 $f32, 32($5)            # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
-  lwc1 $f2, -32769($5)         # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset
-  lwc1 $f2, 32768($5)          # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset
-  lwc1 $f2, 32($32)            # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset
-  swc1 $f32, 369($13)          # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
-  swc1 $f6, -32769($13)        # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset
-  swc1 $f6, 32768($13)         # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset
-  swc1 $f6, 369($32)           # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset
-  ldc2 $32, 1023($12)          # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
-  sdc2 $32, 8($16)             # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
-  lwc2 $32, 16($4)             # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
-  swc2 $32, 777($17)           # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
-  bgec  $0, $2, 12         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction
-  bgec  $2, $2, 12         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different
-  bgec  $2, $4, -131076    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
-  bgec  $2, $4, -131071    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
-  bgec  $2, $4, 131072     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
-  bgec  $2, $4, 131071     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
-  bltc  $0, $2, 12         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction
-  bltc  $2, $2, 12         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different
-  bltc  $2, $4, -131076    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
-  bltc  $2, $4, -131071    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
-  bltc  $2, $4, 131072     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
-  bltc  $2, $4, 131071     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
-  bgeuc $0, $2, 12         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction
-  bgeuc $2, $2, 12         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different
-  bgeuc  $2, $4, -131076   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
-  bgeuc  $2, $4, -131071   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
-  bgeuc  $2, $4, 131072    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
-  bgeuc  $2, $4, 131071    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
-  bltuc $0, $2, 12         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction
-  bltuc $2, $2, 12         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different
-  bltuc  $2, $4, -131076   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
-  bltuc  $2, $4, -131071   # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
-  bltuc  $2, $4, 131072    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
-  bltuc  $2, $4, 131071    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
-  beqc  $0, $2, 12         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction
-  beqc  $2, $2, 12         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different
-  beqc  $2, $4, -131076    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
-  beqc  $2, $4, -131071    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
-  beqc  $2, $4, 131072     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
-  beqc  $2, $4, 131071     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
-  bnec  $0, $2, 12         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction
-  bnec  $2, $2, 12         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different
-  bnec  $2, $4, -131076    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
-  bnec  $2, $4, -131071    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
-  bnec  $2, $4, 131072     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
-  bnec  $2, $4, 131071     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
-  blezc $0, 12             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction
-  blezc $2, -131076        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
-  blezc $2, -131071        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
-  blezc $2, 131072         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
-  blezc $2, 131071         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
-  bgezc $0, 12             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction
-  bgezc $2, -131076        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
-  bgezc $2, -131071        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
-  bgezc $2, 131072         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
-  bgezc $2, 131071         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
-  bgtzc $0, 12             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction
-  bgtzc $2, -131076        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
-  bgtzc $2, -131071        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
-  bgtzc $2, 131072         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
-  bgtzc $2, 131071         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
-  bltzc $0, 12             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction
-  bltzc $2, -131076        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
-  bltzc $2, -131071        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
-  bltzc $2, 131072         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
-  bltzc $2, 131071         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
-  beqzc $0, 12             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction
-  beqzc $2, -4194308       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
-  beqzc $2, -4194303       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
-  beqzc $2, 4194304        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
-  beqzc $2, 4194303        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
-  bnezc $0, 12             # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction
-  bnezc $2, -4194308       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
-  bnezc $2, -4194303       # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
-  bnezc $2, 4194304        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range
-  bnezc $2, 4194303        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address
-  dlsa $3, $4, $5, 5           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected immediate in range 1 .. 4
-  dlsa $3, $4, $5, -1          # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected immediate in range 1 .. 4
-  dlsa $3, $4, $5, 0           # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected immediate in range 1 .. 4
-  lwupc $2, 262145             # CHECK: :[[@LINE]]:13: error: expected both 19-bit signed immediate and multiple of 4
-  lwupc $2, 5                  # CHECK: :[[@LINE]]:13: error: expected both 19-bit signed immediate and multiple of 4
-  lwupc $2, -262145            # CHECK: :[[@LINE]]:13: error: expected both 19-bit signed immediate and multiple of 4
-  lwupc $2, $2                 # CHECK: :[[@LINE]]:13: error: expected both 19-bit signed immediate and multiple of 4
-  lwupc $2, bar+267            # CHECK: :[[@LINE]]:13: error: expected both 19-bit signed immediate and multiple of 4
-  aui $3, $4, 65536            # CHECK: :[[@LINE]]:15: error: expected 16-bit unsigned immediate
-  aui $3, $4, -32769           # CHECK: :[[@LINE]]:15: error: expected 16-bit unsigned immediate
Index: test/MC/Mips/micromips64r6/relocations.s
===================================================================
--- test/MC/Mips/micromips64r6/relocations.s
+++ /dev/null
@@ -1,48 +0,0 @@
-# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r6 \
-# RUN:   -mattr=micromips | FileCheck %s -check-prefix=CHECK-FIXUP
-# RUN: llvm-mc %s -filetype=obj -triple=mips-unknown-linux -mcpu=mips64r6 \
-# RUN:   -mattr=micromips | llvm-readobj -r | FileCheck %s -check-prefix=CHECK-ELF
-#------------------------------------------------------------------------------
-# Check that the assembler can handle the documented syntax for fixups.
-#------------------------------------------------------------------------------
-# CHECK-FIXUP: balc  bar        # encoding: [0b101101AA,A,A,A]
-# CHECK-FIXUP:                  #   fixup A - offset: 0,
-# CHECK-FIXUP:                      value: bar-4, kind: fixup_MICROMIPS_PC26_S1
-# CHECK-FIXUP: bc    bar        # encoding: [0b100101AA,A,A,A]
-# CHECK-FIXUP:                  #   fixup A - offset: 0,
-# CHECK-FIXUP:                      value: bar-4, kind: fixup_MICROMIPS_PC26_S1
-# CHECK-FIXUP: addiupc $2, bar  # encoding: [0x78,0b01000AAA,A,A]
-# CHECK-FIXUP:                  #   fixup A - offset: 0,
-# CHECK-FIXUP:                      value: bar, kind: fixup_MICROMIPS_PC19_S2
-# CHECK-FIXUP: lwpc    $2,  bar # encoding: [0x78,0b01001AAA,A,A]
-# CHECK-FIXUP:                  #   fixup A - offset: 0,
-# CHECK-FIXUP:                      value: bar, kind: fixup_MICROMIPS_PC19_S2
-# CHECK-FIXUP: ldpc  $2, bar    # encoding: [0x78,0b010110AA,A,A]
-# CHECK-FIXUP:                  #   fixup A - offset: 0,
-# CHECK-FIXUP:                      value: bar, kind: fixup_MICROMIPS_PC18_S3
-# CHECK-FIXUP: beqzc $3, bar        # encoding: [0x80,0b011AAAAA,A,A]
-# CHECK-FIXUP:                      #   fixup A - offset: 0,
-# CHECK-FIXUP:                          value: bar-4, kind: fixup_MICROMIPS_PC21_S1
-# CHECK-FIXUP: bnezc $3, bar        # encoding: [0xa0,0b011AAAAA,A,A]
-# CHECK-FIXUP:                      #   fixup A - offset: 0,
-# CHECK-FIXUP:                          value: bar-4, kind: fixup_MICROMIPS_PC21_S1
-#------------------------------------------------------------------------------
-# Check that the appropriate relocations were created.
-#------------------------------------------------------------------------------
-# CHECK-ELF: Relocations [
-# CHECK-ELF:     0x0 R_MICROMIPS_PC26_S1 bar 0x0
-# CHECK-ELF:     0x4 R_MICROMIPS_PC26_S1 bar 0x0
-# CHECK-ELF:     0x8 R_MICROMIPS_PC19_S2 bar 0x0
-# CHECK-ELF:     0xC R_MICROMIPS_PC19_S2 bar 0x0
-# CHECK-ELF:     0x10 R_MICROMIPS_PC18_S3 bar 0x0
-# CHECK-ELF:     0x14 R_MICROMIPS_PC21_S1 bar 0x0
-# CHECK-ELF:     0x18 R_MICROMIPS_PC21_S1 bar 0x0
-# CHECK-ELF: ]
-
-  balc  bar
-  bc    bar
-  addiupc $2,bar
-  lwpc    $2,bar
-  ldpc  $2, bar
-  beqzc  $3, bar
-  bnezc  $3, bar
Index: test/MC/Mips/micromips64r6/valid.s
===================================================================
--- test/MC/Mips/micromips64r6/valid.s
+++ /dev/null
@@ -1,350 +0,0 @@
-# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r6 -mattr=micromips | FileCheck %s
-a:
-        .set noat
-        addiur1sp $7, 4          # CHECK: addiur1sp $7, 4     # encoding: [0x6f,0x83]
-        addiur2 $6, $7, -1       # CHECK: addiur2 $6, $7, -1  # encoding: [0x6f,0x7e]
-        addiur2 $6, $7, 12       # CHECK: addiur2 $6, $7, 12  # encoding: [0x6f,0x76]
-        addius5 $7, -2           # CHECK: addius5 $7, -2      # encoding: [0x4c,0xfc]
-        addiusp -1028            # CHECK: addiusp -1028       # encoding: [0x4f,0xff]
-        addiusp -1032            # CHECK: addiusp -1032       # encoding: [0x4f,0xfd]
-        addiusp 1024             # CHECK: addiusp 1024        # encoding: [0x4c,0x01]
-        addiusp 1028             # CHECK: addiusp 1028        # encoding: [0x4c,0x03]
-        addiusp -16              # CHECK: addiusp -16         # encoding: [0x4f,0xf9]
-        and16 $16, $2            # CHECK: and16 $16, $2       # encoding: [0x44,0x21]
-        andi16 $4, $5, 8         # CHECK: andi16 $4, $5, 8    # encoding: [0x2e,0x56]
-        b 132                    # CHECK: bc16 132            # encoding: [0xcc,0x42]
-        bc16 132                 # CHECK: bc16 132            # encoding: [0xcc,0x42]
-        beqzc16 $6, 20           # CHECK: beqzc16 $6, 20      # encoding: [0x8f,0x0a]
-        bnezc16 $6, 20           # CHECK: bnezc16 $6, 20      # encoding: [0xaf,0x0a]
-        aui $4, $5, 1            # CHECK: aui $4, $5, 1       # encoding: [0x10,0x85,0x00,0x01]
-        daui $3, $4, 5           # CHECK: daui $3, $4, 5      # encoding: [0xf0,0x64,0x00,0x05]
-        dahi $3, $3, 4           # CHECK: dahi $3, $3, 4      # encoding: [0x42,0x23,0x00,0x04]
-        dati $3, $3, 4           # CHECK: dati $3, $3, 4      # encoding: [0x42,0x03,0x00,0x04]
-        dext $9, $6, 3, 7        # CHECK: dext $9, $6, 3, 7   # encoding: [0x59,0x26,0x30,0xec]
-        dextm $9, $6, 3, 39      # CHECK: dextm $9, $6, 3, 39 # encoding: [0x59,0x26,0x30,0xe4]
-        dextu $9, $6, 35, 7      # CHECK: dextu $9, $6, 35, 7  # encoding: [0x59,0x26,0x30,0xd4]
-        dalign $4, $2, $3, 5     # CHECK: dalign $4, $2, $3, 5  # encoding: [0x58,0x43,0x25,0x1c]
-        dsll $4, $5              # CHECK: dsllv $4, $4, $5      # encoding: [0x58,0x85,0x20,0x10]
-        dsll $4, $4, $5          # CHECK: dsllv $4, $4, $5      # encoding: [0x58,0x85,0x20,0x10]
-        dsrl $4, $5              # CHECK: dsrlv $4, $4, $5      # encoding: [0x58,0x85,0x20,0x50]
-        dsrl $4, $4, $5          # CHECK: dsrlv $4, $4, $5      # encoding: [0x58,0x85,0x20,0x50]
-        ldpc $2, 16              # CHECK: ldpc $2, 16           # encoding: [0x78,0x58,0x00,0x02]
-        lw $3, 32($gp)           # CHECK: lw $3, 32($gp)        # encoding: [0x65,0x88]
-        lw $3, 24($sp)           # CHECK: lw $3, 24($sp)        # encoding: [0x48,0x66]
-        lw16 $4, 8($17)          # CHECK: lw16 $4, 8($17)       # encoding: [0x6a,0x12]
-        lhu16 $3, 4($16)         # CHECK: lhu16 $3, 4($16)      # encoding: [0x29,0x82]
-        lbu16 $3, 4($17)         # CHECK: lbu16 $3, 4($17)      # encoding: [0x09,0x94]
-        lbu16 $3, -1($17)        # CHECK: lbu16 $3, -1($17)     # encoding: [0x09,0x9f]
-        movep $5, $6, $2, $3     # CHECK: movep $5, $6, $2, $3  # encoding: [0x84,0x34]
-        not16 $4, $7             # CHECK: not16 $4, $7          # encoding: [0x46,0x70]
-        or16 $3, $7              # CHECK: or16 $3, $7           # encoding: [0x45,0xf9]
-        ll $2, 8($4)                    # CHECK: ll $2, 8($4)                    # encoding: [0x60,0x44,0x30,0x08]
-        lwm32 $16, $17, 8($4)           # CHECK: lwm32 $16, $17, 8($4)           # encoding: [0x20,0x44,0x50,0x08]
-        lwm32 $16, $17, 8($sp)          # CHECK: lwm32 $16, $17, 8($sp)          # encoding: [0x20,0x5d,0x50,0x08]
-        lwm32 $16, $17, $ra, 8($4)      # CHECK: lwm32 $16, $17, $ra, 8($4)      # encoding: [0x22,0x44,0x50,0x08]
-        lwm32 $16, $17, $ra, 64($sp)    # CHECK: lwm32 $16, $17, $ra, 64($sp)    # encoding: [0x22,0x5d,0x50,0x40]
-        lwm32 $16, $17, $18, $19, 8($4) # CHECK: lwm32 $16, $17, $18, $19, 8($4) # encoding: [0x20,0x84,0x50,0x08]
-        lwm32 $16, $17, $18, $19, $ra, 8($4)                          # CHECK: lwm32 $16, $17, $18, $19, $ra, 8($4)                          # encoding: [0x22,0x84,0x50,0x08]
-        lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, 8($4)      # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, 8($4)      # encoding: [0x21,0x24,0x50,0x08]
-        lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # encoding: [0x23,0x24,0x50,0x08]
-        lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # CHECK: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # encoding: [0x23,0x24,0x50,0x08]
-        rotr $2, 7                      # CHECK: rotr $2, $2, 7                  # encoding: [0x00,0x42,0x38,0xc0]
-        rotr $9, $6, 7                  # CHECK: rotr $9, $6, 7                  # encoding: [0x01,0x26,0x38,0xc0]
-        rotrv $9, $6, $7                # CHECK: rotrv $9, $6, $7                # encoding: [0x00,0xc7,0x48,0xd0]
-        sc $2, 8($4)                    # CHECK: sc $2, 8($4)                    # encoding: [0x60,0x44,0xb0,0x08]
-        seb $3, $4                      # CHECK: seb $3, $4                      # encoding: [0x00,0x64,0x2b,0x3c]
-        seb $3                          # CHECK: seb $3, $3                      # encoding: [0x00,0x63,0x2b,0x3c]
-        seh $3, $4                      # CHECK: seh $3, $4                      # encoding: [0x00,0x64,0x3b,0x3c]
-        seh $3                          # CHECK: seh $3, $3                      # encoding: [0x00,0x63,0x3b,0x3c]
-        sgt $4, $5, $6                  # CHECK: slt $4, $6, $5                  # encoding: [0x00,0xa6,0x23,0x50]
-        sgtu $4, $5, $6                 # CHECK: sltu $4, $6, $5                 # encoding: [0x00,0xa6,0x23,0x90]
-        sll $4, $5                      # CHECK: sllv $4, $4, $5                 # encoding: [0x00,0x85,0x20,0x10]
-        sra $4, $5                      # CHECK: srav $4, $4, $5                 # encoding: [0x00,0x85,0x20,0x90]
-        srl $4, $5                      # CHECK: srlv $4, $4, $5                 # encoding: [0x00,0x85,0x20,0x50]
-        swm32 $16, $17, 8($4)           # CHECK: swm32 $16, $17, 8($4)           # encoding: [0x20,0x44,0xd0,0x08]
-        swm32 $16, $17, 8($sp)          # CHECK: swm32 $16, $17, 8($sp)          # encoding: [0x20,0x5d,0xd0,0x08]
-        swm32 $16, $17, $ra, 8($4)      # CHECK: swm32 $16, $17, $ra, 8($4)      # encoding: [0x22,0x44,0xd0,0x08]
-        swm32 $16, $17, $ra, 64($sp)    # CHECK: swm32 $16, $17, $ra, 64($sp)    # encoding: [0x22,0x5d,0xd0,0x40]
-        swm32 $16, $17, $18, $19, 8($4) # CHECK: swm32 $16, $17, $18, $19, 8($4) # encoding: [0x20,0x84,0xd0,0x08]
-        syscall                         # CHECK: syscall                         # encoding: [0x00,0x00,0x8b,0x7c]
-        syscall 396                     # CHECK: syscall 396                     # encoding: [0x01,0x8c,0x8b,0x7c]
-        ddiv $3, $4, $5          # CHECK: ddiv $3, $4, $5     # encoding: [0x58,0xa4,0x19,0x18]
-        dmod $3, $4, $5          # CHECK: dmod $3, $4, $5     # encoding: [0x58,0xa4,0x19,0x58]
-        ddivu $3, $4, $5         # CHECK: ddivu $3, $4, $5    # encoding: [0x58,0xa4,0x19,0x98]
-        dmodu $3, $4, $5         # CHECK: dmodu $3, $4, $5    # encoding: [0x58,0xa4,0x19,0xd8]
-        add.s $f3, $f4, $f5      # CHECK: add.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0x30]
-        add.d $f2, $f4, $f6      # CHECK: add.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0x30]
-        sub.s $f3, $f4, $f5      # CHECK: sub.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0x70]
-        sub.d $f2, $f4, $f6      # CHECK: sub.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0x70]
-        mul.s $f3, $f4, $f5      # CHECK: mul.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0xb0]
-        mul.d $f2, $f4, $f6      # CHECK: mul.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0xb0]
-        div.s $f3, $f4, $f5      # CHECK: div.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x18,0xf0]
-        div.d $f2, $f4, $f6      # CHECK: div.d $f2, $f4, $f6 # encoding: [0x54,0xc4,0x11,0xf0]
-        maddf.s $f3, $f4, $f5    # CHECK: maddf.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x19,0xb8]
-        maddf.d $f3, $f4, $f5    # CHECK: maddf.d $f3, $f4, $f5 # encoding: [0x54,0xa4,0x1b,0xb8]
-        msubf.s $f3, $f4, $f5    # CHECK: msubf.s $f3, $f4, $f5 # encoding: [0x54,0xa4,0x19,0xf8]
-        msubf.d $f3, $f4, $f5    # CHECK: msubf.d $f3, $f4, $f5 # encoding: [0x54,0xa4,0x1b,0xf8]
-        mov.s $f6, $f7           # CHECK: mov.s $f6, $f7      # encoding: [0x54,0xc7,0x00,0x7b]
-        mov.d $f4, $f6           # CHECK: mov.d $f4, $f6      # encoding: [0x54,0x86,0x20,0x7b]
-        neg.s $f6, $f7           # CHECK: neg.s $f6, $f7      # encoding: [0x54,0xc7,0x0b,0x7b]
-        neg.d $f4, $f6           # CHECK: neg.d $f4, $f6      # encoding: [0x54,0x86,0x2b,0x7b]
-        max.s $f5, $f4, $f3      # CHECK: max.s $f5, $f4, $f3      # encoding: [0x54,0x64,0x28,0x0b]
-        max.d $f5, $f4, $f3      # CHECK: max.d $f5, $f4, $f3      # encoding: [0x54,0x64,0x2a,0x0b]
-        maxa.s $f5, $f4, $f3     # CHECK: maxa.s $f5, $f4, $f3     # encoding: [0x54,0x64,0x28,0x2b]
-        maxa.d $f5, $f4, $f3     # CHECK: maxa.d $f5, $f4, $f3     # encoding: [0x54,0x64,0x2a,0x2b]
-        min.s $f5, $f4, $f3      # CHECK: min.s $f5, $f4, $f3      # encoding: [0x54,0x64,0x28,0x03]
-        min.d $f5, $f4, $f3      # CHECK: min.d $f5, $f4, $f3      # encoding: [0x54,0x64,0x2a,0x03]
-        mina.s $f5, $f4, $f3     # CHECK: mina.s $f5, $f4, $f3     # encoding: [0x54,0x64,0x28,0x23]
-        mina.d $f5, $f4, $f3     # CHECK: mina.d $f5, $f4, $f3     # encoding: [0x54,0x64,0x2a,0x23]
-        cmp.af.s $f2, $f3, $f4   # CHECK: cmp.af.s $f2, $f3, $f4   # encoding: [0x54,0x83,0x10,0x05]
-        cmp.af.d $f2, $f3, $f4   # CHECK: cmp.af.d $f2, $f3, $f4   # encoding: [0x54,0x83,0x10,0x15]
-        cmp.un.s $f2, $f3, $f4   # CHECK: cmp.un.s $f2, $f3, $f4   # encoding: [0x54,0x83,0x10,0x45]
-        cmp.un.d $f2, $f3, $f4   # CHECK: cmp.un.d $f2, $f3, $f4   # encoding: [0x54,0x83,0x10,0x55]
-        cmp.eq.s $f2, $f3, $f4   # CHECK: cmp.eq.s $f2, $f3, $f4   # encoding: [0x54,0x83,0x10,0x85]
-        cmp.eq.d $f2, $f3, $f4   # CHECK: cmp.eq.d $f2, $f3, $f4   # encoding: [0x54,0x83,0x10,0x95]
-        cmp.ueq.s $f2, $f3, $f4  # CHECK: cmp.ueq.s $f2, $f3, $f4  # encoding: [0x54,0x83,0x10,0xc5]
-        cmp.ueq.d $f2, $f3, $f4  # CHECK: cmp.ueq.d $f2, $f3, $f4  # encoding: [0x54,0x83,0x10,0xd5]
-        cmp.lt.s $f2, $f3, $f4   # CHECK: cmp.lt.s  $f2, $f3, $f4  # encoding: [0x54,0x83,0x11,0x05]
-        cmp.lt.d $f2, $f3, $f4   # CHECK: cmp.lt.d  $f2, $f3, $f4  # encoding: [0x54,0x83,0x11,0x15]
-        cmp.ult.s $f2, $f3, $f4  # CHECK: cmp.ult.s $f2, $f3, $f4  # encoding: [0x54,0x83,0x11,0x45]
-        cmp.ult.d $f2, $f3, $f4  # CHECK: cmp.ult.d $f2, $f3, $f4  # encoding: [0x54,0x83,0x11,0x55]
-        cmp.le.s $f2, $f3, $f4   # CHECK: cmp.le.s  $f2, $f3, $f4  # encoding: [0x54,0x83,0x11,0x85]
-        cmp.le.d $f2, $f3, $f4   # CHECK: cmp.le.d  $f2, $f3, $f4  # encoding: [0x54,0x83,0x11,0x95]
-        cmp.ule.s $f2, $f3, $f4  # CHECK: cmp.ule.s $f2, $f3, $f4  # encoding: [0x54,0x83,0x11,0xc5]
-        cmp.ule.d $f2, $f3, $f4  # CHECK: cmp.ule.d $f2, $f3, $f4  # encoding: [0x54,0x83,0x11,0xd5]
-        cmp.saf.s $f2, $f3, $f4  # CHECK: cmp.saf.s $f2, $f3, $f4  # encoding: [0x54,0x83,0x12,0x05]
-        cmp.saf.d $f2, $f3, $f4  # CHECK: cmp.saf.d $f2, $f3, $f4  # encoding: [0x54,0x83,0x12,0x15]
-        cmp.sun.s $f2, $f3, $f4  # CHECK: cmp.sun.s $f2, $f3, $f4  # encoding: [0x54,0x83,0x12,0x45]
-        cmp.sun.d $f2, $f3, $f4  # CHECK: cmp.sun.d $f2, $f3, $f4  # encoding: [0x54,0x83,0x12,0x55]
-        cmp.seq.s $f2, $f3, $f4  # CHECK: cmp.seq.s $f2, $f3, $f4  # encoding: [0x54,0x83,0x12,0x85]
-        cmp.seq.d $f2, $f3, $f4  # CHECK: cmp.seq.d $f2, $f3, $f4  # encoding: [0x54,0x83,0x12,0x95]
-        cmp.sueq.s $f2, $f3, $f4 # CHECK: cmp.sueq.s $f2, $f3, $f4 # encoding: [0x54,0x83,0x12,0xc5]
-        cmp.sueq.d $f2, $f3, $f4 # CHECK: cmp.sueq.d $f2, $f3, $f4 # encoding: [0x54,0x83,0x12,0xd5]
-        cmp.slt.s $f2, $f3, $f4  # CHECK: cmp.slt.s $f2, $f3, $f4  # encoding: [0x54,0x83,0x13,0x05]
-        cmp.slt.d $f2, $f3, $f4  # CHECK: cmp.slt.d $f2, $f3, $f4  # encoding: [0x54,0x83,0x13,0x15]
-        cmp.sult.s $f2, $f3, $f4 # CHECK: cmp.sult.s $f2, $f3, $f4 # encoding: [0x54,0x83,0x13,0x45]
-        cmp.sult.d $f2, $f3, $f4 # CHECK: cmp.sult.d $f2, $f3, $f4 # encoding: [0x54,0x83,0x13,0x55]
-        cmp.sle.s $f2, $f3, $f4  # CHECK: cmp.sle.s $f2, $f3, $f4  # encoding: [0x54,0x83,0x13,0x85]
-        cmp.sle.d $f2, $f3, $f4  # CHECK: cmp.sle.d $f2, $f3, $f4  # encoding: [0x54,0x83,0x13,0x95]
-        cmp.sule.s $f2, $f3, $f4 # CHECK: cmp.sule.s $f2, $f3, $f4 # encoding: [0x54,0x83,0x13,0xc5]
-        cmp.sule.d $f2, $f3, $f4 # CHECK: cmp.sule.d $f2, $f3, $f4 # encoding: [0x54,0x83,0x13,0xd5]
-        cvt.l.s $f3, $f4         # CHECK: cvt.l.s $f3, $f4         # encoding: [0x54,0x64,0x01,0x3b]
-        cvt.l.d $f3, $f4         # CHECK: cvt.l.d $f3, $f4         # encoding: [0x54,0x64,0x41,0x3b]
-        cvt.w.s $f3, $f4         # CHECK: cvt.w.s $f3, $f4         # encoding: [0x54,0x64,0x09,0x3b]
-        cvt.w.d $f3, $f4         # CHECK: cvt.w.d $f3, $f4         # encoding: [0x54,0x64,0x49,0x3b]
-        cvt.d.s $f2, $f4         # CHECK: cvt.d.s $f2, $f4         # encoding: [0x54,0x44,0x13,0x7b]
-        cvt.d.w $f2, $f4         # CHECK: cvt.d.w $f2, $f4         # encoding: [0x54,0x44,0x33,0x7b]
-        cvt.d.l $f2, $f4         # CHECK: cvt.d.l $f2, $f4         # encoding: [0x54,0x44,0x53,0x7b]
-        cvt.s.d $f2, $f4         # CHECK: cvt.s.d $f2, $f4         # encoding: [0x54,0x44,0x1b,0x7b]
-        cvt.s.w $f3, $f4         # CHECK: cvt.s.w $f3, $f4         # encoding: [0x54,0x64,0x3b,0x7b]
-        cvt.s.l $f3, $f4         # CHECK: cvt.s.l $f3, $f4         # encoding: [0x54,0x64,0x5b,0x7b]
-        teq $8, $9               # CHECK: teq $8, $9          # encoding: [0x01,0x28,0x00,0x3c]
-        teq $5, $7, 15           # CHECK: teq $5, $7, 15      # encoding: [0x00,0xe5,0xf0,0x3c]
-        tge $7, $10              # CHECK: tge $7, $10         # encoding: [0x01,0x47,0x02,0x3c]
-        tge $7, $19, 15          # CHECK: tge $7, $19, 15     # encoding: [0x02,0x67,0xf2,0x3c]
-        tgeu $22, $gp            # CHECK: tgeu $22, $gp       # encoding: [0x03,0x96,0x04,0x3c]
-        tgeu $20, $14, 15        # CHECK: tgeu $20, $14, 15   # encoding: [0x01,0xd4,0xf4,0x3c]
-        tlt $15, $13             # CHECK: tlt $15, $13        # encoding: [0x01,0xaf,0x08,0x3c]
-        tlt $2, $19, 15          # CHECK: tlt $2, $19, 15     # encoding: [0x02,0x62,0xf8,0x3c]
-        tltu $11, $16            # CHECK: tltu $11, $16       # encoding: [0x02,0x0b,0x0a,0x3c]
-        tltu $16, $sp, 15        # CHECK: tltu $16, $sp, 15   # encoding: [0x03,0xb0,0xfa,0x3c]
-        tne $6, $17              # CHECK: tne $6, $17         # encoding: [0x02,0x26,0x0c,0x3c]
-        tne $7, $8, 15           # CHECK: tne $7, $8, 15      # encoding: [0x01,0x07,0xfc,0x3c]
-        cachee 1, 8($5)          # CHECK: cachee 1, 8($5)     # encoding: [0x60,0x25,0xa6,0x08]
-        wrpgpr $3, $4            # CHECK: wrpgpr $3, $4       # encoding: [0x00,0x64,0xf1,0x7c]
-        wsbh $3, $4              # CHECK: wsbh $3, $4         # encoding: [0x00,0x64,0x7b,0x3c]
-        jalr $9                  # CHECK: jalr $9             # encoding: [0x45,0x2b]
-        jrc16 $9                 # CHECK: jrc16 $9            # encoding: [0x45,0x23]
-        jrcaddiusp 20            # CHECK: jrcaddiusp 20       # encoding: [0x44,0xb3]
-        break16 8                # CHECK: break16 8                # encoding: [0x46,0x1b]
-        li16 $3, -1              # CHECK: li16 $3, -1              # encoding: [0xed,0xff]
-        move16 $3, $5            # CHECK: move16 $3, $5            # encoding: [0x0c,0x65]
-        sdbbp16 8                # CHECK: sdbbp16 8                # encoding: [0x46,0x3b]
-        subu16 $5, $16, $3       # CHECK: subu16 $5, $16, $3       # encoding: [0x04,0x3b]
-        xor16 $17, $5            # CHECK: xor16 $17, $5            # encoding: [0x44,0xd8]
-        lwm $16, $17, $ra, 8($sp)   # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x22]
-        lwm16 $16, $17, $ra, 8($sp) # CHECK: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x22]
-        sb16 $3, 4($16)          # CHECK: sb16 $3, 4($16)     # encoding: [0x89,0x84]
-        sh16 $4, 8($17)          # CHECK: sh16 $4, 8($17)     # encoding: [0xaa,0x14]
-        sw $4, 124($sp)          # CHECK: sw $4, 124($sp)     # encoding: [0xc8,0x9f]
-        sw16 $4, 4($17)          # CHECK: sw16 $4, 4($17)     # encoding: [0xea,0x11]
-        sw16 $0, 4($17)          # CHECK: sw16 $zero, 4($17)  # encoding: [0xe8,0x11]
-        swm $16, $17, $ra, 8($sp)   # CHECK: swm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x2a]
-        swm16 $16, $17, $ra, 8($sp) # CHECK: swm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x2a]
-        recip.s $f2, $f4         # CHECK: recip.s $f2, $f4    # encoding: [0x54,0x44,0x12,0x3b]
-        recip.d $f2, $f4         # CHECK: recip.d $f2, $f4    # encoding: [0x54,0x44,0x52,0x3b]
-        rint.s $f2, $f4          # CHECK: rint.s $f2, $f4     # encoding: [0x54,0x82,0x00,0x20]
-        rint.d $f2, $f4          # CHECK: rint.d $f2, $f4     # encoding: [0x54,0x82,0x02,0x20]
-        round.l.s $f2, $f4       # CHECK: round.l.s $f2, $f4  # encoding: [0x54,0x44,0x33,0x3b]
-        round.l.d $f2, $f4       # CHECK: round.l.d $f2, $f4  # encoding: [0x54,0x44,0x73,0x3b]
-        round.w.s $f2, $f4       # CHECK: round.w.s $f2, $f4  # encoding: [0x54,0x44,0x3b,0x3b]
-        round.w.d $f2, $f4       # CHECK: round.w.d $f2, $f4  # encoding: [0x54,0x44,0x7b,0x3b]
-        sel.s $f1, $f1, $f2      # CHECK: sel.s $f1, $f1, $f2 # encoding: [0x54,0x41,0x08,0xb8]
-        sel.d $f0, $f2, $f4      # CHECK: sel.d $f0, $f2, $f4 # encoding: [0x54,0x82,0x02,0xb8]
-        seleqz.s $f1, $f2, $f3   # CHECK: seleqz.s $f1, $f2, $f3  # encoding: [0x54,0x62,0x08,0x38]
-        seleqz.d $f2, $f4, $f8   # CHECK: seleqz.d $f2, $f4, $f8  # encoding: [0x55,0x04,0x12,0x38]
-        selnez.s $f1, $f2, $f3   # CHECK: selnez.s $f1, $f2, $f3  # encoding: [0x54,0x62,0x08,0x78]
-        selnez.d $f2, $f4, $f8   # CHECK: selnez.d $f2, $f4, $f8  # encoding: [0x55,0x04,0x12,0x78]
-        class.s $f2, $f3         # CHECK: class.s $f2, $f3        # encoding: [0x54,0x62,0x00,0x60]
-        class.d $f2, $f4         # CHECK: class.d $f2, $f4        # encoding: [0x54,0x82,0x02,0x60]
-        deret                    # CHECK: deret                   # encoding: [0x00,0x00,0xe3,0x7c]
-        di                       # CHECK: di                      # encoding: [0x00,0x00,0x47,0x7c]
-        di $0                    # CHECK: di                      # encoding: [0x00,0x00,0x47,0x7c]
-        di $15                   # CHECK: di $15                  # encoding: [0x00,0x0f,0x47,0x7c]
-        ceil.l.s $f1, $f3        # CHECK: ceil.l.s $f1, $f3       # encoding: [0x54,0x23,0x13,0x3b]
-        ceil.l.d $f1, $f3        # CHECK: ceil.l.d $f1, $f3       # encoding: [0x54,0x23,0x53,0x3b]
-        floor.l.s $f1, $f3       # CHECK: floor.l.s $f1, $f3      # encoding: [0x54,0x23,0x03,0x3b]
-        floor.l.d $f1, $f3       # CHECK: floor.l.d $f1, $f3      # encoding: [0x54,0x23,0x43,0x3b]
-        tlbinv                   # CHECK: tlbinv                  # encoding: [0x00,0x00,0x43,0x7c]
-        tlbinvf                  # CHECK: tlbinvf                 # encoding: [0x00,0x00,0x53,0x7c]
-        dinsu $4, $2, 32, 5      # CHECK: dinsu $4, $2, 32, 5     # encoding: [0x58,0x82,0x20,0x34]
-        dinsm $4, $2, 3, 5       # CHECK: dinsm $4, $2, 3, 5      # encoding: [0x58,0x82,0x38,0xc4]
-        dins $4, $2, 3, 5        # CHECK: dins $4, $2, 3, 5       # encoding: [0x58,0x82,0x38,0xcc]
-        lh $2, 8($4)             # CHECK: lh $2, 8($4)            # encoding: [0x3c,0x44,0x00,0x08]
-        lhe $4, 8($2)            # CHECK: lhe $4, 8($2)           # encoding: [0x60,0x82,0x6a,0x08]
-        lhu $4, 8($2)            # CHECK: lhu $4, 8($2)           # encoding: [0x34,0x82,0x00,0x08]
-        lhue $4, 8($2)           # CHECK: lhue $4, 8($2)          # encoding: [0x60,0x82,0x62,0x08]
-        mtc0 $5, $9              # CHECK: mtc0 $5, $9, 0          # encoding: [0x00,0xa9,0x02,0xfc]
-        mtc0 $1, $2, 7           # CHECK: mtc0 $1, $2, 7          # encoding: [0x00,0x22,0x3a,0xfc]
-        mtc1 $3, $f4             # CHECK: mtc1 $3, $f4            # encoding: [0x54,0x64,0x28,0x3b]
-        mtc2 $5, $6              # CHECK: mtc2 $5, $6             # encoding: [0x00,0xa6,0x5d,0x3c]
-        mthc0 $7, $8             # CHECK: mthc0 $7, $8, 0         # encoding: [0x00,0xe8,0x02,0xf4]
-        mthc0 $9, $10, 1         # CHECK: mthc0 $9, $10, 1        # encoding: [0x01,0x2a,0x0a,0xf4]
-        mthc1 $11, $f12          # CHECK: mthc1 $11, $f12         # encoding: [0x55,0x6c,0x38,0x3b]
-        mthc2 $13, $14           # CHECK: mthc2 $13, $14          # encoding: [0x01,0xae,0x9d,0x3c]
-        dmtc0 $15, $16           # CHECK: dmtc0 $15, $16, 0       # encoding: [0x59,0xf0,0x02,0xfc]
-        dmtc0 $17, $18, 5        # CHECK: dmtc0 $17, $18, 5       # encoding: [0x5a,0x32,0x2a,0xfc]
-        dmtc1 $19, $f20          # CHECK: dmtc1 $19, $f20         # encoding: [0x56,0x74,0x2c,0x3b]
-        dmtc2 $21, $22           # CHECK: dmtc2 $21, $22          # encoding: [0x02,0xb6,0x7d,0x3c]
-        dmfc0 $18, $17           # CHECK: dmfc0 $18, $17, 0       # encoding: [0x5a,0x51,0x00,0xfc]
-        dmfc0 $9, $1, 1          # CHECK: dmfc0 $9, $1, 1         # encoding: [0x59,0x21,0x08,0xfc]
-        dmfc1 $9, $f4            # CHECK: dmfc1 $9, $f4           # encoding: [0x55,0x24,0x24,0x3b]
-        dmfc2 $14, $18           # CHECK: dmfc2 $14, $18          # encoding: [0x01,0xd2,0x6d,0x3c]
-        dadd $9, $6, $7          # CHECK: dadd $9, $6, $7         # encoding: [0x58,0xe6,0x49,0x10]
-        dadd $s3, $at, $ra       # CHECK: dadd $19, $1, $ra       # encoding: [0x5b,0xe1,0x99,0x10]
-        daddiu $24, $2, 18079    # CHECK: daddiu $24, $2, 18079   # encoding: [0x5f,0x02,0x46,0x9f]
-        daddiu $9, $6, -15001    # CHECK: daddiu $9, $6, -15001   # encoding: [0x5d,0x26,0xc5,0x67]
-        daddiu $9, -15001        # CHECK: daddiu $9, $9, -15001   # encoding: [0x5d,0x29,0xc5,0x67]
-        daddiu $9, $3, 8 * 4     # CHECK: daddiu $9, $3, 32       # encoding: [0x5d,0x23,0x00,0x20]
-        daddiu $9, $3, (8 * 4)   # CHECK: daddiu $9, $3, 32       # encoding: [0x5d,0x23,0x00,0x20]
-        daddiu $k0, $s6, -4586   # CHECK: daddiu $26, $22, -4586  # encoding: [0x5f,0x56,0xee,0x16]
-        daddiu $15, $11, -5025   # CHECK: daddiu $15, $11, -5025  # encoding: [0x5d,0xeb,0xec,0x5f]
-        daddiu $14, $14, 4586    # CHECK: daddiu $14, $14, 4586   # encoding: [0x5d,0xce,0x11,0xea]
-        daddiu $19, $19, 26943   # CHECK: daddiu $19, $19, 26943  # encoding: [0x5e,0x73,0x69,0x3f]
-        daddiu $11, $26, 31949   # CHECK: daddiu $11, $26, 31949  # encoding: [0x5d,0x7a,0x7c,0xcd]
-        daddiu $sp, $sp, -32     # CHECK: daddiu $sp, $sp, -32    # encoding: [0x5f,0xbd,0xff,0xe0]
-        daddu $26, $1, $11       # CHECK: daddu $26, $1, $11      # encoding: [0x59,0x61,0xd1,0x50]
-        daddu $19, $1, $ra       # CHECK: daddu $19, $1, $ra      # encoding: [0x5b,0xe1,0x99,0x50]
-        daddu $9, $6, $7         # CHECK: daddu $9, $6, $7        # encoding: [0x58,0xe6,0x49,0x50]
-        daddu $9, $3             # CHECK: daddu $9, $9, $3        # encoding: [0x58,0x69,0x49,0x50]
-        daddu $9, $6, -15001     # CHECK: daddiu $9, $6, -15001   # encoding: [0x5d,0x26,0xc5,0x67]
-        daddu $9, 10             # CHECK: daddiu $9, $9, 10       # encoding: [0x5d,0x29,0x00,0x0a]
-        daddu $19, 26943         # CHECK: daddiu $19, $19, 26943  # encoding: [0x5e,0x73,0x69,0x3f]
-        daddu $24, $2, 18079     # CHECK: daddiu $24, $2, 18079   # encoding: [0x5f,0x02,0x46,0x9f]
-        dsubu $3, 5              # CHECK: daddiu $3, $3, -5       # encoding: [0x5c,0x63,0xff,0xfb]
-        dsubu $3, $4, 5          # CHECK: daddiu $3, $4, -5       # encoding: [0x5c,0x64,0xff,0xfb]
-        tlbp                     # CHECK: tlbp                    # encoding: [0x00,0x00,0x03,0x7c]
-        tlbr                     # CHECK: tlbr                    # encoding: [0x00,0x00,0x13,0x7c]
-        tlbwi                    # CHECK: tlbwi                   # encoding: [0x00,0x00,0x23,0x7c]
-        tlbwr                    # CHECK: tlbwr                   # encoding: [0x00,0x00,0x33,0x7c]
-        dvp                      # CHECK: dvp $zero               # encoding: [0x00,0x00,0x19,0x7c]
-        dvp $4                   # CHECK: dvp $4                  # encoding: [0x00,0x04,0x19,0x7c]
-        evp                      # CHECK: evp $zero               # encoding: [0x00,0x00,0x39,0x7c]
-        evp $4                   # CHECK: evp $4                  # encoding: [0x00,0x04,0x39,0x7c]
-        jalrc.hb $4              # CHECK: jalrc.hb $4             # encoding: [0x03,0xe4,0x1f,0x3c]
-        jalrc.hb $4, $5          # CHECK: jalrc.hb $4, $5         # encoding: [0x00,0x85,0x1f,0x3c]
-        sllv $2, $3, $5          # CHECK: sllv $2, $3, $5         # encoding: [0x00,0x65,0x10,0x10]
-        sra $4, $3, 7            # CHECK: sra $4, $3, 7           # encoding: [0x00,0x83,0x38,0x80]
-        srav $2, $3, $5          # CHECK: srav $2, $3, $5         # encoding: [0x00,0x65,0x10,0x90]
-        srl $4, $3, 7            # CHECK: srl $4, $3, 7           # encoding: [0x00,0x83,0x38,0x40]
-        srlv $2, $3, $5          # CHECK: srlv $2, $3, $5         # encoding: [0x00,0x65,0x10,0x50]
-        sll $2, $3, $5           # CHECK: sllv $2, $3, $5         # encoding: [0x00,0x65,0x10,0x10]
-        sra $2, $3, $5           # CHECK: srav $2, $3, $5         # encoding: [0x00,0x65,0x10,0x90]
-        srl $2, $3, $5           # CHECK: srlv $2, $3, $5         # encoding: [0x00,0x65,0x10,0x50]
-        sll $2, $3               # CHECK: sllv $2, $2, $3         # encoding: [0x00,0x43,0x10,0x10]
-        sra $2, $3               # CHECK: srav $2, $2, $3         # encoding: [0x00,0x43,0x10,0x90]
-        srl $2, $3               # CHECK: srlv $2, $2, $3         # encoding: [0x00,0x43,0x10,0x50]
-        sll $3, 7                # CHECK: sll $3, $3, 7           # encoding: [0x00,0x63,0x38,0x00]
-        sra $3, 7                # CHECK: sra $3, $3, 7           # encoding: [0x00,0x63,0x38,0x80]
-        srl $3, 7                # CHECK: srl $3, $3, 7           # encoding: [0x00,0x63,0x38,0x40]
-        dsub $1, $2, $3          # CHECK: dsub $1, $2, $3         # encoding: [0x58,0x62,0x09,0x90]
-        dsubu $3, $7, $15        # CHECK: dsubu $3, $7, $15       # encoding: [0x59,0xe7,0x19,0xd0]
-        dneg $7, $15             # CHECK: dneg $7, $15            # encoding: [0x59,0xe0,0x39,0x90]
-        dneg $10                 # CHECK: dneg $10, $10           # encoding: [0x59,0x40,0x51,0x90]
-        dnegu $1, $11            # CHECK: dnegu $1, $11           # encoding: [0x59,0x60,0x09,0xd0]
-        dnegu $5                 # CHECK: dnegu $5, $5            # encoding: [0x58,0xa0,0x29,0xd0]
-        mul $3, $4, $5           # CHECK: mul $3, $4, $5           # encoding: [0x00,0xa4,0x18,0x18]
-        muh $3, $4, $5           # CHECK: muh $3, $4, $5           # encoding: [0x00,0xa4,0x18,0x58]
-        mulu $3, $4, $5          # CHECK: mulu $3, $4, $5          # encoding: [0x00,0xa4,0x18,0x98]
-        muhu $3, $4, $5          # CHECK: muhu $3, $4, $5          # encoding: [0x00,0xa4,0x18,0xd8]
-        dmul $3, $4, $5          # CHECK: dmul $3, $4, $5          # encoding: [0x58,0xa4,0x18,0x18]
-        dmuh $3, $4, $5          # CHECK: dmuh $3, $4, $5          # encoding: [0x58,0xa4,0x18,0x58]
-        dmulu $3, $4, $5         # CHECK: dmulu $3, $4, $5         # encoding: [0x58,0xa4,0x18,0x98]
-        dmuhu $3, $4, $5         # CHECK: dmuhu $3, $4, $5         # encoding: [0x58,0xa4,0x18,0xd8]
-        lwp $16, 8($4)           # CHECK: lwp $16, 8($4)          # encoding: [0x22,0x04,0x10,0x08]
-        swp $16, 8($4)           # CHECK: swp $16, 8($4)          # encoding: [0x22,0x04,0x90,0x08]
-        dsbh $3, $4              # CHECK: dsbh $3, $4             # encoding: [0x58,0x64,0x7b,0x3c]
-        dshd $3, $4              # CHECK: dshd $3, $4             # encoding: [0x58,0x64,0xfb,0x3c]
-        dsll $3, $4, 5           # CHECK: dsll $3, $4, 5          # encoding: [0x58,0x64,0x28,0x00]
-        dsll32 $3, $4, 5         # CHECK: dsll32 $3, $4, 5        # encoding: [0x58,0x64,0x28,0x08]
-        dsllv $4, $5, $6         # CHECK: dsllv $4, $5, $6        # encoding: [0x58,0xa6,0x20,0x10]
-        dsra $4, $5, 5           # CHECK: dsra $4, $5, 5          # encoding: [0x58,0x85,0x28,0x80]
-        dsra32 $4, $5, 5         # CHECK: dsra32 $4, $5, 5        # encoding: [0x58,0x85,0x28,0x84]
-        dsrav $4, $5, $6         # CHECK: dsrav $4, $5, $6        # encoding: [0x58,0xa6,0x20,0x90]
-        bc1eqzc $f31, 4          # CHECK: bc1eqzc $f31, 4         # encoding: [0x41,0x1f,0x00,0x02]
-        bc1nezc $f31, 4          # CHECK: bc1nezc $f31, 4         # encoding: [0x41,0x3f,0x00,0x02]
-        bc2eqzc $31, 8           # CHECK: bc2eqzc $31, 8          # encoding: [0x41,0x5f,0x00,0x04]
-        bc2nezc $31, 8           # CHECK: bc2nezc $31, 8          # encoding: [0x41,0x7f,0x00,0x04]
-        and $3, 5                # CHECK: andi $3, $3, 5          # encoding: [0xd0,0x63,0x00,0x05]
-        and $3, $4, 5            # CHECK: andi $3, $4, 5          # encoding: [0xd0,0x64,0x00,0x05]
-        and $3, $4, $5           # CHECK: and $3, $4, $5          # encoding: [0x00,0xa4,0x1a,0x50]
-        andi $3, $4, 1234        # CHECK: andi $3, $4, 1234       # encoding: [0xd0,0x64,0x04,0xd2]
-        nor $3, $4, $5           # CHECK: nor $3, $4, $5          # encoding: [0x00,0xa4,0x1a,0xd0]
-        not $3, $4               # CHECK: not $3, $4              # encoding: [0x00,0x04,0x1a,0xd0]
-        not $3                   # CHECK: not $3, $3              # encoding: [0x00,0x03,0x1a,0xd0]
-        or $3, 5                 # CHECK: ori $3, $3, 5           # encoding: [0x50,0x63,0x00,0x05]
-        or $3, $4, 5             # CHECK: ori $3, $4, 5           # encoding: [0x50,0x64,0x00,0x05]
-        or $3, $4, $5            # CHECK: or $3, $4, $5           # encoding: [0x00,0xa4,0x1a,0x90]
-        ori $3, $4, 1234         # CHECK: ori $3, $4, 1234        # encoding: [0x50,0x64,0x04,0xd2]
-        xor $3, 5                # CHECK: xori $3, $3, 5          # encoding: [0x70,0x63,0x00,0x05]
-        xor $3, $4, 5            # CHECK: xori $3, $4, 5          # encoding: [0x70,0x64,0x00,0x05]
-        xor $3, $4, $5           # CHECK: xor $3, $4, $5          # encoding: [0x00,0xa4,0x1b,0x10]
-        xori $3, $4, 1234        # CHECK: xori $3, $4, 1234       # encoding: [0x70,0x64,0x04,0xd2]
-        dclo $1, $2              # CHECK: dclo $1, $2             # encoding: [0x58,0x22,0x4b,0x3c]
-        dclz $1, $2              # CHECK: dclz $1, $2             # encoding: [0x58,0x22,0x5b,0x3c]
-        drotr $5, $10, 8         # CHECK: drotr $5, $10, 8        # encoding: [0x58,0xaa,0x40,0xc0]
-        drotr32 $1, $2, 4        # CHECK: drotr32 $1, $2, 4       # encoding: [0x58,0x22,0x20,0xc8]
-        drotrv $3, $6, $4        # CHECK: drotrv $3, $6, $4       # encoding: [0x58,0xc4,0x18,0xd0]
-        ld $4, 5($2)             # CHECK: ld $4, 5($2)            # encoding: [0xdc,0x82,0x00,0x05]
-        lld $2, 3($8)            # CHECK: lld $2, 3($8)           # encoding: [0x60,0x48,0x70,0x03]
-        lwu $1, 10($2)           # CHECK: lwu $1, 10($2)          # encoding: [0x60,0x22,0xe0,0x0a]
-        sd $4, 5($3)             # CHECK: sd $4, 5($3)            # encoding: [0xd8,0x83,0x00,0x05]
-        dsrl $1, $2, 2           # CHECK: dsrl $1, $2, 2          # encoding: [0x58,0x22,0x10,0x40]
-        dsrl32 $3, $4, 5         # CHECK: dsrl32 $3, $4, 5        # encoding: [0x58,0x64,0x28,0x48]
-        dsrlv $1, $3, $3         # CHECK: dsrlv $1, $3, $3        # encoding: [0x58,0x63,0x08,0x50]
-        ldc1 $f7, 300($10)       # CHECK: ldc1 $f7, 300($10)      # encoding: [0xbc,0xea,0x01,0x2c]
-        ldc1 $f8, 300($10)       # CHECK: ldc1 $f8, 300($10)      # encoding: [0xbd,0x0a,0x01,0x2c]
-        ldc2 $11, 1023($12)      # CHECK: ldc2 $11, 1023($12)     # encoding: [0x21,0x6c,0x23,0xff]
-        lwc1 $f2, 32($5)         # CHECK: lwc1 $f2, 32($5)        # encoding: [0x9c,0x45,0x00,0x20]
-        lwc2 $1, 16($4)          # CHECK: lwc2 $1, 16($4)         # encoding: [0x20,0x24,0x00,0x10]
-        sdc1 $f7, 64($10)        # CHECK: sdc1 $f7, 64($10)       # encoding: [0xb8,0xea,0x00,0x40]
-        sdc1 $f8, 64($10)        # CHECK: sdc1 $f8, 64($10)       # encoding: [0xb9,0x0a,0x00,0x40]
-        sdc2 $2, 8($16)          # CHECK: sdc2 $2, 8($16)         # encoding: [0x20,0x50,0xa0,0x08]
-        swc1 $f6, 369($13)       # CHECK: swc1 $f6, 369($13)      # encoding: [0x98,0xcd,0x01,0x71]
-        swc2 $7, 777($17)        # CHECK: swc2 $7, 777($17)       # encoding: [0x20,0xf1,0x83,0x09]
-        cfc1 $1, $2              # CHECK: cfc1 $1, $2             # encoding: [0x54,0x22,0x10,0x3b]
-        cfc2 $3, $4              # CHECK: cfc2 $3, $4             # encoding: [0x00,0x64,0xcd,0x3c]
-        ctc1 $5, $6              # CHECK: ctc1 $5, $6             # encoding: [0x54,0xa6,0x18,0x3b]
-        ctc2 $7, $8              # CHECK: ctc2 $7, $8             # encoding: [0x00,0xe8,0xdd,0x3c]
-        bltzc $6, 128            # CHECK: bltzc $6, 128           # encoding: [0xd4,0xc6,0x00,0x20]
-        blezc $2, 256            # CHECK: blezc $2, 256           # encoding: [0xf4,0x40,0x00,0x40]
-        bgezc $16, 512           # CHECK: bgezc $16, 512          # encoding: [0xf6,0x10,0x00,0x80]
-        bgtzc $12, 1024          # CHECK: bgtzc $12, 1024         # encoding: [0xd5,0x80,0x01,0x00]
-        aui $3, $4, 256          # CHECK: aui $3, $4, 256         # encoding: [0x10,0x64,0x01,0x00]
-        dbitswap $3, $4          # CHECK: dbitswap $3, $4         # encoding: [0x58,0x83,0x0b,0x3c]
-        dlsa $3, $4, $5, 3       # CHECK: dlsa $3, $4, $5, 3      # encoding: [0x58,0x64,0x2d,0x04]
-        lwupc $2, 268            # CHECK: lwupc $2, 268           # encoding: [0x78,0x50,0x00,0x43]
-        lwupc $2, bar            # CHECK: lwupc $2, bar           # encoding: [0x78,0b01010AAA,A,A]
-        lwupc $2, bar+268        # CHECK: lwupc $2, bar+268       # encoding: [0x78,0b01010AAA,A,A]
-
-1:
Index: Target/Mips/AsmParser/MipsAsmParser.cpp
===================================================================
--- Target/Mips/AsmParser/MipsAsmParser.cpp
+++ Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -1981,9 +1981,7 @@
   case Mips::DDIV:
   case Mips::DDIVU:
   case Mips::DIVU_MMR6:
-  case Mips::DDIVU_MM64R6:
   case Mips::DIV_MMR6:
-  case Mips::DDIV_MM64R6:
     if (Inst.getOperand(SecondOp).getReg() == Mips::ZERO ||
         Inst.getOperand(SecondOp).getReg() == Mips::ZERO_64) {
       if (Inst.getOperand(FirstOp).getReg() == Mips::ZERO ||
@@ -4890,8 +4888,6 @@
     return Match_Success;
   case Mips::DATI:
   case Mips::DAHI:
-  case Mips::DATI_MM64R6:
-  case Mips::DAHI_MM64R6:
     if (static_cast<MipsOperand &>(*Operands[1])
             .isValidForTie(static_cast<MipsOperand &>(*Operands[2])))
       return Match_Success;
@@ -4904,7 +4900,6 @@
   // As described by the MIPSR6 spec, daui must not use the zero operand for
   // its source operand.
   case Mips::DAUI:
-  case Mips::DAUI_MM64R6:
     if (Inst.getOperand(1).getReg() == Mips::ZERO ||
         Inst.getOperand(1).getReg() == Mips::ZERO_64)
       return Match_RequiresNoZeroRegister;
Index: Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
===================================================================
--- Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
+++ Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
@@ -86,18 +86,6 @@
   case Mips::DROTR:
     Inst.setOpcode(Mips::DROTR32);
     return;
-  case Mips::DSLL_MM64R6:
-    Inst.setOpcode(Mips::DSLL32_MM64R6);
-    return;
-  case Mips::DSRL_MM64R6:
-    Inst.setOpcode(Mips::DSRL32_MM64R6);
-    return;
-  case Mips::DSRA_MM64R6:
-    Inst.setOpcode(Mips::DSRA32_MM64R6);
-    return;
-  case Mips::DROTR_MM64R6:
-    Inst.setOpcode(Mips::DROTR32_MM64R6);
-    return;
   }
 }
 
@@ -205,10 +193,6 @@
   case Mips::DSRL:
   case Mips::DSRA:
   case Mips::DROTR:
-  case Mips::DSLL_MM64R6:
-  case Mips::DSRL_MM64R6:
-  case Mips::DSRA_MM64R6:
-  case Mips::DROTR_MM64R6:
     LowerLargeShift(TmpInst);
     break;
     // Double extract instruction is chosen by pos and size operands
Index: lib/Target/Mips/MicroMips64r6InstrFormats.td
===================================================================
--- lib/Target/Mips/MicroMips64r6InstrFormats.td
+++ /dev/null
@@ -1,267 +0,0 @@
-//=-   MicroMips64r6InstrFormats.td - Instruction Formats  -*- tablegen -*  -=//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file describes microMIPS64r6 instruction formats.
-//
-//===----------------------------------------------------------------------===//
-
-class DAUI_FM_MMR6 {
-  bits<5> rt;
-  bits<5> rs;
-  bits<16> imm;
-
-  bits<32> Inst;
-
-  let Inst{31-26} = 0b111100;
-  let Inst{25-21} = rt;
-  let Inst{20-16} = rs;
-  let Inst{15-0}  = imm;
-}
-
-class POOL32I_ADD_IMM_FM_MMR6<bits<5> funct> {
-  bits<5> rs;
-  bits<16> imm;
-
-  bits<32> Inst;
-
-  let Inst{31-26} = 0b010000;
-  let Inst{25-21} = funct;
-  let Inst{20-16} = rs;
-  let Inst{15-0} = imm;
-}
-
-class POOL32S_EXTBITS_FM_MMR6<bits<6> funct> {
-  bits<5> rt;
-  bits<5> rs;
-  bits<5> size;
-  bits<5> pos;
-
-  bits<32> Inst;
-
-  let Inst{31-26} = 0b010110;
-  let Inst{25-21} = rt;
-  let Inst{20-16} = rs;
-  let Inst{15-11} = size;
-  let Inst{10-6}  = pos;
-  let Inst{5-0}   = funct;
-}
-
-class POOL32S_DALIGN_FM_MMR6 {
-  bits<5> rs;
-  bits<5> rt;
-  bits<5> rd;
-  bits<3> bp;
-
-  bits<32> Inst;
-
-  let Inst{31-26} = 0b010110;
-  let Inst{25-21} = rs;
-  let Inst{20-16} = rt;
-  let Inst{15-11} = rd;
-  let Inst{10-8}  = bp;
-  let Inst{7-6}   = 0b00;
-  let Inst{5-0}   = 0b011100;
-}
-
-class POOL32A_DIVMOD_FM_MMR6<string instr_asm, bits<9> funct>
-    : MMR6Arch<instr_asm> {
-  bits<5> rt;
-  bits<5> rs;
-  bits<5> rd;
-
-  bits<32> Inst;
-
-  let Inst{31-26} = 0b010110;
-  let Inst{25-21} = rt;
-  let Inst{20-16} = rs;
-  let Inst{15-11} = rd;
-  let Inst{10-9}  = 0b00;
-  let Inst{8-0}  = funct;
-}
-
-class POOL32S_DMFTC0_FM_MMR6<string instr_asm, bits<5> funct>
-    : MMR6Arch<instr_asm>, MipsR6Inst {
-  bits<5> rt;
-  bits<5> rs;
-  bits<3> sel;
-
-  bits<32> Inst;
-
-  let Inst{31-26} = 0b010110;
-  let Inst{25-21} = rt;
-  let Inst{20-16} = rs;
-  let Inst{15-14} = 0;
-  let Inst{13-11} = sel;
-  let Inst{10-6}  = funct;
-  let Inst{5-0}   = 0b111100;
-}
-
-class POOL32S_ARITH_FM_MMR6<string opstr, bits<9> funct>
-    : MMR6Arch<opstr> {
-  bits<5> rt;
-  bits<5> rs;
-  bits<5> rd;
-
-  bits<32> Inst;
-
-  let Inst{31-26} = 0b010110;
-  let Inst{25-21} = rt;
-  let Inst{20-16} = rs;
-  let Inst{15-11} = rd;
-  let Inst{10-9}  = 0b00;
-  let Inst{8-0}   = funct;
-}
-
-class DADDIU_FM_MMR6<string opstr> : MMR6Arch<opstr> {
-  bits<5> rt;
-  bits<5> rs;
-  bits<16> imm16;
-
-  bits<32> Inst;
-
-  let Inst{31-26} = 0b010111;
-  let Inst{25-21} = rt;
-  let Inst{20-16} = rs;
-  let Inst{15-0}  = imm16;
-}
-
-class PCREL18_FM_MMR6<bits<3> funct> : MipsR6Inst {
-  bits<5> rt;
-  bits<18> imm;
-
-  bits<32> Inst;
-
-  let Inst{31-26} = 0b011110;
-  let Inst{25-21} = rt;
-  let Inst{20-18} = funct;
-  let Inst{17-0} = imm;
-}
-
-class POOL32S_2R_FM_MMR6<string instr_asm, bits<10> funct>
-    : MMR6Arch<instr_asm>, MipsR6Inst {
-  bits<5> rt;
-  bits<5> rs;
-
-  bits<32> Inst;
-
-  let Inst{31-26} = 0b010110;
-  let Inst{25-21} = rt;
-  let Inst{20-16} = rs;
-  let Inst{15-6} = funct;
-  let Inst{5-0} = 0b111100;
-}
-
-class POOL32S_2RSA5B0_FM_MMR6<string instr_asm, bits<9> funct>
-    : MMR6Arch<instr_asm>, MipsR6Inst {
-  bits<5> rt;
-  bits<5> rs;
-  bits<5> sa;
-
-  bits<32> Inst;
-
-  let Inst{31-26} = 0b010110;
-  let Inst{25-21} = rt;
-  let Inst{20-16} = rs;
-  let Inst{15-11} = sa;
-  let Inst{10-9} = 0b00;
-  let Inst{8-0} = funct;
-}
-
-class LD_SD_32_2R_OFFSET16_FM_MMR6<string instr_asm, bits<6> op>
-    : MMR6Arch<instr_asm>, MipsR6Inst {
-  bits<5> rt;
-  bits<21> addr;
-  bits<5> base = addr{20-16};
-  bits<16> offset = addr{15-0};
-
-  bits<32> Inst;
-
-  let Inst{31-26} = op;
-  let Inst{25-21} = rt;
-  let Inst{20-16} = base;
-  let Inst{15-0}  = offset;
-}
-
-class POOL32C_2R_OFFSET12_FM_MMR6<string instr_asm, bits<4> funct>
-    : MMR6Arch<instr_asm>, MipsR6Inst {
-  bits<5> rt;
-  bits<21> addr;
-  bits<5> base = addr{20-16};
-  bits<12> offset = addr{11-0};
-
-  bits<32> Inst;
-
-  let Inst{31-26} = 0b011000;
-  let Inst{25-21} = rt;
-  let Inst{20-16} = base;
-  let Inst{15-12} = funct;
-  let Inst{11-0}  = offset;
-}
-
-class POOL32S_3R_FM_MMR6<string instr_asm, bits<9> funct>
-    : MMR6Arch<instr_asm>, MipsR6Inst {
-  bits<5> rt;
-  bits<5> rs;
-  bits<5> rd;
-
-  bits<32> Inst;
-
-  let Inst{31-26} = 0b010110;
-  let Inst{25-21} = rt;
-  let Inst{20-16} = rs;
-  let Inst{15-11} = rd;
-  let Inst{10-9}  = 0b00;
-  let Inst{8-0}   = funct;
-}
-
-class POOL32S_DBITSWAP_FM_MMR6<string instr_asm> : MMR6Arch<instr_asm>,
-      MipsR6Inst {
-  bits<5> rt;
-  bits<5> rd;
-
-  bits<32> Inst;
-
-  let Inst{31-26} = 0b010110;
-  let Inst{25-21} = rt;
-  let Inst{20-16} = rd;
-  let Inst{15-12}  = 0b0000;
-  let Inst{11-6}  = 0b101100;
-  let Inst{5-0}   = 0b111100;
-}
-
-class POOL32S_3RSA_FM_MMR6<string instr_asm> : MMR6Arch<instr_asm>,
-      MipsR6Inst {
-  bits<5> rt;
-  bits<5> rs;
-  bits<5> rd;
-  bits<2> sa;
-
-  bits<32> Inst;
-
-  let Inst{31-26} = 0b010110;
-  let Inst{25-21} = rt;
-  let Inst{20-16} = rs;
-  let Inst{15-11} = rd;
-  let Inst{10-9} = sa;
-  let Inst{8-6} = 0b100;
-  let Inst{5-0} = 0b000100;
-}
-
-class PCREL_1ROFFSET19_FM_MMR6<string instr_asm> : MMR6Arch<instr_asm>,
-      MipsR6Inst {
-  bits<5> rt;
-  bits<19> offset;
-
-  bits<32> Inst;
-
-  let Inst{31-26} = 0b011110;
-  let Inst{25-21} = rt;
-  let Inst{20-19} = 0b10;
-  let Inst{18-0} = offset;
-}
Index: lib/Target/Mips/MicroMips64r6InstrInfo.td
===================================================================
--- lib/Target/Mips/MicroMips64r6InstrInfo.td
+++ /dev/null
@@ -1,562 +0,0 @@
-//=-  MicroMips64r6InstrInfo.td - Instruction Information  -*- tablegen -*- -=//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file describes MicroMips64r6 instructions.
-//
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-//
-// Instruction Encodings
-//
-//===----------------------------------------------------------------------===//
-
-class DAUI_MMR6_ENC : DAUI_FM_MMR6;
-class DAHI_MMR6_ENC : POOL32I_ADD_IMM_FM_MMR6<0b10001>;
-class DATI_MMR6_ENC : POOL32I_ADD_IMM_FM_MMR6<0b10000>;
-class DEXT_MMR6_ENC : POOL32S_EXTBITS_FM_MMR6<0b101100>;
-class DEXTM_MMR6_ENC : POOL32S_EXTBITS_FM_MMR6<0b100100>;
-class DEXTU_MMR6_ENC : POOL32S_EXTBITS_FM_MMR6<0b010100>;
-class DALIGN_MMR6_ENC : POOL32S_DALIGN_FM_MMR6;
-class DDIV_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"ddiv", 0b100011000>;
-class DMOD_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"dmod", 0b101011000>;
-class DDIVU_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"ddivu", 0b110011000>;
-class DMODU_MM64R6_ENC : POOL32A_DIVMOD_FM_MMR6<"dmodu", 0b111011000>;
-class DINSU_MM64R6_ENC : POOL32S_EXTBITS_FM_MMR6<0b110100>;
-class DINSM_MM64R6_ENC : POOL32S_EXTBITS_FM_MMR6<0b000100>;
-class DINS_MM64R6_ENC : POOL32S_EXTBITS_FM_MMR6<0b001100>;
-class DMTC0_MM64R6_ENC : POOL32S_DMFTC0_FM_MMR6<"dmtc0", 0b01011>;
-class DMTC1_MM64R6_ENC : POOL32F_MFTC1_FM_MMR6<"dmtc1", 0b10110000>;
-class DMTC2_MM64R6_ENC : POOL32A_MFTC2_FM_MMR6<"dmtc2", 0b0111110100>;
-class DMFC0_MM64R6_ENC : POOL32S_DMFTC0_FM_MMR6<"dmfc0", 0b00011>;
-class DMFC1_MM64R6_ENC : POOL32F_MFTC1_FM_MMR6<"dmfc1", 0b10010000>;
-class DMFC2_MM64R6_ENC : POOL32A_MFTC2_FM_MMR6<"dmfc2", 0b0110110100>;
-class DADD_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dadd", 0b100010000>;
-class DADDIU_MM64R6_ENC : DADDIU_FM_MMR6<"daddiu">;
-class DADDU_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"daddu", 0b101010000>;
-class LDPC_MMR646_ENC : PCREL18_FM_MMR6<0b110>;
-class DSUB_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dsub", 0b110010000>;
-class DSUBU_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dsubu", 0b111010000>;
-class DMUL_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dmul", 0b000011000>;
-class DMUH_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dmuh", 0b001011000>;
-class DMULU_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dmulu", 0b010011000>;
-class DMUHU_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dmuhu", 0b011011000>;
-class DSBH_MM64R6_ENC : POOL32S_2R_FM_MMR6<"dsbh", 0b0111101100>;
-class DSHD_MM64R6_ENC : POOL32S_2R_FM_MMR6<"dshd", 0b1111101100>;
-class DSLL_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"dsll", 0b000000000>;
-class DSLL32_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"dsll32", 0b000001000>;
-class DSLLV_MM64R6_ENC : POOL32S_3R_FM_MMR6<"dsllv", 0b000010000>;
-class DSRAV_MM64R6_ENC : POOL32S_3R_FM_MMR6<"dsrav", 0b010010000>;
-class DSRA_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"dsra", 0b010000000>;
-class DSRA32_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"dsra32", 0b010000100>;
-class DCLO_MM64R6_ENC : POOL32S_2R_FM_MMR6<"dclo", 0b0100101100>;
-class DCLZ_MM64R6_ENC : POOL32S_2R_FM_MMR6<"dclz", 0b0101101100>;
-class DROTR_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"drotr", 0b011000000>;
-class DROTR32_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"drotr32", 0b011001000>;
-class DROTRV_MM64R6_ENC : POOL32S_3R_FM_MMR6<"drotrv", 0b011010000>;
-class LD_MM64R6_ENC : LD_SD_32_2R_OFFSET16_FM_MMR6<"ld", 0b110111>;
-class LLD_MM64R6_ENC : POOL32C_2R_OFFSET12_FM_MMR6<"lld", 0b0111>;
-class LWU_MM64R6_ENC : POOL32C_2R_OFFSET12_FM_MMR6<"lwu", 0b1110>;
-class SD_MM64R6_ENC : LD_SD_32_2R_OFFSET16_FM_MMR6<"sd", 0b110110>;
-class DSRL_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"dsrl", 0b001000000>;
-class DSRL32_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"dsrl32", 0b001001000>;
-class DSRLV_MM64R6_ENC : POOL32S_3R_FM_MMR6<"dsrlv", 0b001010000>;
-class DBITSWAP_MM64R6_ENC : POOL32S_DBITSWAP_FM_MMR6<"dbitswap">;
-class DLSA_MM64R6_ENC : POOL32S_3RSA_FM_MMR6<"dlsa">;
-class LWUPC_MM64R6_ENC : PCREL_1ROFFSET19_FM_MMR6<"lwupc">;
-
-//===----------------------------------------------------------------------===//
-//
-// Instruction Descriptions
-//
-//===----------------------------------------------------------------------===//
-
-class DAUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
-                          InstrItinClass Itin>
-    : MMR6Arch<instr_asm>, MipsR6Inst {
-  dag OutOperandList = (outs GPROpnd:$rt);
-  dag InOperandList = (ins GPROpnd:$rs, uimm16:$imm);
-  string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
-  list<dag> Pattern = [];
-  InstrItinClass Itinerary = Itin;
-}
-class DAUI_MMR6_DESC : DAUI_MMR6_DESC_BASE<"daui", GPR64Opnd, II_DAUI>;
-
-class DAHI_DATI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
-                          InstrItinClass Itin>
-    : MMR6Arch<instr_asm>, MipsR6Inst {
-  dag OutOperandList = (outs GPROpnd:$rs);
-  dag InOperandList = (ins GPROpnd:$rt, uimm16:$imm);
-  string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm");
-  string Constraints = "$rs = $rt";
-  InstrItinClass Itinerary = Itin;
-}
-class DAHI_MMR6_DESC : DAHI_DATI_DESC_BASE<"dahi", GPR64Opnd, II_DAHI>;
-class DATI_MMR6_DESC : DAHI_DATI_DESC_BASE<"dati", GPR64Opnd, II_DATI>;
-
-class EXTBITS_DESC_BASE<string instr_asm, RegisterOperand RO, Operand PosOpnd,
-                        Operand SizeOpnd, SDPatternOperator Op = null_frag>
-    : MMR6Arch<instr_asm>, MipsR6Inst {
-  dag OutOperandList = (outs RO:$rt);
-  dag InOperandList = (ins RO:$rs, PosOpnd:$pos, SizeOpnd:$size);
-  string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $pos, $size");
-  list<dag> Pattern = [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))];
-  InstrItinClass Itinerary = II_EXT;
-  Format Form = FrmR;
-  string BaseOpcode = instr_asm;
-}
-// TODO: Add 'pos + size' constraint check to dext* instructions
-//       DEXT: 0 < pos + size <= 63
-//       DEXTM, DEXTU: 32 < pos + size <= 64
-class DEXT_MMR6_DESC : EXTBITS_DESC_BASE<"dext", GPR64Opnd, uimm5_report_uimm6,
-                                         uimm5_plus1, MipsExt>;
-class DEXTM_MMR6_DESC : EXTBITS_DESC_BASE<"dextm", GPR64Opnd, uimm5,
-                                          uimm5_plus33, MipsExt>;
-class DEXTU_MMR6_DESC : EXTBITS_DESC_BASE<"dextu", GPR64Opnd, uimm5_plus32,
-                                          uimm5_plus1, MipsExt>;
-
-class DALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
-                      Operand ImmOpnd, InstrItinClass itin>
-    : MMR6Arch<instr_asm>, MipsR6Inst {
-  dag OutOperandList = (outs GPROpnd:$rd);
-  dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp);
-  string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp");
-  list<dag> Pattern = [];
-  InstrItinClass Itinerary = itin;
-}
-
-class DALIGN_MMR6_DESC : DALIGN_DESC_BASE<"dalign", GPR64Opnd, uimm3,
-                                          II_DALIGN>;
-
-class DDIV_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"ddiv", GPR64Opnd, II_DDIV,
-                                               sdiv>;
-class DMOD_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"dmod", GPR64Opnd, II_DMOD,
-                                               srem>;
-class DDIVU_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"ddivu", GPR64Opnd, II_DDIVU,
-                                                udiv>;
-class DMODU_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"dmodu", GPR64Opnd, II_DMODU,
-                                                urem>;
-
-class DCLO_MM64R6_DESC {
-  dag OutOperandList = (outs GPR64Opnd:$rt);
-  dag InOperandList = (ins GPR64Opnd:$rs);
-  string AsmString = !strconcat("dclo", "\t$rt, $rs");
-  list<dag> Pattern = [(set GPR64Opnd:$rt, (ctlz (not GPR64Opnd:$rs)))];
-  InstrItinClass Itinerary = II_DCLO;
-  Format Form = FrmR;
-  string BaseOpcode = "dclo";
-}
-
-class DCLZ_MM64R6_DESC {
-  dag OutOperandList = (outs GPR64Opnd:$rt);
-  dag InOperandList = (ins GPR64Opnd:$rs);
-  string AsmString = !strconcat("dclz", "\t$rt, $rs");
-  list<dag> Pattern = [(set GPR64Opnd:$rt, (ctlz GPR64Opnd:$rs))];
-  InstrItinClass Itinerary = II_DCLZ;
-  Format Form = FrmR;
-  string BaseOpcode = "dclz";
-}
-
-class DINSU_MM64R6_DESC : InsBase<"dinsu", GPR64Opnd, uimm5_plus32,
-                                  uimm5_inssize_plus1, MipsIns>;
-class DINSM_MM64R6_DESC : InsBase<"dinsm", GPR64Opnd, uimm5, uimm_range_2_64>;
-class DINS_MM64R6_DESC : InsBase<"dins", GPR64Opnd, uimm5, uimm5_inssize_plus1,
-                                 MipsIns>;
-class DMTC0_MM64R6_DESC : MTC0_MMR6_DESC_BASE<"dmtc0", COP0Opnd, GPR64Opnd,
-                                              II_DMTC0>;
-class DMTC1_MM64R6_DESC : MTC1_MMR6_DESC_BASE<"dmtc1", FGR64Opnd, GPR64Opnd,
-                                              II_DMTC1, bitconvert>;
-class DMTC2_MM64R6_DESC : MTC2_MMR6_DESC_BASE<"dmtc2", COP2Opnd, GPR64Opnd,
-                                              II_DMTC2>;
-class DMFC0_MM64R6_DESC : MFC0_MMR6_DESC_BASE<"dmfc0", GPR64Opnd, COP0Opnd,
-                                              II_DMFC0>;
-class DMFC1_MM64R6_DESC : MFC1_MMR6_DESC_BASE<"dmfc1", GPR64Opnd, FGR64Opnd,
-                                              II_DMFC1, bitconvert>;
-class DMFC2_MM64R6_DESC : MFC2_MMR6_DESC_BASE<"dmfc2", GPR64Opnd, COP2Opnd,
-                                              II_DMFC2>;
-class DADD_MM64R6_DESC : ArithLogicR<"dadd", GPR64Opnd, 1, II_DADD>;
-class DADDIU_MM64R6_DESC : ArithLogicI<"daddiu", simm16_64, GPR64Opnd,
-                                       II_DADDIU, immSExt16, add>,
-                           IsAsCheapAsAMove;
-class DADDU_MM64R6_DESC : ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>;
-
-class DSUB_DESC_BASE<string instr_asm, RegisterOperand RO,
-                     InstrItinClass Itin = NoItinerary,
-                     SDPatternOperator OpNode = null_frag>
-                     : MipsR6Inst {
-  dag OutOperandList = (outs RO:$rd);
-  dag InOperandList = (ins RO:$rs, RO:$rt);
-  string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
-  list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rs, RO:$rt))];
-  InstrItinClass Itinerary = Itin;
-  Format Form = FrmR;
-  string BaseOpcode = instr_asm;
-  let isCommutable = 0;
-  let isReMaterializable = 1;
-  let TwoOperandAliasConstraint = "$rd = $rs";
-}
-class DSUB_MM64R6_DESC : DSUB_DESC_BASE<"dsub", GPR64Opnd, II_DSUB>;
-class DSUBU_MM64R6_DESC : DSUB_DESC_BASE<"dsubu", GPR64Opnd, II_DSUBU, sub>;
-
-class LDPC_MM64R6_DESC : PCREL_MMR6_DESC_BASE<"ldpc", GPR64Opnd, simm18_lsl3,
-                                              II_LDPC>;
-
-class MUL_MM64R6_DESC_BASE<string opstr, RegisterOperand GPROpnd,
-                           InstrItinClass Itin = NoItinerary,
-                           SDPatternOperator Op = null_frag> : MipsR6Inst {
-  dag OutOperandList = (outs GPROpnd:$rd);
-  dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt);
-  string AsmString = !strconcat(opstr, "\t$rd, $rs, $rt");
-  InstrItinClass Itinerary = Itin;
-  list<dag> Pattern = [(set GPROpnd:$rd, (Op GPROpnd:$rs, GPROpnd:$rt))];
-}
-
-class DMUL_MM64R6_DESC : MUL_MM64R6_DESC_BASE<"dmul", GPR64Opnd, II_DMUL, mul>;
-class DMUH_MM64R6_DESC : MUL_MM64R6_DESC_BASE<"dmuh", GPR64Opnd, II_DMUH,
-                                              mulhs>;
-class DMULU_MM64R6_DESC : MUL_MM64R6_DESC_BASE<"dmulu", GPR64Opnd, II_DMULU>;
-class DMUHU_MM64R6_DESC : MUL_MM64R6_DESC_BASE<"dmuhu", GPR64Opnd, II_DMUHU,
-                                               mulhu>;
-
-class DSBH_DSHD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd,
-                          InstrItinClass Itin> {
-  dag OutOperandList = (outs GPROpnd:$rt);
-  dag InOperandList = (ins GPROpnd:$rs);
-  string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
-  bit hasSideEffects = 0;
-  list<dag> Pattern = [];
-  InstrItinClass Itinerary = Itin;
-  Format Form = FrmR;
-  string BaseOpcode = instr_asm;
-}
-
-class DSBH_MM64R6_DESC : DSBH_DSHD_DESC_BASE<"dsbh", GPR64Opnd, II_DSBH>;
-class DSHD_MM64R6_DESC : DSBH_DSHD_DESC_BASE<"dshd", GPR64Opnd, II_DSHD>;
-
-class SHIFT_ROTATE_IMM_MM64R6<string instr_asm, Operand ImmOpnd,
-                              InstrItinClass itin,
-                              SDPatternOperator OpNode = null_frag,
-                              SDPatternOperator PO = null_frag> {
-  dag OutOperandList = (outs GPR64Opnd:$rt);
-  dag InOperandList = (ins GPR64Opnd:$rs, ImmOpnd:$sa);
-  string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
-  list<dag> Pattern = [(set GPR64Opnd:$rt, (OpNode GPR64Opnd:$rs, PO:$sa))];
-  InstrItinClass Itinerary = itin;
-  Format Form = FrmR;
-  string TwoOperandAliasConstraint = "$rs = $rt";
-  string BaseOpcode = instr_asm;
-}
-
-class SHIFT_ROTATE_REG_MM64R6<string instr_asm, InstrItinClass itin,
-                              SDPatternOperator OpNode = null_frag> {
-  dag OutOperandList = (outs GPR64Opnd:$rd);
-  dag InOperandList = (ins GPR64Opnd:$rt, GPR32Opnd:$rs);
-  string AsmString = !strconcat(instr_asm, "\t$rd, $rt, $rs");
-  list<dag> Pattern = [(set GPR64Opnd:$rd,
-                       (OpNode GPR64Opnd:$rt, GPR32Opnd:$rs))];
-  InstrItinClass Itinerary = itin;
-  Format Form = FrmR;
-  string BaseOpcode = instr_asm;
-}
-
-class DSLL_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"dsll", uimm6, II_DSLL, shl,
-                                                 immZExt6>;
-class DSLL32_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"dsll32", uimm5, II_DSLL32>;
-class DSLLV_MM64R6_DESC : SHIFT_ROTATE_REG_MM64R6<"dsllv", II_DSLLV, shl>;
-class DSRAV_MM64R6_DESC : SHIFT_ROTATE_REG_MM64R6<"dsrav", II_DSRAV, sra>;
-class DSRA_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"dsra", uimm6, II_DSRA, sra,
-                                                 immZExt6>;
-class DSRA32_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"dsra32", uimm5, II_DSRA32>;
-class DROTR_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"drotr", uimm6, II_DROTR,
-                                                  rotr, immZExt6>;
-class DROTR32_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"drotr32", uimm5,
-                                                    II_DROTR32>;
-class DROTRV_MM64R6_DESC : SHIFT_ROTATE_REG_MM64R6<"drotrv", II_DROTRV, rotr>;
-class DSRL_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"dsrl", uimm6, II_DSRL, srl,
-                                                 immZExt6>;
-class DSRL32_MM64R6_DESC : SHIFT_ROTATE_IMM_MM64R6<"dsrl32", uimm5, II_DSRL32>;
-class DSRLV_MM64R6_DESC : SHIFT_ROTATE_REG_MM64R6<"dsrlv", II_DSRLV, srl>;
-
-class Load_MM64R6<string instr_asm, Operand MemOpnd, InstrItinClass itin,
-                  SDPatternOperator OpNode = null_frag> {
-  dag OutOperandList = (outs GPR64Opnd:$rt);
-  dag InOperandList = (ins MemOpnd:$addr);
-  string AsmString = !strconcat(instr_asm, "\t$rt, $addr");
-  list<dag> Pattern = [(set GPR64Opnd:$rt, (OpNode addr:$addr))];
-  InstrItinClass Itinerary = itin;
-  Format Form = FrmI;
-  bit mayLoad = 1;
-  bit canFoldAsLoad = 1;
-  string BaseOpcode = instr_asm;
-}
-
-class LD_MM64R6_DESC : Load_MM64R6<"ld", mem_simm16, II_LD, load> {
-  string DecoderMethod = "DecodeMemMMImm16";
-}
-class LWU_MM64R6_DESC : Load_MM64R6<"lwu", mem_simm12, II_LWU, zextloadi32>{
-  string DecoderMethod = "DecodeMemMMImm12";
-}
-
-class LLD_MM64R6_DESC {
-  dag OutOperandList = (outs GPR64Opnd:$rt);
-  dag InOperandList = (ins mem_simm12:$addr);
-  string AsmString = "lld\t$rt, $addr";
-  list<dag> Pattern = [];
-  bit mayLoad = 1;
-  InstrItinClass Itinerary = II_LLD;
-  string BaseOpcode = "lld";
-  string DecoderMethod = "DecodeMemMMImm12";
-}
-
-class SD_MM64R6_DESC {
-  dag OutOperandList = (outs);
-  dag InOperandList = (ins GPR64Opnd:$rt, mem_simm16:$addr);
-  string AsmString = "sd\t$rt, $addr";
-  list<dag> Pattern = [(store GPR64Opnd:$rt, addr:$addr)];
-  InstrItinClass Itinerary = II_SD;
-  Format Form = FrmI;
-  bit mayStore = 1;
-  string BaseOpcode = "sd";
-  string DecoderMethod = "DecodeMemMMImm16";
-}
-
-class DBITSWAP_MM64R6_DESC {
-  dag OutOperandList = (outs GPR64Opnd:$rd);
-  dag InOperandList = (ins GPR64Opnd:$rt);
-  string AsmString = !strconcat("dbitswap", "\t$rd, $rt");
-  list<dag> Pattern = [];
-  InstrItinClass Itinerary = II_DBITSWAP;
-}
-
-class DLSA_MM64R6_DESC {
-  dag OutOperandList = (outs GPR64Opnd:$rd);
-  dag InOperandList = (ins GPR64Opnd:$rt, GPR64Opnd:$rs, uimm2_plus1:$sa);
-  string AsmString = "dlsa\t$rt, $rs, $rd, $sa";
-  list<dag> Pattern = [];
-  InstrItinClass Itinerary = II_DLSA;
-}
-
-class LWUPC_MM64R6_DESC {
-  dag OutOperandList = (outs GPR64Opnd:$rt);
-  dag InOperandList = (ins simm19_lsl2:$offset);
-  string AsmString = "lwupc\t$rt, $offset";
-  list<dag> Pattern = [];
-  InstrItinClass Itinerary = II_LWUPC;
-  bit mayLoad = 1;
-  bit IsPCRelativeLoad = 1;
-}
-
-//===----------------------------------------------------------------------===//
-//
-// Instruction Definitions
-//
-//===----------------------------------------------------------------------===//
-
-let DecoderNamespace = "MicroMipsR6" in {
-  def DAUI_MM64R6 : StdMMR6Rel, DAUI_MMR6_DESC, DAUI_MMR6_ENC, ISA_MICROMIPS64R6;
-  let DecoderMethod = "DecodeDAHIDATIMMR6" in {
-    def DAHI_MM64R6 : StdMMR6Rel, DAHI_MMR6_DESC, DAHI_MMR6_ENC, ISA_MICROMIPS64R6;
-    def DATI_MM64R6 : StdMMR6Rel, DATI_MMR6_DESC, DATI_MMR6_ENC, ISA_MICROMIPS64R6;
-  }
-  def DEXT_MM64R6 : StdMMR6Rel, DEXT_MMR6_DESC, DEXT_MMR6_ENC,
-                    ISA_MICROMIPS64R6;
-  def DEXTM_MM64R6 : StdMMR6Rel, DEXTM_MMR6_DESC, DEXTM_MMR6_ENC,
-                     ISA_MICROMIPS64R6;
-  def DEXTU_MM64R6 : StdMMR6Rel, DEXTU_MMR6_DESC, DEXTU_MMR6_ENC,
-                     ISA_MICROMIPS64R6;
-  def DALIGN_MM64R6 : StdMMR6Rel, DALIGN_MMR6_DESC, DALIGN_MMR6_ENC,
-                      ISA_MICROMIPS64R6;
-  def DDIV_MM64R6 : R6MMR6Rel, DDIV_MM64R6_DESC, DDIV_MM64R6_ENC,
-                    ISA_MICROMIPS64R6;
-  def DMOD_MM64R6 : R6MMR6Rel, DMOD_MM64R6_DESC, DMOD_MM64R6_ENC,
-                    ISA_MICROMIPS64R6;
-  def DDIVU_MM64R6 : R6MMR6Rel, DDIVU_MM64R6_DESC, DDIVU_MM64R6_ENC,
-                     ISA_MICROMIPS64R6;
-  def DMODU_MM64R6 : R6MMR6Rel, DMODU_MM64R6_DESC, DMODU_MM64R6_ENC,
-                     ISA_MICROMIPS64R6;
-  def DINSU_MM64R6: R6MMR6Rel, DINSU_MM64R6_DESC, DINSU_MM64R6_ENC,
-                    ISA_MICROMIPS64R6;
-  def DINSM_MM64R6: R6MMR6Rel, DINSM_MM64R6_DESC, DINSM_MM64R6_ENC,
-                    ISA_MICROMIPS64R6;
-  def DINS_MM64R6: R6MMR6Rel, DINS_MM64R6_DESC, DINS_MM64R6_ENC,
-                   ISA_MICROMIPS64R6;
-  def DMTC0_MM64R6 : StdMMR6Rel, DMTC0_MM64R6_ENC, DMTC0_MM64R6_DESC,
-                     ISA_MICROMIPS64R6;
-  def DMTC1_MM64R6 : StdMMR6Rel, DMTC1_MM64R6_DESC, DMTC1_MM64R6_ENC,
-                     ISA_MICROMIPS64R6;
-  def DMTC2_MM64R6 : StdMMR6Rel, DMTC2_MM64R6_ENC, DMTC2_MM64R6_DESC,
-                     ISA_MICROMIPS64R6;
-  def DMFC0_MM64R6 : StdMMR6Rel, DMFC0_MM64R6_ENC, DMFC0_MM64R6_DESC,
-                     ISA_MICROMIPS64R6;
-  def DMFC1_MM64R6 : StdMMR6Rel, DMFC1_MM64R6_DESC, DMFC1_MM64R6_ENC,
-                     ISA_MICROMIPS64R6;
-  def DMFC2_MM64R6 : StdMMR6Rel, DMFC2_MM64R6_ENC, DMFC2_MM64R6_DESC,
-                     ISA_MICROMIPS64R6;
-  def DADD_MM64R6: StdMMR6Rel, DADD_MM64R6_DESC, DADD_MM64R6_ENC,
-                   ISA_MICROMIPS64R6;
-  def DADDIU_MM64R6: StdMMR6Rel, DADDIU_MM64R6_DESC, DADDIU_MM64R6_ENC,
-                     ISA_MICROMIPS64R6;
-  def DADDU_MM64R6: StdMMR6Rel, DADDU_MM64R6_DESC, DADDU_MM64R6_ENC,
-                    ISA_MICROMIPS64R6;
-  def LDPC_MM64R6 :  R6MMR6Rel, LDPC_MMR646_ENC, LDPC_MM64R6_DESC,
-                     ISA_MICROMIPS64R6;
-  def DSUB_MM64R6 : StdMMR6Rel, DSUB_MM64R6_DESC, DSUB_MM64R6_ENC,
-                    ISA_MICROMIPS64R6;
-  def DSUBU_MM64R6 : StdMMR6Rel, DSUBU_MM64R6_DESC, DSUBU_MM64R6_ENC,
-                     ISA_MICROMIPS64R6;
-  def DMUL_MM64R6 : R6MMR6Rel, DMUL_MM64R6_DESC, DMUL_MM64R6_ENC,
-                    ISA_MICROMIPS64R6;
-  def DMUH_MM64R6 : R6MMR6Rel, DMUH_MM64R6_DESC, DMUH_MM64R6_ENC,
-                    ISA_MICROMIPS64R6;
-  def DMULU_MM64R6 : R6MMR6Rel, DMULU_MM64R6_DESC, DMULU_MM64R6_ENC,
-                     ISA_MICROMIPS64R6;
-  def DMUHU_MM64R6 : R6MMR6Rel, DMUHU_MM64R6_DESC, DMUHU_MM64R6_ENC,
-                     ISA_MICROMIPS64R6;
-  def DSBH_MM64R6 : R6MMR6Rel, DSBH_MM64R6_ENC, DSBH_MM64R6_DESC,
-                    ISA_MICROMIPS64R6;
-  def DSHD_MM64R6 : R6MMR6Rel, DSHD_MM64R6_ENC, DSHD_MM64R6_DESC,
-                    ISA_MICROMIPS64R6;
-  def DSLL_MM64R6 : StdMMR6Rel, DSLL_MM64R6_ENC, DSLL_MM64R6_DESC,
-                    ISA_MICROMIPS64R6;
-  def DSLL32_MM64R6 : StdMMR6Rel, DSLL32_MM64R6_ENC, DSLL32_MM64R6_DESC,
-                    ISA_MICROMIPS64R6;
-  def DSLLV_MM64R6 : StdMMR6Rel, DSLLV_MM64R6_ENC, DSLLV_MM64R6_DESC,
-                     ISA_MICROMIPS64R6;
-  def DSRAV_MM64R6 : StdMMR6Rel, DSRAV_MM64R6_ENC, DSRAV_MM64R6_DESC,
-                    ISA_MICROMIPS64R6;
-  def DSRA_MM64R6 : StdMMR6Rel, DSRA_MM64R6_ENC, DSRA_MM64R6_DESC,
-                    ISA_MICROMIPS64R6;
-  def DSRA32_MM64R6 : StdMMR6Rel, DSRA32_MM64R6_ENC, DSRA32_MM64R6_DESC,
-                    ISA_MICROMIPS64R6;
-  def DCLO_MM64R6 : StdMMR6Rel, R6MMR6Rel, DCLO_MM64R6_ENC, DCLO_MM64R6_DESC,
-                    ISA_MICROMIPS64R6;
-  def DCLZ_MM64R6 : StdMMR6Rel, R6MMR6Rel, DCLZ_MM64R6_ENC, DCLZ_MM64R6_DESC,
-                    ISA_MICROMIPS64R6;
-  def DROTR_MM64R6 : StdMMR6Rel, DROTR_MM64R6_ENC, DROTR_MM64R6_DESC,
-                     ISA_MICROMIPS64R6;
-  def DROTR32_MM64R6 : StdMMR6Rel, DROTR32_MM64R6_ENC, DROTR32_MM64R6_DESC,
-                       ISA_MICROMIPS64R6;
-  def DROTRV_MM64R6 : StdMMR6Rel, DROTRV_MM64R6_ENC, DROTRV_MM64R6_DESC,
-                      ISA_MICROMIPS64R6;
-  def LD_MM64R6 : StdMMR6Rel, LD_MM64R6_ENC, LD_MM64R6_DESC,
-                  ISA_MICROMIPS64R6;
-  def LLD_MM64R6 : StdMMR6Rel, R6MMR6Rel, LLD_MM64R6_ENC, LLD_MM64R6_DESC,
-                   ISA_MICROMIPS64R6;
-  def LWU_MM64R6 : StdMMR6Rel, LWU_MM64R6_ENC, LWU_MM64R6_DESC,
-                   ISA_MICROMIPS64R6;
-  def SD_MM64R6 : StdMMR6Rel, SD_MM64R6_ENC, SD_MM64R6_DESC,
-                  ISA_MICROMIPS64R6;
-  def DSRL_MM64R6 : StdMMR6Rel, DSRL_MM64R6_ENC, DSRL_MM64R6_DESC,
-                    ISA_MICROMIPS64R6;
-  def DSRL32_MM64R6 : StdMMR6Rel, DSRL32_MM64R6_ENC, DSRL32_MM64R6_DESC,
-                      ISA_MICROMIPS64R6;
-  def DSRLV_MM64R6 : StdMMR6Rel, DSRLV_MM64R6_ENC, DSRLV_MM64R6_DESC,
-                     ISA_MICROMIPS64R6;
-  def DBITSWAP_MM64R6 : R6MMR6Rel, DBITSWAP_MM64R6_ENC, DBITSWAP_MM64R6_DESC,
-                        ISA_MICROMIPS64R6;
-  def DLSA_MM64R6 : R6MMR6Rel, DLSA_MM64R6_ENC, DLSA_MM64R6_DESC,
-                    ISA_MICROMIPS64R6;
-  def LWUPC_MM64R6 : R6MMR6Rel, LWUPC_MM64R6_ENC, LWUPC_MM64R6_DESC,
-                     ISA_MICROMIPS64R6;
-}
-
-let AdditionalPredicates = [InMicroMips] in
-defm : MaterializeImms<i64, ZERO_64, DADDIU_MM64R6, LUi64, ORi64>;
-
-//===----------------------------------------------------------------------===//
-//
-// Arbitrary patterns that map to one or more instructions
-//
-//===----------------------------------------------------------------------===//
-
-defm : MipsHiLoRelocs<LUi64, DADDIU_MM64R6, ZERO_64, GPR64Opnd>, SYM_32,
-                      ISA_MICROMIPS64R6;
-
-defm : MipsHighestHigherHiLoRelocs<LUi64, DADDIU_MM64R6>, SYM_64,
-                                   ISA_MICROMIPS64R6;
-
-def : MipsPat<(addc GPR64:$lhs, GPR64:$rhs),
-              (DADDU_MM64R6 GPR64:$lhs, GPR64:$rhs)>, ISA_MICROMIPS64R6;
-def : MipsPat<(addc GPR64:$lhs, immSExt16:$imm),
-              (DADDIU_MM64R6 GPR64:$lhs, imm:$imm)>, ISA_MICROMIPS64R6;
-
-
-def : MipsPat<(rotr GPR64:$rt, (i32 (trunc GPR64:$rs))),
-              (DROTRV_MM64R6 GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>,
-              ISA_MICROMIPS64R6;
-
-
-def : WrapperPat<tglobaladdr, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
-def : WrapperPat<tconstpool, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
-def : WrapperPat<texternalsym, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
-def : WrapperPat<tblockaddress, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
-def : WrapperPat<tjumptable, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
-def : WrapperPat<tglobaltlsaddr, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
-
-// Carry pattern
-def : MipsPat<(subc GPR64:$lhs, GPR64:$rhs),
-              (DSUBU_MM64R6 GPR64:$lhs, GPR64:$rhs)>, ISA_MICROMIPS64R6;
-
-def : MipsPat<(atomic_load_64 addr:$a), (LD_MM64R6 addr:$a)>, ISA_MICROMIPS64R6;
-
-//===----------------------------------------------------------------------===//
-//
-// Instruction aliases
-//
-//===----------------------------------------------------------------------===//
-
-def : MipsInstAlias<"dmtc0 $rt, $rd",
-                    (DMTC0_MM64R6 COP0Opnd:$rd, GPR64Opnd:$rt, 0), 0>;
-def : MipsInstAlias<"dmfc0 $rt, $rd",
-                    (DMFC0_MM64R6 GPR64Opnd:$rt, COP0Opnd:$rd, 0), 0>,
-                    ISA_MICROMIPS64R6;
-def : MipsInstAlias<"daddu $rs, $rt, $imm",
-                    (DADDIU_MM64R6 GPR64Opnd:$rs,
-                                   GPR64Opnd:$rt,
-                                   simm16_64:$imm),
-                    0>, ISA_MICROMIPS64R6;
-def : MipsInstAlias<"daddu $rs, $imm",
-                    (DADDIU_MM64R6 GPR64Opnd:$rs,
-                                   GPR64Opnd:$rs,
-                                   simm16_64:$imm),
-                    0>, ISA_MICROMIPS64R6;
-def : MipsInstAlias<"dsubu $rt, $rs, $imm",
-                    (DADDIU_MM64R6 GPR64Opnd:$rt,
-                                   GPR64Opnd:$rs,
-                                   InvertedImOperand64:$imm),
-                    0>, ISA_MICROMIPS64R6;
-def : MipsInstAlias<"dsubu $rs, $imm",
-                    (DADDIU_MM64R6 GPR64Opnd:$rs,
-                                   GPR64Opnd:$rs,
-                                   InvertedImOperand64:$imm),
-                    0>, ISA_MICROMIPS64R6;
-def : MipsInstAlias<"dneg $rt, $rs",
-                    (DSUB_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
-                    ISA_MICROMIPS64R6;
-def : MipsInstAlias<"dneg $rt",
-                    (DSUB_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 1>,
-                    ISA_MICROMIPS64R6;
-def : MipsInstAlias<"dnegu $rt, $rs",
-                    (DSUBU_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
-                    ISA_MICROMIPS64R6;
-def : MipsInstAlias<"dnegu $rt",
-                    (DSUBU_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 1>,
-                    ISA_MICROMIPS64R6;
-def : MipsInstAlias<"dsll $rd, $rt, $rs",
-                    (DSLLV_MM64R6 GPR64Opnd:$rd, GPR64Opnd:$rt,
-                                  GPR32Opnd:$rs), 0>, ISA_MICROMIPS64R6;
-def : MipsInstAlias<"dsrl $rd, $rt, $rs",
-                    (DSRLV_MM64R6 GPR64Opnd:$rd, GPR64Opnd:$rt,
-                                  GPR32Opnd:$rs), 0>, ISA_MICROMIPS64R6;
-def : MipsInstAlias<"dsrl $rd, $rt",
-                    (DSRLV_MM64R6 GPR64Opnd:$rd, GPR64Opnd:$rd,
-                                  GPR32Opnd:$rt), 0>, ISA_MICROMIPS64R6;
-def : MipsInstAlias<"dsll $rd, $rt",
-                    (DSLLV_MM64R6 GPR64Opnd:$rd, GPR64Opnd:$rd,
-                                  GPR32Opnd:$rt), 0>, ISA_MICROMIPS64R6;
Index: Target/Mips/MicroMipsInstrInfo.td
===================================================================
--- Target/Mips/MicroMipsInstrInfo.td
+++ Target/Mips/MicroMipsInstrInfo.td
@@ -587,24 +587,24 @@
 }
 
 def ADDU16_MM : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
-    ARITH_FM_MM16<0>, ISA_MICROMIPS_NOT_32R6_64R6;
+    ARITH_FM_MM16<0>, ISA_MICROMIPS_NOT_32R6;
 def AND16_MM : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
-    LOGIC_FM_MM16<0x2>, ISA_MICROMIPS_NOT_32R6_64R6;
+    LOGIC_FM_MM16<0x2>, ISA_MICROMIPS_NOT_32R6;
 def ANDI16_MM : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>, ANDI_FM_MM16<0x0b>,
-    ISA_MICROMIPS_NOT_32R6_64R6;
+    ISA_MICROMIPS_NOT_32R6;
 def NOT16_MM : NotMM16<"not16", GPRMM16Opnd>, LOGIC_FM_MM16<0x0>,
-    ISA_MICROMIPS_NOT_32R6_64R6;
+    ISA_MICROMIPS_NOT_32R6;
 def OR16_MM : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>, LOGIC_FM_MM16<0x3>,
-    ISA_MICROMIPS_NOT_32R6_64R6;
+    ISA_MICROMIPS_NOT_32R6;
 def SLL16_MM : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
-    SHIFT_FM_MM16<0>, ISA_MICROMIPS_NOT_32R6_64R6;
+    SHIFT_FM_MM16<0>, ISA_MICROMIPS_NOT_32R6;
 def SRL16_MM : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
-    SHIFT_FM_MM16<1>, ISA_MICROMIPS_NOT_32R6_64R6;
+    SHIFT_FM_MM16<1>, ISA_MICROMIPS_NOT_32R6;
 
 def SUBU16_MM : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
-                ARITH_FM_MM16<1>, ISA_MICROMIPS_NOT_32R6_64R6;
+                ARITH_FM_MM16<1>, ISA_MICROMIPS_NOT_32R6;
 def XOR16_MM : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
-               LOGIC_FM_MM16<0x1>, ISA_MICROMIPS_NOT_32R6_64R6;
+               LOGIC_FM_MM16<0x1>, ISA_MICROMIPS_NOT_32R6;
 def LBU16_MM : LoadMM16<"lbu16", GPRMM16Opnd, zextloadi8, II_LBU,
                         mem_mm_4>, LOAD_STORE_FM_MM16<0x02>;
 def LHU16_MM : LoadMM16<"lhu16", GPRMM16Opnd, zextloadi16, II_LHU,
@@ -646,9 +646,9 @@
                 BEQNEZ_FM_MM16<0x2b>;
 def B16_MM : UncondBranchMM16<"b16">, B16_FM;
 def BREAK16_MM : BrkSdbbp16MM<"break16", II_BREAK>, BRKSDBBP16_FM_MM<0x28>,
-    ISA_MICROMIPS_NOT_32R6_64R6;
+    ISA_MICROMIPS_NOT_32R6;
 def SDBBP16_MM : BrkSdbbp16MM<"sdbbp16", II_SDBBP>, BRKSDBBP16_FM_MM<0x2C>,
-    ISA_MICROMIPS_NOT_32R6_64R6;
+    ISA_MICROMIPS_NOT_32R6;
 
 let DecoderNamespace = "MicroMips" in {
   /// Load and Store Instructions - multiple
Index: Target/Mips/MipsISelLowering.cpp
===================================================================
--- Target/Mips/MipsISelLowering.cpp
+++ Target/Mips/MipsISelLowering.cpp
@@ -1395,12 +1395,6 @@
   case Mips::DMOD:
   case Mips::DMODU:
     return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, false);
-  case Mips::DDIV_MM64R6:
-  case Mips::DDIVU_MM64R6:
-  case Mips::DMOD_MM64R6:
-  case Mips::DMODU_MM64R6:
-    return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, true);
-
   case Mips::PseudoSELECT_I:
   case Mips::PseudoSELECT_I64:
   case Mips::PseudoSELECT_S:
Index: Target/Mips/MipsInstrInfo.td
===================================================================
--- Target/Mips/MipsInstrInfo.td
+++ Target/Mips/MipsInstrInfo.td
@@ -208,8 +208,6 @@
                       AssemblerPredicate<"!FeatureMips64r6">;
 def HasMicroMips32r6 : Predicate<"Subtarget->inMicroMips32r6Mode()">,
                        AssemblerPredicate<"FeatureMicroMips,FeatureMips32r6">;
-def HasMicroMips64r6 : Predicate<"Subtarget->inMicroMips64r6Mode()">,
-                       AssemblerPredicate<"FeatureMicroMips,FeatureMips64r6">;
 def InMips16Mode :    Predicate<"Subtarget->inMips16Mode()">,
                       AssemblerPredicate<"FeatureMips16">;
 def HasCnMips    :    Predicate<"Subtarget->hasCnMips()">,
@@ -309,9 +307,6 @@
 class ISA_MICROMIPS32R6 {
   list<Predicate> InsnPredicates = [HasMicroMips32r6];
 }
-class ISA_MICROMIPS64R6 {
-  list<Predicate> InsnPredicates = [HasMicroMips64r6];
-}
 class ISA_MICROMIPS32_NOT_MIPS32R6 {
   list<Predicate> InsnPredicates = [InMicroMips, NotMips32r6];
 }
@@ -389,7 +384,7 @@
 
 // Class used for separating microMIPSr6 and microMIPS (r3) instruction.
 // It can be used only on instructions that doesn't inherit PredicateControl.
-class ISA_MICROMIPS_NOT_32R6_64R6 : PredicateControl {
+class ISA_MICROMIPS_NOT_32R6 : PredicateControl {
   let InsnPredicates = [InMicroMips, NotMips32r6, NotMips64r6];
 }
 
@@ -2937,10 +2932,6 @@
 include "MicroMips32r6InstrFormats.td"
 include "MicroMips32r6InstrInfo.td"
 
-// Micromips64 r6
-include "MicroMips64r6InstrFormats.td"
-include "MicroMips64r6InstrInfo.td"
-
 // Micromips DSP
 include "MicroMipsDSPInstrFormats.td"
 include "MicroMipsDSPInstrInfo.td"
Index: Target/Mips/MipsScheduleP5600.td
===================================================================
--- Target/Mips/MipsScheduleP5600.td
+++ Target/Mips/MipsScheduleP5600.td
@@ -18,8 +18,8 @@
   list<Predicate> UnsupportedFeatures = [HasMips32r6, HasMips64r6,
                                          HasMips64, HasMips64r2, HasCnMips,
                                          InMicroMips, InMips16Mode,
-                                         HasMicroMips32r6, HasMicroMips64r6,
-                                         HasDSP, HasDSPR2, HasMT];
+                                         HasMicroMips32r6, HasDSP, 
+                                         HasDSPR2, HasMT];
 
 }
 
Index: Target/Mips/MipsSubtarget.h
===================================================================
--- Target/Mips/MipsSubtarget.h
+++ Target/Mips/MipsSubtarget.h
@@ -258,7 +258,6 @@
   }
   bool inMicroMipsMode() const { return InMicroMipsMode; }
   bool inMicroMips32r6Mode() const { return InMicroMipsMode && hasMips32r6(); }
-  bool inMicroMips64r6Mode() const { return InMicroMipsMode && hasMips64r6(); }
   bool hasDSP() const { return HasDSP; }
   bool hasDSPR2() const { return HasDSPR2; }
   bool hasDSPR3() const { return HasDSPR3; }
Index: Target/Mips/MipsSubtarget.cpp
===================================================================
--- Target/Mips/MipsSubtarget.cpp
+++ Target/Mips/MipsSubtarget.cpp
@@ -103,6 +103,10 @@
   if (IsFPXX && (isABI_N32() || isABI_N64()))
     report_fatal_error("FPXX is not permitted for the N32/N64 ABI's.", false);
 
+  if (hasMips64r6() && InMicroMipsMode) {
+    report_fatal_error("microMIPS64R6 is not supported");
+  }
+
   if (hasMips32r6()) {
     StringRef ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6";
 
Index: Target/Mips/MipsTargetMachine.cpp
===================================================================
--- Target/Mips/MipsTargetMachine.cpp
+++ Target/Mips/MipsTargetMachine.cpp
@@ -177,6 +177,12 @@
   if (softFloat)
     FS += FS.empty() ? "+soft-float" : ",+soft-float";
 
+  if (CPU == "mips64r6" && HasMicroMipsAttr) {
+    errs() << "LLVM currently does not support microMIPS for '" << CPU << "'.\n";
+    HasMicroMipsAttr = false;
+    HasNoMicroMipsAttr = true;
+  }
+
   auto &I = SubtargetMap[CPU + FS];
   if (!I) {
     // This needs to be done before we create a new subtarget since any