Index: lib/Target/Mips/MicroMipsInstrFPU.td =================================================================== --- lib/Target/Mips/MicroMipsInstrFPU.td +++ lib/Target/Mips/MicroMipsInstrFPU.td @@ -95,7 +95,7 @@ ABS_FM_MM<1, 0x2d>; def FMOV_D32_MM : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>, - ABS_FM_MM<1, 0x1>, Requires<[HasStdEnc, NotFP64bit]>; + ABS_FM_MM<1, 0x1>, AdditionalRequires<[NotFP64bit]>; def MOVZ_I_S_MM : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd, II_MOVZ_S>, CMov_I_F_FM_MM<0x78, 0>; Index: lib/Target/Mips/Mips.td =================================================================== --- lib/Target/Mips/Mips.td +++ lib/Target/Mips/Mips.td @@ -15,6 +15,24 @@ include "llvm/Target/Target.td" +// The overall idea of the PredicateControl class is to chop the Predicates list +// into subsets that are usually overridden independently. This allows +// subclasses to partially override the predicates of their superclasses without +// having to re-add all the existing predicates. +class PredicateControl { + // Predicates for the encoding scheme in use such as HasStdEnc + list EncodingPredicates = []; + // Predicates for anything else + list AdditionalPredicates = []; + list Predicates = !listconcat(EncodingPredicates, + AdditionalPredicates); +} + +// Like Requires<> but for the AdditionalPredicates list +class AdditionalRequires preds> { + list AdditionalPredicates = preds; +} + //===----------------------------------------------------------------------===// // Register File, Calling Conv, Instruction Descriptions //===----------------------------------------------------------------------===// Index: lib/Target/Mips/Mips64InstrInfo.td =================================================================== --- lib/Target/Mips/Mips64InstrInfo.td +++ lib/Target/Mips/Mips64InstrInfo.td @@ -118,7 +118,7 @@ SRA_FM<0x3f, 0>; // Rotate Instructions -let Predicates = [HasStdEnc, HasMips64r2] in { +let AdditionalPredicates = [HasMips64r2] in { def DROTR : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR, rotr, immZExt6>, SRA_FM<0x3a, 1>; def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV, rotr>, @@ -238,7 +238,8 @@ } // Cavium Octeon cmMIPS instructions -let Predicates = [HasCnMips] in { +let EncodingPredicates = [], // FIXME: The lack of HasStdEnc is probably a bug + AdditionalPredicates = [HasCnMips] in { class Count1s: InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), @@ -387,8 +388,7 @@ // truncate def : MipsPat<(i32 (trunc GPR64:$src)), - (SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>, - Requires<[HasStdEnc]>; + (SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>; // 32-to-64-bit extension def : MipsPat<(i64 (anyext GPR32:$src)), (SLL64_32 GPR32:$src)>; Index: lib/Target/Mips/MipsCondMov.td =================================================================== --- lib/Target/Mips/MipsCondMov.td +++ lib/Target/Mips/MipsCondMov.td @@ -132,23 +132,23 @@ let isCodeGenOnly = 1 in def MOVZ_I64_S : CMov_I_F_FT<"movz.s", GPR64Opnd, FGR32Opnd, II_MOVZ_S>, - CMov_I_F_FM<18, 16>, Requires<[HasStdEnc, HasMips64]>; + CMov_I_F_FM<18, 16>, AdditionalRequires<[HasMips64]>; def MOVN_I_S : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd, II_MOVN_S>, CMov_I_F_FM<19, 16>; let isCodeGenOnly = 1 in def MOVN_I64_S : CMov_I_F_FT<"movn.s", GPR64Opnd, FGR32Opnd, II_MOVN_S>, - CMov_I_F_FM<19, 16>, Requires<[HasStdEnc, IsGP64bit]>; + CMov_I_F_FM<19, 16>, AdditionalRequires<[IsGP64bit]>; -let Predicates = [HasStdEnc, NotFP64bit] in { +let AdditionalPredicates = [NotFP64bit] in { def MOVZ_I_D32 : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd, II_MOVZ_D>, CMov_I_F_FM<18, 17>; def MOVN_I_D32 : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd, II_MOVN_D>, CMov_I_F_FM<19, 17>; } -let Predicates = [HasStdEnc, IsFP64bit], DecoderNamespace = "Mips64" in { +let AdditionalPredicates = [IsFP64bit], DecoderNamespace = "Mips64" in { def MOVZ_I_D64 : CMov_I_F_FT<"movz.d", GPR32Opnd, FGR64Opnd, II_MOVZ_D>, CMov_I_F_FM<18, 17>; def MOVN_I_D64 : CMov_I_F_FT<"movn.d", GPR32Opnd, FGR64Opnd, II_MOVN_D>, @@ -166,28 +166,28 @@ let isCodeGenOnly = 1 in def MOVT_I64 : CMov_F_I_FT<"movt", GPR64Opnd, II_MOVT, MipsCMovFP_T>, - CMov_F_I_FM<1>, Requires<[HasStdEnc, IsGP64bit]>; + CMov_F_I_FM<1>, AdditionalRequires<[IsGP64bit]>; def MOVF_I : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF, MipsCMovFP_F>, CMov_F_I_FM<0>; let isCodeGenOnly = 1 in def MOVF_I64 : CMov_F_I_FT<"movf", GPR64Opnd, II_MOVF, MipsCMovFP_F>, - CMov_F_I_FM<0>, Requires<[HasStdEnc, IsGP64bit]>; + CMov_F_I_FM<0>, AdditionalRequires<[IsGP64bit]>; def MOVT_S : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, II_MOVT_S, MipsCMovFP_T>, CMov_F_F_FM<16, 1>; def MOVF_S : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, II_MOVF_S, MipsCMovFP_F>, CMov_F_F_FM<16, 0>; -let Predicates = [HasStdEnc, NotFP64bit] in { +let AdditionalPredicates = [NotFP64bit] in { def MOVT_D32 : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, II_MOVT_D, MipsCMovFP_T>, CMov_F_F_FM<17, 1>; def MOVF_D32 : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, II_MOVF_D, MipsCMovFP_F>, CMov_F_F_FM<17, 0>; } -let Predicates = [HasStdEnc, IsFP64bit], DecoderNamespace = "Mips64" in { +let AdditionalPredicates = [IsFP64bit], DecoderNamespace = "Mips64" in { def MOVT_D64 : CMov_F_F_FT<"movt.d", FGR64Opnd, II_MOVT_D, MipsCMovFP_T>, CMov_F_F_FM<17, 1>; def MOVF_D64 : CMov_F_F_FT<"movf.d", FGR64Opnd, II_MOVF_D, MipsCMovFP_F>, @@ -198,7 +198,7 @@ defm : MovzPats0; defm : MovzPats1; defm : MovzPats2; -let Predicates = [HasStdEnc, IsGP64bit] in { +let AdditionalPredicates = [IsGP64bit] in { defm : MovzPats0; defm : MovzPats0; @@ -213,7 +213,7 @@ } defm : MovnPats; -let Predicates = [HasStdEnc, IsGP64bit] in { +let AdditionalPredicates = [IsGP64bit] in { defm : MovnPats; defm : MovnPats; defm : MovnPats; @@ -222,19 +222,19 @@ defm : MovzPats0; defm : MovzPats1; defm : MovnPats; -let Predicates = [HasStdEnc, IsGP64bit] in { +let AdditionalPredicates = [IsGP64bit] in { defm : MovzPats0; defm : MovzPats1; defm : MovnPats; } -let Predicates = [HasStdEnc, NotFP64bit] in { +let AdditionalPredicates = [NotFP64bit] in { defm : MovzPats0; defm : MovzPats1; defm : MovnPats; } -let Predicates = [HasStdEnc, IsFP64bit] in { +let AdditionalPredicates = [IsFP64bit] in { defm : MovzPats0; defm : MovzPats0; Index: lib/Target/Mips/MipsInstrFPU.td =================================================================== --- lib/Target/Mips/MipsInstrFPU.td +++ lib/Target/Mips/MipsInstrFPU.td @@ -100,10 +100,10 @@ multiclass ADDS_M { def _D32 : MMRel, ADDS_FT, - Requires<[HasStdEnc, NotFP64bit]>; + AdditionalRequires<[NotFP64bit]>; def _D64 : ADDS_FT, - Requires<[HasStdEnc, IsFP64bit]> { + AdditionalRequires<[IsFP64bit]> { string DecoderNamespace = "Mips64"; } } @@ -117,18 +117,18 @@ multiclass ABSS_M { def _D32 : MMRel, ABSS_FT, - Requires<[HasStdEnc, NotFP64bit]>; + AdditionalRequires<[NotFP64bit]>; def _D64 : ABSS_FT, - Requires<[HasStdEnc, IsFP64bit]> { + AdditionalRequires<[IsFP64bit]> { string DecoderNamespace = "Mips64"; } } multiclass ROUND_M { def _D32 : MMRel, ABSS_FT, - Requires<[HasStdEnc, NotFP64bit]>; + AdditionalRequires<[NotFP64bit]>; def _D64 : ABSS_FT, - Requires<[HasStdEnc, IsFP64bit]> { + AdditionalRequires<[IsFP64bit]> { let DecoderNamespace = "Mips64"; } } @@ -241,10 +241,10 @@ defm S : C_COND_M<"s", FGR32Opnd, 16, II_C_CC_S>; defm D32 : C_COND_M<"d", AFGR64Opnd, 17, II_C_CC_D>, - Requires<[HasStdEnc, NotFP64bit]>; + AdditionalRequires<[NotFP64bit]>; let DecoderNamespace = "Mips64" in defm D64 : C_COND_M<"d", FGR64Opnd, 17, II_C_CC_D>, - Requires<[HasStdEnc, IsFP64bit]>; + AdditionalRequires<[IsFP64bit]>; //===----------------------------------------------------------------------===// // Floating Point Instructions @@ -266,7 +266,7 @@ defm FLOOR_W : ROUND_M<"floor.w.d", II_FLOOR>, ABSS_FM<0xf, 17>; defm CVT_W : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>; -let Predicates = [HasStdEnc, IsFP64bit], DecoderNamespace = "Mips64" in { +let AdditionalPredicates = [IsFP64bit], DecoderNamespace = "Mips64" in { def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, II_ROUND>, ABSS_FM<0x8, 16>; def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64Opnd, FGR64Opnd, II_ROUND>, @@ -292,7 +292,7 @@ def CVT_L_D64: MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>, ABSS_FM<0x25, 17>; -let Predicates = [HasStdEnc, NotFP64bit] in { +let AdditionalPredicates = [NotFP64bit] in { def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>, ABSS_FM<0x20, 17>; def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>, @@ -301,7 +301,7 @@ ABSS_FM<0x21, 16>; } -let Predicates = [HasStdEnc, IsFP64bit], DecoderNamespace = "Mips64" in { +let AdditionalPredicates = [IsFP64bit], DecoderNamespace = "Mips64" in { def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>, ABSS_FM<0x20, 17>; def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, II_CVT>, @@ -357,9 +357,9 @@ def FMOV_S : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>, ABSS_FM<0x6, 16>; def FMOV_D32 : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, II_MOV_D>, - ABSS_FM<0x6, 17>, Requires<[HasStdEnc, NotFP64bit]>; + ABSS_FM<0x6, 17>, AdditionalRequires<[NotFP64bit]>; def FMOV_D64 : ABSS_FT<"mov.d", FGR64Opnd, FGR64Opnd, II_MOV_D>, - ABSS_FM<0x6, 17>, Requires<[HasStdEnc, IsFP64bit]> { + ABSS_FM<0x6, 17>, AdditionalRequires<[IsFP64bit]> { let DecoderNamespace = "Mips64"; } @@ -367,12 +367,12 @@ def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opnd, II_LWC1, load>, LW_FM<0x31>; def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, II_SWC1, store>, LW_FM<0x39>; -let Predicates = [HasStdEnc, IsFP64bit], DecoderNamespace = "Mips64" in { +let AdditionalPredicates = [IsFP64bit], DecoderNamespace = "Mips64" in { def LDC164 : LW_FT<"ldc1", FGR64Opnd, II_LDC1, load>, LW_FM<0x35>; def SDC164 : SW_FT<"sdc1", FGR64Opnd, II_SDC1, store>, LW_FM<0x3d>; } -let Predicates = [HasStdEnc, NotFP64bit] in { +let AdditionalPredicates = [NotFP64bit] in { def LDC1 : MMRel, LW_FT<"ldc1", AFGR64Opnd, II_LDC1, load>, LW_FM<0x35>; def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, II_SDC1, store>, LW_FM<0x3d>; } @@ -386,30 +386,30 @@ // Indexed loads and stores. // Base register + offset register addressing mode (indicated by "x" in the // instruction mnemonic) is disallowed under NaCl. -let Predicates = [HasStdEnc, IsNotNaCl, HasFPIdx] in { +let AdditionalPredicates = [IsNotNaCl, HasFPIdx] in { def LWXC1 : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>, LWXC1_FM<0>; def SWXC1 : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, SWXC1_FM<8>; } -let Predicates = [HasStdEnc, HasFPIdx, NotFP64bit, NotInMicroMips, - IsNotNaCl] in { +let AdditionalPredicates = [HasFPIdx, NotFP64bit, NotInMicroMips, + IsNotNaCl] in { def LDXC1 : LWXC1_FT<"ldxc1", AFGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>; def SDXC1 : SWXC1_FT<"sdxc1", AFGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>; } -let Predicates = [HasStdEnc, HasFPIdx, IsFP64bit], +let AdditionalPredicates = [HasFPIdx, IsFP64bit], DecoderNamespace="Mips64" in { def LDXC164 : LWXC1_FT<"ldxc1", FGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>; def SDXC164 : SWXC1_FT<"sdxc1", FGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>; } // Load/store doubleword indexed unaligned. -let Predicates = [HasStdEnc, NotFP64bit, IsNotNaCl] in { +let AdditionalPredicates = [NotFP64bit, IsNotNaCl] in { def LUXC1 : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>; def SUXC1 : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>; } -let Predicates = [HasStdEnc, IsFP64bit], DecoderNamespace="Mips64" in { +let AdditionalPredicates = [IsFP64bit], DecoderNamespace="Mips64" in { def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>; def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>; } @@ -428,42 +428,42 @@ ADDS_FM<0x01, 16>; defm FSUB : ADDS_M<"sub.d", II_SUB_D, 0, fsub>, ADDS_FM<0x01, 17>; -let Predicates = [HasStdEnc, HasMips32r2] in { +let AdditionalPredicates = [HasMips32r2] in { def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>, MADDS_FM<4, 0>; def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>, MADDS_FM<5, 0>; } -let Predicates = [HasStdEnc, HasMips32r2, NoNaNsFPMath] in { +let AdditionalPredicates = [HasMips32r2, NoNaNsFPMath] in { def NMADD_S : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>, MADDS_FM<6, 0>; def NMSUB_S : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>, MADDS_FM<7, 0>; } -let Predicates = [HasStdEnc, HasMips32r2, NotFP64bit] in { +let AdditionalPredicates = [HasMips32r2, NotFP64bit] in { def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>, MADDS_FM<4, 1>; def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>, MADDS_FM<5, 1>; } -let Predicates = [HasStdEnc, HasMips32r2, NotFP64bit, NoNaNsFPMath] in { +let AdditionalPredicates = [HasMips32r2, NotFP64bit, NoNaNsFPMath] in { def NMADD_D32 : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>, MADDS_FM<6, 1>; def NMSUB_D32 : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>, MADDS_FM<7, 1>; } -let Predicates = [HasStdEnc, HasMips32r2, IsFP64bit], isCodeGenOnly=1 in { +let AdditionalPredicates = [HasMips32r2, IsFP64bit], isCodeGenOnly=1 in { def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, fadd>, MADDS_FM<4, 1>; def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, fsub>, MADDS_FM<5, 1>; } -let Predicates = [HasStdEnc, HasMips32r2, IsFP64bit, NoNaNsFPMath], +let AdditionalPredicates = [HasMips32r2, IsFP64bit, NoNaNsFPMath], isCodeGenOnly=1 in { def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, II_NMADD_D, fadd>, MADDS_FM<6, 1>; @@ -509,10 +509,10 @@ /// Floating Point Compare def FCMP_S32 : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>, CEQS_FM<16>; def FCMP_D32 : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>, - Requires<[HasStdEnc, NotFP64bit]>; + AdditionalRequires<[NotFP64bit]>; let DecoderNamespace = "Mips64" in def FCMP_D64 : CEQS_FT<"d", FGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>, - Requires<[HasStdEnc, IsFP64bit]>; + AdditionalRequires<[IsFP64bit]>; //===----------------------------------------------------------------------===// // Floating Point Pseudo-Instructions @@ -525,9 +525,9 @@ [(set RO:$dst, (MipsBuildPairF64 GPR32Opnd:$lo, GPR32Opnd:$hi))]>; def BuildPairF64 : BuildPairF64Base, - Requires<[HasStdEnc, NotFP64bit]>; + AdditionalRequires<[NotFP64bit]>; def BuildPairF64_64 : BuildPairF64Base, - Requires<[HasStdEnc, IsFP64bit]>; + AdditionalRequires<[IsFP64bit]>; // This pseudo instr gets expanded into 2 mfc1 instrs after register // allocation. @@ -538,9 +538,9 @@ [(set GPR32Opnd:$dst, (MipsExtractElementF64 RO:$src, imm:$n))]>; def ExtractElementF64 : ExtractElementF64Base, - Requires<[HasStdEnc, NotFP64bit]>; + AdditionalRequires<[NotFP64bit]>; def ExtractElementF64_64 : ExtractElementF64Base, - Requires<[HasStdEnc, IsFP64bit]>; + AdditionalRequires<[IsFP64bit]>; //===----------------------------------------------------------------------===// // InstAliases. @@ -559,7 +559,7 @@ def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src), (TRUNC_W_S FGR32Opnd:$src)>; -let Predicates = [HasStdEnc, NotFP64bit] in { +let AdditionalPredicates = [NotFP64bit] in { def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)), (PseudoCVT_D32_W GPR32Opnd:$src)>; def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src), @@ -570,7 +570,7 @@ (CVT_D32_S FGR32Opnd:$src)>; } -let Predicates = [HasStdEnc, IsFP64bit] in { +let AdditionalPredicates = [IsFP64bit] in { def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>; def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>; @@ -599,12 +599,12 @@ def : LoadRegImmPat; def : StoreRegImmPat; - let Predicates = [HasStdEnc, IsFP64bit] in { + let AdditionalPredicates = [IsFP64bit] in { def : LoadRegImmPat; def : StoreRegImmPat; } - let Predicates = [HasStdEnc, NotFP64bit] in { + let AdditionalPredicates = [NotFP64bit] in { def : LoadRegImmPat; def : StoreRegImmPat; } Index: lib/Target/Mips/MipsInstrFormats.td =================================================================== --- lib/Target/Mips/MipsInstrFormats.td +++ lib/Target/Mips/MipsInstrFormats.td @@ -93,8 +93,8 @@ // Mips32/64 Instruction Format class InstSE pattern, InstrItinClass itin, Format f, string opstr = ""> : - MipsInst { - let Predicates = [HasStdEnc]; + MipsInst, PredicateControl { + let EncodingPredicates = [HasStdEnc]; string BaseOpcode = opstr; string Arch; } @@ -109,9 +109,9 @@ // Mips32/64 Pseudo Instruction Format class PseudoSE pattern, - InstrItinClass itin = IIPseudo>: - MipsPseudo { - let Predicates = [HasStdEnc]; + InstrItinClass itin = IIPseudo> : + MipsPseudo, PredicateControl { + let EncodingPredicates = [HasStdEnc]; } // Pseudo-instructions for alternate assembly syntax (never used by codegen). Index: lib/Target/Mips/MipsInstrInfo.td =================================================================== --- lib/Target/Mips/MipsInstrInfo.td +++ lib/Target/Mips/MipsInstrInfo.td @@ -194,8 +194,8 @@ def IsBE : Predicate<"!Subtarget.isLittle()">; def IsNotNaCl : Predicate<"!Subtarget.isTargetNaCl()">; -class MipsPat : Pat { - let Predicates = [HasStdEnc]; +class MipsPat : Pat, PredicateControl { + let EncodingPredicates = [HasStdEnc]; } class IsCommutable { @@ -603,7 +603,7 @@ let isTerminator = 1; let isBarrier = 1; let hasDelaySlot = 1; - let Predicates = [HasStdEnc, RelocPIC]; + let AdditionalPredicates = [RelocPIC]; let Defs = [AT]; } @@ -793,26 +793,26 @@ class CountLeading0: InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>, - Requires<[HasStdEnc, HasBitCount]>; + AdditionalRequires<[HasBitCount]>; class CountLeading1: InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>, - Requires<[HasStdEnc, HasBitCount]>; + AdditionalRequires<[HasBitCount]>; // Sign Extend in Register. class SignExtInReg : InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr> { - let Predicates = [HasStdEnc, HasSEInReg]; + let AdditionalPredicates = [HasSEInReg]; } // Subword Swap class SubwordSwap: InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [], NoItinerary, FrmR, opstr> { - let Predicates = [HasStdEnc, HasSwap]; + let AdditionalPredicates = [HasSwap]; let neverHasSideEffects = 1; } @@ -828,7 +828,7 @@ !strconcat(opstr, " $rt, $rs, $pos, $size"), [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary, FrmR, opstr> { - let Predicates = [HasStdEnc, HasMips32r2]; + let AdditionalPredicates = [HasMips32r2]; } class InsBase { - let Predicates = [HasStdEnc, HasMips32r2]; + let AdditionalPredicates = [HasMips32r2]; let Constraints = "$src = $rt"; } @@ -990,7 +990,7 @@ SRLV_FM<7, 0>; // Rotate Instructions -let Predicates = [HasStdEnc, HasMips32r2] in { +let AdditionalPredicates = [HasMips32r2] in { def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr, immZExt5>, SRA_FM<2, 1>; def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>, @@ -1012,7 +1012,8 @@ def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>; /// load/store left/right -let Predicates = [NotInMicroMips] in { +let EncodingPredicates = [], // FIXME: Lack of HasStdEnc is probably a bug + AdditionalPredicates = [NotInMicroMips] in { def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>; def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>; def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>; @@ -1044,7 +1045,8 @@ def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>; def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>; -let Predicates = [NotInMicroMips] in { +let EncodingPredicates = [], // FIXME: Lack of HasStdEnc is probably a bug + AdditionalPredicates = [NotInMicroMips] in { def WAIT : WAIT_FT<"wait">, WAIT_FM; /// Load-linked, Store-conditional @@ -1054,7 +1056,7 @@ /// Jump and Branch Instructions def J : MMRel, JumpFJ, FJ<2>, - Requires<[HasStdEnc, RelocStatic]>, IsBranch; + AdditionalRequires<[RelocStatic]>, IsBranch; def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>; def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>; def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>; @@ -1069,7 +1071,7 @@ def B : UncondBranch; def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>; -let Predicates = [HasStdEnc, NotInMicroMips] in { +let AdditionalPredicates = [NotInMicroMips] in { def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM; def JALRPseudo : JumpLinkRegPseudo; } @@ -1115,7 +1117,8 @@ def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>; def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>; -let Predicates = [NotInMicroMips] in { +let EncodingPredicates = [], // FIXME: Lack of HasStdEnc is probably a bug + AdditionalPredicates = [NotInMicroMips] in { def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>; def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>; } @@ -1146,7 +1149,7 @@ def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>; def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>; -let Predicates = [HasStdEnc, NotDSP] in { +let AdditionalPredicates = [NotDSP] in { def PseudoMULT : MultDivPseudo; def PseudoMULTu : MultDivPseudo; def PseudoMFHI : PseudoMFLOHI; @@ -1289,7 +1292,7 @@ // Carry MipsPatterns def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs), (SUBu GPR32:$lhs, GPR32:$rhs)>; -let Predicates = [HasStdEnc, NotDSP] in { +let AdditionalPredicates = [NotDSP] in { def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs), (ADDu GPR32:$lhs, GPR32:$rhs)>; def : MipsPat<(addc GPR32:$src, immSExt16:$imm),