Index: lib/Target/X86/X86.td =================================================================== --- lib/Target/X86/X86.td +++ lib/Target/X86/X86.td @@ -296,29 +296,100 @@ include "X86Schedule.td" +def ProcIntelGeneric : SubtargetFeature<"generic", "X86ProcFamily", + "IntelGeneric", "Intel Generic processors">; +def ProcIntelI386 : SubtargetFeature<"i386", "X86ProcFamily", + "IntelI386", "Intel I386 processors">; +def ProcIntelI486 : SubtargetFeature<"i486", "X86ProcFamily", + "IntelI486", "Intel I486 processors">; +def ProcIntelI586 : SubtargetFeature<"i586", "X86ProcFamily", + "IntelI586", "Intel I586 processors">; +def ProcIntelPentium : SubtargetFeature<"pentium", "X86ProcFamily", + "IntelPentium", "Intel Pentium processors">; +def ProcIntelPentiumMMX : SubtargetFeature<"pentium-mmx", "X86ProcFamily", + "IntelPentiumMMX", "Intel MMX processors">; +def ProcIntelI686 : SubtargetFeature<"i686", "X86ProcFamily", + "IntelI686", "Intel I686 processors">; +def ProcIntelPentiumPro : SubtargetFeature<"pentiumpro", "X86ProcFamily", + "IntelPentiumPro", "Intel Pro processors">; +def ProcIntelPentium2 : SubtargetFeature<"pentium2", "X86ProcFamily", + "IntelPentium2", "Intel Pentium2 processors">; +def ProcIntelPentium3 : SubtargetFeature<"pentium3", "X86ProcFamily", + "IntelPentium3", "Intel Pentium3 processors">; +def ProcIntelPentium3m : SubtargetFeature<"pentium3m", "X86ProcFamily", + "IntelPentium3m", "Intel Pentium3M processors">; +def ProcIntelPentiumM : SubtargetFeature<"pentium-m", "X86ProcFamily", + "IntelPentiumM", "Intel PentiumM processors">; +def ProcIntelPentium4 : SubtargetFeature<"pentium4", "X86ProcFamily", + "IntelPentium4", "Intel Pentium4 processors">; +def ProcIntelPentium4m : SubtargetFeature<"pentium4m", "X86ProcFamily", + "IntelPentium4m", "Intel Pentium4M processors">; +def ProcIntelLakemont : SubtargetFeature<"lakemont", "X86ProcFamily", + "IntelLakemont", "Intel Lakemont processors">; +def ProcIntelYonah : SubtargetFeature<"yonah", "X86ProcFamily", + "IntelYonah", "Intel Yonah processors">; +def ProcIntelPrescott : SubtargetFeature<"prescott", "X86ProcFamily", + "IntelPrescott", "Intel Prescott processors">; +def ProcIntelNocona : SubtargetFeature<"nocona", "X86ProcFamily", + "IntelNocona", "Intel Nocona processors">; +def ProcIntelCore2 : SubtargetFeature<"core2", "X86ProcFamily", + "IntelCore2", "Intel Core2 processors">; +def ProcIntelPenryn : SubtargetFeature<"penryn", "X86ProcFamily", + "IntelPenryn", "Intel Penryn processors">; def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom", "Intel Atom processors">; def ProcIntelSLM : SubtargetFeature<"slm", "X86ProcFamily", "IntelSLM", "Intel Silvermont processors">; def ProcIntelGLM : SubtargetFeature<"glm", "X86ProcFamily", "IntelGLM", "Intel Goldmont processors">; +def ProcIntelNehalem : SubtargetFeature<"nehalem", "X86ProcFamily", + "IntelNehalem", "Intel Nehalem processors">; +def ProcIntelWestmere : SubtargetFeature<"westmere", "X86ProcFamily", + "IntelWestmere", "Intel Westmere processors">; +def ProcIntelSNB : SubtargetFeature<"sandybridge", "X86ProcFamily", + "IntelSandyBridge", "Intel SandyBridge processors">; +def ProcIntelIVB : SubtargetFeature<"ivybridge", "X86ProcFamily", + "IntelIvyBridge", "Intel IvyBridge processors">; +def ProcIntelHSW : SubtargetFeature<"haswell", "X86ProcFamily", + "IntelHaswell", "Intel Haswell processors">; +def ProcIntelBDW : SubtargetFeature<"broadwell", "X86ProcFamily", + "IntelBroadwell", "Intel Broadwell processors">; +def ProcIntelSKL : SubtargetFeature<"skylake", "X86ProcFamily", + "IntelSkylake", "Intel Skylake processors">; +def ProcIntelKNL : SubtargetFeature<"knl", "X86ProcFamily", + "IntelKNL", "Intel Knights Landing processors">; +def ProcIntelSKX : SubtargetFeature<"skx", "X86ProcFamily", + "IntelSKX", "Intel Skylake Server processors">; +def ProcIntelCNL : SubtargetFeature<"cannonlake", "X86ProcFamily", + "IntelCannonlake", "Intel Cannonlake processors">; class Proc Features> : ProcessorModel; -def : Proc<"generic", [FeatureX87, FeatureSlowUAMem16]>; -def : Proc<"i386", [FeatureX87, FeatureSlowUAMem16]>; -def : Proc<"i486", [FeatureX87, FeatureSlowUAMem16]>; -def : Proc<"i586", [FeatureX87, FeatureSlowUAMem16]>; -def : Proc<"pentium", [FeatureX87, FeatureSlowUAMem16]>; -def : Proc<"pentium-mmx", [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>; -def : Proc<"i686", [FeatureX87, FeatureSlowUAMem16]>; -def : Proc<"pentiumpro", [FeatureX87, FeatureSlowUAMem16, FeatureCMOV]>; -def : Proc<"pentium2", [FeatureX87, FeatureSlowUAMem16, FeatureMMX, +def : Proc<"generic", [ProcIntelGeneric, FeatureX87, + FeatureSlowUAMem16]>; +def : Proc<"i386", [ProcIntelI386, FeatureX87, + FeatureSlowUAMem16]>; +def : Proc<"i486", [ProcIntelI486, FeatureX87, + FeatureSlowUAMem16]>; +def : Proc<"i586", [ProcIntelI586, FeatureX87, + FeatureSlowUAMem16]>; +def : Proc<"pentium", [ProcIntelPentium, FeatureX87, + FeatureSlowUAMem16]>; +def : Proc<"pentium-mmx", [ProcIntelPentiumMMX, FeatureX87, + FeatureSlowUAMem16, FeatureMMX]>; +def : Proc<"i686", [ProcIntelI686, FeatureX87, + FeatureSlowUAMem16]>; +def : Proc<"pentiumpro", [ProcIntelPentiumPro, FeatureX87, + FeatureSlowUAMem16, FeatureCMOV]>; +def : Proc<"pentium2", [ProcIntelPentium2, FeatureX87, + FeatureSlowUAMem16, FeatureMMX, FeatureCMOV, FeatureFXSR]>; -def : Proc<"pentium3", [FeatureX87, FeatureSlowUAMem16, FeatureMMX, +def : Proc<"pentium3", [ProcIntelPentium3, FeatureX87, + FeatureSlowUAMem16, FeatureMMX, FeatureSSE1, FeatureFXSR]>; -def : Proc<"pentium3m", [FeatureX87, FeatureSlowUAMem16, FeatureMMX, +def : Proc<"pentium3m", [ProcIntelPentium3m, FeatureX87, + FeatureSlowUAMem16, FeatureMMX, FeatureSSE1, FeatureFXSR, FeatureSlowBTMem]>; // Enable the PostRAScheduler for SSE2 and SSE3 class cpus. @@ -332,30 +403,36 @@ // changes slightly. def : ProcessorModel<"pentium-m", GenericPostRAModel, - [FeatureX87, FeatureSlowUAMem16, FeatureMMX, + [ProcIntelPentiumM, FeatureX87, + FeatureSlowUAMem16, FeatureMMX, FeatureSSE2, FeatureFXSR, FeatureSlowBTMem]>; def : ProcessorModel<"pentium4", GenericPostRAModel, - [FeatureX87, FeatureSlowUAMem16, FeatureMMX, + [ProcIntelPentium4, FeatureX87, + FeatureSlowUAMem16, FeatureMMX, FeatureSSE2, FeatureFXSR]>; def : ProcessorModel<"pentium4m", GenericPostRAModel, - [FeatureX87, FeatureSlowUAMem16, FeatureMMX, + [ProcIntelPentium4m, FeatureX87, + FeatureSlowUAMem16, FeatureMMX, FeatureSSE2, FeatureFXSR, FeatureSlowBTMem]>; // Intel Quark. -def : Proc<"lakemont", []>; +def : Proc<"lakemont", [ProcIntelLakemont]>; // Intel Core Duo. def : ProcessorModel<"yonah", SandyBridgeModel, - [FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, + [ProcIntelYonah, FeatureX87, + FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, FeatureFXSR, FeatureSlowBTMem]>; // NetBurst. def : ProcessorModel<"prescott", GenericPostRAModel, - [FeatureX87, FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, + [ProcIntelPrescott, FeatureX87, + FeatureSlowUAMem16, FeatureMMX, FeatureSSE3, FeatureFXSR, FeatureSlowBTMem]>; def : ProcessorModel<"nocona", GenericPostRAModel, [ + ProcIntelNocona, FeatureX87, FeatureSlowUAMem16, FeatureMMX, @@ -367,6 +444,7 @@ // Intel Core 2 Solo/Duo. def : ProcessorModel<"core2", SandyBridgeModel, [ + ProcIntelCore2, FeatureX87, FeatureSlowUAMem16, FeatureMMX, @@ -377,6 +455,7 @@ FeatureLAHFSAHF ]>; def : ProcessorModel<"penryn", SandyBridgeModel, [ + ProcIntelPenryn, FeatureX87, FeatureSlowUAMem16, FeatureMMX, @@ -463,6 +542,7 @@ // "Arrandale" along with corei3 and corei5 class NehalemProc : ProcessorModel : ProcessorModel : ProcModel; @@ -537,6 +619,7 @@ class IvyBridgeProc : ProcModel; @@ -555,11 +638,14 @@ ]>; class HaswellProc : ProcModel; + HSWFeatures.Value, [ + ProcIntelHSW + ]>; def : HaswellProc<"haswell">; def : HaswellProc<"core-avx2">; // Legacy alias. def BDWFeatures : ProcessorFeatures; @@ -579,12 +665,15 @@ // FIXME: define SKL model class SkylakeClientProc : ProcModel; + SKLFeatures.Value, [ + ProcIntelSKL + ]>; def : SkylakeClientProc<"skylake">; // FIXME: define KNL model class KnightsLandingProc : ProcModel : ProcModel; + SKXFeatures.Value, [ + ProcIntelSKX + ]>; def : SkylakeServerProc<"skylake-avx512">; def : SkylakeServerProc<"skx">; // Legacy alias. @@ -624,7 +715,9 @@ ]>; class CannonlakeProc : ProcModel; + CNLFeatures.Value, [ + ProcIntelCNL + ]>; def : CannonlakeProc<"cannonlake">; // AMD CPUs. Index: lib/Target/X86/X86Subtarget.h =================================================================== --- lib/Target/X86/X86Subtarget.h +++ lib/Target/X86/X86Subtarget.h @@ -58,7 +58,40 @@ }; enum X86ProcFamilyEnum { - Others, IntelAtom, IntelSLM, IntelGLM + Others, + IntelGeneric, + IntelI386, + IntelI486, + IntelI586, + IntelPentium, + IntelPentiumMMX, + IntelI686, + IntelPentiumPro, + IntelPentium2, + IntelPentium3, + IntelPentium3m, + IntelPentiumM, + IntelPentium4, + IntelPentium4m, + IntelLakemont, + IntelYonah, + IntelPrescott, + IntelNocona, + IntelCore2, + IntelPenryn, + IntelAtom, + IntelSLM, + IntelGLM, + IntelNehalem, + IntelWestmere, + IntelSandyBridge, + IntelIvyBridge, + IntelHaswell, + IntelBroadwell, + IntelSkylake, + IntelKNL, + IntelSKX, + IntelCannonlake }; /// X86 processor family: Intel Atom, and others @@ -332,6 +365,9 @@ /// True if compiling for 16-bit, false for 32-bit or 64-bit. bool In16BitMode; + /// Contains the Overhead of gather instruction + unsigned GatherOverhead; + X86SelectionDAGInfo TSInfo; // Ordering here is important. X86InstrInfo initializes X86RegisterInfo which // X86TargetLowering needs. @@ -477,6 +513,7 @@ bool isPMULLDSlow() const { return IsPMULLDSlow; } bool isUnalignedMem16Slow() const { return IsUAMem16Slow; } bool isUnalignedMem32Slow() const { return IsUAMem32Slow; } + unsigned getGatherOverhead() const { return GatherOverhead; } bool hasSSEUnalignedMem() const { return HasSSEUnalignedMem; } bool hasCmpxchg16b() const { return HasCmpxchg16b; } bool useLeaForSP() const { return UseLeaForSP; } @@ -509,8 +546,12 @@ bool isXRaySupported() const override { return is64Bit(); } + X86ProcFamilyEnum getProcFamily() const { return X86ProcFamily; } + + /// TODO: to be removed later and replaced with suitable properties bool isAtom() const { return X86ProcFamily == IntelAtom; } bool isSLM() const { return X86ProcFamily == IntelSLM; } + bool useSoftFloat() const { return UseSoftFloat; } /// Use mfence if we have SSE2 or we're on x86-64 (even if we asked for Index: lib/Target/X86/X86Subtarget.cpp =================================================================== --- lib/Target/X86/X86Subtarget.cpp +++ lib/Target/X86/X86Subtarget.cpp @@ -263,6 +263,15 @@ else if (isTargetDarwin() || isTargetLinux() || isTargetSolaris() || isTargetKFreeBSD() || In64BitMode) stackAlignment = 16; + + switch(X86ProcFamily) { + case IntelSkylake: + case IntelSKX: + GatherOverhead = 2; + break; + default: + GatherOverhead = INT_MAX; + } } void X86Subtarget::initializeEnvironment() { @@ -340,6 +349,7 @@ // FIXME: this is a known good value for Yonah. How about others? MaxInlineSizeThreshold = 128; UseSoftFloat = false; + GatherOverhead = INT_MAX; } X86Subtarget &X86Subtarget::initializeSubtargetDependencies(StringRef CPU,