Index: lib/Target/Hexagon/HexagonInstrFormats.td =================================================================== --- lib/Target/Hexagon/HexagonInstrFormats.td +++ lib/Target/Hexagon/HexagonInstrFormats.td @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// -// Hexagon Intruction Flags + +// Hexagon Instruction Flags + // // *** Must match HexagonBaseInfo.h *** //===----------------------------------------------------------------------===// @@ -68,7 +68,7 @@ //===----------------------------------------------------------------------===// -// Intruction Class Declaration + +// Instruction Class Declaration + //===----------------------------------------------------------------------===// class OpcodeHexagon { @@ -104,54 +104,72 @@ // Solo instructions, i.e., those that cannot be in a packet with others. bits<1> isSolo = 0; let TSFlags{5} = isSolo; + // Packed only with A or X-type instructions. + bits<1> isSoloAX = 0; + let TSFlags{6} = isSoloAX; + // Only A-type instruction in first slot or nothing. + bits<1> isSoloAin1 = 0; + let TSFlags{7} = isSoloAin1; // Predicated instructions. bits<1> isPredicated = 0; - let TSFlags{6} = isPredicated; + let TSFlags{8} = isPredicated; bits<1> isPredicatedFalse = 0; - let TSFlags{7} = isPredicatedFalse; + let TSFlags{9} = isPredicatedFalse; bits<1> isPredicatedNew = 0; - let TSFlags{8} = isPredicatedNew; + let TSFlags{10} = isPredicatedNew; + bits<1> isPredicateLate = 0; + let TSFlags{11} = isPredicateLate; // Late predicate producer insn. // New-value insn helper fields. bits<1> isNewValue = 0; - let TSFlags{9} = isNewValue; // New-value consumer insn. + let TSFlags{12} = isNewValue; // New-value consumer insn. bits<1> hasNewValue = 0; - let TSFlags{10} = hasNewValue; // New-value producer insn. + let TSFlags{13} = hasNewValue; // New-value producer insn. bits<3> opNewValue = 0; - let TSFlags{13-11} = opNewValue; // New-value produced operand. - bits<2> opNewBits = 0; - let TSFlags{15-14} = opNewBits; // New-value opcode bits location: 0, 8, 16. + let TSFlags{16-14} = opNewValue; // New-value produced operand. bits<1> isNVStorable = 0; - let TSFlags{16} = isNVStorable; // Store that can become new-value store. + let TSFlags{17} = isNVStorable; // Store that can become new-value store. bits<1> isNVStore = 0; - let TSFlags{17} = isNVStore; // New-value store insn. + let TSFlags{18} = isNVStore; // New-value store insn. + bits<1> isCVLoadable = 0; + let TSFlags{19} = isCVLoadable; // Load that can become cur-value load. + bits<1> isCVLoad = 0; + let TSFlags{20} = isCVLoad; // Cur-value load insn. // Immediate extender helper fields. bits<1> isExtendable = 0; - let TSFlags{18} = isExtendable; // Insn may be extended. + let TSFlags{21} = isExtendable; // Insn may be extended. bits<1> isExtended = 0; - let TSFlags{19} = isExtended; // Insn must be extended. + let TSFlags{22} = isExtended; // Insn must be extended. bits<3> opExtendable = 0; - let TSFlags{22-20} = opExtendable; // Which operand may be extended. + let TSFlags{25-23} = opExtendable; // Which operand may be extended. bits<1> isExtentSigned = 0; - let TSFlags{23} = isExtentSigned; // Signed or unsigned range. + let TSFlags{26} = isExtentSigned; // Signed or unsigned range. bits<5> opExtentBits = 0; - let TSFlags{28-24} = opExtentBits; //Number of bits of range before extending. + let TSFlags{31-27} = opExtentBits; //Number of bits of range before extending. + bits<2> opExtentAlign = 0; + let TSFlags{33-32} = opExtentAlign; // Alignment exponent before extending. // If an instruction is valid on a subtarget (v2-v5), set the corresponding // bit from validSubTargets. v2 is the least significant bit. // By default, instruction is valid on all subtargets. SubTarget validSubTargets = HasV2SubT; - let TSFlags{32-29} = validSubTargets.Value; + let TSFlags{37-34} = validSubTargets.Value; // Addressing mode for load/store instructions. AddrModeType addrMode = NoAddrMode; - let TSFlags{35-33} = addrMode.Value; + let TSFlags{42-40} = addrMode.Value; // Memory access size for mem access instructions (load/store) MemAccessSize accessSize = NoMemAccess; - let TSFlags{38-36} = accessSize.Value; + let TSFlags{45-43} = accessSize.Value; + + bits<1> isTaken = 0; + let TSFlags {47} = isTaken; // Branch prediction. + + bits<1> isFP = 0; + let TSFlags {48} = isFP; // Floating-point. // Fields used for relation models. string BaseOpcode = ""; @@ -173,7 +191,7 @@ } //===----------------------------------------------------------------------===// -// Intruction Classes Definitions + +// Instruction Classes Definitions + //===----------------------------------------------------------------------===// // LD Instruction Class in V2/V3/V4. @@ -317,7 +335,7 @@ : InstHexagon; //===----------------------------------------------------------------------===// -// Intruction Classes Definitions - +// Instruction Classes Definitions - //===----------------------------------------------------------------------===// Index: lib/Target/Hexagon/HexagonInstrInfo.td =================================================================== --- lib/Target/Hexagon/HexagonInstrInfo.td +++ lib/Target/Hexagon/HexagonInstrInfo.td @@ -768,12 +768,13 @@ let InputType = "imm", isExtendable = 1, opExtendable = 1, isExtentSigned = 1, Defs = [PC], isPredicated = 1, opExtentBits = 17 in -class T_JMP_c : +class T_JMP_c : JInst<(outs ), (ins PredRegs:$src, brtarget:$dst), !if(PredNot, "if (!$src", "if ($src")# !if(isPredNew, ".new) ", ") ")#"jump"# - !if(isPredNew, !if(isTaken, ":t ", ":nt "), " ")#"$dst"> { + !if(isPredNew, !if(isTak, ":t ", ":nt "), " ")#"$dst"> { + let isTaken = isTak; let isBrTaken = !if(isPredNew, !if(isTaken, "true", "false"), ""); let isPredicatedFalse = PredNot; let isPredicatedNew = isPredNew; @@ -784,7 +785,7 @@ let Inst{27-24} = 0b1100; let Inst{21} = PredNot; - let Inst{12} = !if(isPredNew, isTaken, zero); + let Inst{12} = !if(isPredNew, isTak, zero); let Inst{11} = isPredNew; let Inst{9-8} = src; let Inst{23-22} = dst{16-15}; @@ -806,12 +807,13 @@ } let Defs = [PC], isPredicated = 1, InputType = "reg" in -class T_JMPr_c : +class T_JMPr_c : JRInst <(outs ), (ins PredRegs:$src, IntRegs:$dst), !if(PredNot, "if (!$src", "if ($src")# !if(isPredNew, ".new) ", ") ")#"jumpr"# - !if(isPredNew, !if(isTaken, ":t ", ":nt "), " ")#"$dst"> { + !if(isPredNew, !if(isTak, ":t ", ":nt "), " ")#"$dst"> { + let isTaken = isTak; let isBrTaken = !if(isPredNew, !if(isTaken, "true", "false"), ""); let isPredicatedFalse = PredNot; let isPredicatedNew = isPredNew; @@ -823,7 +825,7 @@ let Inst{27-22} = 0b001101; let Inst{21} = PredNot; let Inst{20-16} = dst; - let Inst{12} = !if(isPredNew, isTaken, zero); + let Inst{12} = !if(isPredNew, isTak, zero); let Inst{11} = isPredNew; let Inst{9-8} = src; let Predicates = !if(isPredNew, [HasV3T], [HasV2T]); Index: lib/Target/Hexagon/HexagonInstrInfoV4.td =================================================================== --- lib/Target/Hexagon/HexagonInstrInfoV4.td +++ lib/Target/Hexagon/HexagonInstrInfoV4.td @@ -1004,13 +1004,13 @@ let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11 in class NVJrr_template majOp, bit NvOpNum, - bit isNegCond, bit isTaken> + bit isNegCond, bit isTak> : NVInst_V4<(outs), (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset), "if ("#!if(isNegCond, "!","")#mnemonic# "($src1"#!if(!eq(NvOpNum, 0),".new, ",", ")# "$src2"#!if(!eq(NvOpNum, 1),".new))","))")#" jump:" - #!if(isTaken, "t","nt")#" $offset", + #!if(isTak, "t","nt")#" $offset", []>, Requires<[HasV4T]> { bits<5> src1; @@ -1019,6 +1019,7 @@ bits<5> RegOp; // Non-New-Value Operand bits<11> offset; + let isTaken = isTak; let isBrTaken = !if(isTaken, "true", "false"); let isPredicatedFalse = isNegCond; @@ -1030,7 +1031,7 @@ let Inst{25-23} = majOp; let Inst{22} = isNegCond; let Inst{18-16} = Ns; - let Inst{13} = isTaken; + let Inst{13} = isTak; let Inst{12-8} = RegOp; let Inst{21-20} = offset{10-9}; let Inst{7-1} = offset{8-2}; @@ -1078,13 +1079,14 @@ let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11 in class NVJri_template majOp, bit isNegCond, - bit isTaken> + bit isTak> : NVInst_V4<(outs), (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset), "if ("#!if(isNegCond, "!","")#mnemonic#"($src1.new, #$src2)) jump:" - #!if(isTaken, "t","nt")#" $offset", + #!if(isTak, "t","nt")#" $offset", []>, Requires<[HasV4T]> { + let isTaken = isTak; let isPredicatedFalse = isNegCond; let isBrTaken = !if(isTaken, "true", "false"); @@ -1097,7 +1099,7 @@ let Inst{25-23} = majOp; let Inst{22} = isNegCond; let Inst{18-16} = src1; - let Inst{13} = isTaken; + let Inst{13} = isTak; let Inst{12-8} = src2; let Inst{21-20} = offset{10-9}; let Inst{7-1} = offset{8-2}; @@ -1135,14 +1137,15 @@ let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 11 in class NVJ_ConstImm_template majOp, string ImmVal, - bit isNegCond, bit isTaken> + bit isNegCond, bit isTak> : NVInst_V4<(outs), (ins IntRegs:$src1, brtarget:$offset), "if ("#!if(isNegCond, "!","")#mnemonic #"($src1.new, #"#ImmVal#")) jump:" - #!if(isTaken, "t","nt")#" $offset", + #!if(isTak, "t","nt")#" $offset", []>, Requires<[HasV4T]> { + let isTaken = isTak; let isPredicatedFalse = isNegCond; let isBrTaken = !if(isTaken, "true", "false"); @@ -1153,7 +1156,7 @@ let Inst{25-23} = majOp; let Inst{22} = isNegCond; let Inst{18-16} = src1; - let Inst{13} = isTaken; + let Inst{13} = isTak; let Inst{21-20} = offset{10-9}; let Inst{7-1} = offset{8-2}; } Index: lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h =================================================================== --- lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h +++ lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h @@ -87,70 +87,82 @@ // Solo instructions. SoloPos = 5, SoloMask = 0x1, + // Packed only with A or X-type instructions. + SoloAXPos = 6, + SoloAXMask = 0x1, + // Only A-type instruction in first slot or nothing. + SoloAin1Pos = 7, + SoloAin1Mask = 0x1, // Predicated instructions. - PredicatedPos = 6, + PredicatedPos = 8, PredicatedMask = 0x1, - PredicatedFalsePos = 7, + PredicatedFalsePos = 9, PredicatedFalseMask = 0x1, - PredicatedNewPos = 8, + PredicatedNewPos = 10, PredicatedNewMask = 0x1, + PredicateLatePos = 11, + PredicateLateMask = 0x1, // New-Value consumer instructions. - NewValuePos = 9, + NewValuePos = 12, NewValueMask = 0x1, - // New-Value producer instructions. - hasNewValuePos = 10, + hasNewValuePos = 13, hasNewValueMask = 0x1, - // Which operand consumes or produces a new value. - NewValueOpPos = 11, + NewValueOpPos = 14, NewValueOpMask = 0x7, - - // Which bits encode the new value. - NewValueBitsPos = 14, - NewValueBitsMask = 0x3, - // Stores that can become new-value stores. - mayNVStorePos = 16, + mayNVStorePos = 17, mayNVStoreMask = 0x1, - // New-value store instructions. - NVStorePos = 17, + NVStorePos = 18, NVStoreMask = 0x1, + // Loads that can become current-value loads. + mayCVLoadPos = 19, + mayCVLoadMask = 0x1, + // Current-value load instructions. + CVLoadPos = 20, + CVLoadMask = 0x1, // Extendable insns. - ExtendablePos = 18, + ExtendablePos = 21, ExtendableMask = 0x1, - // Insns must be extended. - ExtendedPos = 19, + ExtendedPos = 22, ExtendedMask = 0x1, - // Which operand may be extended. - ExtendableOpPos = 20, + ExtendableOpPos = 23, ExtendableOpMask = 0x7, - // Signed or unsigned range. - ExtentSignedPos = 23, + ExtentSignedPos = 26, ExtentSignedMask = 0x1, - // Number of bits of range before extending operand. - ExtentBitsPos = 24, + ExtentBitsPos = 27, ExtentBitsMask = 0x1f, + // Alignment power-of-two before extending operand. + ExtentAlignPos = 32, + ExtentAlignMask = 0x3, // Valid subtargets - validSubTargetPos = 29, + validSubTargetPos = 34, validSubTargetMask = 0xf, // Addressing mode for load/store instructions. - AddrModePos = 33, + AddrModePos = 40, AddrModeMask = 0x7, + // Access size for load/store instructions. + MemAccessSizePos = 43, + MemAccesSizeMask = 0x7, + + // Branch predicted taken. + TakenPos = 47, + TakenMask = 0x1, - // Access size of memory access instructions (load/store). - MemAccessSizePos = 36, - MemAccesSizeMask = 0x7 + // Floating-point instructions. + FPPos = 48, + FPMask = 0x1 }; // *** The code above must match HexagonInstrFormat*.td *** //