Index: lib/Target/Mips/AsmParser/MipsAsmParser.cpp =================================================================== --- lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -171,6 +171,8 @@ bool expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc, SmallVectorImpl &Instructions); + bool expandUncondBranchMMPseudo(MCInst &Inst, SMLoc IDLoc, + SmallVectorImpl &Instructions); void expandLoadAddressSym(MCInst &Inst, SMLoc IDLoc, SmallVectorImpl &Instructions); @@ -1426,6 +1428,7 @@ case Mips::LoadAddr32Imm: case Mips::LoadAddr32Reg: case Mips::LoadImm64Reg: + case Mips::B_MM_Pseudo: return true; default: return false; @@ -1450,6 +1453,8 @@ return expandLoadAddressImm(Inst, IDLoc, Instructions); case Mips::LoadAddr32Reg: return expandLoadAddressReg(Inst, IDLoc, Instructions); + case Mips::B_MM_Pseudo: + return expandUncondBranchMMPseudo(Inst, IDLoc, Instructions); } } @@ -1735,6 +1740,52 @@ } } +bool MipsAsmParser:: +expandUncondBranchMMPseudo(MCInst &Inst, SMLoc IDLoc, + SmallVectorImpl &Instructions) { + const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode()); + + assert(MCID.getNumOperands() == 1 && "unexpected number of operands"); + + MCOperand Offset = Inst.getOperand(0); + if (Offset.isExpr()) { + Inst.clear(); + Inst.setOpcode(Mips::BEQ_MM); + Inst.addOperand(MCOperand::CreateReg(Mips::ZERO)); + Inst.addOperand(MCOperand::CreateReg(Mips::ZERO)); + Inst.addOperand(MCOperand::CreateExpr(Offset.getExpr())); + } else { + assert(Offset.isImm() && "expected immediate operand kind"); + if (isIntN(11, Offset.getImm())) { + // If offset fits into 11 bits then this instruction becomes microMIPS + // 16-bit unconditional branch instruction. + Inst.setOpcode(Mips::B16_MM); + } else { + if (!isIntN(17, Offset.getImm())) + Error(IDLoc, "branch target out of range"); + if (OffsetToAlignment(Offset.getImm(), 1LL << 1)) + Error(IDLoc, "branch to misaligned address"); + Inst.clear(); + Inst.setOpcode(Mips::BEQ_MM); + Inst.addOperand(MCOperand::CreateReg(Mips::ZERO)); + Inst.addOperand(MCOperand::CreateReg(Mips::ZERO)); + Inst.addOperand(MCOperand::CreateImm(Offset.getImm())); + } + } + Instructions.push_back(Inst); + + if (AssemblerOptions.back()->isReorder()) { + // If .set reorder is active, emit a NOP after the branch instruction. + MCInst NopInst; + NopInst.setOpcode(Mips::SLL); + NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO)); + NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO)); + NopInst.addOperand(MCOperand::CreateImm(0)); + Instructions.push_back(NopInst); + } + return false; +} + void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc, SmallVectorImpl &Instructions, bool isLoad, bool isImmOpnd) { Index: lib/Target/Mips/Disassembler/MipsDisassembler.cpp =================================================================== --- lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -235,6 +235,13 @@ uint64_t Address, const void *Decoder); +// DecodeBranchTarget10MM - Decode microMIPS branch offset, which is +// shifted left by 1 bit. +static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, + unsigned Offset, + uint64_t Address, + const void *Decoder); + // DecodeBranchTargetMM - Decode microMIPS branch offset, which is // shifted left by 1 bit. static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, @@ -1580,6 +1587,15 @@ return MCDisassembler::Success; } +static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, + unsigned Offset, + uint64_t Address, + const void *Decoder) { + int32_t BranchOffset = SignExtend32<10>(Offset) << 1; + Inst.addOperand(MCOperand::CreateImm(BranchOffset)); + return MCDisassembler::Success; +} + static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, unsigned Offset, uint64_t Address, Index: lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp +++ lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp @@ -111,6 +111,14 @@ if (!isIntN(7, Value) && Ctx) Ctx->FatalError(Fixup.getLoc(), "out of range PC7 fixup"); break; + case Mips::fixup_MICROMIPS_PC10_S1: + Value -= 2; + // Forcing a signed division because Value can be negative. + Value = (int64_t) Value / 2; + // We now check if Value can be encoded as a 10-bit signed immediate. + if (!isIntN(10, Value) && Ctx) + Ctx->FatalError(Fixup.getLoc(), "out of range PC10 fixup"); + break; case Mips::fixup_MICROMIPS_PC16_S1: Value -= 4; // Forcing a signed division because Value can be negative. @@ -207,6 +215,14 @@ bool microMipsLEByteOrder = needsMMLEByteOrder((unsigned) Kind); + if ((unsigned) Kind == Mips::fixup_MICROMIPS_PC10_S1) { + // We have 16-bit unconditional branch instruction. + FullSize = 2; + // We don't want microMIPS specific little-endian byte ordering + // for 16-bit instructions. + microMipsLEByteOrder = false; + } + for (unsigned i = 0; i != NumBytes; ++i) { unsigned Idx = IsLittle ? (microMipsLEByteOrder ? calculateMMLEIndex(i) : i) @@ -280,6 +296,7 @@ { "fixup_MICROMIPS_LO16", 0, 16, 0 }, { "fixup_MICROMIPS_GOT16", 0, 16, 0 }, { "fixup_MICROMIPS_PC7_S1", 0, 7, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MICROMIPS_PC10_S1", 0, 10, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_MICROMIPS_PC16_S1", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_MICROMIPS_CALL16", 0, 16, 0 }, { "fixup_MICROMIPS_GOT_DISP", 0, 16, 0 }, @@ -344,6 +361,7 @@ { "fixup_MICROMIPS_LO16", 16, 16, 0 }, { "fixup_MICROMIPS_GOT16", 16, 16, 0 }, { "fixup_MICROMIPS_PC7_S1", 9, 7, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_MICROMIPS_PC10_S1", 6, 10, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_MICROMIPS_PC16_S1",16, 16, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_MICROMIPS_CALL16", 16, 16, 0 }, { "fixup_MICROMIPS_GOT_DISP", 16, 16, 0 }, Index: lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp +++ lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp @@ -164,6 +164,9 @@ case Mips::fixup_MICROMIPS_PC7_S1: Type = ELF::R_MICROMIPS_PC7_S1; break; + case Mips::fixup_MICROMIPS_PC10_S1: + Type = ELF::R_MICROMIPS_PC10_S1; + break; case Mips::fixup_MICROMIPS_PC16_S1: Type = ELF::R_MICROMIPS_PC16_S1; break; Index: lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h +++ lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h @@ -161,6 +161,9 @@ // resulting in - R_MICROMIPS_PC7_S1 fixup_MICROMIPS_PC7_S1, + // resulting in - R_MICROMIPS_PC10_S1 + fixup_MICROMIPS_PC10_S1, + // resulting in - R_MICROMIPS_PC16_S1 fixup_MICROMIPS_PC16_S1, Index: lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h +++ lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h @@ -108,6 +108,13 @@ SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const; + // getBranchTargetOpValue - Return binary encoding of the microMIPS 10-bit + // branch target operand. If the machine operand requires relocation, record + // the relocation and return zero. + unsigned getBranchTargetOpValueMMPC10(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + // getBranchTargetOpValue - Return binary encoding of the microMIPS branch // target operand. If the machine operand requires relocation, // record the relocation and return zero. Index: lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp +++ lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp @@ -242,6 +242,28 @@ return 0; } +/// getBranchTargetOpValue - Return binary encoding of the microMIPS 10-bit +/// branch target operand. If the machine operand requires relocation, record +/// the relocation and return zero. +unsigned MipsMCCodeEmitter:: +getBranchTargetOpValueMMPC10(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + + const MCOperand &MO = MI.getOperand(OpNo); + + // If the destination is an immediate, divide by 2. + if (MO.isImm()) return MO.getImm() >> 1; + + assert(MO.isExpr() && + "getBranchTargetOpValuePC10 expects only expressions or immediates"); + + const MCExpr *Expr = MO.getExpr(); + Fixups.push_back(MCFixup::Create(0, Expr, + MCFixupKind(Mips::fixup_MICROMIPS_PC10_S1))); + return 0; +} + /// getBranchTargetOpValue - Return binary encoding of the microMIPS branch /// target operand. If the machine operand requires relocation, /// record the relocation and return zero. Index: lib/Target/Mips/MicroMipsInstrFormats.td =================================================================== --- lib/Target/Mips/MicroMipsInstrFormats.td +++ lib/Target/Mips/MicroMipsInstrFormats.td @@ -249,6 +249,15 @@ let Inst{6-0} = offset; } +class B16_FM { + bits<10> offset; + + bits<16> Inst; + + let Inst{15-10} = 0x33; + let Inst{9-0} = offset; +} + //===----------------------------------------------------------------------===// // MicroMIPS 32-bit Instruction Formats //===----------------------------------------------------------------------===// Index: lib/Target/Mips/MicroMipsInstrInfo.td =================================================================== --- lib/Target/Mips/MicroMipsInstrInfo.td +++ lib/Target/Mips/MicroMipsInstrInfo.td @@ -151,10 +151,18 @@ let ParserMatchClass = MipsJumpTargetAsmOperand; } +def brtarget10_mm : Operand { + let EncoderMethod = "getBranchTargetOpValueMMPC10"; + let OperandType = "OPERAND_PCREL"; + let DecoderMethod = "DecodeBranchTarget10MM"; + let ParserMatchClass = MipsJumpTargetAsmOperand; +} + def brtarget_mm : Operand { let EncoderMethod = "getBranchTargetOpValueMM"; let OperandType = "OPERAND_PCREL"; let DecoderMethod = "DecodeBranchTargetMM"; + let ParserMatchClass = MipsJumpTargetAsmOperand; } def simm23_lsl2 : Operand { @@ -518,6 +526,18 @@ let mayLoad = 1; } +class UncondBranchMM16 : + MicroMipsInst16<(outs), (ins brtarget10_mm:$offset), + !strconcat(opstr, "\t$offset"), + [], IIBranch, FrmI> { + let isBranch = 1; + let isTerminator = 1; + let isBarrier = 1; + let hasDelaySlot = 1; + let Predicates = [RelocPIC, InMicroMips]; + let Defs = [AT]; +} + def ADDU16_MM : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>, ARITH_FM_MM16<0>; def SUBU16_MM : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>, @@ -571,6 +591,7 @@ BEQNEZ_FM_MM16<0x23>; def BNEZ16_MM : CBranchZeroMM<"bnez16", brtarget7_mm, GPRMM16Opnd>, BEQNEZ_FM_MM16<0x2b>; +def B16_MM : UncondBranchMM16<"b16">, B16_FM; def BREAK16_MM : BrkSdbbp16MM<"break16">, BRKSDBBP16_FM_MM<0x28>; def SDBBP16_MM : BrkSdbbp16MM<"sdbbp16">, BRKSDBBP16_FM_MM<0x2C>; @@ -860,6 +881,12 @@ // MicroMips instruction aliases //===----------------------------------------------------------------------===// +class UncondBranchMMPseudo : + MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset), + !strconcat(opstr, "\t$offset")>; + + def B_MM_Pseudo : UncondBranchMMPseudo<"b">; + def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>; def : MipsInstAlias<"nop", (SLL_MM ZERO, ZERO, 0), 1>; def : MipsInstAlias<"nop", (MOVE16_MM ZERO, ZERO), 1>; Index: lib/Target/Mips/MipsInstrInfo.td =================================================================== --- lib/Target/Mips/MipsInstrInfo.td +++ lib/Target/Mips/MipsInstrInfo.td @@ -1584,7 +1584,9 @@ def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>; def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>; def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>; +let AdditionalPredicates = [NotInMicroMips] in { def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>; +} def : MipsInstAlias<"bnez $rs,$offset", (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; def : MipsInstAlias<"beqz $rs,$offset", Index: lib/Target/Mips/MipsLongBranch.cpp =================================================================== --- lib/Target/Mips/MipsLongBranch.cpp +++ lib/Target/Mips/MipsLongBranch.cpp @@ -82,6 +82,7 @@ void replaceBranch(MachineBasicBlock &MBB, Iter Br, DebugLoc DL, MachineBasicBlock *MBBOpnd); void expandToLongBranch(MBBInfo &Info); + bool buildMMUncondBranchInst(MBBInfo &Info); const TargetMachine &TM; MachineFunction *MF; @@ -448,6 +449,26 @@ MBB.removeLiveIn(Mips::V0); } +bool MipsLongBranch::buildMMUncondBranchInst(MBBInfo &I) { + MachineBasicBlock::iterator Pos; + MachineBasicBlock *MBB = I.Br->getParent(); + MachineBasicBlock *TgtMBB = getTargetMBB(*I.Br); + DebugLoc DL = I.Br->getDebugLoc(); + const MipsInstrInfo *TII = + static_cast(TM.getSubtargetImpl()->getInstrInfo()); + + Pos = MBB->begin(); + if (Pos->getOpcode() == (unsigned) Mips::B) { + BuildMI(*MBB, Pos, DL, TII->get(Mips::B16_MM)).addMBB(TgtMBB); + + MachineBasicBlock::instr_iterator II(Pos); + MIBundleBuilder(*MBB, Pos).append((++II)->removeFromBundle()); + Pos->eraseFromParent(); + } + + return true; +} + bool MipsLongBranch::runOnMachineFunction(MachineFunction &F) { const MipsInstrInfo *TII = static_cast(TM.getSubtargetImpl()->getInstrInfo()); @@ -478,7 +499,16 @@ if (!I->Br || I->HasLongBranch) continue; - int ShVal = TM.getSubtarget().inMicroMipsMode() ? 2 : 4; + bool IsMicroMips = TM.getSubtarget().inMicroMipsMode(); + int ShVal = IsMicroMips ? 2 : 4; + + // Check if offset fits into 16-bit immediate field of branches. + if (IsMicroMips && !ForceLongBranch && I->Br->isUnconditionalBranch() && + isInt<10>(computeOffset(I->Br) / ShVal)) { + if (buildMMUncondBranchInst(*I)) + continue; + } + int64_t Offset = computeOffset(I->Br) / ShVal; if (TM.getSubtarget().isTargetNaCl()) { Index: test/MC/Disassembler/Mips/micromips.txt =================================================================== --- test/MC/Disassembler/Mips/micromips.txt +++ test/MC/Disassembler/Mips/micromips.txt @@ -486,3 +486,6 @@ # CHECK: bnez16 $6, 20 0xaf 0x0a + +# CHECK: b16 132 +0xcc 0x42 Index: test/MC/Disassembler/Mips/micromips_le.txt =================================================================== --- test/MC/Disassembler/Mips/micromips_le.txt +++ test/MC/Disassembler/Mips/micromips_le.txt @@ -486,3 +486,6 @@ # CHECK: bnez16 $6, 20 0x0a 0xaf + +# CHECK: b16 132 +0x42 0xcc Index: test/MC/Mips/micromips-16-bit-instructions.s =================================================================== --- test/MC/Mips/micromips-16-bit-instructions.s +++ test/MC/Mips/micromips-16-bit-instructions.s @@ -53,6 +53,10 @@ # CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00] # CHECK-EL: bnez16 $6, 20 # encoding: [0x0a,0xaf] # CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK-EL: b16 132 # encoding: [0x42,0xcc] +# CHECK-EL: nop +# CHECK-EL: b16 132 # encoding: [0x42,0xcc] +# CHECK-EL: nop # CHECK-EL: break16 8 # encoding: [0x88,0x46] # CHECK-EL: sdbbp16 14 # encoding: [0xce,0x46] #------------------------------------------------------------------------------ @@ -102,6 +106,10 @@ # CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00] # CHECK-EB: bnez16 $6, 20 # encoding: [0xaf,0x0a] # CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK-EB: b16 132 # encoding: [0xcc,0x42] +# CHECK-EB: nop +# CHECK-EB: b16 132 # encoding: [0xcc,0x42] +# CHECK-EB: nop # CHECK-EB: break16 8 # encoding: [0x46,0x88] # CHECK-EB: sdbbp16 14 # encoding: [0x46,0xce] @@ -145,5 +153,7 @@ jr16 $9 beqz16 $6, 20 bnez16 $6, 20 + b 132 + b16 132 break16 8 sdbbp16 14 Index: test/MC/Mips/micromips-branch-instructions.s =================================================================== --- test/MC/Mips/micromips-branch-instructions.s +++ test/MC/Mips/micromips-branch-instructions.s @@ -9,7 +9,7 @@ #------------------------------------------------------------------------------ # Little endian #------------------------------------------------------------------------------ -# CHECK-EL: b 1332 # encoding: [0x00,0x94,0x9a,0x02] +# CHECK-EL: beq $zero, $zero, 1332 # encoding: [0x00,0x94,0x9a,0x02] # CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00] # CHECK-EL: beq $9, $6, 1332 # encoding: [0xc9,0x94,0x9a,0x02] # CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00] @@ -36,7 +36,7 @@ #------------------------------------------------------------------------------ # Big endian #------------------------------------------------------------------------------ -# CHECK-EB: b 1332 # encoding: [0x94,0x00,0x02,0x9a] +# CHECK-EB: beq $zero, $zero, 1332 # encoding: [0x94,0x00,0x02,0x9a] # CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00] # CHECK-EB: beq $9, $6, 1332 # encoding: [0x94,0xc9,0x02,0x9a] # CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00] @@ -61,6 +61,10 @@ # CHECK-EB: bltzals $6, 1332 # encoding: [0x42,0x26,0x02,0x9a] # CHECK-EB: nop # encoding: [0x0c,0x00] + .text + .type main, @function + .set micromips +main: b 1332 beq $9,$6,1332 bgez $6,1332 Index: test/MC/Mips/micromips-branch10.s =================================================================== --- /dev/null +++ test/MC/Mips/micromips-branch10.s @@ -0,0 +1,25 @@ +# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding \ +# RUN: -mattr=micromips | FileCheck %s -check-prefix=CHECK-FIXUP +# RUN: llvm-mc %s -filetype=obj -triple=mipsel-unknown-linux \ +# RUN: -mattr=micromips | llvm-readobj -r \ +# RUN: | FileCheck %s -check-prefix=CHECK-ELF +#------------------------------------------------------------------------------ +# Check that the assembler can handle the documented syntax +# for relocations. +#------------------------------------------------------------------------------ +# CHECK-FIXUP: b16 bar # encoding: [A,0b110011AA] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar, kind: fixup_MICROMIPS_PC10_S1 +# CHECK-FIXUP: nop # encoding: [0x00,0x00,0x00,0x00] +#------------------------------------------------------------------------------ +# Check that the appropriate relocations were created. +#------------------------------------------------------------------------------ +# CHECK-ELF: Relocations [ +# CHECK-ELF: 0x{{[0-9,A-F]+}} R_MICROMIPS_PC10_S1 +# CHECK-ELF: ] + + .text + .type main, @function + .set micromips +main: + b16 bar Index: test/MC/Mips/micromips-branch16.s =================================================================== --- test/MC/Mips/micromips-branch16.s +++ test/MC/Mips/micromips-branch16.s @@ -7,7 +7,7 @@ # Check that the assembler can handle the documented syntax # for relocations. #------------------------------------------------------------------------------ -# CHECK-FIXUP: b bar # encoding: [A,0x94'A',0x00,0x00] +# CHECK-FIXUP: beq $zero, $zero, bar # encoding: [A,0x94'A',0x00,0x00] # CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: value: bar, kind: fixup_MICROMIPS_PC16_S1 # CHECK-FIXUP: nop # encoding: [0x00,0x00,0x00,0x00] @@ -58,6 +58,10 @@ # CHECK-ELF: 0x{{[0-9,A-F]+}} R_MICROMIPS_PC16_S1 # CHECK-ELF: ] + .text + .type main, @function + .set micromips +main: b bar beq $3, $4, bar bne $3, $4, bar