Index: include/llvm/IR/IntrinsicsARM.td
===================================================================
--- include/llvm/IR/IntrinsicsARM.td
+++ include/llvm/IR/IntrinsicsARM.td
@@ -122,7 +122,6 @@
 
 //===----------------------------------------------------------------------===//
 // HINT
-def int_arm_sevl : Intrinsic<[], []>;
 
 def int_arm_hint : Intrinsic<[], [llvm_i32_ty]>;
 
Index: lib/Target/ARM/ARMInstrInfo.td
===================================================================
--- lib/Target/ARM/ARMInstrInfo.td
+++ lib/Target/ARM/ARMInstrInfo.td
@@ -1840,8 +1840,6 @@
 def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6T2]>;
 def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>;
 
-def : Pat<(int_arm_sevl), (HINT 5)>;
-
 def : Pat<(int_arm_hint 0), (HINT 0)>;
 def : Pat<(int_arm_hint 1), (HINT 1)>;
 def : Pat<(int_arm_hint 2), (HINT 2)>;
Index: lib/Target/ARM/ARMInstrThumb.td
===================================================================
--- lib/Target/ARM/ARMInstrThumb.td
+++ lib/Target/ARM/ARMInstrThumb.td
@@ -289,8 +289,6 @@
   let Predicates = [IsThumb2, HasV8];
 }
 
-def : T2Pat<(int_arm_sevl), (tHINT 5)>;
-
 def : T2Pat<(int_arm_hint 0), (tHINT 0)>;
 def : T2Pat<(int_arm_hint 1), (tHINT 1)>;
 def : T2Pat<(int_arm_hint 2), (tHINT 2)>;
Index: test/CodeGen/ARM/intrinsics-v8.ll
===================================================================
--- test/CodeGen/ARM/intrinsics-v8.ll
+++ test/CodeGen/ARM/intrinsics-v8.ll
@@ -10,10 +10,10 @@
   ; CHECK: dsb ishld
   call void @llvm.arm.dsb(i32 9)
   ; CHECK: sevl
-  tail call void @llvm.arm.sevl() nounwind
+  tail call void @llvm.arm.hint(i32 5) nounwind
   ret void
 }
 
 declare void @llvm.arm.dmb(i32)
 declare void @llvm.arm.dsb(i32)
-declare void @llvm.arm.sevl() nounwind
+declare void @llvm.arm.hint(i32) nounwind