Index: lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp =================================================================== --- lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp +++ lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp @@ -104,8 +104,9 @@ case FK_Data_1: return 1; - case FK_Data_2: case AArch64::fixup_aarch64_movw: + case FK_Data_2: + case FK_SecRel_2: return 2; case AArch64::fixup_aarch64_pcrel_branch14: @@ -124,6 +125,7 @@ case AArch64::fixup_aarch64_pcrel_branch26: case AArch64::fixup_aarch64_pcrel_call26: case FK_Data_4: + case FK_SecRel_4: return 4; case FK_Data_8: @@ -218,6 +220,8 @@ case FK_Data_2: case FK_Data_4: case FK_Data_8: + case FK_SecRel_2: + case FK_SecRel_4: return Value; } } Index: lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFObjectWriter.cpp =================================================================== --- lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFObjectWriter.cpp +++ lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFObjectWriter.cpp @@ -47,8 +47,49 @@ const MCFixup &Fixup, bool IsCrossSection, const MCAsmBackend &MAB) const { - const MCFixupKindInfo &Info = MAB.getFixupKindInfo(Fixup.getKind()); - report_fatal_error(Twine("unsupported relocation type: ") + Info.Name); + MCSymbolRefExpr::VariantKind Modifier = Target.isAbsolute() ? + MCSymbolRefExpr::VK_None : + Target.getSymA()->getKind(); + + switch (static_cast(Fixup.getKind())) { + default: { + const MCFixupKindInfo &Info = MAB.getFixupKindInfo(Fixup.getKind()); + report_fatal_error(Twine("unsupported relocation type: ") + Info.Name); + } + case FK_Data_4: + switch (Modifier) { + default: + return COFF::IMAGE_REL_ARM64_ADDR32; + case MCSymbolRefExpr::VK_COFF_IMGREL32: + return COFF::IMAGE_REL_ARM64_ADDR32NB; + case MCSymbolRefExpr::VK_SECREL: + return COFF::IMAGE_REL_ARM_SECREL; + } + case FK_Data_8: + return COFF::IMAGE_REL_ARM64_ADDR64; + + case FK_SecRel_2: + return COFF::IMAGE_REL_ARM64_SECTION; + case FK_SecRel_4: + return COFF::IMAGE_REL_ARM64_SECREL; + + case AArch64::fixup_aarch64_add_imm12: + return COFF::IMAGE_REL_ARM64_PAGEOFFSET_12A; + + case AArch64::fixup_aarch64_ldst_imm12_scale1: + case AArch64::fixup_aarch64_ldst_imm12_scale2: + case AArch64::fixup_aarch64_ldst_imm12_scale4: + case AArch64::fixup_aarch64_ldst_imm12_scale8: + case AArch64::fixup_aarch64_ldst_imm12_scale16: + return COFF::IMAGE_REL_ARM64_PAGEOFFSET_12L; + + case AArch64::fixup_aarch64_pcrel_adrp_imm21: + return COFF::IMAGE_REL_ARM64_PAGEBASE_REL21; + + case AArch64::fixup_aarch64_pcrel_branch26: + case AArch64::fixup_aarch64_pcrel_call26: + return COFF::IMAGE_REL_ARM64_BRANCH26; + } } bool AArch64WinCOFFObjectWriter::recordRelocation(const MCFixup &Fixup) const { Index: test/MC/AArch64/coff-relocations.s =================================================================== --- /dev/null +++ test/MC/AArch64/coff-relocations.s @@ -0,0 +1,44 @@ +; RUN: llvm-mc -triple aarch64-windows -filetype obj -o - %s | \ +; RUN: llvm-readobj -r - | FileCheck %s + +; IMAGE_REL_ARM64_ADDR32 +.Linfo_foo: + .asciz "var" + .long var + +; IMAGE_REL_ARM64_ADDR32NB +.long func@IMGREL + +; IMAGE_REL_ARM64_ADDR64 +.globl struc +struc: + .quad arr + +; IMAGE_REL_ARM64_BRANCH26 +b target + +; IMAGE_REL_ARM64_PAGEBASE_REL21 +adrp x0, var + +; IMAGE_REL_ARM64_SECREL +.secrel32 .Linfo_bar +.Linfo_bar: + +; IMAGE_REL_ARM64_SECTION +.secidx func + + +; CHECK: Format: COFF-ARM64 +; CHECK: Arch: aarch64 +; CHECK: AddressSize: 64bit +; CHECK: Relocations [ +; CHECK: Section (1) .text { +; CHECK: 0x4 IMAGE_REL_ARM64_ADDR32 var +; CHECK: 0x8 IMAGE_REL_ARM64_ADDR32NB func +; CHECK: 0xC IMAGE_REL_ARM64_ADDR64 arr +; CHECK: 0x14 IMAGE_REL_ARM64_BRANCH26 target +; CHECK: 0x18 IMAGE_REL_ARM64_PAGEBASE_REL21 var +; CHECK: 0x1C IMAGE_REL_ARM64_SECREL .text +; CHECK: 0x20 IMAGE_REL_ARM64_SECTION func +; CHECK: } +; CHECK: ]