Index: lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- lib/Target/AMDGPU/SIInstrInfo.cpp
+++ lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -3856,7 +3856,9 @@
          E = MRI.use_end(); I != E;) {
     MachineInstr &UseMI = *I->getParent();
     if (!canReadVGPR(UseMI, I.getOperandNo())) {
-      Worklist.push_back(&UseMI);
+      // Do not add to worklist twice!
+      if(Worklist.end() == llvm::find(Worklist, &MI))
+        Worklist.push_back(&UseMI);
 
       do {
         ++I;
@@ -3941,7 +3943,9 @@
       return;
 
     if (MI.findRegisterUseOperandIdx(AMDGPU::SCC) != -1)
-      Worklist.push_back(&MI);
+      // Do not add to worklist twice!
+      if(Worklist.end() == llvm::find(Worklist, &MI))
+        Worklist.push_back(&MI);
   }
 }
 
Index: test/CodeGen/AMDGPU/move-to-valu-worklist.ll
===================================================================
--- /dev/null
+++ test/CodeGen/AMDGPU/move-to-valu-worklist.ll
@@ -0,0 +1,31 @@
+; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck %s
+
+; CHECK-LABEL: {{^}}in_worklist_once:
+; CHECK: buffer_load_dword
+; CHECK: BB0_1:
+; CHECK: s_branch BB0_1
+define amdgpu_kernel void @in_worklist_once() #0 {
+bb:
+  %tmp = load i64, i64* undef
+  br label %bb1
+
+bb1:                                              ; preds = %bb1, %bb
+  %tmp2 = phi i64 [ undef, %bb ], [ %tmp16, %bb1 ]
+  %tmp3 = phi i64 [ %tmp, %bb ], [ undef, %bb1 ]
+  %tmp4 = xor i64 0, %tmp2
+  %tmp5 = xor i64 %tmp4, 0
+  %tmp6 = xor i64 %tmp5, 0
+  %tmp7 = xor i64 %tmp6, 0
+  %tmp8 = xor i64 0, %tmp7
+  %tmp9 = xor i64 0, %tmp3
+  %tmp10 = xor i64 0, %tmp8
+  %tmp11 = shl i64 %tmp10, 14
+  %tmp12 = lshr i64 %tmp10, 50
+  %tmp13 = or i64 %tmp11, %tmp12
+  %tmp14 = xor i64 0, %tmp9
+  %tmp15 = and i64 %tmp9, %tmp13
+  %tmp16 = xor i64 %tmp15, %tmp14
+  br label %bb1
+}
+
+attributes #0 = { nounwind }