Index: lib/Target/X86/X86InterleavedAccess.cpp =================================================================== --- lib/Target/X86/X86InterleavedAccess.cpp +++ lib/Target/X86/X86InterleavedAccess.cpp @@ -70,7 +70,8 @@ /// Out-V3 = P4, q4, r4, s4 void transpose_4x4(ArrayRef InputVectors, SmallVectorImpl &TrasposedVectors); - + void transposeChar_32x4(ArrayRef InputVectors, + SmallVectorImpl &TrasposedVectors); public: /// In order to form an interleaved access group X86InterleavedAccessGroup /// requires a wide-load instruction \p 'I', a group of interleaved-vectors @@ -108,8 +109,9 @@ else ExpectedShuffleVecSize = 1024; - if (!Subtarget.hasAVX() || ShuffleVecSize != ExpectedShuffleVecSize || - DL.getTypeSizeInBits(ShuffleEltTy) != 64 || Factor != 4) + if (((DL.getTypeSizeInBits(ShuffleEltTy) != 64 || !Subtarget.hasAVX()) && + ((DL.getTypeSizeInBits(ShuffleEltTy) != 8 || !Subtarget.hasAVX2()))) || + ShuffleVecSize != ExpectedShuffleVecSize || Factor != 4) return false; return true; @@ -158,6 +160,138 @@ } } +/// Generate unpacklo/unpackhi shuffle mask. +static void createUnpackShuffleMask(int NumElts, SmallVectorImpl &Mask, + bool Lo, bool Unary) { + int NumEltsInLane = NumElts / 2; + assert(Mask.empty() && "Expected an empty shuffle mask vector"); + for (int i = 0; i < NumElts; ++i) { + unsigned LaneStart = (i / NumEltsInLane) * NumEltsInLane; + int Pos = (i % NumEltsInLane) / 2 + LaneStart; + Pos += (Unary ? 0 : NumElts * (i % 2)); + Pos += (Lo ? 0 : NumEltsInLane / 2); + Mask.push_back(Pos); + } +} + +// Create shuffle mask for concatenation of two half vectors. +// Low = false: mask generated for the shuffle +// shufle(vec1,vec2,{NumElement/2,NumElement/2+1,NumElement/2+2...,NumElement-1, +// NumElement-NumElement/2,NumElement-NumElement/2+1...,2*NumElement-1}) +// = concat(high_half(VEC1),high_half(VEC2)) +// Low = true: mask generated for the shuffle +// shufle(vec1,vec2,{0,1,2,...,NumElement/2-1,NumElement, +// NumElement+1...,NumElement+NumElement/2-1}) +// = concat(low_half(VEC1),low_half(VEC2)) +static void createConcatShuffleMask(int NumElement, + SmallVectorImpl &Mask, bool Low) { + int BeginIndex = Low ? 0 : NumElement / 2; + int EndIndex = BeginIndex + NumElement / 2; + for (int i = 0; i < NumElement; ++i) { + if (BeginIndex == EndIndex) + BeginIndex += NumElement / 2; + Mask.push_back(BeginIndex); + BeginIndex++; + } +} + +void X86InterleavedAccessGroup::transposeChar_32x4( + ArrayRef Matrix, + SmallVectorImpl &TransposedMatrix) { + + // Example: Assuming we start from the following vectors: + // Matrix[0]= c0 c1 c2 c3 c4 ... c31 + // Matrix[1]= m0 m1 m2 m3 m4 ... m31 + // Matrix[2]= y0 y1 y2 y3 y4 ... y31 + // Matrix[3]= k0 k1 k2 k3 k4 ... k31 + + TransposedMatrix.resize(4); + + SmallVector MaskHighTemp; + SmallVector MaskLowTemp; + SmallVector MaskHighTemp1; + SmallVector MaskLowTemp1; + SmallVector ConcatLow; + SmallVector ConcatHigh; + + // MaskHighTemp and MaskLowTemp built in the vpunpckhbw and vpunpcklbw X86 + // shuffle pattern. + createUnpackShuffleMask(32, MaskHighTemp, false, false); + createUnpackShuffleMask(32, MaskLowTemp, true, false); + + // MaskHighTemp1 and MaskLowTemp1 built in the vpunpckhdw and vpunpckldw X86 + // shuffle pattern. + createUnpackShuffleMask(16, MaskLowTemp1, true, false); + createUnpackShuffleMask(16, MaskHighTemp1, false, false); + + // ConcatHigh and ConcatLow built in the vperm2i128 and vinserti128 X86 + // shuffle pattern. + createConcatShuffleMask(16, ConcatLow, true); + createConcatShuffleMask(16, ConcatHigh, false); + + ArrayRef MaskHigh = makeArrayRef(MaskHighTemp); + ArrayRef MaskLow = makeArrayRef(MaskLowTemp); + ArrayRef MaskConcatLow = makeArrayRef(ConcatLow); + ArrayRef MaskConcatHigh = makeArrayRef(ConcatHigh); + ArrayRef MaskHighWord = makeArrayRef(MaskHighTemp1); + ArrayRef MaskLowWord = makeArrayRef(MaskLowTemp1); + + // IntrVec1Low = c0 m0 c1 m1 ... c7 m7 | c16 m16 c17 m17 ... c23 m23 + // IntrVec1High = c8 m8 c9 m9 ... c15 m15 | c24 m24 c25 m25 ... c31 m31 + // IntrVec2Low = y0 k0 y1 k1 ... y7 k7 | y16 k16 y17 k17 ... y23 k23 + // IntrVec2High = y8 k8 y9 k9 ... y15 k15 | y24 k24 y25 k25 ... y31 k31 + + Value *IntrVec1Low = + Builder.CreateShuffleVector(Matrix[0], Matrix[1], MaskLow); + Value *IntrVec1High = + Builder.CreateShuffleVector(Matrix[0], Matrix[1], MaskHigh); + Value *IntrVec2Low = + Builder.CreateShuffleVector(Matrix[2], Matrix[3], MaskLow); + Value *IntrVec2High = + Builder.CreateShuffleVector(Matrix[2], Matrix[3], MaskHigh); + + IntrVec1Low = Builder.CreateBitCast( + IntrVec1Low, + VectorType::get(Type::getInt16Ty(Shuffles[0]->getContext()), 16)); + IntrVec1High = Builder.CreateBitCast( + IntrVec1High, + VectorType::get(Type::getInt16Ty(Shuffles[0]->getContext()), 16)); + IntrVec2Low = Builder.CreateBitCast( + IntrVec2Low, + VectorType::get(Type::getInt16Ty(Shuffles[0]->getContext()), 16)); + IntrVec2High = Builder.CreateBitCast( + IntrVec2High, + VectorType::get(Type::getInt16Ty(Shuffles[0]->getContext()), 16)); + + // cmyk4 cmyk5 cmyk6 cmyk7 | cmyk20 cmyk21 cmyk22 cmyk23 + // cmyk12 cmyk13 cmyk14 cmyk15 | cmyk28 cmyk29 cmyk30 cmyk31 + // cmyk0 cmyk1 cmyk2 cmyk3 | cmyk16 cmyk17 cmyk18 cmyk19 + // cmyk8 cmyk9 cmyk10 cmyk11 | cmyk24 cmyk25 cmyk26 cmyk27 + + Value *High = Builder.CreateShuffleVector(IntrVec1Low, IntrVec2Low, + MaskHighWord); + Value *High1 = Builder.CreateShuffleVector(IntrVec1High, IntrVec2High, + MaskHighWord); + Value *Low = Builder.CreateShuffleVector(IntrVec1Low, IntrVec2Low, + MaskLowWord); + Value *Low1 = Builder.CreateShuffleVector(IntrVec1High, IntrVec2High, + MaskLowWord); + + // cmyk0 cmyk1 cmyk2 cmyk3 | cmyk4 cmyk5 cmyk6 cmyk7 + // cmyk8 cmyk9 cmyk10 cmyk11 | cmyk12 cmyk13 cmyk14 cmyk15 + // cmyk16 cmyk17 cmyk18 cmyk19 | cmyk20 cmyk21 cmyk22 cmyk23 + // cmyk24 cmyk25 cmyk26 cmyk27 | cmyk28 cmyk29 cmyk30 cmyk31 + + TransposedMatrix[0] = + Builder.CreateShuffleVector(Low, High, MaskConcatLow); + TransposedMatrix[1] = + Builder.CreateShuffleVector(Low1, High1, MaskConcatLow); + TransposedMatrix[2] = + Builder.CreateShuffleVector(Low, High, MaskConcatHigh); + TransposedMatrix[3] = + Builder.CreateShuffleVector(Low1, High1, MaskConcatHigh); +} + void X86InterleavedAccessGroup::transpose_4x4( ArrayRef Matrix, SmallVectorImpl &TransposedMatrix) { @@ -224,15 +358,38 @@ // 2. Transpose the interleaved-vectors into vectors of contiguous // elements. - transpose_4x4(DecomposedVectors, TransposedVectors); + StoreInst *SI = cast(Inst); + switch (NumSubVecElems) { + case 4: { + transpose_4x4(DecomposedVectors, TransposedVectors); // 3. Concatenate the contiguous-vectors back into a wide vector. Value *WideVec = concatenateVectors(Builder, TransposedVectors); - // 4. Generate a store instruction for wide-vec. - StoreInst *SI = cast(Inst); - Builder.CreateAlignedStore(WideVec, SI->getPointerOperand(), - SI->getAlignment()); + // 4. Generate a store instruction for wide-vec. + Builder.CreateAlignedStore(WideVec, SI->getPointerOperand(), + SI->getAlignment()); + break; + } + case 32: { + transposeChar_32x4(DecomposedVectors, TransposedVectors); + // VecInst contains the Ptr argument. + Value *VecInst = Inst->getOperand(1); + // From <128xi8>* to <16xi16>* + Type *VecTran = + VectorType::get(Type::getInt16Ty(Shuffles[0]->getContext()), 16) + ->getPointerTo(); + Value *VecBasePtr = Builder.CreateBitCast(VecInst, VecTran); + for (unsigned i = 0; i < 4; i++) { + Value *NewBasePtr = Builder.CreateGEP(VecBasePtr, Builder.getInt32(i)); + Builder.CreateAlignedStore(TransposedVectors[i], NewBasePtr, + SI->getAlignment()); + } + break; + } + default: + return false; + } return true; } @@ -258,6 +415,9 @@ return Grp.isSupported() && Grp.lowerIntoOptimizedSequence(); } +// Currently lowering is supported for the following interleaves: +// 1. stride4 x 64bit elements with vector factor 4 on AVX +// 2. stride4 x 8bit elements with vector factor 32 on AVX2 bool X86TargetLowering::lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI, unsigned Factor) const { Index: test/CodeGen/X86/x86-interleaved-access.ll =================================================================== --- test/CodeGen/X86/x86-interleaved-access.ll +++ test/CodeGen/X86/x86-interleaved-access.ll @@ -139,3 +139,31 @@ %add3 = add <4 x i64> %add2, %strided.v3 ret <4 x i64> %add3 } + +define void @interleaved_store_vf32_i8_stride4(<32 x i8> %x1, <32 x i8> %x2, <32 x i8> %x3, <32 x i8> %x4, <128 x i8>* %p) { +; AVX2-LABEL: interleaved_store_vf32_i8_stride4: +; AVX2: # BB#0: +; AVX2-NEXT: vpunpcklbw {{.*#+}} ymm4 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[4],ymm1[4],ymm0[5],ymm1[5],ymm0[6],ymm1[6],ymm0[7],ymm1[7],ymm0[16],ymm1[16],ymm0[17],ymm1[17],ymm0[18],ymm1[18],ymm0[19],ymm1[19],ymm0[20],ymm1[20],ymm0[21],ymm1[21],ymm0[22],ymm1[22],ymm0[23],ymm1[23] +; AVX2-NEXT: vpunpckhbw {{.*#+}} ymm0 = ymm0[8],ymm1[8],ymm0[9],ymm1[9],ymm0[10],ymm1[10],ymm0[11],ymm1[11],ymm0[12],ymm1[12],ymm0[13],ymm1[13],ymm0[14],ymm1[14],ymm0[15],ymm1[15],ymm0[24],ymm1[24],ymm0[25],ymm1[25],ymm0[26],ymm1[26],ymm0[27],ymm1[27],ymm0[28],ymm1[28],ymm0[29],ymm1[29],ymm0[30],ymm1[30],ymm0[31],ymm1[31] +; AVX2-NEXT: vpunpcklbw {{.*#+}} ymm1 = ymm2[0],ymm3[0],ymm2[1],ymm3[1],ymm2[2],ymm3[2],ymm2[3],ymm3[3],ymm2[4],ymm3[4],ymm2[5],ymm3[5],ymm2[6],ymm3[6],ymm2[7],ymm3[7],ymm2[16],ymm3[16],ymm2[17],ymm3[17],ymm2[18],ymm3[18],ymm2[19],ymm3[19],ymm2[20],ymm3[20],ymm2[21],ymm3[21],ymm2[22],ymm3[22],ymm2[23],ymm3[23] +; AVX2-NEXT: vpunpckhbw {{.*#+}} ymm2 = ymm2[8],ymm3[8],ymm2[9],ymm3[9],ymm2[10],ymm3[10],ymm2[11],ymm3[11],ymm2[12],ymm3[12],ymm2[13],ymm3[13],ymm2[14],ymm3[14],ymm2[15],ymm3[15],ymm2[24],ymm3[24],ymm2[25],ymm3[25],ymm2[26],ymm3[26],ymm2[27],ymm3[27],ymm2[28],ymm3[28],ymm2[29],ymm3[29],ymm2[30],ymm3[30],ymm2[31],ymm3[31] +; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm4[4],ymm1[4],ymm4[5],ymm1[5],ymm4[6],ymm1[6],ymm4[7],ymm1[7],ymm4[12],ymm1[12],ymm4[13],ymm1[13],ymm4[14],ymm1[14],ymm4[15],ymm1[15] +; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm5 = ymm0[4],ymm2[4],ymm0[5],ymm2[5],ymm0[6],ymm2[6],ymm0[7],ymm2[7],ymm0[12],ymm2[12],ymm0[13],ymm2[13],ymm0[14],ymm2[14],ymm0[15],ymm2[15] +; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm1 = ymm4[0],ymm1[0],ymm4[1],ymm1[1],ymm4[2],ymm1[2],ymm4[3],ymm1[3],ymm4[8],ymm1[8],ymm4[9],ymm1[9],ymm4[10],ymm1[10],ymm4[11],ymm1[11] +; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm0[0],ymm2[0],ymm0[1],ymm2[1],ymm0[2],ymm2[2],ymm0[3],ymm2[3],ymm0[8],ymm2[8],ymm0[9],ymm2[9],ymm0[10],ymm2[10],ymm0[11],ymm2[11] +; AVX2-NEXT: vinserti128 $1, %xmm3, %ymm1, %ymm2 +; AVX2-NEXT: vinserti128 $1, %xmm5, %ymm0, %ymm4 +; AVX2-NEXT: vperm2i128 {{.*#+}} ymm1 = ymm1[2,3],ymm3[2,3] +; AVX2-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm0[2,3],ymm5[2,3] +; AVX2-NEXT: vmovdqa %ymm2, (%rdi) +; AVX2-NEXT: vmovdqa %ymm4, 32(%rdi) +; AVX2-NEXT: vmovdqa %ymm1, 64(%rdi) +; AVX2-NEXT: vmovdqa %ymm0, 96(%rdi) +; AVX2-NEXT: vzeroupper +; AVX2-NEXT: retq + %v1 = shufflevector <32 x i8> %x1, <32 x i8> %x2, <64 x i32> + %v2 = shufflevector <32 x i8> %x3, <32 x i8> %x4, <64 x i32> + %interleaved.vec = shufflevector <64 x i8> %v1, <64 x i8> %v2, <128 x i32> + store <128 x i8> %interleaved.vec, <128 x i8>* %p +ret void +} Index: test/Transforms/InterleavedAccess/X86/interleavedStore.ll =================================================================== --- /dev/null +++ test/Transforms/InterleavedAccess/X86/interleavedStore.ll @@ -0,0 +1,44 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt < %s -mtriple=x86_64-pc-linux -mattr=+avx -mattr=+avx2 -interleaved-access -S | FileCheck %s + +define void @interleaved_store_vf32_i8_stride4(<32 x i8> %x1, <32 x i8> %x2, <32 x i8> %x3, <32 x i8> %x4, <128 x i8>* %p) { +; CHECK-LABEL: @interleaved_store_vf32_i8_stride4( +; CHECK-NEXT: [[V1:%.*]] = shufflevector <32 x i8> [[X1:%.*]], <32 x i8> [[X2:%.*]], <64 x i32> +; CHECK-NEXT: [[V2:%.*]] = shufflevector <32 x i8> [[X3:%.*]], <32 x i8> [[X4:%.*]], <64 x i32> +; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <64 x i8> [[V1]], <64 x i8> [[V2]], <32 x i32> +; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <64 x i8> [[V1]], <64 x i8> [[V2]], <32 x i32> +; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <64 x i8> [[V1]], <64 x i8> [[V2]], <32 x i32> +; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <64 x i8> [[V1]], <64 x i8> [[V2]], <32 x i32> +; CHECK-NEXT: [[VPUNPCKLBW:%.*]] = shufflevector <32 x i8> [[TMP1]], <32 x i8> [[TMP2]], <32 x i32> +; CHECK-NEXT: [[VPUNPCKHBW:%.*]] = shufflevector <32 x i8> [[TMP1]], <32 x i8> [[TMP2]], <32 x i32> +; CHECK-NEXT: [[VPUNPCKLBW1:%.*]] = shufflevector <32 x i8> [[TMP3]], <32 x i8> [[TMP4]], <32 x i32> +; CHECK-NEXT: [[VPUNPCKHBW2:%.*]] = shufflevector <32 x i8> [[TMP3]], <32 x i8> [[TMP4]], <32 x i32> +; CHECK-NEXT: [[TMP5:%.*]] = bitcast <32 x i8> [[VPUNPCKLBW]] to <16 x i16> +; CHECK-NEXT: [[TMP6:%.*]] = bitcast <32 x i8> [[VPUNPCKHBW]] to <16 x i16> +; CHECK-NEXT: [[TMP7:%.*]] = bitcast <32 x i8> [[VPUNPCKLBW1]] to <16 x i16> +; CHECK-NEXT: [[TMP8:%.*]] = bitcast <32 x i8> [[VPUNPCKHBW2]] to <16 x i16> +; CHECK-NEXT: [[VPUNPCKHBW3:%.*]] = shufflevector <16 x i16> [[TMP5]], <16 x i16> [[TMP7]], <16 x i32> +; CHECK-NEXT: [[VPUNPCKHBW4:%.*]] = shufflevector <16 x i16> [[TMP6]], <16 x i16> [[TMP8]], <16 x i32> +; CHECK-NEXT: [[VPUNPCKLBW5:%.*]] = shufflevector <16 x i16> [[TMP5]], <16 x i16> [[TMP7]], <16 x i32> +; CHECK-NEXT: [[VPUNPCKLBW6:%.*]] = shufflevector <16 x i16> [[TMP6]], <16 x i16> [[TMP8]], <16 x i32> +; CHECK-NEXT: [[CONCATLOW:%.*]] = shufflevector <16 x i16> [[VPUNPCKLBW5]], <16 x i16> [[VPUNPCKHBW3]], <16 x i32> +; CHECK-NEXT: [[CONCATLOW7:%.*]] = shufflevector <16 x i16> [[VPUNPCKLBW6]], <16 x i16> [[VPUNPCKHBW4]], <16 x i32> +; CHECK-NEXT: [[CONCATHIGH:%.*]] = shufflevector <16 x i16> [[VPUNPCKLBW5]], <16 x i16> [[VPUNPCKHBW3]], <16 x i32> +; CHECK-NEXT: [[CONCATHIGH8:%.*]] = shufflevector <16 x i16> [[VPUNPCKLBW6]], <16 x i16> [[VPUNPCKHBW4]], <16 x i32> +; CHECK-NEXT: [[TMP9:%.*]] = bitcast <128 x i8>* [[P:%.*]] to <16 x i16>* +; CHECK-NEXT: [[TMP10:%.*]] = getelementptr <16 x i16>, <16 x i16>* [[TMP9]], i32 0 +; CHECK-NEXT: store <16 x i16> [[CONCATLOW]], <16 x i16>* [[TMP10]] +; CHECK-NEXT: [[TMP11:%.*]] = getelementptr <16 x i16>, <16 x i16>* [[TMP9]], i32 1 +; CHECK-NEXT: store <16 x i16> [[CONCATLOW7]], <16 x i16>* [[TMP11]] +; CHECK-NEXT: [[TMP12:%.*]] = getelementptr <16 x i16>, <16 x i16>* [[TMP9]], i32 2 +; CHECK-NEXT: store <16 x i16> [[CONCATHIGH]], <16 x i16>* [[TMP12]] +; CHECK-NEXT: [[TMP13:%.*]] = getelementptr <16 x i16>, <16 x i16>* [[TMP9]], i32 3 +; CHECK-NEXT: store <16 x i16> [[CONCATHIGH8]], <16 x i16>* [[TMP13]] +; CHECK-NEXT: ret void +; + %v1 = shufflevector <32 x i8> %x1, <32 x i8> %x2, <64 x i32> + %v2 = shufflevector <32 x i8> %x3, <32 x i8> %x4, <64 x i32> + %interleaved.vec = shufflevector <64 x i8> %v1, <64 x i8> %v2, <128 x i32> + store <128 x i8> %interleaved.vec, <128 x i8>* %p + ret void +}