Index: lib/CodeGen/MachineVerifier.cpp
===================================================================
--- lib/CodeGen/MachineVerifier.cpp
+++ lib/CodeGen/MachineVerifier.cpp
@@ -985,6 +985,15 @@
         report("Operand should be tied", MO, MONum);
       else if (unsigned(TiedTo) != MI->findTiedOperandIdx(MONum))
         report("Tied def doesn't match MCInstrDesc", MO, MONum);
+      else if (TargetRegisterInfo::isPhysicalRegister(MO->getReg())) {
+        const MachineOperand &MOTied = MI->getOperand(TiedTo);
+        if (!MOTied.isReg())
+          report("Tied counterpart must be a register", &MOTied, TiedTo);
+        else if (!TargetRegisterInfo::isPhysicalRegister(MOTied.getReg()))
+          report("Tied counterpart must also be physical", &MOTied, TiedTo);
+        else if (MO->getReg() != MOTied.getReg())
+          report("Tied physical registers must match.", &MOTied, TiedTo);
+      }
     } else if (MO->isReg() && MO->isTied())
       report("Explicit operand should not be tied", MO, MONum);
   } else {
Index: test/CodeGen/MIR/X86/subregister-index-operands.mir
===================================================================
--- test/CodeGen/MIR/X86/subregister-index-operands.mir
+++ test/CodeGen/MIR/X86/subregister-index-operands.mir
@@ -12,20 +12,19 @@
 ...
 ---
 # CHECK-LABEL: name: t
-# CHECK: %0 = INSERT_SUBREG %edi, %al, {{[0-9]+}}
-# CHECK: %1 = EXTRACT_SUBREG %eax, {{[0-9]+}}
-# CHECK: %ax = REG_SEQUENCE %1, {{[0-9]+}}, %1, {{[0-9]+}}
+# CHECK: %edi = INSERT_SUBREG %edi, %al, {{[0-9]+}}
+# CHECK: %0 = EXTRACT_SUBREG %eax, {{[0-9]+}}
+# CHECK: %ax = REG_SEQUENCE %0, {{[0-9]+}}, %0, {{[0-9]+}}
 name:            t
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: gr32 }
-  - { id: 1, class: gr8 }
+  - { id: 0, class: gr8 }
 body: |
   bb.0.entry:
     liveins: %edi, %eax
-    %0 = INSERT_SUBREG %edi, %al, %subreg.sub_8bit
-    %1 = EXTRACT_SUBREG %eax, %subreg.sub_8bit_hi
-    %ax = REG_SEQUENCE %1, %subreg.sub_8bit, %1, %subreg.sub_8bit_hi
+    %edi = INSERT_SUBREG %edi, %al, %subreg.sub_8bit
+    %0 = EXTRACT_SUBREG %eax, %subreg.sub_8bit_hi
+    %ax = REG_SEQUENCE %0, %subreg.sub_8bit, %0, %subreg.sub_8bit_hi
     RETQ %ax
 ...