Index: lib/Target/AMDGPU/SIFoldOperands.cpp
===================================================================
--- lib/Target/AMDGPU/SIFoldOperands.cpp
+++ lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -166,6 +166,8 @@
   if (TargetRegisterInfo::isVirtualRegister(Old.getReg()) &&
       TargetRegisterInfo::isVirtualRegister(New->getReg())) {
     Old.substVirtReg(New->getReg(), New->getSubReg(), TRI);
+
+    Old.setIsUndef(New->isUndef());
     return true;
   }
 
Index: test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
===================================================================
--- test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
+++ test/CodeGen/AMDGPU/constant-fold-imm-immreg.mir
@@ -864,16 +864,22 @@
 # There is only an undef use operand for %1, so there is no
 # corresponding defining instruction
 
+# GCN-LABEL: name: undefined_vreg_operand{{$}}
+# GCN: bb.0
+# GCN-NEXT: FLAT_STORE_DWORD undef %3, undef %1,
+# GCN-NEXT: S_ENDPGM
 name: undefined_vreg_operand
 tracksRegLiveness: true
 registers:
   - { id: 0, class: vgpr_32, preferred-register: '' }
   - { id: 1, class: vgpr_32, preferred-register: '' }
   - { id: 2, class: vgpr_32, preferred-register: '' }
+  - { id: 3, class: vreg_64, preferred-register: '' }
 body:             |
   bb.0:
     %0 = V_MOV_B32_e32 0, implicit %exec
     %2 = V_XOR_B32_e64 killed %0, undef %1, implicit %exec
+    FLAT_STORE_DWORD undef %3, %2, 0, 0, 0, implicit %exec, implicit %flat_scr
     S_ENDPGM
 
 ...